TWI501370B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TWI501370B
TWI501370B TW102109980A TW102109980A TWI501370B TW I501370 B TWI501370 B TW I501370B TW 102109980 A TW102109980 A TW 102109980A TW 102109980 A TW102109980 A TW 102109980A TW I501370 B TWI501370 B TW I501370B
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electrical contact
pad
semiconductor package
substrate
layer
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TW102109980A
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TW201438168A (zh
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林邦群
程協仁
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矽品精密工業股份有限公司
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Priority to TW102109980A priority Critical patent/TWI501370B/zh
Priority to CN201310115674.1A priority patent/CN104064530B/zh
Priority to US13/922,858 priority patent/US9318354B2/en
Publication of TW201438168A publication Critical patent/TW201438168A/zh
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Description

半導體封裝件及其製法
本發明係有關一種半導體封裝件及其製法，尤指一種利於輕薄短小化之半導體封裝件及其製法。
隨著電子產業的蓬勃發展，隨著半導體製程技術的進步，使更多電子元件整合於半導體晶片中，且晶片的效能亦更好，因而晶片上所設置的輸入/輸出連接端(I/O connections)數目漸多。於現今封裝技術發展趨勢下，封裝件朝輕、薄、短、小之技術發展，因而承載晶片用之基板上需密集地佈設複數個與該等輸入/輸出連接端電性連通之打線墊作為晶片之外接電性連接點，如第1A圖所示之半導體封裝件1。
如第1A圖所示，一基板10上承載一半導體晶片13，且該半導體晶片13之電極墊130以複數銲線14電性連接該基板10之打線墊102，再形成封裝膠體15於該基板10上，以包覆該半導體晶片13與銲線14。
然而，於輕、薄、短、小之需求下，需減縮該基板10於晶片周圍之空間以設置符合該電極墊130之數目的該些 打線墊102，致使佈線極為困難，且於如此密集的打線墊102之佈設區域中，該些銲線14間極容易相互接觸k而造成短路。
為避免發生上述因銲線接觸而造成短路之問題，因而發展出一種利用轉接方式，係將半導體晶片之電極墊與轉接元件經第一組銲線連接，再利用第二組銲線連接該轉接元件與基板之打線墊，如第1B及1B’圖所示之半導體封裝件1’。
如第1B圖所示，一基板10係包含一絕緣保護層10b及埋設於該絕緣保護層10b中之線路層10a，該線路層10a具有轉接墊100、第一與第二打線墊101,102’、及位於該轉接墊100與第一打線墊101之間的線路103。將一半導體晶片13結合於該基板10上，且該半導體晶片13之部分電極墊130係以第一短銲線14a連接該轉接墊100，該轉接墊100再以第二短銲線14b連接該第一打線墊101，而另一部分電極墊130係以複數銲線14電性連接該第二打線墊102’。接著，形成封裝膠體15於該基板10上，以包覆該半導體晶片13、第一及第二短銲線14a,14b、銲線14、轉接墊100、第一與第二打線墊101,102’。之後，形成如銲球之導電元件16於該線路層10a之下表面外露處。
惟，習知半導體封裝件1’中，該第二短銲線14b具有一定弧高，故該第二短銲線14b與該銲線14容易相互接觸k，因而造成短路。
再者，為了避免該第二短銲線14b與該銲線14之間因 相互接觸k而短路，故增加該銲線14之弧高，卻因而使該半導體封裝件1’之整體結構高度增加，致使該半導體封裝件1’無法滿足薄化之需求。
又，習知半導體封裝件1’中，當僅有單層線路層10a時，佈局空間將大幅受限而難以彈性化，致使許多線路103僅能於平面上進行佈設，而無法製作多層線路，因而無法經由上、下層之繞線方式進行迴避。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，係包括：基板，係具有複數轉接墊、複數第一電性接觸墊及複數位於該轉接墊與第一電性接觸墊之間的線路；絕緣層，係覆蓋該線路；導電層，係設於該絕緣層上，且該導電層延伸至該轉接墊與第一電性接觸墊上；以及半導體元件，係設於該基板上，且該半導體元件以複數銲線電性連接該轉接墊。
前述之半導體封裝件中，該基板復具有絕緣保護層，供該轉接墊與第一電性接觸墊埋設於該絕緣保護層中，並令該轉接墊與第一電性接觸墊外露於該絕緣保護層
本發明復提供一種半導體封裝件之製法，係包括：提供一基板，該基板具有複數轉接墊、複數第一電性接觸墊及複數位於該轉接墊與第一電性接觸墊之間的線路；覆蓋絕緣層於該線路上；形成導電層於該絕緣層上，且該導電 層延伸至該轉接墊與第一電性接觸墊上；以及設置半導體元件於該基板上，並以複數銲線電性連接該半導體元件及該轉接墊。
前述之半導體封裝件及其製法中，該基板復具有複數第二電性接觸墊，以供該半導體元件以該些銲線電性連接該第二電性接觸墊。
前述之半導體封裝件及其製法中，該線路係相對凸出該基板表面。
前述之半導體封裝件及其製法中，該轉接墊、導電層與第一電性接觸墊係成為導電路徑。
前述之半導體封裝件及其製法中，該轉接墊、線路與第一電性接觸墊上具有表面處理層。
前述之半導體封裝件及其製法中，該絕緣層係為膠體，例如，以噴墨或塗佈方式形成之。
前述之半導體封裝件及其製法中，該導電層係為膠體、噴墨形成之金屬層或經由塗佈形成之導電跡線。
另外，前述之半導體封裝件及其製法中，復包括形成封裝膠體於該基板上，以包覆該半導體元件、銲線、轉接墊、導電層與第一電性接觸墊。
由上可知，本發明之半導體封裝件及其製法，係藉由該導電層連接該轉接墊與第一電性接觸墊，且該導電層之高度遠低於銲線弧高，故以該導電層取代習知短銲線，長銲線於打線製程中不會接觸該導電層，因而可避免短路，使本發明不僅能避免產品失效，且能降低長銲線之線弧， 以減低該封裝膠體之厚度，而利於薄化該半導體封裝件。
再者，當基板僅有單層線路層時，利用該轉接墊與第一電性接觸墊之間的空間作為佈線區，以形成該絕緣層與導電層，使該導電層作為線路結構，故能增加佈線空間，以使線路佈局更具彈性化。
1,1’,2‧‧‧半導體封裝件
10,20‧‧‧基板
10a,20a‧‧‧線路層
10b,20b‧‧‧絕緣保護層
100,200‧‧‧轉接墊
101‧‧‧第一打線墊
102‧‧‧打線墊
102’‧‧‧第二打線墊
103,203‧‧‧線路
13‧‧‧半導體晶片
130,230‧‧‧電極墊
14,24,24’‧‧‧銲線
14a‧‧‧第一短銲線
14b‧‧‧第二短銲線
15,25‧‧‧封裝膠體
16,26‧‧‧導電元件
200b‧‧‧開孔
201‧‧‧第一電性接觸墊
202‧‧‧第二電性接觸墊
204‧‧‧置晶墊
205‧‧‧植球墊
21‧‧‧絕緣層
22‧‧‧導電層
23‧‧‧半導體元件
231‧‧‧黏著材
27‧‧‧表面處理層
h‧‧‧凸出高度
第1A圖係為習知半導體封裝件之剖視示意圖；第1B圖係為習知半導體封裝件之剖視示意圖；第1B’圖係為第1B圖之局部上視示意圖；第2A至2C圖係為本發明之半導體封裝件之製法之剖視示意圖；第2A’圖係為第2A圖之另一實施例；以及第2C’圖係為第2C圖之局部上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上” 及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2C圖係為本發明之半導體封裝件2之製法之剖面示意圖。
如第2A圖所示，提供一基板20，該基板20係包含一絕緣保護層20b及嵌埋於該絕緣保護層20b中之線路層20a，該線路層20a之上側具有轉接墊200、第一與第二電性接觸墊201,202、置晶墊204、及位於該轉接墊200與第一電性接觸墊201之間的線路203，而該線路層20a之下側具有複數植球墊205。
於本實施例中，該基板20係為單層之線路結構，該絕緣保護層20b係為封裝膠體，且該線路203係相對凸出該絕緣保護層20b，而該線路203之凸出高度h係為5至15um。
再者，該轉接墊200、第一與第二電性接觸墊201,202、線路203及置晶墊204係外露於該絕緣保護層20b之上側，而該植球墊205係外露於該絕緣保護層20b之下側，例如，該絕緣保護層20b具有複數開孔200b，以外露該植球墊205。
又，該第一與第二電性接觸墊201,202、線路203及置晶墊204係電性連接該植球墊205。
另外，如第2A’圖所示，可形成一表面處理層27於該轉接墊200、第一與第二電性接觸墊201,202、線路203與置晶墊204上。其中，該表面處理層27係為鎳金層或有機 保銲劑(Organic Solderability Preservative,OSP)。
如第2B圖所示，形成一絕緣層21於該基板20上以覆蓋該線路203，再形成一導電層22於該絕緣層21上，且該導電層22延伸至該轉接墊200與該第一電性接觸墊201上，使該轉接墊200、導電層22與第一電性接觸墊201成為一導電路徑。該線路203與該導電層22之間係藉由該絕緣層21而電性隔絕，以防止該線路203與該導電層22因相接觸而短路。
於本實施例中，該絕緣層21可為膠體，且以噴墨、塗佈或點膠方式形成，且該導電層22可為金屬層經由網印、噴墨或其它方式形成，或經由塗佈形成之導電跡線；該導電層22亦可為一膠體，經由塗佈、點膠、噴墨或其它方式形成。
如第2C及2C’圖所示，藉由黏著材231結合一具有複數電極墊230之半導體元件23於該基板20之置晶墊204上，且該半導體元件23之電極墊230以複數銲線24,24’電性連接該轉接墊200及該第二電性接觸墊202。換言之，該半導體元件23之部分電極墊230係以該銲線24連接該轉接墊200，再經由該轉接墊200、導電層22與第一電性接觸墊201連接至植球墊205所構成之導電路徑，以令該半導體元件23電性連接至外部。
接著，形成封裝膠體25於該基板20上，以包覆該半導體元件23、銲線24,24’、轉接墊200、導電層22、第一與第二電性接觸墊201,202。之後，形成如銲球之導電元件 26於該植球墊205上。
本發明之半導體封裝件2之製法中，係以該導電層22連接該轉接墊200與第一電性接觸墊201，且該導電層22之高度遠低於銲線弧高，故以該導電層22取代習知短銲線，該較長銲線24’於打線製程中不會接觸該導電層22，因而可避免短路。因此，本發明之製法不僅能避免產品失效，且能降低該較長銲線24’之線弧，以減低該封裝膠體25之厚度，有利於該半導體封裝件2朝輕、薄、短、小之技術發展。
再者，當基板20僅有單層線路層20a時，利用該轉接墊200與第一電性接觸墊201之間的空間作為佈線區，以形成該絕緣層21與導電層22，使該導電層22作為線路結構，故藉該導電層22之設計，能增加佈線空間，以使線路佈局更具彈性化，致使許多線路203與該導電層22能經由上、下層之繞線方式進行迴避。
本發明提供一種半導體封裝件2，係包括：一基板20、形成於該基板20上之一絕緣層21、形成於該絕緣層21上之一導電層22、設於該基板20上之一半導體元件23以及形成於該基板20上之封裝膠體25。
所述之基板20係具有轉接墊200、第一電性接觸墊201及位於該轉接墊200與第一電性接觸墊201之間的線路203。
於一實施例中，該基板20復具有絕緣保護層20b，令該轉接墊200與第一電性接觸墊201埋設於該絕緣保護層 20b中，且令該轉接墊200與第一電性接觸墊201外露於該絕緣保護層20b。
於一實施例中，該線路203係相對凸出該基板20表面(或該絕緣保護層20b表面)。
所述之絕緣層21係覆蓋該線路203，且該絕緣層21可為膠體。
所述之導電層22係延伸至該轉接墊200與第一電性接觸墊201上，且該導電層22可為膠體、金屬層或線路。
所述之半導體元件23係以複數銲線24電性連接該轉接墊200，且該轉接墊200、導電層22與第一電性接觸墊201係成為一導電路徑。
於一實施例中，該基板20復具有第二電性接觸墊202，且該半導體元件23以另一銲線24’直接電性連接該第二電性接觸墊202。
所述之封裝膠體25係包覆該半導體元件23、銲線24,24’、轉接墊200、導電層22與第一電性接觸墊201。
於一實施例中，該轉接墊200、線路203與第一電性接觸墊201上具有表面處理層36。
綜上所述，本發明之半導體封裝件及其製法，主要藉由該導電層取代習知短銲線，以作為連接該轉接墊與第一電性接觸墊之轉接元件，而能避免該銲線相互接觸所造成之短路問題，故能提升產品之可靠度，且利於該半導體封裝件朝輕、薄、短、小之技術發展。
再者，於該轉接墊與第一電性接觸墊之間的線路上形 成線路結構(即該絕緣層與導電層)，故能增加佈線空間，以達到線路佈局彈性化之目的。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體封裝件
20‧‧‧基板
200‧‧‧轉接墊
201‧‧‧第一電性接觸墊
202‧‧‧第二電性接觸墊
203‧‧‧線路
204‧‧‧置晶墊
205‧‧‧植球墊
21‧‧‧絕緣層
22‧‧‧導電層
23‧‧‧半導體元件
230‧‧‧電極墊
231‧‧‧黏著材
24,24’‧‧‧銲線
25‧‧‧封裝膠體
26‧‧‧導電元件

Claims (18)

  1. 一種半導體封裝件，係包括：基板，係具有複數轉接墊、複數第一電性接觸墊及複數位於該轉接墊與第一電性接觸墊之間的線路，其中，該些轉接墊、該些第一電性接觸墊及該線路係佈設於同一表面；絕緣層，係覆蓋該線路；導電層，係形成於該絕緣層上，且該導電層延伸至該轉接墊與第一電性接觸墊上；以及半導體元件，係設於該基板上，且該半導體元件以複數銲線電性連接該轉接墊。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該基板復具有複數第二電性接觸墊，以供該半導體元件以該些銲線電性連接該第二電性接觸墊。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該基板復具有絕緣保護層，供該轉接墊與第一電性接觸墊埋設於該絕緣保護層中，並令該轉接墊與第一電性接觸墊外露於該絕緣保護層。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路係相對凸出該基板表面。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該轉接墊、導電層與第一電性接觸墊係成為導電路徑。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該轉接墊、線路與第一電性接觸墊上具有表面處理層。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該絕緣層係為膠體。
  8. 如申請專利範圍第1項所述之半導體封裝件，其中，該導電層係為膠體或金屬層。
  9. 如申請專利範圍第1項所述之半導體封裝件，復包括封裝膠體，係形成於該基板上，以包覆該半導體元件、銲線、轉接墊、導電層與第一電性接觸墊。
  10. 一種半導體封裝件之製法，係包括：提供一基板，該基板具有複數轉接墊、複數第一電性接觸墊及複數位於該轉接墊與第一電性接觸墊之間的線路，其中，該些轉接墊、該些第一電性接觸墊及該線路係佈設於同一表面；覆蓋絕緣層於該線路上；形成導電層於該絕緣層上，且該導電層延伸至該轉接墊與第一電性接觸墊上；以及設置半導體元件於該基板上，並以複數銲線電性連接該半導體元件及該轉接墊。
  11. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該基板復具有複數第二電性接觸墊，以供該半導體元件以該些銲線電性連接該第二電性接觸墊。
  12. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該線路係相對凸出該基板表面。
  13. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該轉接墊、導電層與第一電性接觸墊係成為導 電路徑。
  14. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該轉接墊、線路與第一電性接觸墊上形成有表面處理層。
  15. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該絕緣層係為膠體。
  16. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該絕緣層之形成係以噴墨或塗佈方式為之。
  17. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，該導電層係為金屬層經由噴墨或網印方式形成或係為膠體經由塗佈、點膠或噴墨方式形成之導電跡線。
  18. 如申請專利範圍第10項所述之半導體封裝件之製法，復包括形成封裝膠體於該基板上，以包覆該半導體元件、銲線、轉接墊、導電層與第一電性接觸墊。
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