TWI501240B

TWI501240B - Flash memory and method for operating memory device

Info

Publication number: TWI501240B
Application number: TW101121363A
Authority: TW
Inventors: Johnny Chan; Teng Su; Michael Chi Li
Original assignee: Winbond Electronics Corp
Priority date: 2012-06-14
Filing date: 2012-06-14
Publication date: 2015-09-21
Also published as: TW201351414A

Description

快閃記憶體及操作記憶體裝置的方法Flash memory and method of operating memory device

本發明是有關於一種快閃記憶體，且特別是有關於一種在快閃記憶體上的邏輯資料讀取。The present invention relates to a flash memory, and more particularly to a logical data reading on a flash memory.

由於較少的腳位數及簡單的介面，單位元串列及多位元串列快閃記憶體已經變得普遍。最簡單的介面是一位元串列週邊介面(Serial Peripheral Interface，SPI)。一位元串列週邊介面通訊協定包含使用者送出8位元的指令、位址位元組、以及選擇性的虛擬位元組(dummy bytes)給串列週邊介面快閃記憶體裝置，並且串列週邊介面快閃記憶體裝置將回傳資料給使用者作為回應。單一的8位元指令可識別讀取、抹除/程式化、或另一個適當的操作。對於要求快速讀取效能的高效能系統應用，已經發展出例如雙串列週邊介面(SPI-Dual)、四串列週邊介面(SPI-Quad)、以及四元週邊介面(Quad Peripheral Interface，QPI)之多位元串列介面。在四串列週邊介面中，以一次一位元的方式串列地提供8位元指令，但是所有的後續欄位(例如位址、選擇性的虛擬位元組、以及資料)是在4位元(四)串列基礎上完成以改善讀取量。在四元週邊介面中，所有的欄位(例如8位元指令、位址、選擇性的虛擬位元組以及資料)都是以4位元串列完成。以此方式，四元週邊介面於兩個時脈週期提供8位元指令，而四串列週邊介面則需要8個時脈週期。各種多位元串列快閃介面通訊協定說明於例如由Jigour等人申請的第7558900號美國專利，其發布於2009年7月7日。Unitary string and multi-bit serial flash memory have become commonplace due to fewer pin counts and simple interfaces. The simplest interface is a Serial Peripheral Interface (SPI). A meta-string peripheral interface protocol includes a user sending an 8-bit instruction, an address byte, and a selective dummy byte to the serial peripheral flash device, and the string The column peripheral interface flash memory device will respond to the user by returning the data. A single 8-bit instruction can identify read, erase/stylize, or another suitable operation. For high-performance system applications that require fast read performance, for example, a dual serial peripheral interface (SPI-Dual), a four-string peripheral interface (SPI-Quad), and a Quad Peripheral Interface (QPI) have been developed. The multi-bit serial interface. In the four-column peripheral interface, 8-bit instructions are provided in tandem in a one-bit manner, but all subsequent fields (such as address, selective virtual byte, and data) are in 4 bits. Yuan (4) is completed on a serial basis to improve the reading amount. In the quaternary interface, all fields (such as 8-bit instructions, addresses, selective virtual bytes, and data) are all done in 4-bit serials. In this way, the quaternary peripheral interface provides 8-bit instructions in two clock cycles, while the four-string peripheral interface requires eight clock cycles. each A multi-bit serial flash interface protocol is described, for example, in U.S. Patent No. 7,558,900, filed on Jan. 7, 2009.

快閃記憶體所執行的讀取操作類型典型上包括記憶體陣列讀取以及邏輯讀取。圖1繪示在典型的快閃記憶體中，用以執行邏輯讀取的電路方塊示意圖。邏輯12從不同的暫存器(例如圖2中的暫存器4)接收邏輯資料，例如狀態資料、聯合電子設備工程委員會(Joint Electron Device Engineering Council，JEDEC)製造商以及部分認證資料。邏輯12也接收串列輸入SI，其包括多個指令以及不同的輸入資料。邏輯12完全地解碼在第8個時脈上的各個指令，假若所述指令為信號JEDEC、RDSR1或RDSR2時，則分別選擇資料JEDECID、SR1或是SR2，並將所選擇的指令以邏輯資料LOGICDATA的身分提供至資料暫存器14。當指令為記憶體讀取指令時，資料暫存器14也從所述記憶胞陣列中接收陣列資料ARRAYDATA。基於來自邏輯12的輸入信號，例如信號JEDEC、RDSR1以及RDSR2，資料暫存器14選擇邏輯資料LOGICDATA或是陣列資料ARRAYDATA，並且將所選擇資料以串列資料輸出信號SDOUT/輸出。焊墊串列輸出電路16包括輸出驅動器，當焊墊串列輸出電路16在串列資料輸出信號SDOUT/為邏輯資料時被信號RDLD所致能，或是在串列資料輸出信號SDOUT/為記憶體陣列資料時被信號OEIN所致能時，所述輸出驅動器即輸出串列資料輸出信號SDOUT/至封裝的快閃記憶體裝置的接觸面，例如鉛、焊墊或是腳位等。焊墊串列輸出電路16是由系統時脈SCK控制，而邏輯12以及資料暫存器14則由時脈信號CLK所控制，也就是由輸入焊墊電路10所緩衝的系統時脈SCK。The types of read operations performed by flash memory typically include memory array reads and logical reads. 1 is a block diagram of a circuit for performing a logic read in a typical flash memory. Logic 12 receives logic data from different registers (e.g., register 4 in Figure 2), such as status data, Joint Electron Device Engineering Council (JEDEC) manufacturers, and partial certification materials. Logic 12 also receives a serial input SI that includes a plurality of instructions and different input data. The logic 12 completely decodes each instruction on the eighth clock. If the instruction is the signal JEDEC, RDSR1 or RDSR2, respectively selects the data JEDECID, SR1 or SR2, and selects the selected instruction as the logical data LOGICDATA. The identity is provided to the data register 14. When the instruction is a memory read instruction, the data register 14 also receives the array data ARRAYDATA from the memory cell array. Based on the input signals from the logic 12, such as the signals JEDEC, RDSR1, and RDSR2, the data register 14 selects the logical data LOGICDATA or the array data ARRAYDATA, and outputs the selected data as a serial data output signal SDOUT/output. The pad serial output circuit 16 includes an output driver. When the pad serial output circuit 16 is enabled by the signal RDLD when the serial data output signal SDOUT/ is logic data, or the serial data output signal SDOUT/ is memory When the body array data is enabled by the signal OEIN, the output driver is the output string Output signal SDOUT/ to the contact surface of the packaged flash memory device, such as lead, pad or pin. The pad serial output circuit 16 is controlled by the system clock SCK, while the logic 12 and data register 14 are controlled by the clock signal CLK, that is, the system clock SCK buffered by the input pad circuit 10.

邏輯12的更詳細細節繪示於圖2中。邏輯12對串列輸入SI中的指令解碼，並且提供一信號，其可唯一識別邏輯讀取指令、用於讀取資料JEDECID的說明性信號JEDEC、用於讀取第一狀態暫存器的信號RDSR1以及用於讀取第二狀態暫存器的信號RDSR2。這些信號在組合性邏輯24中組合，以獲得象徵邏輯資料讀取指令的信號RDLD。信號RDLD被施於多工器26的選定輸入，當觸發信號RDLD時，多工器26從其多個資料輸入的其中之一選擇邏輯資料LOGICDATA，否則即選擇來自於暫存器25的資料，暫存器25儲存由主陣列感測放大器2接收的記憶體陣列資料。More detailed details of the logic 12 are shown in FIG. The logic 12 decodes the instructions in the serial input SI and provides a signal that uniquely identifies the logical read instruction, the illustrative signal JEDEC for reading the data JEDECID, and the signal for reading the first state register RDSR1 and signal RDSR2 for reading the second status register. These signals are combined in combination logic 24 to obtain a signal RDLD that symbolizes a logical data read instruction. The signal RDLD is applied to the selected input of the multiplexer 26. When the trigger signal RDLD, the multiplexer 26 selects the logic data LOGICDATA from one of its plurality of data inputs, otherwise selects the data from the register 25, The register 25 stores the memory array data received by the main array sense amplifier 2.

焊墊串列輸出電路16的更詳細細節繪示於圖3中。輸出驅動器34由時脈信號CLK以及來自D型正反器32的輸出致能信號OE控制。D型正反器32基於施加於輸入端SET的信號RDLD以及施加於輸入端D的信號OEIN而產生輸出致能信號OE。輸入信號OEIN用於陣列讀取。D型正反器32以及輸出驅動器34皆由時脈信號CLK控制。More detailed details of the pad serial output circuit 16 are shown in FIG. The output driver 34 is controlled by a clock signal CLK and an output enable signal OE from the D-type flip-flop 32. The D-type flip-flop 32 generates an output enable signal OE based on the signal RDLD applied to the input terminal SET and the signal OEIN applied to the input terminal D. The input signal OEIN is used for array reading. Both the D-type flip-flop 32 and the output driver 34 are controlled by the clock signal CLK.

本發明的一實施例提供一種快閃記憶體，其具有可回應於一組邏輯讀取指令而輸出邏輯資料的能力，包括外部信號輸入端、可定址快閃記憶胞陣列、資料暫存器、多數個暫存器以及指令和控制邏輯電路。資料暫存器耦接於所述可定址快閃記憶胞陣列，用以接收並儲存來自於所述可定址快閃記憶胞陣列的陣列資料。多數個暫存器用以儲存邏輯資料。指令和控制邏輯電路，包括預取邏輯(pre-fetch logic)以及輸出控制邏輯。預取邏輯耦接於所述外部信號輸入端，用以當所述外部信號輸入端接收指令的最高有效位元的第一部分序列為預測的特定邏輯資料讀取指令時，依據所述多個邏輯讀取指令的特定其中之一，從所述多個邏輯資料暫存器的其中之一預取邏輯資料。輸出控制邏輯耦接於所述外部信入輸入端，用以當所述外部信號輸入端接收指令的最高有效位元的第二部分序列為預測的所述多數個邏輯資料讀取指令的任意其中之一時，產生預測的邏輯讀取指令信號。所述快閃記憶體更包括輸出焊墊電路，其耦接於所述資料暫存器、預取邏輯、輸出控制邏輯以及外部信號接收端，用以當該預測的邏輯讀取指令信號以及除了所述第一部分序列及第二部分序列之外的部分指令解析收到的所述多個邏輯資料讀取指令的任意其中之一時，選擇及輸出來自所述預取邏輯的邏輯資料。An embodiment of the present invention provides a flash memory having the capability of outputting logic data in response to a set of logical read commands, including an external signal input terminal, an addressable flash memory cell array, a data register, Most of the scratchpads as well as the instruction and control logic. The data register is coupled to the addressable flash memory cell array for receiving and storing array data from the addressable flash memory cell array. Most registers are used to store logical data. Instruction and control logic, including pre-fetch logic and output control logic. Prefetching logic is coupled to the external signal input terminal, when the first signal sequence of the most significant bit of the instruction received by the external signal input terminal is a predicted specific logic data read instruction, according to the multiple logic Reading one of the specific ones of the instructions, prefetching the logical data from one of the plurality of logical data registers. The output control logic is coupled to the external signal input terminal, and the second partial sequence of the most significant bit of the command received by the external signal input terminal is any one of the predicted plurality of logical data read commands. In one of the cases, a predicted logical read command signal is generated. The flash memory further includes an output pad circuit coupled to the data register, the prefetch logic, the output control logic, and the external signal receiving end for reading the command signal and the And when the part of the first partial sequence and the second partial sequence parse the received one of the plurality of logical data read instructions, the logical data from the prefetch logic is selected and outputted.

本發明的另一實施例提供一種操作記憶體裝置的方法，所述記憶體裝置具有快閃記憶胞陣列，用以回應於具有預定指令位元數量的邏輯讀取指令，以提供邏輯資料至應用程式。所述方法包括：接收位元數少於預定指令位元數量的指令的位元序列，所述多個接收的位元序列為所述指令的多個最高有效位元。在所述記憶體裝置的邏輯電路中對所述接收的位元序列預解碼(pre-decoding)，以判別所述接收位元序列是否匹配對應的邏輯讀取指令的位元序列。在所述焊墊輸出電路中完成對所述指令其餘位元的解碼，以判別在所述預解碼的步驟中的匹配是否正確地預測所述邏輯讀取指令。依據所述邏輯讀取指令輸出邏輯資料。Another embodiment of the present invention provides a method of operating a memory device having a flash memory cell array for responding to a logical read instruction having a predetermined number of instruction bits to provide logic data to application. The method includes receiving a sequence of bits of instructions having fewer than a predetermined number of instruction bits, the plurality of received bit sequences being a plurality of most significant bits of the instruction. The received bit sequence is pre-decoded in a logic circuit of the memory device to determine whether the received bit sequence matches a bit sequence of a corresponding logical read instruction. Decoding of the remaining bits of the instruction is done in the pad output circuit to determine if the match in the pre-decoding step correctly predicts the logical read instruction. The logic data is output according to the logic read instruction.

本發明的另一實施例提供一種操作記憶體裝置的方法，所述記憶體裝置具有快閃記憶胞陣列，用以回應於具有預定指令位元數量的邏輯讀取指令，以提供邏輯資料至應用程式，所述方法包括：接收位元數少於預定指令位元數量的指令的第一位元序列，所述多個接收的第一位元序列為所述指令的多個最高有效位元。在所述記憶體裝置的邏輯電路中對所述接收的第一位元序列預解碼，以判別所述接收的第一位元序列是否匹配對應的邏輯讀取指令的位元序列。依據在所述預解碼步驟中匹配的所述邏輯讀取指令來預取邏輯資料。接收位元數少於預定指令位元數量但多於所述第一位元序列的指令的第二位元序列，所述多個接收的第二位元序列為所述指令的多個最高有效位元。在所述記憶體裝置的邏輯電路中對所述接收的第二位元序列預解碼，以判別所述接收的第二位元序列是否匹配對應的邏輯讀取指令的位元序列。在所述焊墊輸出電路中完成對所述指令其餘位元的解碼，以判別在所述第二序列預解碼的步驟中的匹配是否正確地預測所述邏輯讀取指令。輸出在所述預取步驟中所預取的邏輯資料。在一變化中，最高有效位元的所述第一序列以及第二序列為7位元。在另一變化中，最高有效位元的所述第一部分序列為4位元，且最高有效位元的所述第二部分序列為7位元。Another embodiment of the present invention provides a method of operating a memory device having a flash memory cell array for responding to a logical read instruction having a predetermined number of instruction bits to provide logic data to an application The program includes: receiving a first bit sequence of instructions having a number of bits less than a predetermined number of instruction bits, the plurality of received first bit sequences being a plurality of most significant bits of the instruction. The received first bit sequence is pre-decoded in a logic circuit of the memory device to determine whether the received first bit sequence matches a bit sequence of a corresponding logical read instruction. The logical data is prefetched according to the logical read instruction matched in the pre-decoding step. Receiving a second bit sequence of instructions having fewer than a predetermined number of instruction bits but more than the first bit sequence, the plurality of received second bit sequences being the most significant of the plurality of instructions Bit. The received second bit sequence is pre-decoded in a logic circuit of the memory device to determine whether the received second bit sequence matches a bit sequence of a corresponding logical read instruction. Decoding the remaining bits of the instruction in the pad output circuit to determine pre-decoding in the second sequence Whether the matching in the step correctly predicts the logical read instruction. The logical data prefetched in the prefetching step is output. In a variation, the first sequence and the second sequence of the most significant bits are 7 bits. In another variation, the first partial sequence of the most significant bits is 4 bits and the second partial sequence of the most significant bits is 7 bits.

快閃記憶體可廣泛地適用於數位電子裝置及系統中。然而，具有高效能的裝置及系統通常需要快閃記憶體操作在較高的頻率。舉例而言，在記憶體讀取的操作情形中，雖然在所述指令後使用虛置時脈(dummy clock)可允許較高頻率的操作，但邏輯讀取操作的速度仍可能出現瓶頸。此問題是因在指令解碼和邏輯電路、資料暫存器電路、互聯內部信號線中過多的延遲所造成。Flash memory is widely used in digital electronic devices and systems. However, high performance devices and systems typically require flash memory to operate at higher frequencies. For example, in an operational situation of memory reading, although the use of a dummy clock after the instruction may allow for higher frequency operations, the speed of the logical read operation may still be bottlenecked. This problem is caused by excessive delays in the instruction decode and logic circuits, the data register circuits, and the interconnect internal signal lines.

例如信號JEDEC讀取指令(9Fh)、第一狀態暫存器讀取指令(信號RDSR1 05h)以及第二狀態暫存器讀取指令(信號RDSR2 35h)，其皆為邏輯讀取指令的例子。信號JEDEC讀取指令從所述裝置輸出製造商以及裝置身分位元組，用以判斷所述裝置的身分。信號RDSR1以及RDSR2讀取指令分別輸出第一狀態暫存器以及第二狀態暫存器的內容。For example, the signal JEDEC read command (9Fh), the first state register read command (signal RDSR1 05h), and the second state register read command (signal RDSR2 35h) are all examples of logical read instructions. A signal JEDEC read command outputs a manufacturer and device identity bit from the device to determine the identity of the device. The signals RDSR1 and RDSR2 read instructions respectively output the contents of the first state register and the second state register.

圖4繪示信號JEDEC、RDSR1以及RDSR2在非常高頻操作中的操作情形，並假設在所述快閃記憶體裝置中沒有其他瓶頸。串列輸入SI包括8個時脈，用以在上升邊緣控制8個指令位元，之後接著多個在下降邊緣用於控制資料的額外時脈。所述快閃記憶體可設計為使第8個時脈不只在指令的上升邊緣控制其最低有效位元(Least Significant Bit，LSB)，也在其下降邊緣控制其第1個資料位元，亦即最左邊的向下箭頭所指之處。因此，用於完成指令解碼及抓取(fetch)以及輸出資料的時序容忍度(timing margin)僅為相當短的半週期。Figure 4 illustrates the operation of signals JEDEC, RDSR1, and RDSR2 in very high frequency operation, and assumes that there are no other bottlenecks in the flash memory device. The serial input SI includes 8 clocks to control 8 instruction bits on the rising edge, followed by multiple control edges at the falling edge. Additional timing of the material. The flash memory can be designed such that the 8th clock not only controls its Least Significant Bit (LSB) at the rising edge of the command, but also controls its first data bit at its falling edge. That is, the leftmost down arrow points to it. Therefore, the timing margin for completing instruction decoding and fetching and outputting data is only a relatively short half cycle.

不幸的是，假設在所述快閃記憶體中沒有其他瓶頸，則當操作的頻率提升至一特定點時，所述半週期的時序容忍度是不足的，如同圖5中所繪示。當出現許多延遲時，其中較為顯著的延遲以箭號A1、B1、C1、D1及E1標示。箭號A1標示由系統時脈SCK的緩衝所導致的延遲，其使得內部時脈信號CLK可以被提供。箭號B1標示在所述第8個位元到達後，解碼所述指令以產生信號JEDEC、RDSR1或是RDSR2的延遲。箭號C1標示在邏輯12中，在信號JEDEC、RDSR1或是RDSR2產生後選擇適當邏輯資料的延遲。箭號D1標示在陣列資料ARRAYDATA和邏輯資料LOGICDATA之間選擇用於輸出串列資料輸出信號SDOUT/時，與資料暫存器14中的組合性邏輯24以及多工器26(繪示於圖2)中的時脈信號CLK的上升邊緣有關的延遲。箭號E1標示延著RDLR信號路徑以及在D型正反器32中的時脈信號CLK的上升邊緣，與用於產生輸出致能信號OE有關的延遲，其中輸出致能信號OE致能輸出驅動器34。箭號F1標示整體的延遲，其在此例中為將近整個週期且遠超過所述半週期的時序容忍度。Unfortunately, assuming that there are no other bottlenecks in the flash memory, the timing tolerance of the half cycle is insufficient when the frequency of operation is raised to a particular point, as depicted in FIG. When there are many delays, the more significant delays are indicated by arrows A1, B1, C1, D1 and E1. Arrow A1 indicates the delay caused by the buffering of the system clock SCK, which allows the internal clock signal CLK to be provided. Arrow B1 indicates that after the arrival of the eighth bit, the instruction is decoded to produce a delay of signal JEDEC, RDSR1 or RDSR2. The arrow C1 is indicated in logic 12, and the delay of selecting the appropriate logic data after the signal JEDEC, RDSR1 or RDSR2 is generated. The arrow D1 indicates the combination logic 24 and the multiplexer 26 in the data register 14 when the serial data output signal SDOUT/ is selected between the array data ARRAYDATA and the logic data LOGICDATA (shown in FIG. 2). The delay associated with the rising edge of the clock signal CLK. The arrow E1 indicates the delay along the rising edge of the RDLR signal path and the clock signal CLK in the D-type flip-flop 32, and the delay associated with the output enable signal OE, wherein the output enable signal OE enables the output driver 34. The arrow F1 indicates the overall delay, which in this example is nearly the entire period and far exceeds the timing tolerance of the half period.

理想的快閃記憶體的操作頻率一般而言是較高的。在記憶體陣列讀取操作中，當改善的時機消除瓶頸時，邏輯讀取操作中的時機延遲可能超過所述半週期的時序容忍度，且成為更高頻率操作中的下一個瓶頸。有利的是，此處的多個實施方式可用不同的方式改善邏輯讀取操作的時機。The operating frequency of an ideal flash memory is generally higher. In a memory array read operation, when the improved timing eliminates bottlenecks, the timing delay in the logical read operation may exceed the timing tolerance of the half cycle and become the next bottleneck in higher frequency operation. Advantageously, the various embodiments herein can improve the timing of logical read operations in different ways.

邏輯讀取操作的時機可由焊墊串列輸出電路改善，其在最後一個指令時脈前接收預解碼指令信號以及預取邏輯資料，並且對所述焊墊串列輸出電路的指令輸入序列的最後一個時脈的指令執行快速解析(fast resolution)，以避免串列邏輯電路延遲、資料暫存器延遲以及內部信號線延遲。在一SPI的說明性實施方式中，指令預解碼在指令輸入的第7個時脈中完成，且用以產生預指令(pre-command)信號，所述預指令信號可預先提供至所述焊墊串列輸出電路，所述預解碼指令也可用以預取邏輯資料，所述邏輯資料可預先提供至所述焊墊串列輸出電路。在另一SPI的說明性實施方式中，指令預解碼在指令輸入的第4個時脈中完成，用以產生預指令信號，所述預指令信號可預先提供至所述焊墊串列輸出電路，而另一指令預解碼則在指令輸入的第7個時脈中完成，用以預取邏輯資料，所述邏輯資料可預先提供至所述焊墊串列輸出電路。在一QPI的說明性實施方式中，指令預解碼在4位元指令輸入的第一個時脈中完成，用以產生預指令信號，所述預指令信號可預先提供至所述四個焊墊串列輸出電路的各個電路，所述預指令信號也可預取邏輯資料，所述邏輯資料可預先提供至所述四個焊墊串列輸出電路的各個電路。快速指令解析可在四個焊墊串列輸出電路的各個電路的指令輸入序列的第2個時脈中完成，所述四個焊墊串列輸出電路各接收所述指令的4個LSB。所述指令預解碼、邏輯資料預取以及在焊墊串列輸出電路中的快速指令解析的技術可單獨或以任意組合使用，以改善邏輯讀取的時機。The timing of the logic read operation can be improved by the pad serial output circuit, which receives the pre-decode command signal and the prefetch logic data before the last instruction clock, and the last of the command input sequence of the pad serial output circuit A clock instruction performs fast resolution to avoid serial logic delay, data register latency, and internal signal line delay. In an illustrative embodiment of an SPI, instruction pre-decoding is done in a seventh clock of the instruction input and is used to generate a pre-command signal, which may be pre-provisioned to the solder The pad serial output circuit can also be used to prefetch logic data, which can be provided in advance to the pad serial output circuit. In an illustrative embodiment of another SPI, instruction pre-decoding is performed in a fourth clock of the instruction input to generate a pre-command signal, which may be provided in advance to the pad serial output circuit And another instruction pre-decoding is completed in the seventh clock of the instruction input for prefetching logic data, which may be provided in advance to the pad serial output circuit. In an illustrative embodiment of a QPI, instruction pre-decoding is performed in a first clock of a 4-bit instruction input to generate a pre-command signal, which may be pre-provisioned to the four pads Each circuit of the serial output circuit, the pre-finger The signal is also pre-fetched with logic data that can be provided in advance to the various circuits of the four pad serial output circuits. The fast instruction parsing can be done in the second clock of the command input sequence of the various circuits of the four pad serial output circuits, each of the four pad serial output circuits receiving the four LSBs of the command. The techniques of instruction pre-decoding, logic data prefetching, and fast instruction parsing in pad array output circuits can be used alone or in any combination to improve the timing of logic reads.

圖6繪示一快閃記憶體裝置結構的方塊示意圖，其包括邏輯讀取指令預解碼、邏輯資料預取以及在焊墊串列輸出電路中的快速指令解析。由於不同的定址、讀取以及寫入電路，快閃記憶胞陣列66可定址用於讀取以及寫入，所述電路包括列解碼電路64以及行解碼電路68，其中，行解碼電路68包括32感測放大器區塊68_1以及256位元組頁面緩衝器68_2，32感測放大器區塊68_1用以讀取快閃記憶胞陣列66，256位元組頁面緩衝器68_2用以寫入快閃記憶胞陣列66。寫入保護邏輯64_1回應於狀態暫存器42以在特定情形下防止寫入快閃記憶胞陣列66。指令和控制邏輯50控制高壓產生器56以及頁面位址閂鎖及計數器58，其中高壓產生器56以及頁面位址閂鎖及計數器58輪流控制列解碼電路64。指令和控制邏輯50也控制位元組位址閂鎖及計數器60，其輪流控制行解碼電路68。指令和控制邏輯50包括四個輸入/輸出信號線IO0~IO3、緩衝時脈輸入腳位CLK1以及芯片選擇輸入腳位CS。支援SPI和QPI，包括標準SPI指令、雙(dual)SPI指令、四元(quad)SPI 指令以及QPI指令。當使用「致能QPI(38h)」指令將所述裝置從標準/雙/四元SPI模式切換至QPI模式時，QPI操作即被支援。使用「禁能QPI(FFh)」指令可將所述裝置切回至標準/雙/四元SPI模式。6 is a block diagram showing the structure of a flash memory device, including logic read instruction pre-decoding, logic data prefetching, and fast instruction parsing in a pad array output circuit. The flash memory cell array 66 can be addressed for reading and writing due to different addressing, reading and writing circuits, including a column decoding circuit 64 and a row decoding circuit 68, wherein the row decoding circuit 68 includes 32 The sense amplifier block 68_1 and the 256-bit block page buffer 68_2, 32 sense amplifier block 68_1 are used to read the flash memory cell array 66, and the 256-bit block page buffer 68_2 is used to write the flash memory cell. Array 66. Write protection logic 64_1 is responsive to status register 42 to prevent writing to flash memory cell array 66 under certain circumstances. The instruction and control logic 50 controls the high voltage generator 56 and the page address latch and counter 58, wherein the high voltage generator 56 and the page address latch and counter 58 alternately control the column decode circuit 64. The instruction and control logic 50 also controls the byte address latch and counter 60, which in turn controls the row decode circuit 68. The instruction and control logic 50 includes four input/output signal lines IO0~IO3, a buffered clock input pin CLK1, and a chip select input pin CS. Supports SPI and QPI, including standard SPI instructions, dual SPI instructions, quad SPI Instructions and QPI instructions. QPI operation is supported when the device is switched from standard/dual/quaternary SPI mode to QPI mode using the Enable QPI (38h) command. Use the Disable QPI (FFh) command to switch the device back to standard/dual/quaternary SPI mode.

指令預解碼的實施方式可用三個指令說明，亦即信號RDSR1(05h)、RDSR2(35h)以及JEDEC(9Fh)。其可加入額外的邏輯資料以及邏輯讀取指令，舉例而言，第三狀態暫存器，但此處所描述的原則仍可應用。由於指令位元是在時脈的上升邊緣感測，所以任何指令皆可以明確地在第8個時脈的上升邊緣判斷。然而，如同圖7所繪示，信號JEDEC、RDSR1以及RDSR2指令的LSB為相同，即皆為1。因此，在這些指令中，在第7個時脈的上升邊緣可以進行明確的判斷。雖然所述8個指令位元對於所述指令解碼器仍為未知，但所述指令可由提早一個時脈週期對指令位元解析而獲得，亦即僅基於7個指令位元。此外，如同圖7所繪示，這些指令的4個最高有效位元(Most Significant Bit，MSB)是不同的。所以，在這些指令中，在第4個時脈的上升邊緣可進行明確的判斷，用以從狀態暫存器42預取資料JEDEC、SR1以及SR2。在所述4個指令位元之後的解碼操作可能不會像其他指令一般的明確，但這樣的不明確性可以基於7個位元的預解碼及/或在焊墊串列輸出電路46(繪示於圖6)執行的指令解析而解決。The implementation of the instruction pre-decoding can be illustrated by three instructions, namely signals RDSR1 (05h), RDSR2 (35h) and JEDEC (9Fh). It can add additional logic and logical read instructions, for example, a third state register, but the principles described herein are still applicable. Since the instruction bit is sensed at the rising edge of the clock, any instruction can be explicitly determined at the rising edge of the 8th clock. However, as shown in FIG. 7, the LSBs of the signals JEDEC, RDSR1, and RDSR2 are the same, that is, both are 1. Therefore, in these instructions, a clear judgment can be made on the rising edge of the seventh clock. Although the eight instruction bits are still unknown to the instruction decoder, the instructions may be obtained by parsing the instruction bits one clock cycle earlier, that is, based on only seven instruction bits. In addition, as shown in Figure 7, the four Most Significant Bits (MSBs) of these instructions are different. Therefore, in these instructions, an explicit decision can be made at the rising edge of the fourth clock to prefetch the data JEDEC, SR1, and SR2 from the state register 42. The decoding operation after the 4 instruction bits may not be as clear as other instructions, but such ambiguity may be based on pre-decoding of 7 bits and/or in the pad array output circuit 46 (painting This is solved by the instruction analysis executed in Figure 6).

圖8是具有4位元指令預解碼以及資料預取、7位元指令預解碼以及在所述焊墊串列輸出電路的指令解析的信號JEDEC、RDSR1和RDSR2指令的時序圖。圖9是繪示圖6中的快閃記憶體電路中，用於實現上述操作的詳細方塊示意圖。邏輯54的細節繪示於圖10中，焊墊串列輸出電路46的細節繪示於圖11中。8 is a letter with 4-bit instruction pre-decoding and data prefetching, 7-bit instruction pre-decoding, and instruction parsing in the pad serial output circuit Timing diagram for JEDEC, RDSR1, and RDSR2 instructions. FIG. 9 is a detailed block diagram showing the above operation in the flash memory circuit of FIG. 6. The details of logic 54 are shown in FIG. 10, and the details of pad array output circuit 46 are shown in FIG.

如圖9所示，系統時脈SCK施於焊墊串列輸出電路46，並且同時施於輸入焊墊電路48，系統時脈SCK緩衝於輸入焊墊電路48且以時脈信號CLK的身分提供。時脈信號CLK施於邏輯54以及資料暫存器52，所述資料暫存器52配置於指令和控制邏輯50(繪示於圖6)。邏輯54也接收邏輯資料，例如信號JEDEC以及來自狀態暫存器的狀態資料SR1以及SR2。邏輯54額外接收串列輸入SI。As shown in FIG. 9, the system clock SCK is applied to the pad serial output circuit 46 and simultaneously applied to the input pad circuit 48. The system clock SCK is buffered in the input pad circuit 48 and provided as the clock signal CLK. . The clock signal CLK is applied to logic 54 and data register 52, which is disposed in instruction and control logic 50 (shown in Figure 6). Logic 54 also receives logic data such as signal JEDEC and status data SR1 and SR2 from the status register. Logic 54 additionally receives the serial input SI.

如圖10繪示，邏輯54包括4位元預解碼器100，其解碼串列輸入SI的4個MSB，並且若所述4個MSB分別指示為信號RDSR1、RDSR2或JEDEC時，4位元預解碼器100觸發信號PD4_RDSR1、PD4_RDSR2或PD4_JEDEC。信號PD4_RDSR1、PD4_RDSR2以及PD4_JEDEC施於組合性邏輯102，其產生用於控制多工器104的選擇信號SELECT<1：0>。製造商和部分標識信號JEDEC以及來自狀態暫存器的狀態資料SR1和SR2以資料輸入的身分施於多工器104，這些信號的選擇是基於選擇信號SELECT<1：0>，並以預取資料信號邏輯資料LOGICDATA的身分施於焊墊串列輸出電路46(繪示於圖9)。因此，如圖8所示，在時間點A2時，邏輯資料LOGICDATA可以在第4個時脈的上升邊緣後即提供至焊墊串列輸出電路46。As shown in FIG. 10, the logic 54 includes a 4-bit pre-decoder 100 that decodes 4 MSBs of the serial input SI, and if the 4 MSBs are respectively indicated as signals RDSR1, RDSR2 or JEDEC, 4-bit pre- The decoder 100 triggers signals PD4_RDSR1, PD4_RDSR2 or PD4_JEDEC. The signals PD4_RDSR1, PD4_RDSR2, and PD4_JEDEC are applied to the combinational logic 102, which generates a selection signal SELECT<1:0> for controlling the multiplexer 104. The manufacturer and partial identification signal JEDEC and the status data SR1 and SR2 from the status register are applied to the multiplexer 104 as data inputs, and the selection of these signals is based on the selection signal SELECT<1:0> and is prefetched. The identity of the data signal logic LOGICDATA is applied to the pad serial output circuit 46 (shown in Figure 9). Therefore, as shown in FIG. 8, at time point A2, the logic data LOGICDATA can be supplied to the solder after the rising edge of the fourth clock. The pad array output circuit 46.

圖10繪示邏輯54包括7位元預解碼器106，其解碼串列輸入SI的7個MSB，並且若所述7個MSB分別指示為信號RDSR1、RDSR2或JEDEC時，7位元預解碼器106觸發信號PD7_RDSR1、PD7_RDSR2或PD7_JEDEC。信號線PD7_RDSR1、PD7_RDSR2以及PD7_JEDEC施於組合性邏輯108，其產生預指令信號PRECMD<1：0>。所述預指令信號PRECMD<1：0>可以在時間點B2(繪示於圖8)提供至焊墊串列輸出電路46，亦即緩衝時脈信號CLK的第7個時脈的上升邊緣。如圖8所示，預指令信號PRECMD<1：0>的值如同所繪示的為0及1。10 illustrates that logic 54 includes a 7-bit predecoder 106 that decodes 7 MSBs of a serial input SI, and a 7-bit predecoder if the 7 MSBs are indicated as signals RDSR1, RDSR2, or JEDEC, respectively. 106 trigger signal PD7_RDSR1, PD7_RDSR2 or PD7_JEDEC. Signal lines PD7_RDSR1, PD7_RDSR2, and PD7_JEDEC are applied to combination logic 108, which generates pre-command signals PRECMD<1:0>. The pre-command signal PRECMD<1:0> may be supplied to the pad serial output circuit 46 at time point B2 (shown in FIG. 8), that is, the rising edge of the seventh clock of the buffer clock signal CLK. As shown in FIG. 8, the values of the pre-command signals PRECMD<1:0> are 0 and 1 as shown.

如圖11所示，焊墊串列輸出電路46包括組合性邏輯110，其接收預指令信號PRECMD<1：0>以及串列輸入SI，用以在最後一個運算碼(opcode)週期中執行快速指令解析。預指令信號PRECMD<1：0>標示所述指令是否為預期的信號RDSR1、RDSR2、JEDEC或是這些指令以外的指令。組合性邏輯110組合預指令信號PRECMD<1：0>與所述指令的LSB，以解析所述指令是否確實為信號RDSR1、RDSR2或JEDEC，並且將此結果施於D型正反器112的輸入端D，用以在時間點C2(繪示於圖8)產生輸出至輸入端SET1’，亦即在第8個時脈信號CLK之後的上升邊緣。因此，當所述指令為預期的信號RDSR1、RDSR2或JEDEC，並且所述指令的LSB為1(繪示於圖7)時，信號SET1被觸發。否則，信號SET1不會被觸發。As shown in FIG. 11, the pad serial output circuit 46 includes combinational logic 110 that receives the pre-command signals PRECMD<1:0> and the serial input SI for performing fast in the last opcode cycle. Instruction parsing. The pre-command signals PRECMD<1:0> indicate whether the instructions are the expected signals RDSR1, RDSR2, JEDEC or instructions other than these instructions. The combinational logic 110 combines the pre-instruction signals PRECMD<1:0> with the LSB of the instruction to resolve whether the instruction is indeed the signal RDSR1, RDSR2 or JEDEC and applies this result to the input of the D-type flip-flop 112 The terminal D is used to generate an output to the input terminal SET1' at a time point C2 (shown in FIG. 8), that is, a rising edge after the 8th clock signal CLK. Thus, when the instruction is the expected signal RDSR1, RDSR2 or JEDEC and the LSB of the instruction is 1 (shown in Figure 7), the signal SET1 is triggered. Otherwise, the signal SET1 will not be triggered.

焊墊串列輸出電路46也包括另一D型正反器114，其在輸出端Q提供輸出致能訊號OE至輸出驅動器118。D型正反器114在其輸入端D接收信號OEIN，其用於致能陣列讀取。D型正反器114也包括輸入端SET1’以及SET，其分別接收信號SET1和RDLD。當信號SET1和RDLD皆為0時，D型正反器114的狀態以及輸出驅動器118的致能情形是由用來執行陣列讀取的信號OEIN所決定。然而，當信號SET1為1，即確認應執行邏輯讀取時，輸出致能訊號OE在時間點D2(繪示於圖8)產生，亦即在第8個指令時脈的下降邊緣產生。此時機確保來自輸出驅動器118的資料在第8個指令的時脈下降邊緣為可用的，並可預期在所述快閃記憶體裝置中用於適當的操作中。The pad serial output circuit 46 also includes another D-type flip-flop 114 that provides an output enable signal OE to the output driver 118 at the output Q. The D-type flip-flop 114 receives a signal OEIN at its input D, which is used to enable array reading. The D-type flip-flop 114 also includes an input SET1' and a SET that receive signals SET1 and RDLD, respectively. When both signals SET1 and RDLD are zero, the state of D-type flip-flop 114 and the enablement of output driver 118 are determined by the signal OEIN used to perform the array read. However, when the signal SET1 is 1, that is, it is confirmed that the logic reading should be performed, the output enable signal OE is generated at the time point D2 (shown in FIG. 8), that is, at the falling edge of the eighth instruction clock. The machine ensures that the data from the output driver 118 is available at the clock falling edge of the eighth command and can be expected to be used in the flash memory device for proper operation.

串列資料輸出信號SDOUT/和邏輯資料LOGICDATA施於多工器116的輸入端，並且在以下的方法中擇其一施於輸出驅動器118的輸入端。信號ARRAY_READ與快閃記憶胞陣列66的讀取相關，且在陣列讀取指令解碼前都不會被觸發。因此，信號ARRAY_READ預設是不會觸發的，此使得所述多工器將預設為選擇邏輯資料LOGICDATA。The serial data output signal SDOUT/ and the logic data LOGICDATA are applied to the input of the multiplexer 116, and one of the following methods is applied to the input of the output driver 118. The signal ARRAY_READ is associated with the reading of the flash memory cell array 66 and is not triggered until the array read command is decoded. Therefore, the signal ARRAY_READ is preset to be untriggered, which causes the multiplexer to be preset as the selection logic LOGICDATA.

在一些指令組中，無法基於所述指令的7個MSB作出所述指令的明確判斷。舉例而言，信號JEDEC(9Fh或是10011111)即無法基於所述7個MSB與9Eh(10011110)區隔。類似地，信號RDSR1(05h或00000101)亦無法基於所述7個MSB與04h(00000100)區隔。當無法基於所述7個MSB進行明確判斷時，將出現兩種可能的結果。In some instruction sets, an unambiguous determination of the instruction cannot be made based on the 7 MSBs of the instruction. For example, the signal JEDEC (9Fh or 10011111) cannot be separated from 9Eh (10011110) based on the 7 MSBs. Similarly, the signal RDSR1 (05h or 00000101) cannot be separated from 04h (00000100) based on the 7 MSBs. When an unambiguous determination cannot be made based on the 7 MSBs, two possible outcomes will occur.

第一個情況以指令9Eh為例。目前9Eh為無效的指令，由於輸出信號JEDEC資料不會影響所述快閃記憶體且可能會被所述裝置或系統忽略，因此從所述無效的9Eh推測信號JEDEC實務上可能不會出現問題。此外，一個精心設計的系統或裝置不應發布此種無效的指令。因此，當因無效指令產生不明確性時，此問題可忽視。儘管如此，對於所述快閃記憶體控制系統而言，理想上仍希望能避免將無效的指令誤解為有效的指令。The first case is the example of the instruction 9Eh. Currently 9Eh is an invalid instruction. Since the output signal JEDEC data does not affect the flash memory and may be ignored by the device or system, there may be no problem from the invalid 9Eh speculative signal JEDEC. In addition, a well-designed system or device should not issue such invalid instructions. Therefore, this problem can be ignored when ambiguity arises due to invalid instructions. Nonetheless, for the flash memory control system, it is desirable to avoid avoiding misinterpreting invalid instructions as valid instructions.

第二個情況以指令04h為例。在一些快閃記憶體中，目前04h為寫入禁能指令，其被發布以將所述狀態暫存器中的寫入致能閂鎖(write enable latch，WEL)位元從1重置為0。因此，以電腦程式的觀點而言，04h可以是有效的指令。然而，假若如此的指令被所述快閃記憶體控制電路誤解為信號RDSR1 05h，電腦程式將發生故障。對於接收這些無法基於其7個MSB進行明確判斷的有效指令的快閃記憶體而言，理想上希望所述快閃記憶體控制系統能夠偵測潛在的錯誤指令以及適當地處理其解碼。The second case is the command 04h. In some flash memory, currently 04h is a write disable command, which is issued to reset the write enable latch (WEL) bit in the status register from 1 to 1. 0. Therefore, from the point of view of the computer program, 04h can be a valid instruction. However, if such an instruction is misinterpreted by the flash memory control circuit as the signal RDSR1 05h, the computer program will malfunction. For flash memory that receives these valid instructions that cannot be explicitly determined based on its seven MSBs, it is desirable to have the flash memory control system be able to detect potentially erroneous instructions and properly process their decoding.

焊墊串列輸出電路46中的組合性邏輯110在以下的方法中對7位元預解碼進行模糊解析。無效指令9Eh以及寫入致能閂鎖指令04h的LSB皆包括一個0。在此情形中，組合性邏輯110的輸出端傳輸0至正反器112的輸入端D，使D型正反器112儲存0並使得輸出端Q傳輸0至正反器114的輸入端SET1’，其不覆蓋輸入端D的邏輯值。因此，輸出致能信號OE的任何觸發(assertion)由輸入端D 所控制。The combination logic 110 in the pad serial output circuit 46 performs fuzzy analysis on the 7-bit pre-decoding in the following method. Both the invalid instruction 9Eh and the LSB of the write enable latch instruction 04h include a zero. In this case, the output of the combinational logic 110 transmits 0 to the input D of the flip-flop 112, causes the D-type flip-flop 112 to store 0 and causes the output Q to transmit 0 to the input SET1' of the flip-flop 114. , which does not cover the logical value of input D. Therefore, any assertion of the output enable signal OE is made by input D Controlled.

此處描述的技術可應用於SPI或QPI介面中。圖6中所示的記憶體裝置結構可以修改為如圖12所示，用以如同QPI一般支援一位元以及多位元SPI。The techniques described herein can be applied to SPI or QPI interfaces. The memory device structure shown in FIG. 6 can be modified as shown in FIG. 12 to support one-bit and multi-bit SPI as in the case of QPI.

在一位元以及多位元SPI介面中，8位元指令以一位元的串列提供，也就是在8個時脈的各個時脈中各提供一個位元。此輸入以串列輸入SI提供。對於多位元SPI而言，圖6所示的記憶體裝置結構可修改為包括多個焊墊串列輸出電路電路，其數量等於在一時間點中控制的多個輸出位元數量，並且在每個焊墊串列輸出電路中可執行快速指令解析。預指令信號PRECMD<1：0>可以具有0、1值以致能各個焊墊串列輸出電路，用以輸出。In the one-bit and multi-bit SPI interfaces, 8-bit instructions are provided in a one-bit string, that is, one bit is provided in each of the eight clocks. This input is provided as a serial input SI. For a multi-bit SPI, the memory device structure shown in FIG. 6 can be modified to include a plurality of pad serial output circuit circuits equal in number to a plurality of output bit numbers controlled at a time point, and Fast instruction parsing can be performed in each pad serial output circuit. The pre-command signals PRECMD<1:0> may have a value of 0 and 1 to enable each pad serial output circuit for output.

在QPI介面中，8位元的指令以4位元串列提供，也就是使用兩個時脈個別傳送4個位元。對於QPI介面而言，圖6所示的記憶體結構可以修改為如圖12所示。指令和控制邏輯區塊120包括資料暫存器122以及邏輯124。焊墊串列輸出電路130、131、132以及133可以搭配分別與其連接的輸入/輸出信號線IO0、IO1、IO2以及IO3使用。此外，邏輯資料LOGICDATA的位元<4,0>、<5,1>、<6,2>以及<7,3>可以分別由邏輯124傳輸至焊墊串列輸出電路130、131、132以及133，且預指令信號PRECMD<1：0>可以由邏輯124傳輸至焊墊串列輸出電路130、131、132以及133。串列資料輸出信號SDOUT/的位元<4,0>、<5,1>、<6,2>以及<7,3>可以分別由資料暫存器122傳輸至焊墊串列輸出電路130、131、132以及133。系統時脈SCK可以傳輸至焊墊串列輸出電路130、131、132以及133。用於QPI的快速指令解析可用以下的方法執行。亦即，當信號RDSR1、RDSR2以及JEDEC的IO3至IO0分別為0101、0101以及1111(圖7)時，預指令信號PRECMD<1：0>的0、1值可用於致能焊墊串列輸出電路130、131、132以及133的輸出。In the QPI interface, 8-bit instructions are provided in 4-bit concatenation, that is, 4 bits are transmitted individually using two clocks. For the QPI interface, the memory structure shown in FIG. 6 can be modified as shown in FIG. The instruction and control logic block 120 includes a data register 122 and logic 124. The pad serial output circuits 130, 131, 132, and 133 can be used in conjunction with the input/output signal lines IO0, IO1, IO2, and IO3 respectively connected thereto. In addition, the bits <4, 0>, <5, 1>, <6, 2>, and <7, 3> of the logic data LOGICDATA may be transferred from the logic 124 to the pad serial output circuits 130, 131, 132, respectively. 133, and the pre-command signals PRECMD<1:0> may be transmitted by logic 124 to pad serial output circuits 130, 131, 132, and 133. Serial data output signal SDOUT/ bit The elements <4, 0>, <5, 1>, <6, 2>, and <7, 3> may be transmitted from the data register 122 to the pad serial output circuits 130, 131, 132, and 133, respectively. The system clock SCK can be transmitted to the pad serial output circuits 130, 131, 132, and 133. The fast instruction parsing for QPI can be performed by the following method. That is, when IO3 to IO0 of signals RDSR1, RDSR2, and JEDEC are 0101, 0101, and 1111, respectively (FIG. 7), the 0, 1 values of the pre-command signals PRECMD<1:0> can be used to enable the pad serial output. The outputs of circuits 130, 131, 132, and 133.

圖13是繪示使用4位元和7位元指令預解碼進行邏輯資料讀取操作的概括流程圖140。系統時脈SCK緩衝於輸入焊墊電路48以提供緩衝的時脈信號CLK至邏輯54以及資料暫存器52(步驟141)。在4個時脈信號CLK控制進入指令的4個MSB，且所述4個MSB被邏輯54預解碼(步驟142)之後，在邏輯54中根據在所述4個位元中預解碼的邏輯讀取指令(例如信號JEDEC或是狀態暫存器中的狀態資料SR1或SR2)預取邏輯資料(步驟143)。所述預取邏輯資料在第8個系統時脈SCK時脈之前提供至焊墊串列輸出電路46(步驟144)。在7個時脈信號CLK控制進入指令的7個MSB，且在邏輯54中被預解碼以產生預指令信號(步驟145)之後，提供所述預指令信號至焊墊串列輸出電路46(步驟146)。所述預指令信號與在焊墊串列輸出電路46中，用於快速指令解析的LSB(在第8個系統時脈SCK的上升邊緣)結合，以解決預解碼指令的模糊性(步驟147)。假若所述指令不為邏輯讀取指令(步驟148中的否)，不進行邏輯資料讀取而繼續記憶體操作(步驟150)。假若所述指令為邏輯讀取指令(步驟148中的是)，所述預取邏輯資料在第8個系統時脈SCK的下降邊緣被選擇，且由系統時脈SCK控制的焊墊串列輸出電路46輸出(步驟149)。13 is a generalized flow diagram 140 showing logical data read operations using 4-bit and 7-bit instruction pre-decoding. The system clock SCK is buffered in the input pad circuit 48 to provide the buffered clock signal CLK to logic 54 and data register 52 (step 141). After the four clock signals CLK control the four MSBs entering the instruction, and the four MSBs are pre-decoded by the logic 54 (step 142), the logic reads in the logic 54 based on the pre-decoding in the four bits. The instruction fetch (e.g., signal JEDEC or status data SR1 or SR2 in the status register) prefetches the logic data (step 143). The prefetch logic is provided to the pad serial output circuit 46 prior to the eighth system clock SCK clock (step 144). After the seven clock signals CLK control the 7 MSBs of the incoming command and are pre-decoded in logic 54 to generate the pre-command signals (step 145), the pre-command signals are provided to the pad serial output circuit 46 (steps) 146). The pre-command signal is combined with the LSB (in the rising edge of the eighth system clock SCK) for fast instruction parsing in the pad serial output circuit 46 to account for the ambiguity of the pre-decode instruction (step 147) . If the instruction is not a logical read instruction (No in step 148), The memory operation is continued without logical data reading (step 150). If the instruction is a logical read instruction (YES in step 148), the prefetch logic is selected at the falling edge of the eighth system clock SCK, and the pad serial output controlled by the system clock SCK Circuit 46 outputs (step 149).

有利的是，邏輯資料、SR1資料以及SR2資料的其中之一可在第4個時脈即預取，因此即使在邏輯54中執行多工，所述的選定資料仍具有充足的時間被處理為對於在焊墊串列輸出電路46中的多工器116是可用的。有利的是，邏輯資料可在焊墊串列輸出電路46中的多工器116進行多工，且由多工器116直接提供至輸出驅動器118，因而避免信號線及其他傳輸和閘延遲。有利的是，包括多工器116以及輸出驅動器118的焊墊串列輸出電路46可由系統時脈SCK控制，因而避免時脈緩衝延遲。有利的是，解碼模糊性可在焊墊串列輸出電路46中的組合性邏輯110的系統時脈SCK的上升邊緣解決，使得除非所述指令被解析為邏輯讀取指令，否則任何在邏輯讀取指令中被預取的資料皆不會選為輸出驅動器118的輸入。Advantageously, one of the logical data, the SR1 data, and the SR2 data can be prefetched at the 4th clock, so even if multiplex is performed in logic 54, the selected data has sufficient time to be processed as It is available to the multiplexer 116 in the pad serial output circuit 46. Advantageously, the logic data can be multiplexed in the multiplexer 116 in the pad serial output circuit 46 and provided directly by the multiplexer 116 to the output driver 118, thereby avoiding signal lines and other transmission and gate delays. Advantageously, the pad serial output circuit 46, including the multiplexer 116 and the output driver 118, can be controlled by the system clock SCK, thereby avoiding clock buffering delays. Advantageously, the decoding ambiguity can be resolved at the rising edge of the system clock SCK of the combinational logic 110 in the pad serial output circuit 46 such that any logical read is performed unless the instruction is parsed as a logical read instruction The prefetched data in the instruction fetch is not selected as the input to the output driver 118.

圖14繪示使用7位元指令預解碼的邏輯資料讀取操作的概括流程圖160。系統時脈SCK緩衝於輸入焊墊電路48中以提供緩衝的時脈信號CLK至邏輯54以及資料暫存器52(步驟161)。在7個時脈信號CLK控制進入指令的7個MSB，且所述7個MSB被邏輯54預解碼以產生預指令信號(步驟162)之後，將所述預指令信號提供至焊墊串列輸出電路46(步驟163)。此外，邏輯資料(例如信號JEDEC 或是狀態暫存器中的狀態資料SR1或SR2)在邏輯54中被預取，此是根據在所述7個位元中預解碼出哪個邏輯讀取指令(步驟164)，並將所述邏輯資料提供至焊墊串列輸出電路46(步驟165)。所述預指令信號與在焊墊串列輸出電路46中，用於快速指令解析的LSB(在第8個系統時脈SCK的上升邊緣)結合，以解決預解碼指令的模糊性(步驟166)。若所述指令不為邏輯讀取指令(步驟167中的否)，不進行邏輯資料讀取而繼續記憶體操作(步驟169)。假若所述指令為邏輯讀取指令(步驟167中的是)，所述預取邏輯資料在第8個系統時脈SCK的下降邊緣被選擇，且由系統時脈SCK控制的焊墊串列輸出電路46輸出(步驟168)。14 depicts a general flow diagram 160 of a logical data read operation using a 7-bit instruction pre-decode. The system clock SCK is buffered in input pad circuit 48 to provide buffered clock signal CLK to logic 54 and data register 52 (step 161). After the seven clock signals CLK control the 7 MSBs entering the command, and the 7 MSBs are pre-decoded by the logic 54 to generate the pre-command signals (step 162), the pre-command signals are provided to the pad serial output. Circuit 46 (step 163). In addition, logic data (such as signal JEDEC Or the status data SR1 or SR2 in the status register is prefetched in logic 54, based on which logical read instruction was pre-decoded in the 7 bits (step 164), and The logic data is provided to the pad serial output circuit 46 (step 165). The pre-command signal is combined with the LSB (in the rising edge of the eighth system clock SCK) for fast instruction parsing in the pad serial output circuit 46 to account for the ambiguity of the pre-decode instruction (step 166) . If the instruction is not a logical read instruction (NO in step 167), the memory operation is continued without performing the logic data reading (step 169). If the instruction is a logical read instruction (YES in step 167), the prefetch logic is selected at the falling edge of the eighth system clock SCK, and the pad serial output controlled by the system clock SCK Circuit 46 outputs (step 168).

本發明的描述，包括所提出的優點及其應用僅用以說明，此說明並非用以限定本發明，故本發明之保護範圍當視申請專利範圍所界定者為準。在此所揭露之實施例可能改變及修改，任何所屬技術領域中具有通常知識者研讀本專利文件之後將明瞭該些實施例的各種元件之實際替換及等效。除非另有界定，否則在此所給予的特定數值僅用以說明，其可依需求而變化。其中，本發明所提出的各個時間點除非另有明確界定，否則皆非確切時間點，且將隨著電路佈局、信號線阻抗、以及本領域熟知的其他實際設計因素而變化。所參考之某一範圍的各種數值將包括此範圍內的所有數值。在不脫離本發明之範圍內，當可進行在此所揭露之實施例的這些及其他改變及修改，包含該些實施例的各種元件之替換及等效。The description of the present invention, including the advantages and the application thereof, are intended to be illustrative only, and the description is not intended to limit the invention, and the scope of the invention is defined by the scope of the claims. The embodiments disclosed herein may be changed and modified, and the actual replacement and equivalents of the various elements of the embodiments will be apparent to those skilled in the art. The specific numerical values given herein are for illustrative purposes only, and may vary as needed. Here, the various points in time proposed by the present invention are not exact time points unless otherwise explicitly defined, and will vary with circuit layout, signal line impedance, and other practical design factors well known in the art. Various values in a range that are referenced will include all values within the range. These and other variations and modifications of the embodiments disclosed herein may be made without departing from the scope of the invention.

2、109‧‧‧主陣列感測放大器2, 109‧‧‧ main array sense amplifier

4、25、107‧‧‧暫存器4, 25, 107‧‧‧ register

10、48、134‧‧‧輸入焊墊電路10, 48, 134‧‧‧ Input pad circuit

12、54、124‧‧‧邏輯12, 54, 124‧‧ ‧ Logic

14、52、122‧‧‧資料暫存器14, 52, 122‧‧‧ data registers

16、46、130、131、132、133‧‧‧焊墊串列輸出電路16, 46, 130, 131, 132, 133‧‧‧ solder pad serial output circuit

24、102、108、110‧‧‧組合性邏輯24, 102, 108, 110‧‧‧ combinational logic

26、104、116‧‧‧多工器26, 104, 116‧‧‧ multiplexers

32、112、114‧‧‧D型正反器32, 112, 114‧‧‧D type flip-flops

34、118‧‧‧輸出驅動器34, 118‧‧‧ Output Driver

40‧‧‧寫入控制邏輯40‧‧‧Write Control Logic

42‧‧‧狀態暫存器42‧‧‧Status register

50、120‧‧‧指令和控制邏輯50, 120‧‧‧ instruction and control logic

56‧‧‧高壓產生器56‧‧‧High voltage generator

58‧‧‧頁面位址閂鎖及計數器58‧‧‧Page address latch and counter

60‧‧‧位元組位址閂鎖及計數器60‧‧‧-byte address latches and counters

62‧‧‧安全暫存器62‧‧‧secure register

64‧‧‧列解碼電路64‧‧‧ column decoding circuit

64_1‧‧‧寫入保護邏輯64_1‧‧‧Write protection logic

66‧‧‧快閃記憶胞陣列66‧‧‧Flash memory cell array

68‧‧‧行解碼電路68‧‧‧ line decoding circuit

68_1‧‧‧256位元組頁面緩衝器68_1‧‧‧256 byte page buffer

68_2‧‧‧32感測放大器區塊68_2‧‧‧32 sense amplifier block

100‧‧‧4位元預解碼器100‧‧‧4-ary predecoder

106‧‧‧7位元預解碼器106‧‧7-bit predecoder

140、160‧‧‧流程圖140, 160‧‧‧ Flowchart

141~150、161~169‧‧‧步驟141~150, 161~169‧‧‧ steps

ARRAYDATA‧‧‧陣列資料ARRAYDATA‧‧‧Array data

A1、B1、C1、D1、E1、F1‧‧‧箭號A1, B1, C1, D1, E1, F1‧‧‧ arrows

A2、B2、C2、D2‧‧‧時間點A2, B2, C2, D2‧‧‧ points

CLK‧‧‧時脈信號CLK‧‧‧ clock signal

CLK1、CLK’‧‧‧緩衝時脈輸入腳位CLK1, CLK'‧‧‧ buffer clock input pin

CS‧‧‧芯片選擇輸入腳位CS‧‧‧chip selection input pin

D、SET、SET1’‧‧‧輸入端D, SET, SET1'‧‧‧ input

IO0、IO1、IO2、IO3‧‧‧輸入/輸出信號線IO0, IO1, IO2, IO3‧‧‧ input/output signal lines

JEDEC、RDSR1、RDSR2、RDLD、OEIN、PD4_RDSR1、PD4_RDSR2、PD4_JEDEC、PD7_RDSR1、PD7_RDSR2、PD7_JEDEC、SET1、ARRAY_READ‧‧‧信號JEDEC, RDSR1, RDSR2, RDLD, OEIN, PD4_RDSR1, PD4_RDSR2, PD4_JEDEC, PD7_RDSR1, PD7_RDSR2, PD7_JEDEC, SET1, ARRAY_READ‧‧‧ signals

JEDECID、SR1、SR2‧‧‧資料JEDECID, SR1, SR2‧‧‧ data

LOGICDATA‧‧‧邏輯資料LOGICDATA‧‧‧Logical Information

OE‧‧‧輸出致能信號OE‧‧‧ output enable signal

PRECMD<1：0>‧‧‧預指令信號PRECMD<1:0>‧‧‧ pre-command signal

Q‧‧‧輸出端Q‧‧‧output

SI‧‧‧串列輸入SI‧‧‧serial input

SDOUT/‧‧‧串列資料輸出信號SDOUT/‧‧‧Listed data output signal

SCK‧‧‧系統時脈SCK‧‧‧ system clock

SCK’‧‧‧系統時脈輸入腳位SCK’‧‧‧ system clock input pin

SELECT<1：0>‧‧‧選擇信號SELECT<1:0>‧‧‧Selection signal

圖1是習知技術中一種快閃記憶體裝置的焊墊、邏輯以及資料暫存器電路的方塊示意圖。1 is a block diagram of a pad, logic, and data register circuit of a flash memory device in the prior art.

圖2是圖1中的邏輯電路的細部方塊示意圖。2 is a detailed block diagram of the logic circuit of FIG. 1.

圖3是圖1中的焊墊輸出電路的細部方塊示意圖。3 is a detailed block diagram of the pad output circuit of FIG. 1.

圖4是繪示圖1中的快閃記憶體裝置的失效情形的時序圖。4 is a timing diagram showing a failure condition of the flash memory device of FIG. 1.

圖5是繪示圖4的時序圖的部分的細部時序圖。FIG. 5 is a detailed timing chart showing a portion of the timing chart of FIG. 4. FIG.

圖6是一種包括指令預解碼及資料預取的快閃記憶體架構的電路示意圖。6 is a circuit diagram of a flash memory architecture including instruction pre-decoding and data prefetching.

圖7是繪示不同的邏輯讀取指令的數位表示法的示意圖。Figure 7 is a schematic diagram showing the digital representation of different logical read instructions.

圖8是繪示包括於圖6中的快閃記憶體的操作的不同信號的時序圖。FIG. 8 is a timing diagram showing different signals of the operation of the flash memory included in FIG. 6.

圖9是圖6中的快閃記憶體裝置的焊墊、邏輯以及資料暫存器電路的方塊示意圖。9 is a block diagram of the pad, logic, and data register circuit of the flash memory device of FIG. 6.

圖10是圖9中的邏輯電路的細部方塊示意圖。Figure 10 is a detailed block diagram of the logic circuit of Figure 9.

圖11是圖9中的焊墊輸出電路的細部方塊示意圖。Figure 11 is a detailed block diagram of the pad output circuit of Figure 9.

圖12是一種包括用於QPI模式中的指令預解碼及資料預取的快閃記憶體架構的部分電路示意圖。12 is a partial circuit diagram of a flash memory architecture including instruction pre-decoding and data prefetching in QPI mode.

圖13是概述圖6的快閃記憶體裝置的操作中，使用指令預解碼以及邏輯資料預取進行邏輯資料讀取的流程圖。Figure 13 is a flow chart summarizing the logic data reading using instruction pre-decoding and logical data prefetching in the operation of the flash memory device of Figure 6.

圖14是概述快閃記憶體裝置的操作中，僅使用7位元指令預解碼以及邏輯資料預取進行邏輯資料讀取的流程圖。Figure 14 is a flow chart outlining the operation of the flash memory device, using only 7-bit instruction pre-decoding and logical data prefetching for logical data reading.

140‧‧‧流程圖140‧‧‧Flowchart

141~150‧‧‧步驟141~150‧‧‧Steps

Claims

一種快閃記憶體，其具有可回應於一組邏輯讀取指令而輸出邏輯資料的能力，包括：外部信號輸入端；可定址快閃記憶胞陣列；資料暫存器，耦接於該可定址快閃記憶胞陣列，用以接收並儲存來自於該可定址快閃記憶胞陣列的陣列資料；多數個暫存器，用以儲存邏輯資料；指令和控制邏輯電路，包括：預取邏輯(pre-fetch logic)，耦接於該外部信號輸入端，用以當該外部信號輸入端接收指令的最高有效位元的第一部分序列為預測的特定邏輯資料讀取指令時，依據該些邏輯讀取指令的特定其中之一，從該些邏輯資料暫存器的其中之一預取邏輯資料；輸出控制邏輯，耦接於該外部信號輸入端，用以當該外部信號輸入端接收指令的最高有效位元的第二部分序列為預測的該些多數個邏輯資料讀取指令的任意其中之一時，產生預測的邏輯讀取指令信號；以及輸出焊墊電路，耦接於該資料暫存器、該預取邏輯、該輸出控制邏輯以及該外部信號接收端，用以當該預測的邏輯讀取指令信號以及除了該第一部分序列及該第二部分序列之外的部分指令解析收到的該些邏輯資料讀取指令的任意其中之一時，選擇及輸出來自該預取邏輯的邏輯資料。 A flash memory having the ability to output logic data in response to a set of logical read commands, comprising: an external signal input; an addressable flash memory cell array; a data register coupled to the addressable a flash memory cell array for receiving and storing array data from the addressable flash memory cell array; a plurality of registers for storing logic data; instruction and control logic circuits, including: prefetch logic (pre -fetch logic), coupled to the external signal input terminal, when the first signal sequence of the most significant bit of the instruction received by the external signal input terminal is a predicted specific logic data read instruction, and is read according to the logic One of the specific instructions, prefetching logic data from one of the logic data registers; and output control logic coupled to the external signal input terminal for receiving the most effective command when the external signal input terminal receives The second partial sequence of the bit is any one of the predicted plurality of logical data read instructions, and the predicted logical read command signal is generated; and the output a pad circuit coupled to the data register, the prefetch logic, the output control logic, and the external signal receiving end for reading the command signal and the first partial sequence and the second portion when the predicted logic When a part of the instructions other than the sequence parses any one of the received logical data read instructions, the logical data from the prefetch logic is selected and output.

如申請專利範圍第1項所述之快閃記憶體，其中：該外部信號輸入端配置於串列週邊介面協定(serial peripheral interface，SPI)，並包括串列輸入信號線；以及該輸出焊墊電路配置於該串列週邊介面協定，並包括串列資料輸出線。 For example, the flash memory described in claim 1 of the patent scope, wherein: The external signal input end is disposed in a serial peripheral interface (SPI) and includes a serial input signal line; and the output pad circuit is disposed in the serial peripheral interface protocol, and includes a serial data output line .

如申請專利範圍第1項所述之快閃記憶體，其中：該外部信號輸入端配置於四元週邊介面協定(quad peripheral interface，QPI)，並且包括第一串列輸入/輸出信號線、第二串列輸入/輸出信號線、第三串列輸入/輸出信號線以及第四串列輸入/輸出信號線；以及該輸出焊墊電路配置於該四元週邊介面協定，並且包括第一一位元焊墊輸出電路，其耦接於該第一串列輸入/輸出信號線、第二一位元焊墊輸出電路，其耦接於該第二串列輸入/輸出信號線、第三一位元焊墊輸出電路，其耦接於該第三串列輸入/輸出信號線以及第四一位元焊墊輸出電路，其耦接於該第四串列輸入/輸出信號線。 The flash memory according to claim 1, wherein the external signal input terminal is disposed in a quad-peripheral interface (QPI), and includes a first serial input/output signal line, a two-column input/output signal line, a third serial input/output signal line, and a fourth serial input/output signal line; and the output pad circuit is disposed in the quaternary peripheral interface protocol and includes the first bit The first pad input/output signal line and the second one-bit pad output circuit are coupled to the second serial input/output signal line and the third bit. And a fourth serial input/output signal line coupled to the fourth serial input/output signal line.

如申請專利範圍第1項所述之快閃記憶體，其中該第一以及該第二部分序列的最高有效位元為7位元。 The flash memory of claim 1, wherein the most significant bit of the first and second partial sequences is 7 bits.

如申請專利範圍第4項所述之快閃記憶體，其中：該外部信號輸入端配置於串列週邊介面協定，並且包括串列輸入信號線；以及該輸出焊墊電路配置於該串列週邊介面協定，並且包括串列資料輸出線。 The flash memory as described in claim 4, wherein: the external signal input end is disposed in the serial peripheral interface protocol, and includes a serial input signal line; and the output pad circuit is disposed in the series periphery Interface protocol and includes serial data output lines.

如申請專利範圍第1項所述之快閃記憶體，其中：最高有效位元的該第一部分序列為4位元；以及最高有效位元的該第二部分序列為7位元。 The flash memory of claim 1, wherein: the first partial sequence of the most significant bit is 4 bits; The second partial sequence of the most significant bits is 7 bits.

如申請專利範圍第6項所述之快閃記憶體，其中：該外部信號輸入端配置於四元週邊介面協定，並且包括第一串列輸入/輸出信號線、第二串列輸入/輸出信號線、第三串列輸入/輸出信號線以及第四串列輸入/輸出信號線；以及該輸出焊墊電路配置於該四元週邊介面協定，並且包括第一一位元焊墊輸出電路，其耦接於該第一串列輸入/輸出信號線、第二一位元焊墊輸出電路，其耦接於該第二串列輸入/輸出信號線、第三一位元焊墊輸出電路，其耦接於該第三串列輸入/輸出信號線以及第四一位元焊墊輸出電路，其耦接於該第四串列輸入/輸出信號線。 The flash memory of claim 6, wherein the external signal input terminal is disposed in a quaternary peripheral interface protocol, and includes a first serial input/output signal line and a second serial input/output signal. a line, a third serial input/output signal line, and a fourth serial input/output signal line; and the output pad circuit is disposed in the quaternary peripheral interface protocol, and includes a first one-bit pad output circuit, The first serial input/output signal line and the second one-bit pad output circuit are coupled to the second serial input/output signal line and the third one-bit pad output circuit. The third serial input/output signal line and the fourth one-bit pad output circuit are coupled to the fourth serial input/output signal line.

如申請專利範圍第1項所述之快閃記憶體，更包括：系統時脈輸入信號線，耦接於該輸出焊墊電路；以及輸入焊墊電路，耦接於該系統時脈，用以提供緩衝的時脈信號至該預取邏輯、該輸出控制邏輯以及該資料暫存器。 The flash memory of claim 1, further comprising: a system clock input signal line coupled to the output pad circuit; and an input pad circuit coupled to the system clock for A buffered clock signal is provided to the prefetch logic, the output control logic, and the data register.

一種操作記憶體裝置的方法，該記憶體裝置具有快閃記憶胞陣列，用以回應於具有預定指令位元數量的邏輯讀取指令，以提供邏輯資料至應用程式，該方法包括：接收位元數少於預定指令位元數量的指令的位元序列，該些接收的位元序列為該指令的多個最高有效位元；在該記憶體裝置的邏輯電路中對該接收的位元序列預解碼(pre-decoding)，以判別該接收位元序列是否匹配對應的邏輯讀取指令的位元序列；在焊墊輸出電路中完成對該指令其餘位元的解碼，以判別在該預解碼的步驟中的匹配是否正確地預測該邏輯讀取指令；以及依據該邏輯讀取指令輸出邏輯資料。 A method of operating a memory device, the memory device having a flash memory cell array responsive to a logical read instruction having a predetermined number of instruction bits to provide logic data to an application, the method comprising: receiving a bit a sequence of bits of instructions less than a predetermined number of instruction bits, the received sequence of bits being a plurality of most significant bits of the instruction; the sequence of received bits in the logic circuit of the memory device Pre-decoding to determine whether the received bit sequence matches the bit sequence of the corresponding logical read command; decoding the remaining bits of the instruction in the pad output circuit to determine the pre-decode Whether the matching in the step correctly predicts the logical read instruction; and outputs the logical data according to the logical read instruction.

一種操作記憶體裝置的方法，該記憶體裝置具有快閃記憶胞陣列，用以回應於具有預定指令位元數量的邏輯讀取指令，以提供邏輯資料至應用程式，該方法包括：接收位元數少於預定指令位元數量的指令的第一位元序列，該些接收的第一位元序列為該指令的多個最高有效位元；在該記憶體裝置的邏輯電路中對該接收的第一位元序列預解碼，以判別該接收的第一位元序列是否匹配對應的邏輯讀取指令的位元序列；依據在該預解碼步驟中匹配的該邏輯讀取指令來預取邏輯資料；接收位元數少於預定指令位元數量但多於該第一位元序列的指令的第二位元序列，該些接收的第二位元序列為該指令的多個最高有效位元；在該記憶體裝置的邏輯電路中對該接收的第二位元序列預解碼，以判別該接收的第二位元序列是否匹配對應的邏輯讀取指令的位元序列；在焊墊輸出電路中完成對該指令其餘位元的解碼，以判別在該第二位元序列預解碼的步驟中的匹配是否正確地預測該邏輯讀取指令；以及輸出在該預取步驟中所預取的邏輯資料。 A method of operating a memory device, the memory device having a flash memory cell array responsive to a logical read instruction having a predetermined number of instruction bits to provide logic data to an application, the method comprising: receiving a bit a first bit sequence of instructions less than a predetermined number of instruction bits, the received first bit sequence being a plurality of most significant bits of the instruction; the received in the logic circuit of the memory device The first bit sequence is pre-decoded to determine whether the received first bit sequence matches the bit sequence of the corresponding logical read instruction; prefetching the logical data according to the logical read instruction matched in the pre-decoding step Receiving a second bit sequence of instructions having less than a predetermined number of instruction bits but more than the first bit sequence, the received second bit sequence being a plurality of most significant bits of the instruction; Pre-decoding the received second bit sequence in a logic circuit of the memory device to determine whether the received second bit sequence matches a bit sequence of a corresponding logical read command; Decoding the remaining bits of the complete command output circuit to Determining whether the matching in the step of precoding the second bit sequence correctly predicts the logical read instruction; and outputting the logical data prefetched in the prefetching step.

如申請專利範圍第10項所述之方法，其中該第一位元序列以及該第二位元序列為該指令的7個最高有效位元。 The method of claim 10, wherein the first bit sequence and the second bit sequence are the 7 most significant bits of the instruction.

如申請專利範圍第10項所述之方法，其中：該第一位元序列為該指令的4個最高有效位元；以及該第二位元序列為該指令7個最高有效位元。The method of claim 10, wherein: the first bit sequence is the 4 most significant bits of the instruction; and the second bit sequence is the 7 most significant bits of the instruction.