TWI499217B - Prescaler of divide-by-7 with a high division-ratio and phase-locked loop system using the same - Google Patents
Prescaler of divide-by-7 with a high division-ratio and phase-locked loop system using the same Download PDFInfo
- Publication number
- TWI499217B TWI499217B TW101148040A TW101148040A TWI499217B TW I499217 B TWI499217 B TW I499217B TW 101148040 A TW101148040 A TW 101148040A TW 101148040 A TW101148040 A TW 101148040A TW I499217 B TWI499217 B TW I499217B
- Authority
- TW
- Taiwan
- Prior art keywords
- frequency
- signal
- phase
- locked loop
- divide
- Prior art date
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
本發明係關於鎖相迴路之技術領域,尤指一種高除數除7預除器及使用該高除數除7預除器之鎖相迴路系統。The invention relates to the technical field of a phase-locked loop, in particular to a high divisor division 7 pre-discharger and a phase-locked loop system using the high divisor division and 7 pre-discharger.
從1到6 GHz的頻率頻譜容納當前的無線標準和絕大多數的應用程式。而低成本射頻(RF)元件和成熟的積體電路(IC)技術,使得無線接收/傳送系統快速發展。The frequency spectrum from 1 to 6 GHz accommodates current wireless standards and most applications. Low-cost radio frequency (RF) components and sophisticated integrated circuit (IC) technology have led to the rapid development of wireless receive/transmit systems.
在大多數的無線接收/傳送系統中,鎖相迴路是一個重要的元件。而於無線接收/傳送系統中,設計一可提供電視接收器、WiMax接收器等廣泛適應性鎖相迴路是一種艱鉅的挑戰。對鎖相迴路的每一輸出頻率,鎖相迴路的參數(例如:輸入訊號的頻率、乘法因數等)必須精確調整以使相位雜訊(phase noise)減至最小並維持鎖相迴路的穩定。In most wireless receive/transmit systems, the phase-locked loop is an important component. In the wireless receiving/transmitting system, designing a wide range of adaptive phase-locked loops such as TV receivers and WiMax receivers is a daunting challenge. For each output frequency of the phase-locked loop, the parameters of the phase-locked loop (eg, the frequency of the input signal, the multiplication factor, etc.) must be precisely adjusted to minimize phase noise and maintain the stability of the phase-locked loop.
圖1係一習知鎖相迴路100的方塊圖,其包含一相位檢測器(Phase Detector)110、一電荷泵(Charge Pump)120、一濾波器130、一電壓控制振盪器(VCO)140、及一除頻裝置150。當鎖相迴路100鎖定時,該鎖相迴路100所產生訊號CKOUT 的頻率為參考訊號CKREF 的頻率之N倍。1 is a block diagram of a conventional phase-locked loop 100, including a phase detector (Detect Detector) 110, a charge pump 120, a filter 130, a voltage controlled oscillator (VCO) 140, and a Frequency dividing device 150. When the phase locked loop 100 is locked, the frequency of the signal CK OUT generated by the phase locked loop 100 is N times the frequency of the reference signal CK REF .
鎖相迴路100常工作在不同的頻率。其工作頻率在超過GHz頻率時,該除頻裝置150一般分成第一階段預除器151及後段除頻器153。電壓控制振盪器和第一階段預除器被稱 為鎖相迴路100的前端,因其在最高頻率工作,因此是最具有挑戰性的元件。Phase-locked loop 100 often operates at different frequencies. When the operating frequency exceeds the GHz frequency, the frequency dividing device 150 is generally divided into a first stage pre-processor 151 and a rear stage frequency divider 153. The voltage controlled oscillator and the first stage prescaler are called The front end of the phase-locked loop 100 is the most challenging component because it operates at the highest frequency.
預除器可分為數位式、類比式、及混合數位及類比式。數位式又可分為靜態頻率除頻器(static frequency divider,SFD)及動態頻率除頻器(dynamic frequency divider,DFD)。混合數位及類比式則為行波頻率除頻器(travelling wave frequency divider)。類比式可分為再生除頻器(regenerative frequency divider)及注入鎖定除頻器(injection locked frequency divider,ILFD)。The pre-processor can be divided into digital, analog, and mixed digits and analogs. The digital type can be further divided into a static frequency divider (SFD) and a dynamic frequency divider (DFD). The mixed digit and analogy are the traveling wave frequency divider. The analogy can be divided into a regenerative frequency divider and an injection locked frequency divider (ILFD).
在鎖相迴路中,預除器是除頻裝置的第一階段。當鎖相迴路的輸出訊號的頻率低時,預除器的設計相當直接且簡單。然而,當鎖相迴路的輸出訊號的頻率超過GHz,甚至高達60GHz時,預除器一般使用注入鎖定除頻器(ILFD)。在釐米波長(millimeter wave,mm-wave)的應用中,已有除2預除器及除3預除器。然而由於除數較低,其輸出頻率仍高,例如:在60GHz應用中,一除2預除器的輸出訊號的頻率仍高達30GHz,增加後段除頻器153的設計難度。因此,本發明提出一種高除數除7預除器及使用該高除數除7預除器之鎖相迴路系統。In the phase-locked loop, the pre-discharger is the first stage of the frequency division device. When the frequency of the output signal of the phase-locked loop is low, the design of the pre-processor is quite straightforward and simple. However, when the frequency of the output signal of the phase-locked loop exceeds GHz, even up to 60 GHz, the pre-discharger typically uses an injection-locked frequency divider (ILFD). In the application of millimeter wave (mm-wave), there are two pre-dividers and three pre-dividers. However, due to the lower divisor, the output frequency is still high. For example, in a 60 GHz application, the frequency of the output signal of a divide-by-2 pre-divider is still as high as 30 GHz, which increases the design difficulty of the rear-stage frequency divider 153. Accordingly, the present invention provides a high divisor divide-by-seven pre-discharger and a phase-locked loop system using the high divisor divide-by-seven pre-discharger.
本發明之主要目的係在提供一種高除數除7預除器及使用該高除數除7預除器之鎖相迴路系統,可更快達到較低頻帶,進而減少整體電路所使用到的除頻器級數,亦可因 為除頻器級數之減少,可減少電路複雜度,同時降低任何可能經由供應電壓端所饋入電路之耦合雜訊,也能使鎖定頻率範圍可有效增加。The main object of the present invention is to provide a high divisor division 7 pre-discharger and a phase-locked loop system using the high divisor division and 7 pre-discharger, which can reach a lower frequency band faster, thereby reducing the use of the overall circuit. Frequency divider stage, but also due to As the number of stages of the frequency divider is reduced, the circuit complexity can be reduced, and any coupling noise that may be fed into the circuit via the supply voltage terminal can be reduced, and the locked frequency range can be effectively increased.
依據本發明之一特色,本發明提出一種高除數除7預除器,包括一注入式電晶體組、一環形振盪器、及一輸出緩衝級電路。該注入式電晶體組將一注入訊號混成一高頻率訊號及一低頻率訊號。該環形振盪器連接至該注入式電晶體組,保留該低頻率訊號,同時抑制該高頻率訊號。該輸出緩衝級電路連接至該環形振盪器,以將保留該低頻率訊號能量逐漸增加,而產生一除頻訊號,其中,該注入訊號的頻率為該除頻訊號的頻率之7倍。According to a feature of the present invention, the present invention provides a high divisor divide-by-seven pre-discharger comprising an injection transistor group, a ring oscillator, and an output buffer stage circuit. The injection transistor group mixes an injection signal into a high frequency signal and a low frequency signal. The ring oscillator is coupled to the injection transistor group to retain the low frequency signal while suppressing the high frequency signal. The output buffer stage circuit is coupled to the ring oscillator to gradually increase the energy of the low frequency signal to generate a frequency division signal, wherein the frequency of the injection signal is 7 times the frequency of the frequency division signal.
依據本發明之另一特色,本發明提出一種鎖相迴路系統,包括一檢測器、一電荷泵、一濾波器、一可控式振盪器、一高除數除7預除器、及一除頻裝置。該檢測器係依據一輸入訊號與一反饋訊號之邏輯位準值的差異,進而產生一檢測訊號。該電荷泵耦合於該檢測器,以依據該檢測訊號而產生一控制訊號。該濾波器耦合於該電荷泵,以依據該控制訊號而產生一調整訊號。該可控式振盪器耦合於該濾波器,以依據該調整訊號,進而產生一差動輸出訊號。該高除數除7預除器耦合於該可控式振盪器,用以將該差動輸出訊號除頻,以產生一除頻訊號。該除頻裝置耦合於該高除數除7預除器,以依據該除頻訊號而產生該反饋訊號。According to another feature of the present invention, the present invention provides a phase locked loop system including a detector, a charge pump, a filter, a controllable oscillator, a high divisor division 7 prescaler, and a divide Frequency device. The detector generates a detection signal according to the difference between the logic level values of an input signal and a feedback signal. The charge pump is coupled to the detector to generate a control signal based on the detection signal. The filter is coupled to the charge pump to generate an adjustment signal based on the control signal. The controllable oscillator is coupled to the filter to generate a differential output signal based on the adjusted signal. The high divisor divide-by-seven preprocessor is coupled to the controllable oscillator for dividing the differential output signal to generate a divisor signal. The frequency dividing device is coupled to the high divisor dividing 7 pre-divider to generate the feedback signal according to the frequency dividing signal.
圖2係本發明之鎖相迴路系統200的方塊圖,包括一檢測器210、一電荷泵220、一濾波器230、一可控式振盪器240、一高除數除7預除器250、及一除頻裝置260。2 is a block diagram of a phase locked loop system 200 of the present invention, including a detector 210, a charge pump 220, a filter 230, a controllable oscillator 240, a high divisor divide and 7 prescaler 250, And a frequency dividing device 260.
該檢測器210係依據一輸入訊號CKREF 與一反饋訊號CKFB 之邏輯位準值的差異,進而產生一檢測訊號UP、DN。The detector 210 generates a detection signal UP, DN according to the difference between the logic level values of an input signal CK REF and a feedback signal CK FB .
該電荷泵220耦合於該檢測器210,以依據該檢測訊號UP、DN而產生一控制訊號Vctrl。The charge pump 220 is coupled to the detector 210 to generate a control signal Vctrl according to the detection signals UP and DN.
該濾波器230耦合於該電荷泵220,以依據該控制訊號Vctrl而產生一調整訊號Vfilter。The filter 230 is coupled to the charge pump 220 to generate an adjustment signal Vfilter according to the control signal Vctrl.
該可控式振盪器240耦合於該濾波器230,以依據該調整訊號Vfilter,進而產生一差動輸出訊號CKOUT+ 、CKOUT- 。該差動輸出訊號CKOUT+ 、CKOUT- 的頻率為24GHz。The controllable oscillator 240 is coupled to the filter 230 to generate a differential output signal CK OUT+ , CK OUT- according to the adjustment signal Vfilter. The frequency of the differential output signals CK OUT+ and CK OUT- is 24 GHz.
該高除數除7預除器250耦合於該可控式振盪器240,用以將該差動輸出訊號CKOUT+ 、CKOUT- 除頻,以產生一除頻訊號CKDIV7+ 、CKDIV7- 。The high-divide divide-by-seven pre- discharger 250 is coupled to the controllable oscillator 240 for dividing the differential output signals CK OUT+ and CK OUT- to generate a frequency-divided signal CK DIV7+ , CK DIV7- .
該除頻裝置260耦合於該高除數除7預除器250,以依據該除頻訊號而產生該反饋訊號CKFB 。該除頻裝置260係由一第一級除2除頻器261、一第二級除2除頻器263、及一除3除頻器265所組成。其中,輸入訊號CKREF 與該反饋訊號CKFB 的頻率為287MHz。The frequency dividing device 260 is coupled to the high divisor dividing and dividing unit 250 to generate the feedback signal CK FB according to the frequency dividing signal. The frequency dividing device 260 is composed of a first stage divide by 2 frequency divider 261, a second stage divide by 2 frequency divider 263, and a divide by 3 frequency divider 265. The frequency of the input signal CK REF and the feedback signal CK FB is 287 MHz.
圖3A及圖3B係本發明之高除數除7預除器250的電路圖,該高除數除7預除器250包括一注入式電晶體組310、一環形振盪器320、及一輸出緩衝級電路330。3A and 3B are circuit diagrams of a high divisor division 7 pre-discharger 250 of the present invention. The high divisor division 7 pre-discharger 250 includes an injection transistor group 310, a ring oscillator 320, and an output buffer. Stage circuit 330.
該注入式電晶體組310以將一注入訊號Vin混成一高頻率訊號及一低頻率訊號。The injection transistor group 310 mixes an injection signal Vin into a high frequency signal and a low frequency signal.
該環形振盪器320連接至該注入式電晶體組310,以保留該低頻率訊號,同時抑制該高頻率訊號。The ring oscillator 320 is coupled to the injection transistor group 310 to retain the low frequency signal while suppressing the high frequency signal.
該輸出緩衝級電路330連接至該環形振盪器320,以將保留之該低頻率訊號的能量逐漸增加,而產生一除頻訊號Voutp、Voutn。其中,該注入訊號Vin的頻率為該除頻訊號Voutp、Voutn的頻率之7倍。The output buffer stage circuit 330 is coupled to the ring oscillator 320 to gradually increase the energy of the low frequency signal retained to generate a divisor signal Voutp, Voutn. The frequency of the injection signal Vin is 7 times the frequency of the frequency-divided signals Voutp and Voutn.
該注入式電晶體組310係由一第一至第七電晶體M1-M7所組成。第一至第七電晶體M1-M7的閘極均連接至一節點A,第一電晶體M1的源極(source)連接至第七電晶體M7的汲極(drain),第一電晶體M1的汲極連接至第二電晶體M2的源極。其他電晶體的連接可參閱圖式,對所屬技術領域的技術人員來說,可基於本發明圖式即可瞭解其連接方式,在此不再贅述。The injection type transistor group 310 is composed of a first to seventh transistors M1-M7. The gates of the first to seventh transistors M1-M7 are both connected to a node A, the source of the first transistor M1 is connected to the drain of the seventh transistor M7, and the first transistor M1 The drain is connected to the source of the second transistor M2. The connection of other transistors can be referred to the drawings. For those skilled in the art, the connection manner can be understood based on the drawings of the present invention, and details are not described herein again.
該環形振盪320器係為一低通濾波器,且由七級反相器所組成,該環形振盪器320係由一第八至第二十一電晶體M8-M21所組成。The ring oscillator 320 is a low pass filter and is composed of a seven-stage inverter consisting of an eighth to twenty-first transistor M8-M21.
該高除數除7預除器250以七級環形振盪器為基底架構,主要分成該注入式電晶體組310及七級反相器所組成的該環形振盪器320。該注入式電晶體組310可視為混波器(mixer)架構,將該注入訊號Vin混成高低頻率。該注入訊號Vin可為該可控式振盪器240的差動輸出訊號CKOUT+ 、 CKOUT- 的其中之一,或是將差動輸出訊號CKOUT+ 、CKOUT- 經差動訊號轉單端訊號後的單端訊號。The high divisor division 7 pre-divider 250 is based on a seven-stage ring oscillator, and is mainly divided into the ring oscillator 320 composed of the injection transistor group 310 and a seven-stage inverter. The injection transistor group 310 can be regarded as a mixer architecture, and the injection signal Vin is mixed into high and low frequencies. The injection signal Vin can be one of the differential output signals CK OUT+ and CK OUT- of the controllable oscillator 240, or the differential output signals CK OUT+ and CK OUT- can be converted to a single-ended signal by the differential signal. After the single-ended signal.
接著,透過該環形振盪器320執行低通濾波,將低頻項保留下來,同時高頻項抑制掉。因為該環形振盪器320是利用相位偏移,依據級數不同而分成不同相位,其優勢在於頻率鎖定範圍可增加,可成功將上一級的可控式振盪器240之所有振盪頻率除頻下來。同時,本發明該環形振盪器320架構,可有效解決傳統電感電容諧振(LC-tank)架構的除頻器在高除數情況下會碰到的頻率鎖定範圍不足之問題。Then, low-pass filtering is performed through the ring oscillator 320 to preserve the low-frequency term while the high-frequency term is suppressed. Because the ring oscillator 320 utilizes the phase offset and is divided into different phases according to the number of stages, the advantage is that the frequency lock range can be increased, and all the oscillation frequencies of the controllable oscillator 240 of the previous stage can be successfully divided. At the same time, the ring oscillator 320 architecture of the invention can effectively solve the problem that the frequency locking range that the frequency divider of the conventional LC-tank architecture encounters in the case of high divisibility is insufficient.
如圖3B所示,輸出緩衝級電路330利用三級反相器電路331,將輸出能量逐漸增加。此外,三級反相器331輸出端Voutp接至下一級的該第一級除2除頻器261之一端輸入,同時此輸出端Voutp又接一級反相器333後再接至該第一級除2除頻器261之另一端輸入。雖然其相位因為電路延遲效應,不會呈現完美的180°相位差,但透過適當參數調校,可使得延遲減至最小,同時下一級的該第一級除2除頻器261也可正常運作。As shown in FIG. 3B, the output buffer stage circuit 330 utilizes the three-stage inverter circuit 331 to gradually increase the output energy. In addition, the output terminal Voutp of the third-stage inverter 331 is connected to one end of the first stage divided by the second frequency divider 261, and the output terminal Voutp is connected to the first-stage inverter 333 and then connected to the first stage. The other end of the 2 frequency divider 261 is input. Although the phase does not exhibit a perfect 180° phase difference due to the circuit delay effect, the delay can be minimized by proper parameter adjustment, and the first stage divide-by-two frequency divider 261 of the next stage can also operate normally. .
圖4係習知單端考畢茲壓控振盪器電路的電路圖,習知單端考畢茲壓控振盪器電路透過閘極接至固定電壓源Vbias以決定電晶體M410的偏壓值,此方式會使得電晶體M410轉導值為一個固定值,其等效轉導值如公式(1)所示:
圖5係本發明可控式振盪器240的電路圖。該可控式振盪器240包含一第一電感L1、一第二電感L2、一第一可變電容Cvar1、一第二可變電容Cvar2、一第三至第六電容C3-C6、及一第二十二至第二十五電晶體M22-M25所組成。Figure 5 is a circuit diagram of a controllable oscillator 240 of the present invention. The controllable oscillator 240 includes a first inductor L1, a second inductor L2, a first variable capacitor Cvar1, a second variable capacitor Cvar2, a third to sixth capacitor C3-C6, and a first Twenty-two to twenty-fifth transistors M22-M25.
該濾波器230產生的調整訊號Vfilter連接於節點B,以調整該可控式振盪器240的該差動輸出訊號CKOUT+ 、CKOUT- 的頻率。該第一電感L1的一端連接至一高電壓VDD,其另一端連接至該第一可變電容Cvar1的一端、該第三電容C3的一端、該第二十二電晶體M22的汲極、及該第二十三電晶體M22的閘極。其他電路的連接可參閱圖式,對所屬技術領域的技術人員來說,可基於本發明圖式即可瞭解其連接方式,在此不再贅述。The adjustment signal Vfilter generated by the filter 230 is connected to the node B to adjust the frequency of the differential output signals CK OUT+ and CK OUT- of the controllable oscillator 240. One end of the first inductor L1 is connected to a high voltage VDD, and the other end is connected to one end of the first variable capacitor Cvar1, one end of the third capacitor C3, the drain of the second twelve transistor M22, and The gate of the twenty-third transistor M22. For the connection of other circuits, reference may be made to the drawings, and the connection manner of the present invention can be understood based on the drawings of the present invention, and details are not described herein again.
圖6係習知單端考畢茲壓控振盪器電路與本發明可控式振盪器240的比較示意圖。該可控式振盪器240係為轉導提升考畢茲振盪器架構,其概念可透過加入一個放大器610來作理解。當***一個增益為-A之放大器610於電晶體M620的閘極G與源極S之間時,此回授路徑不額外消耗電流,同時可提升轉導值為(1+A)倍。在本發明的可控式振盪器240電路中,汲極D與源極S為同相訊號,並透過回授以產生振盪。因此,不管選擇汲極D或是源極S作為耦合端,均
可達到相同效果,而在此電路中選擇汲極D作為耦合端。此外,由電晶體M610看入之等效轉導值如公式(2)所示:
由公式(2)可發現,可控式振盪器240的等效轉導值比圖4中習知單端考畢茲壓控振盪器電路多了倍,同時可知其增加因子A為,故透過此轉導提升方式,可減少確保振盪時所需要的功率消耗。It can be found from equation (2) that the equivalent transconductance value of the controllable oscillator 240 is more than that of the conventional single-ended Cobbitz voltage controlled oscillator circuit in FIG. Times, it is known that the increase factor A is Therefore, through this transfer promotion mode, the power consumption required to ensure oscillation can be reduced.
圖7係本發明第一級除2除頻器261及第二級除2除頻器263的方塊圖。其中,該第一級除2除頻器261及該第二級除2除頻器263係電流模式邏輯(current mode logic,CML)。該第一級除2除頻器261及該第二級除2除頻器263係均由兩個D型正反器710作正回授連結而成。7 is a block diagram of a first stage divide by two frequency divider 261 and a second stage divide by two frequency divider 263 of the present invention. The first stage divide by 2 frequency divider 261 and the second stage divide by 2 frequency divider 263 are current mode logic (CML). The first stage divide by two frequency divider 261 and the second stage divide by two frequency dividers 263 are each formed by positive feedback connection of two D-type flip-flops 710.
該高除數除7預除器250輸出的差動訊號Voutp、Voutn連接至兩個D型正反器710的時序輸入端clk、。經過該第二級除2除頻器263除2後產生四相位訊號(IP、IN、QP、QN)後,接著再經由該第二級除2除頻器263除2產生四相位訊號,最後再注入到除3除頻器265中。電流模式邏輯的該第一級除2除頻器261及該第二級除2除頻器263可利用電流以及負載控制所操作的頻率,故其優點為:(1)可操作較高的頻率,(2)能除出四相位訊號,及(3)可容許較小的輸入擺幅。The differential signals Voutp and Voutn output by the high divisor 7 pre-processor 250 are connected to the timing input terminal clk of the two D-type flip-flops 710, . After the second stage divide/divider 263 divides by 2 to generate the four-phase signal (IP, IN, QP, QN), the second stage divides the second frequency divider 263 to generate the four-phase signal, and finally generates the four-phase signal. Re-injection into the divide-by-three frequency divider 265. The first stage divide by 2 frequency divider 261 of the current mode logic and the second stage divide by 2 frequency divider 263 can utilize the current and the frequency controlled by the load control, so the advantages are: (1) operable higher frequency (2) can remove the four-phase signal, and (3) can tolerate a smaller input swing.
圖8係本發明D型正反器710的電路圖。每一個D型正反器包含第二十六至第三十三電晶體M26-M33。電晶體的連 接可參閱圖式,對所屬技術領域的技術人員來說,可基於本發明圖式即可瞭解其連接方式,在此不再贅述。圖7中係為D型正反器710的符號(symbol),故D型正反器710的輸入D、及輸出Q、分別對應圖8中的In1n、In1p、Out1n、Out1p。Figure 8 is a circuit diagram of a D-type flip-flop 710 of the present invention. Each of the D-type flip-flops includes the twenty-sixth to thirty-thirdth transistors M26-M33. For the connection of the transistor, reference may be made to the drawings, and the connection manner of the present invention can be understood based on the drawings of the present invention, and details are not described herein again. In FIG. 7, the symbol of the D-type flip-flop 710 is used, so the input D of the D-type flip-flop 710, And output Q, Corresponding to In1n, In1p, Out1n, and Out1p in Fig. 8, respectively.
圖9係本發明除3除頻器265的方塊圖。該除3除頻器265係由二個真實單相時脈(True Single Phase Clock,TSPC)除3電路910組成。該除3除頻器265係將前兩級之第一級除2除頻器261及第二級除2除頻器263除頻後之交流訊號繼續除頻至更低頻率,並透過回授路徑和該檢測器210進行相位頻率誤差之比較。因此該除3除頻器265雖然其可操作頻率較低,但是可擁有非常低的功率消耗,同時也有很好的操作頻率範圍和效能。Figure 9 is a block diagram of a divide-by-three frequency divider 265 of the present invention. The divide-by-three frequency divider 265 is composed of two true single phase clock (TSPC) divide-by-three circuits 910. The divide-by-three frequency divider 265 continuously divides the alternating current signal of the first two stages of the first two stages except the two frequency dividers 261 and the second stage divided by two frequency dividers 263 to a lower frequency, and transmits the feedback. The path and the detector 210 compare the phase frequency errors. Therefore, the divide-by-three frequency divider 265 has a low operating frequency, but has a very low power consumption, and also has a good operating frequency range and performance.
圖10係本發明真實單相時脈(TSPC)除3電路910的電路圖。真實單相時脈(TSPC)除3電路910包含第三十四至第四十七電晶體M34-M47。Figure 10 is a circuit diagram of a real single phase clock (TSPC) divide by 3 circuit 910 of the present invention. The True Single Phase Clock (TSPC) divide 3 circuit 910 includes thirty-fourth to forty-seventh transistors M34-M47.
圖11係本發明檢測器210的電路圖。該檢測器210包含第四十八至第五十九電晶體M48-M59、第一至第七反相器Inv01-Inv07、及一延遲電路(delay chain)1110。Figure 11 is a circuit diagram of the detector 210 of the present invention. The detector 210 includes forty-eighth to fifty-ninth transistors M48-M59, first to seventh inverters Inv01-Inv07, and a delay chain 1110.
為了解決檢測器210所產生的禁止區(dead zone)效應,所以於電路中加入該延遲電路1110。該延遲電路1110包含第八至第十反相器Inv08-Inv10、及第一至第二反及閘Nand1-Nand2。即使當輸入訊號CKREF 與反饋訊號CKFB 相位差很小的情況發生時,檢測訊號UP和DN也能夠完整地 充放電,進而正確控制該電荷泵220充放電。此外,在該延遲電路1110有一個CLEAR控制訊號端,在一開始CLEAR訊號會為1,電路將會進行重置動作;緊接著CLEAR訊號變為0,電路即開始進行輸入訊號CKREF 與反饋訊號CKFB 的比較。由於事先已重置過,電路先前狀態已被清除,以避免造成判斷上錯誤,將可增進相位頻率偵測器偵測之準確度。In order to solve the dead zone effect generated by the detector 210, the delay circuit 1110 is incorporated in the circuit. The delay circuit 1110 includes eighth to tenth inverters Inv08-Inv10, and first to second inverse gates Nand1-Nand2. Even when the phase difference between the input signal CK REF and the feedback signal CK FB is small, the detection signals UP and DN can be completely charged and discharged, thereby properly controlling the charge pump 220 to be charged and discharged. In addition, the delay circuit 1110 has a CLEAR control signal terminal. At the beginning, the CLEAR signal will be 1, and the circuit will perform a reset operation. Then, after the CLEAR signal becomes 0, the circuit starts to input the signal CK REF and the feedback signal. Comparison of CK FB . Since the previous state has been reset, the previous state of the circuit has been cleared to avoid causing a judgment error, which will improve the accuracy of the phase frequency detector detection.
圖12係本發明該電荷泵220的電路圖。該電荷泵220包含第六十至第七十三電晶體M60-M73、及一錯誤放大器(error amplifier)1210。Figure 12 is a circuit diagram of the charge pump 220 of the present invention. The charge pump 220 includes sixty to seventy-third transistors M60-M73, and an error amplifier 1210.
該電荷泵220在鎖相迴路系統200中扮演重要的角色,當檢測訊號UP、DN的電流產生不匹配時就會產生抖動,並透過下一級該濾波器230轉變成電壓抖動,進而造成雜訊影響該可控式振盪器240,使得該可控式振盪器240的相位雜訊降低,同時增加了整個鎖相迴路系統200。The charge pump 220 plays an important role in the phase-locked loop system 200. When the currents of the detection signals UP and DN are mismatched, jitter is generated, and the filter 230 is converted into voltage jitter through the next stage of the filter 230, thereby causing noise. The controllable oscillator 240 is affected such that the phase noise of the controllable oscillator 240 is reduced while the entire phase locked loop system 200 is added.
而會發生此種現象之原因為該電荷泵220中電晶體之通道長度調變效應(channel length modulation,CLM)關係,因此在該電荷泵220即選用電流操縱電荷泵(current steering charge pump)電路。在原始電流操縱電荷泵電路架構下,該錯誤放大器(error amplifier)1210的使用可以解決UP與DN電流不匹配問題,進而降低偏移電荷所造成的抖動。而在電荷泵220速開與關的過程中,所產生的漏電荷有可能透過路徑影響到控制訊號Vctrl,造成上述所提到的電壓抖動,並降低該可控式振盪器240的相位雜訊。為 了解決不匹配效應,因此將電路作稍許改進,在電路上中加入兩顆NMOS電晶體M60、M61以及兩顆PMOS電晶體M72、M73當作電容使用。在開關為開路時將所產生的漏電荷儲存進所加入的電容中,而導通時將所儲存的電荷再釋放出,據此降低漏電荷所產生的影響。The reason why this phenomenon occurs is the channel length modulation (CLM) relationship of the transistor in the charge pump 220. Therefore, the charge pump 220 selects a current steering charge pump circuit. . Under the original current-operated charge pump circuit architecture, the use of the error amplifier 1210 can solve the UP-DN current mismatch problem, thereby reducing the jitter caused by the offset charge. During the rapid opening and closing of the charge pump 220, the generated leakage charge may affect the control signal Vctrl through the path, causing the voltage jitter mentioned above, and reducing the phase noise of the controllable oscillator 240. . for To solve the mismatch effect, the circuit is slightly improved. Two NMOS transistors M60 and M61 and two PMOS transistors M72 and M73 are added to the circuit as capacitors. When the switch is open, the generated leakage charge is stored in the added capacitor, and when stored, the stored charge is released again, thereby reducing the influence of the leakage charge.
圖13係本發明錯誤放大器(error amplifier)1210的電路圖。該錯誤放大器1210包含第七十四至第八十七電晶體M74-M87。Figure 13 is a circuit diagram of an error amplifier 1210 of the present invention. The error amplifier 1210 includes seventy-fourth to eighty-seventh transistors M74-M87.
圖14係本發明之濾波器230的電路圖,該濾波器230係為一低通濾波器。其中,該低通濾波器230包含一第一電阻R1、一第一電容C1、及一第二電容C2。該低通濾波器230之迴路頻寬為3 MHz、充放電電流為65 μA、KVCO為2.833 GHz/V、同時相位邊限(phase margin,PM)取66°,可計算出第一電阻R1為21.477 kΩ、第一電容C1為10.385 pF、第二電容C2為0.4914 pF。Figure 14 is a circuit diagram of a filter 230 of the present invention, which is a low pass filter. The low pass filter 230 includes a first resistor R1, a first capacitor C1, and a second capacitor C2. The loop width of the low pass filter 230 is 3 MHz, the charge and discharge current is 65 μA, the KVCO is 2.833 GHz/V, and the phase margin (PM) is 66°, and the first resistor R1 can be calculated as 21.477 kΩ, the first capacitor C1 is 10.385 pF, and the second capacitor C2 is 0.4914 pF.
圖15係本發明鎖相迴路系統200暫態模擬的示意圖。如圖15所示,其中鎖定時間約為800 ns,此時對應到的鎖定電壓約為0.81 V。圖16係本發明鎖相迴路系統200模擬參數與結果的示意圖。Figure 15 is a schematic illustration of a transient simulation of a phase locked loop system 200 of the present invention. As shown in Figure 15, where the lock time is approximately 800 ns, the corresponding lock voltage is approximately 0.81 V. Figure 16 is a schematic illustration of the simulated parameters and results of the phase locked loop system 200 of the present invention.
圖17係一習知電感電容諧振振盪器(LC-tank oscillator)的電路圖,如圖17所示,其除頻概念即是在中心Vcm共模點,透過以一電感和電容元件所組成之抑制2階諧波項濾波器,藉此即可將4階高頻諧波項和注入訊號進行混頻機 制,並透過等同帶通濾波器的電感電容諧振基底壓控振盪器,即可達到除頻之功能。17 is a circuit diagram of a conventional LC-tank oscillator. As shown in FIG. 17, the frequency division concept is a common mode point at the center Vcm, and is suppressed by an inductor and a capacitor. 2nd order harmonic term filter, which can be used to mix 4th order high frequency harmonic terms and injection signals The frequency division function can be achieved by using an inductor-capacitor resonant base voltage controlled oscillator with an equivalent bandpass filter.
圖18係本發明高除數除7預除器250與圖17中預除器之最大鎖定頻率範圍之比較示意圖。從圖18結果可得知,不管當注入功率為1.5dBm或是3dBm時,本發明高除數除7預除器250皆有較大的頻率鎖定範圍。此即為本發明核心技術,同時也是本發明最大改進之處。在因應製程變異時,本發明高除數除7預除器250較能確保整體鎖相迴路之正確運作。而應用於24 GHz鎖相迴路系統中,其注入功率來自前一級可控式振盪器240之輸出功率,大小為3 dBm,因此其最大頻率鎖定範圍為1.8 GHz,此時電路偏壓點為0.34 V。Figure 18 is a graphical representation of a comparison of the maximum lock frequency range of the high divisor divide-by-seven pre-discharger 250 of the present invention and the pre-discharger of Figure 17. As can be seen from the results of Fig. 18, the high divisor division 7 pre-discharger 250 of the present invention has a large frequency locking range regardless of the injection power of 1.5 dBm or 3 dBm. This is the core technology of the present invention and is also the greatest improvement of the present invention. In view of process variation, the high divisor division 7 pre-remover 250 of the present invention can ensure the correct operation of the overall phase-locked loop. In the 24 GHz phase-locked loop system, the injected power comes from the output power of the previous stage controllable oscillator 240, which is 3 dBm. Therefore, the maximum frequency locking range is 1.8 GHz, and the circuit bias point is 0.34. V.
本發明由於使用更高除數之高除數除7預除器250,和使用其它較低除數之類比除頻器相比,可更快達到較低頻帶,進而減少整體電路所使用到的除頻器級數;因為除頻器級數之減少,可減少電路複雜度,同時降低任何可能經由供應電壓端所饋入電路之耦合雜訊。此外,本技術所使用的Ring-oscillator-based架構的注入鎖定除頻器和傳統使用LC-tank-oscillator-based架構的除頻器相比,鎖定頻率範圍可有效增加。The present invention can achieve a lower frequency band faster by using a higher divisor division 7 pre-divider 250 using a higher divisor, thereby reducing the use of the overall circuit. The number of divider stages; because the number of stages of the divider is reduced, circuit complexity can be reduced while reducing any coupling noise that may be fed into the circuit via the supply voltage terminal. In addition, the injection-locked frequency divider of the Ring-oscillator-based architecture used in the present technology can effectively increase the locked frequency range compared with the traditional frequency divider using the LC-tank-oscillator-based architecture.
由上述可知,本發明無論就目的、手段及功效,在在均顯示其迥異於習知技術之特徵,極具實用價值。惟應注意的是,上述諸多實施例僅係為了便於說明而舉例而已, 本發明所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。From the above, it can be seen that the present invention is extremely useful in terms of its purpose, means, and efficacy, both of which are different from those of the prior art. It should be noted that the above various embodiments are merely examples for convenience of explanation. The scope of the claims is intended to be limited only by the scope of the claims.
100‧‧‧鎖相迴路100‧‧‧ phase-locked loop
110‧‧‧相位檢測器110‧‧‧ phase detector
120‧‧‧電荷泵120‧‧‧Charge pump
130‧‧‧濾波器130‧‧‧ Filter
140‧‧‧電壓控制振盪器140‧‧‧Voltage Controlled Oscillator
150‧‧‧除頻裝置150‧‧‧Dividing device
151‧‧‧第一階段預除器151‧‧‧First stage pre-processor
153‧‧‧後段除頻器153‧‧‧ Rear section frequency divider
200‧‧‧鎖相迴路系統200‧‧‧ phase-locked loop system
210‧‧‧檢測器210‧‧‧Detector
220‧‧‧電荷泵220‧‧‧Charge pump
230‧‧‧濾波器230‧‧‧ filter
240‧‧‧可控式振盪器240‧‧‧Controllable Oscillator
250‧‧‧高除數除7預除器250‧‧‧High Divisor Division 7 Prescaler
260‧‧‧除頻裝置260‧‧‧frequency divider
261‧‧‧第一級除2除頻器261‧‧‧First stage divide by 2 frequency divider
263‧‧‧第二級除2除頻器263‧‧‧Second stage divide by 2 frequency divider
265‧‧‧除3除頻器265‧‧‧ except 3 frequency divider
310‧‧‧注入式電晶體組310‧‧‧Injected transistor group
320‧‧‧環形振盪器320‧‧‧Ring Oscillator
330‧‧‧輸出緩衝級電路330‧‧‧Output buffer stage circuit
M1-M7‧‧‧第一至第七電晶體M1-M7‧‧‧first to seventh transistors
M8-M21‧‧‧第八至第二十一電晶體M8-M21‧‧‧ eighth to twenty-first crystal
M410‧‧‧電晶體M410‧‧‧O crystal
C420‧‧‧電容C420‧‧‧ capacitor
Vbias‧‧‧固定電壓源Vbias‧‧‧ fixed voltage source
L1‧‧‧第一電感L1‧‧‧first inductance
L2‧‧‧第二電感L2‧‧‧second inductance
Cvar1‧‧‧第一可變電容Cvar1‧‧‧first variable capacitor
Cvar2‧‧‧第二可變電容Cvar2‧‧‧Second variable capacitor
C3-C6‧‧‧第三至第六電容C3-C6‧‧‧ third to sixth capacitor
M22-M25‧‧‧第二十二至第二十五電晶體M22-M25‧‧‧22nd to 25th crystal
610‧‧‧放大器610‧‧Amplifier
M620‧‧‧電晶體M620‧‧‧O crystal
710‧‧‧D型正反器710‧‧‧D type flip-flop
M26-M33‧‧‧第二十六至第三十三電晶體M26-M33‧‧‧Twenty-sixth to thirty-third crystals
910‧‧‧真實單相時脈除3電路910‧‧‧Real single phase clock divided by 3 circuits
M34-M47‧‧‧第三十四至第四十七電晶體M34-M47‧‧‧Thirteenth to forty-seventh transistor
M48-M59‧‧‧第四十八至第五十九電晶體M48-M59‧‧‧48th to 59th Crystal
Inv01-Inv07‧‧‧第一至第七反相器Inv01-Inv07‧‧‧First to Seventh Inverters
1110‧‧‧延遲電路1110‧‧‧Delay circuit
Inv08-Inv10‧‧‧第八至第十反相器Inv08-Inv10‧‧‧ eighth to tenth inverter
Nand1-Nand2‧‧‧第一至第二反及閘Nand1-Nand2‧‧‧first to second reverse gates
M60-M73‧‧‧六十至第七十三電晶體M60-M73‧‧‧60 to 73 crystal
1210‧‧‧錯誤放大器1210‧‧‧Error amplifier
M74-M87‧‧‧第七十四至第八十七電晶體M74-M87‧‧‧ Seventy-fourth to eighty-seventh crystal
R1‧‧‧第一電阻R1‧‧‧first resistance
C‧‧‧第一電容C‧‧‧first capacitor
C2‧‧‧第二電容C2‧‧‧second capacitor
圖1係一習知鎖相迴路的方塊圖。Figure 1 is a block diagram of a conventional phase-locked loop.
圖2係本發明之鎖相迴路系統的方塊圖。2 is a block diagram of a phase locked loop system of the present invention.
圖3A及圖3B係本發明之高除數除7預除器的電路圖。3A and 3B are circuit diagrams of the high divisor division 7 pre-discharger of the present invention.
圖4係習知單端考畢茲壓控振盪器電路的電路圖。Figure 4 is a circuit diagram of a conventional single-ended Cobbitz voltage controlled oscillator circuit.
圖5係本發明可控式振盪器的電路圖。Figure 5 is a circuit diagram of a controllable oscillator of the present invention.
圖6係習知單端考畢茲壓控振盪器電路與本發明可控式振盪器的比較示意圖。6 is a schematic diagram showing a comparison between a conventional single-ended Cobbitz voltage controlled oscillator circuit and a controllable oscillator of the present invention.
圖7係本發明第一級除2除頻器及第二級除2除頻器的方塊圖。Figure 7 is a block diagram of a first stage divide by two frequency divider and a second stage divide by two frequency divider of the present invention.
圖8係本發明D型正反器的電路圖。Figure 8 is a circuit diagram of a D-type flip-flop of the present invention.
圖9係本發明除3除頻器的方塊圖。Figure 9 is a block diagram of a divide-by-three frequency divider of the present invention.
圖10係本發明真實單相時脈除3電路的電路圖。Figure 10 is a circuit diagram of a true single phase clock division 3 circuit of the present invention.
圖11係本發明檢測器的電路圖。Figure 11 is a circuit diagram of the detector of the present invention.
圖12係本發明該電荷泵的電路圖。Figure 12 is a circuit diagram of the charge pump of the present invention.
圖13係本發明錯誤放大器的電路圖。Figure 13 is a circuit diagram of the error amplifier of the present invention.
圖14係本發明之濾波器的電路圖。Figure 14 is a circuit diagram of a filter of the present invention.
圖15係本發明鎖相迴路系統暫態模擬的示意圖。Figure 15 is a schematic illustration of a transient simulation of a phase locked loop system of the present invention.
圖16係本發明鎖相迴路系統模擬參數與結果的示意圖。Figure 16 is a schematic illustration of simulation parameters and results of a phase locked loop system of the present invention.
圖17係一習知電感電容諧振振盪器的電路圖。Figure 17 is a circuit diagram of a conventional inductor-capacitor resonator oscillator.
圖18係本發明高除數除7預除器與圖17中預除器之最大鎖定頻率範圍之比較示意圖。Figure 18 is a graphical representation of a comparison of the maximum lock frequency range of the high divisor divide-by-seven pre-discharger of the present invention and the pre-discharger of Figure 17.
200‧‧‧鎖相迴路系統200‧‧‧ phase-locked loop system
210‧‧‧檢測器210‧‧‧Detector
220‧‧‧電荷泵220‧‧‧Charge pump
230‧‧‧濾波器230‧‧‧ filter
240‧‧‧可控式振盪器240‧‧‧Controllable Oscillator
250‧‧‧高除數除7預除器250‧‧‧High Divisor Division 7 Prescaler
260‧‧‧除頻裝置260‧‧‧frequency divider
261‧‧‧第一級除2除頻器261‧‧‧First stage divide by 2 frequency divider
263‧‧‧第二級除2除頻器263‧‧‧Second stage divide by 2 frequency divider
265‧‧‧除3除頻器265‧‧‧ except 3 frequency divider
Claims (11)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW101148040A TWI499217B (en) | 2012-12-18 | 2012-12-18 | Prescaler of divide-by-7 with a high division-ratio and phase-locked loop system using the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW101148040A TWI499217B (en) | 2012-12-18 | 2012-12-18 | Prescaler of divide-by-7 with a high division-ratio and phase-locked loop system using the same |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201427284A TW201427284A (en) | 2014-07-01 |
TWI499217B true TWI499217B (en) | 2015-09-01 |
Family
ID=51725774
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW101148040A TWI499217B (en) | 2012-12-18 | 2012-12-18 | Prescaler of divide-by-7 with a high division-ratio and phase-locked loop system using the same |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI499217B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW202017318A (en) | 2018-10-16 | 2020-05-01 | 財團法人工業技術研究院 | Transconductance controlling circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6031425A (en) * | 1997-07-25 | 2000-02-29 | Fujitsu Limited | Low power prescaler for a PLL circuit |
TW201015869A (en) * | 2008-10-03 | 2010-04-16 | Novatek Microelectronics Corp | Frequency synthesizer and frequency prescaler thereof and frequency synthesizing method thereof |
-
2012
- 2012-12-18 TW TW101148040A patent/TWI499217B/en active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6031425A (en) * | 1997-07-25 | 2000-02-29 | Fujitsu Limited | Low power prescaler for a PLL circuit |
TW201015869A (en) * | 2008-10-03 | 2010-04-16 | Novatek Microelectronics Corp | Frequency synthesizer and frequency prescaler thereof and frequency synthesizing method thereof |
Non-Patent Citations (1)
Title |
---|
2008年12月8日公開文獻Yu, X.P. ; Inst. of VLSI Design, Zhejiang Univ., Hangzhou ; Lim, W.M. ; Do, M.A. ; Yan, X.L. "6.1 GHz 4.6 mW CMOS divide-by-55/56 prescaler" Electronics Letters 2001年公開文獻B. Razavi, "Design of Analog CMOS Integrated Circuits", McGraw-Hill, 2001 * |
Also Published As
Publication number | Publication date |
---|---|
TW201427284A (en) | 2014-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Chang et al. | A low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked PLL with self-aligned DLL in 65-nm CMOS technology | |
JP5174055B2 (en) | Broadband oscillator circuit | |
Osorio et al. | A 21.7-to-27.8 GHz 2.6-degrees-rms 40mW frequency synthesizer in 45nm CMOS for mm-wave communication applications | |
TW200908563A (en) | Phase lock loop, voltage controlled oscillator and phase-frequency detector | |
US8860511B2 (en) | Frequency divider and PLL circuit | |
Moghavvemi et al. | Recent advances in delay cell VCOs [application notes] | |
Luong et al. | Low-voltage CMOS RF frequency synthesizers | |
Lee et al. | An inductorless injection-locked PLL with 1/2-and 1/4-integral subharmonic locking in 90 nm CMOS | |
CN106788410B (en) | Circuit for generating quadrature local oscillator signals by using injection locking ring oscillator | |
Tong et al. | An injection-locked frequency divider with multiple highly nonlinear injection stages and large division ratios | |
US9088285B2 (en) | Dynamic divider having interlocking circuit | |
TWI499217B (en) | Prescaler of divide-by-7 with a high division-ratio and phase-locked loop system using the same | |
Chiu et al. | A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-μm CMOS | |
Li et al. | An inductor-less fractional-N injection-locked PLL with a spur-and-phase-noise filtering technique | |
Wang et al. | A K-band fractional-N frequency synthesizer with a low phase noise LC VCO in 90nm CMOS | |
Abiri et al. | A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology | |
Yang et al. | A 3GHz Phase-Locked Loop Design for SerDes Application | |
Jain et al. | Millimeter-wave CMOS PLL using a push-push oscillator | |
Hokrani et al. | Design and implementation of Phase Locked Loop on 180nm Technology node | |
Park et al. | CMOS integrated 1 GHz ring oscillator with injection-locked frequency divider for low power PLL | |
yeop Lee et al. | High-frequency half-integral subharmonic locked ring-VCO-based scalable PLL in 90 nm CMOS | |
Essawy et al. | A 2.8-mW Sub-Harmonic Injection-Locked Frequency Multiplier in 130-nm CMOS for 2.4-GHz WLAN Applications | |
Karra et al. | An Ultra-low Phase Noise, Low Power 28GHz Frequency Synthesizer for 5G Applications | |
Lo et al. | A 0.6 ps jitter 2–16 GHz 130nm CMOS frequency synthesizer for broadband applications | |
Wang et al. | 1.5 GHz sigma-delta fractional-N ring-based PLL realized using 40 nm CMOS technology for SoC applications |