TWI499039B - Apparatus for sram bit cell and cam bit cell - Google Patents

Apparatus for sram bit cell and cam bit cell Download PDF

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TWI499039B
TWI499039B TW099131597A TW99131597A TWI499039B TW I499039 B TWI499039 B TW I499039B TW 099131597 A TW099131597 A TW 099131597A TW 99131597 A TW99131597 A TW 99131597A TW I499039 B TWI499039 B TW I499039B
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gate dielectric
dielectric layer
read
thickness
sram
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TW099131597A
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TW201112404A (en
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Ping Wei Wang
Chang Ta Yang
Yuh Jier Mii
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Taiwan Semiconductor Mfg Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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Description

靜態隨機存取記憶體位元單元與內容定址記憶體位元單元的裝置Device for static random access memory bit unit and content addressed memory bit unit

本發明係有關於靜態隨機存取記憶體(Static Random Access Memory,SRAM)的位元單元結構與提供具有改善的待機漏電流(Isb)的位元單元的方法，以獲得改善的待機動作、改善的Vcc,min、降低的供應位準有最小功率、高速讀取時間。The present invention relates to a bit cell structure of a static random access memory (SRAM) and a method of providing a bit cell having an improved standby leakage current (Isb) to obtain improved standby operation and improvement. The Vcc, min, reduced supply level has minimum power and high speed read time.

位元單元包括一個新的佈局與單元電晶體中的多重厚度閘極氧化層。本發明的用途提供將SRAM利用於具備邏輯電路或使用者指定的電路之積體電路的優點。除了SRAM位元單元的SRAM陣列，SRAM單元也具備改善的穩定度且提供可靠的操作於廣泛的狀況中。製作包括本發明特徵的SRAM位元單元的方法可以相容於現存的技術狀況與計劃的半導體製程。The bit cell includes a new layout and multiple thickness gate oxide layers in the cell transistor. The use of the present invention provides the advantage of utilizing SRAM for an integrated circuit having logic circuitry or user specified circuitry. In addition to SRAM arrays of SRAM bit cells, SRAM cells also have improved stability and provide reliable operation in a wide range of conditions. The method of fabricating an SRAM cell comprising features of the present invention can be compatible with existing state of the art and planned semiconductor processes.

現今一般對電子電路的需求，特別是被製作為半導體製程中積體電路的電子電路的需求，是基板上的或內建的記憶儲存元件陣列。這些元件可以是動態隨機存取記憶體(DRAM)單元，也可以是靜態隨機存取記憶體(SRAM)單元。DRAM與SRAM記憶體稱為揮發性記憶單元，其中要是移除供應積體電路的電源，儲存的資料就會消失。DRAM單元可以提供非常密集的陣列，因為DRAM單元只需要單一的存取電晶體與儲存電容。然而，DRAM電路具有相對較慢的讀取與寫入時間，而且需要較複雜的控制電路。每一個DRAM單元以充電於漏電容的方式儲存資料，因此DRAM陣列必須週期性地更新來維持狀態。這需要處理器週期性地停止其他運算來執行更新循環，或是專用的記憶控制器(較常使用於目前生產的裝置)來執行更新循環。SRAM陣列需要較多的矽區域，因為每個位元單元一般是由6個或更多電晶體所組成的鎖相器。然而只要供應電壓存在，SRAM單元就會保持資料。更進一步的優點是SRAM單元的存取時間比起DRAM單元快，使得SRAM單元在暫存或工作資料的儲存上(如處理器的快取記憶體)特別有吸引力。最近的晶片系統(SOC)設計通常併入一個或多個核心。這些核心通常是預先設計的流程的處理器(如DSPs、ARMs、RISC、或微處理器)，與該處理器鄰接或在附近配置了一個SRAM單元的第1級(L1)快取記憶體，使得運算處理速度能夠更快。The demand for electronic circuits today, particularly for electronic circuits that are fabricated as integrated circuits in semiconductor processes, is an array of on-board or built-in memory storage elements. These components may be dynamic random access memory (DRAM) cells or static random access memory (SRAM) cells. DRAM and SRAM memory are called volatile memory cells, and if the power supply to the integrated circuit is removed, the stored data will disappear. DRAM cells can provide very dense arrays because DRAM cells require only a single access transistor and storage capacitor. However, DRAM circuits have relatively slow read and write times and require more complex control circuits. Each DRAM cell stores data in a manner that is charged to the drain capacitor, so the DRAM array must be periodically updated to maintain state. This requires the processor to periodically stop other operations to perform the update cycle, or a dedicated memory controller (usually used in currently produced devices) to perform the update cycle. SRAM arrays require more germanium regions because each bit cell is typically a phase lock consisting of six or more transistors. However, as long as the supply voltage is present, the SRAM cell will retain the data. A further advantage is that the access time of the SRAM cell is faster than that of the DRAM cell, making the SRAM cell particularly attractive for temporary storage or storage of work data, such as the processor's cache memory. Recent wafer system (SOC) designs are typically incorporated into one or more cores. These cores are typically processors of pre-designed processes (such as DSPs, ARMs, RISCs, or microprocessors), with Level 1 (L1) cache memory of an SRAM cell adjacent to or adjacent to the processor. Make the processing speed faster.

積體電路使用於電池驅動裝置的情況日漸提高。例如，SOC可能用於提供全部或大部分用來實現行動電話、手提電腦、筆記型電腦、影音播放器、攝錄影機、相機、智慧型電話、或PDA主要功能的電路。在這些裝置中，客戶定義的邏輯或許可的處理器核心設計會與其他預定的或巨集的單元(如微處理器、數位信號處理器、核心(如ARM、RISC、或相似核心功能)、行動電話模組等)整合在一起。The use of an integrated circuit for a battery drive device is increasing. For example, the SOC may be used to provide all or most of the circuitry used to implement the main functions of a mobile phone, laptop, notebook, video player, video camera, camera, smart phone, or PDA. In these devices, customer-defined logic or licensed processor cores are designed with other predetermined or macro-units (such as microprocessors, digital signal processors, cores (such as ARM, RISC, or similar core functions), Mobile phone modules, etc.) are integrated.

在SRAM位元單元中，資料會儲存在兩個逆相關的儲存節點中。一對CMOS反相器(由四個MOS電晶體組成)被配置做為一拴鎖單元。在互補式MOS(CMOS)技術中，每一個儲存節點是由兩個MOS電晶體的閘極端子所形成，並且接收由兩個MOS電晶體組成的反相器的輸出。In the SRAM bit cell, the data is stored in two inverse correlation storage nodes. A pair of CMOS inverters (consisting of four MOS transistors) are configured as a shackle unit. In complementary MOS (CMOS) technology, each storage node is formed by the gate terminals of two MOS transistors and receives the output of an inverter consisting of two MOS transistors.

第1圖顯示一典型6T配置的SRAM位元單元10。在第1圖中，一對MOS傳導閘PG1、PG2電性分別連接一對資料線(也稱為位元線BL與BLB)至儲存接點SN1與SN2。傳導閘PG1與PG2在習知技術中一般是由NMOS電晶體所組成。圖中顯示一正的供應電壓Vdd，其範圍在0.6伏特到3.0伏特或更高，主要視技術而定。上拉電晶體PU1與PU2由PMOS電晶體組成，並且會將正的供應電壓電性連接至一個或另一個儲存節點，依SRAM單元10的狀態而定。圖中也顯示一第2供應電壓Vss，通常是接地。Figure 1 shows a SRAM bit cell 10 of a typical 6T configuration. In Fig. 1, a pair of MOS conductive gates PG1, PG2 are electrically connected to a pair of data lines (also referred to as bit lines BL and BLB) to storage contacts SN1 and SN2, respectively. The conductive gates PG1 and PG2 are generally composed of NMOS transistors in the prior art. The figure shows a positive supply voltage Vdd ranging from 0.6 volts to 3.0 volts or more, depending on the technology. The pull-up transistors PU1 and PU2 are composed of PMOS transistors and electrically connect the positive supply voltage to one or the other storage node, depending on the state of the SRAM cell 10. Also shown is a second supply voltage Vss, typically grounded.

兩個下拉電晶體PD1與PD2(也是NMOS電晶體)將負的或接地電壓Vss電性連接至一個或另一個儲存節點SN1與SN2，依位元單元的狀態而定。位元單元是一個鎖相器，只要供應電源足以正確地操作電路，該鎖相器會無限時地保存資料狀態。兩個分別由PU1、PD1與PU2、PD2所組成CMOS反相器彼此交錯耦合，而他們的操作用來連續地增強儲存於儲存節點SN1與SN2的電荷。兩個儲存節點如圖中顯示彼此反相。當SN1為邏輯狀態1(通常為高電位)，SN2在同一時間會為邏輯狀態0(通常是低電位)，反之亦然。The two pull-down transistors PD1 and PD2 (also NMOS transistors) electrically connect the negative or ground voltage Vss to one or the other of the storage nodes SN1 and SN2, depending on the state of the bit cell. The bit cell is a phase locker that saves the data state indefinitely as long as the power supply is sufficient to operate the circuit correctly. Two CMOS inverters, each consisting of PU1, PD1 and PU2, PD2, are interleaved with each other, and their operation is used to continuously enhance the charge stored in storage nodes SN1 and SN2. The two storage nodes are shown as being inverted from each other as shown. When SN1 is in logic state 1 (usually high), SN2 will be logic state 0 (usually low) at the same time, and vice versa.

當SRAM位元單元10被寫入，互補的寫入資料會分別輸入位元線對BL與BLB。字元線WL上正的控制信號會電性連接至兩個傳導閘PG1與PG2的閘極。電晶體PU1、PD1與PU2、PD2的所訂定的尺寸能夠使位元線上的資料覆寫儲存的資料，藉此寫入SRAM位元單元10中。When the SRAM bit cell 10 is written, the complementary write data is input to the bit line pair BL and BLB, respectively. A positive control signal on word line WL is electrically coupled to the gates of the two conductive gates PG1 and PG2. The predetermined dimensions of the transistors PU1, PD1 and PU2, PD2 enable the data on the bit line to overwrite the stored material, thereby being written into the SRAM bit cell 10.

當SRAM位元單元10被讀取，正的電壓施加於字元線WL，傳導閘PG1與PG2允許位元線BL與BLB電性連接至儲存節點SN1與SN2來接收資料。不同於動態記憶單元，如果電源供應Vdd維持在足夠的高位準下，SRAM位元單元在讀取期間不會喪失其儲存的狀態。因此讀取動作結束後就不需要進行寫回(write back)的動作。When the SRAM bit cell 10 is read, a positive voltage is applied to the word line WL, and the conductive gates PG1 and PG2 allow the bit lines BL and BLB to be electrically connected to the storage nodes SN1 and SN2 to receive the data. Unlike the dynamic memory unit, if the power supply Vdd is maintained at a sufficiently high level, the SRAM bit cell will not lose its stored state during reading. Therefore, there is no need to perform a write back operation after the reading operation is completed.

位元線BL與BLB構成一對互補的資料線對。這兩條成對的資料線可電性連接至一差動感應放大器(未表示於圖中)，而差動電壓可以被感應且放大，此為該技術領域知識者所熟知的設計。這個既放大且感應的輸出信號可以做為資料往該裝置中其他的邏輯電路的輸出。The bit lines BL and BLB form a pair of complementary data line pairs. The two pairs of data lines can be electrically connected to a differential sense amplifier (not shown), and the differential voltage can be sensed and amplified, a design well known to those skilled in the art. This amplified and sensed output signal can be used as an output to other logic circuits in the device.

第2圖顯示另一種形式的傳統SRAM位元單元12，其中使用了8個電晶體(8T)並且讀取埠14的配置有附加的功能。在第2圖中，具有第1圖所示的6T的單元10。SRAM位元單元12另外具有一個由兩個NMOS電晶體組成的讀取埠14，這兩個電晶體分別為讀取埠下拉電晶體RPD與讀取埠傳導閘電晶體RPG。該讀取埠14還具有一條只供讀取用讀取字元線RWL。先前在第1圖中的字元線WL在第2圖的8T的單元12中是僅供寫入的寫入字元線WWL。將讀取埠分離出來的好處是減低了讀取干擾的機率，因為儲存於位元單元的資料會被讀取動作所影響。相對地，讀取下拉電晶體RPD會根據電性連接至其閘極的儲存節點SN2來導通或截止。因為NMOS電晶體具有增益，儲存在節點SN2的資料信號會被電晶體RPD的增益放大。因此當讀取字元線RWL被施加正電壓時，讀取傳導閘RPG會導通並且將讀取位元線RBL電性連接至讀取下拉電晶體，因此讀取埠會輸出一個對應的資料位元在讀取位元線RBL上。在許多應用當中，許多位元單元的SRAM陣列被用來儲存恢復用與稍後使用的資料或程式。SRAM單元在同樣的時間內經歷的讀取動作會比寫入動作多。因此透過讀取埠14將讀取動作與位元單元分離是相當有幫助的，縱使8T的單元要使用較多的矽佈局面積來完成。另外，當嘗試節省電力(Vdd)時，最小的特性量測對讀取電路而言變得更為重要，因為那是電路中最常作動的部份。Figure 2 shows another form of conventional SRAM bit cell unit 12 in which eight transistors (8T) are used and the configuration of the read port 14 has additional functionality. In Fig. 2, there is a unit 10 of 6T shown in Fig. 1. The SRAM bit cell 12 additionally has a read 埠 14 composed of two NMOS transistors, which are a read 埠 pull-down transistor RPD and a read 埠 conductive gate transistor RPG, respectively. The read cassette 14 also has a read word line RWL for reading only. The word line WL previously in Fig. 1 is a write-only write word line WWL in the unit 12 of 8T of Fig. 2 . The advantage of separating the read 埠 is to reduce the chance of reading interference, because the data stored in the bit cell will be affected by the read action. In contrast, the read pull-down transistor RPD is turned on or off according to the storage node SN2 electrically connected to its gate. Since the NMOS transistor has a gain, the data signal stored at the node SN2 is amplified by the gain of the transistor RPD. Therefore, when the read word line RWL is applied with a positive voltage, the read conduction gate RPG is turned on and the read bit line RBL is electrically connected to the read pull-down transistor, so the read 埠 outputs a corresponding data bit. The element is read on the bit line RBL. In many applications, many SRAM arrays of bit cells are used to store recovered data and programs for later use. The SRAM unit will experience more read operations than write operations in the same amount of time. Therefore, it is quite helpful to separate the reading operation from the bit unit by reading the 埠14, even though the 8T unit is to be used with a larger 矽 layout area. In addition, when attempting to conserve power (Vdd), the minimum characteristic measurement becomes more important to the read circuit because it is the most frequently active part of the circuit.

第3圖顯示另一種習知的SRAM位元單元20，其中使用了10個電晶體(10T)。在這個配置中，電路具備兩個讀取埠，分別電性連接至6T單元10的儲存節點SN1與SN2。讀取埠22與24分別具有各自的控制線RWL1與RWL2及下拉NMOS電晶體與傳導閘NMOS電晶體。兩條讀取位元線RBL1與RBL2分別透過傳導閘RPG1與RPG2電性連接至下拉電晶體RPD1與RPD2。下拉電晶體分別具有一連接至儲存節點SN1與SN2的閘極。讀取動作可以獨立或同時地進行。使用兩個讀取埠提供了附加的彈性並且能夠使兩個輸出同時從單元讀取出來。Figure 3 shows another conventional SRAM bit cell 20 in which 10 transistors (10T) are used. In this configuration, the circuit has two read ports, which are electrically connected to the storage nodes SN1 and SN2 of the 6T unit 10, respectively. The read ports 22 and 24 have respective control lines RWL1 and RWL2 and a pull-down NMOS transistor and a conductive gate NMOS transistor, respectively. The two read bit lines RBL1 and RBL2 are electrically connected to the pull-down transistors RPD1 and RPD2 through the conductive gates RPG1 and RPG2, respectively. The pull-down transistors each have a gate connected to storage nodes SN1 and SN2. The reading action can be performed independently or simultaneously. The use of two read ports provides additional flexibility and enables both outputs to be read out of the unit simultaneously.

由於低耗電積體電路需求的持續與增加(特別是更複雜的電池供電的攜帶裝置)，SRAM單元需要具有良好的省電特性。電力消耗的限制方法之一必須倚靠待機漏電流(此後以Isb表示)。當SRAM單元沒有正在使用，SRAM陣列會處於待機模式。待機時的漏電流Isb必須被減小。在習知的技術中，盡可能地降低待機模式時的正電源供應來減低CMOS電路的電力消耗的方法廣為知曉。用來決定Vcc位準的公制是Vcc,min。提供一個具備低的Vcc,min值的SRAM單元是很明顯有利的。而這對於6T儲存單元而言很難有效地去實施，這是因為裝置尺寸的縮小以及製程的進步所導致的製程變動與其他限制漸增。Due to the continued and increased demand for low-power integrated circuits (especially more complex battery-powered carriers), SRAM cells need to have good power-saving characteristics. One of the limiting methods of power consumption must rely on standby leakage current (hereafter referred to as Isb). When the SRAM cell is not in use, the SRAM array will be in standby mode. The leakage current Isb during standby must be reduced. In the prior art, a method of reducing the power supply of the CMOS circuit as much as possible while reducing the positive power supply in the standby mode is widely known. The metric used to determine the Vcc level is Vcc,min. It is obviously advantageous to provide an SRAM cell with a low Vcc,min value. This is difficult for the 6T storage unit to implement effectively because of the shrinking device size and the progress of the process, and the process variation and other restrictions are increasing.

然而上述的電路仍具有優秀的時間(讀取速度)並且可以不產生讀取干擾錯誤而有效地操作。最後的特性可以稱為電路的穩定性。一個維持穩定性的方法是降低施加至SRAM儲存單元的Vcc,min。而隨著半導體製程的進步，裝置尺寸持續縮小。更小的裝置的使用導致裝置的表現有極大的變動幅度。為了維持這些裝置的操作可靠性，必須要有一個較低的Vcc,min。雖然降低Vcc,min是一個降低耗電的好方法，但降低Vcc,min對SRAM陣列也是必要的。However, the above circuit still has excellent time (reading speed) and can operate efficiently without generating read disturb errors. The final characteristic can be called the stability of the circuit. One way to maintain stability is to reduce the Vcc,min applied to the SRAM storage unit. As semiconductor processes progress, device sizes continue to shrink. The use of smaller devices results in a significant variation in the performance of the device. In order to maintain the operational reliability of these devices, a lower Vcc, min must be available. Although reducing Vcc, min is a good way to reduce power consumption, reducing Vcc, min is also necessary for SRAM arrays.

因此，我們需要一個改良的SRAM位元單元結構，該結構具有較低待機漏電流Isb、改善的Vcc,min用以降低待機耗電、與改善的存取速度(特別是讀取動作時)，同時維持習知半導體製程技術用來製造積體電路的相容性，並且不增加明顯的部驟與成本。Therefore, we need an improved SRAM bit cell structure with a low standby leakage current Isb, improved Vcc, min to reduce standby power consumption, and improved access speed (especially during read operations). At the same time, the compatibility of conventional semiconductor process technology for manufacturing integrated circuits is maintained without adding significant parts and costs.

這些或其他問題大致被解決或避開，藉由本發明的實施例達成了技術上的優點。本發明提供一種SRAM位元單元在儲存單元電晶體具備較厚的閘極氧化層，在讀取埠電晶體具備較薄的閘極氧化層。厚閘極氧化層使用於儲存單元電晶體提供了穩定的資料儲存與較低的待機電流。薄閘極氧化層使用於讀取埠電晶體提供了快的讀取時間與允許較低的Vcc,min。供應至讀取埠的電力可電性連接至裝置的邏輯部分，同時供給至儲存單元電晶體的電力可以比較高來改善可靠度。本方法是用來形成具有雙重閘極氧化層厚度的SRAM單元並且其製程步驟可以相容於現行用於半導體製造的步驟流程。These or other problems are generally solved or avoided, and technical advantages are achieved by embodiments of the present invention. The invention provides an SRAM bit cell having a thick gate oxide layer in the memory cell transistor and a thin gate oxide layer in the read germanium transistor. The thick gate oxide layer used in the memory cell transistor provides stable data storage and low standby current. The thin gate oxide layer used to read the germanium transistor provides a fast read time with a lower allowable Vcc, min. The power supplied to the read cartridge can be electrically connected to the logic portion of the device while the power supplied to the storage unit transistor can be relatively high to improve reliability. The method is used to form an SRAM cell having a double gate oxide thickness and the process steps can be compatible with current flow steps for semiconductor fabrication.

在一個實施例中，一種SRAM位元單元的裝置，包括：一半導體基板；以及至少一個SRAM位元單元，形成於上述半導體基板的一個部分。其中上述至少一個SRAM位元單元更包括具備第一閘極介電層厚度的電晶體，與具備較薄的第二閘極介電層厚度的附加電晶體，上述較薄的第二閘極介電層厚度在上述第一閘極介電層厚度的75%-99%之間。In one embodiment, an apparatus for an SRAM bit cell includes: a semiconductor substrate; and at least one SRAM bit cell formed on a portion of the semiconductor substrate. The at least one SRAM bit cell further includes a transistor having a first gate dielectric layer thickness and an additional transistor having a thinner second gate dielectric layer thickness, and the thinner second gate dielectric The thickness of the electrical layer is between 75% and 99% of the thickness of the first gate dielectric layer.

在另一個實施例中，一種SRAM位元單元的積體電路，包括：一邏輯部分，形成於半導體基板的第一部分，且具備複數電晶體，上述電晶體的其中一些具有較薄的閘極介電層；與一SRAM陣列。其中SRAM陣列包括複數個SRAM位元單元，每個SRAM位元單元形成在半導體基板的第二部分。SRAM位元單元更包括具備較厚的閘極介電層厚度的電晶體，與具備較薄的第二閘極介電層厚度的附加電晶體，上述附加電晶體電性連接至具備較厚的閘極介電層厚度的電晶體。上述較薄的第二閘極介電層厚度在上述第一閘極介電層厚度的75%-99%之間。In another embodiment, an integrated circuit of an SRAM bit cell includes: a logic portion formed on a first portion of a semiconductor substrate and having a plurality of transistors, some of the transistors having a thin gate dielectric Electrical layer; with an SRAM array. The SRAM array includes a plurality of SRAM bit cells, each SRAM cell being formed in a second portion of the semiconductor substrate. The SRAM bit cell further includes a transistor having a thicker thickness of the gate dielectric layer and an additional transistor having a thinner thickness of the second gate dielectric layer, the additional transistor being electrically connected to have a thicker A transistor with a gate dielectric thickness. The thinner second gate dielectric layer has a thickness between 75% and 99% of the thickness of the first gate dielectric layer.

在另一個實施例中，一種CAM位元單元的裝置，包括：一半導體基板；以及至少一個CAM位元單元，形成於上述半導體基板的一個部分。其中上述至少一個CAM位元單元更包括具備第一閘極介電層厚度的電晶體，與具備較薄的第二閘極介電層厚度的附加電晶體，上述較薄的第二閘極介電層厚度在上述第一閘極介電層厚度的75%-99%之間。In another embodiment, an apparatus for a CAM cell unit includes: a semiconductor substrate; and at least one CAM cell unit formed on a portion of the semiconductor substrate. The at least one CAM cell unit further includes a transistor having a first gate dielectric layer thickness and an additional transistor having a thinner second gate dielectric layer thickness, and the thinner second gate dielectric layer The thickness of the electrical layer is between 75% and 99% of the thickness of the first gate dielectric layer.

本發明內容描述了本發明部分的實施例，並非限定本發明。本發明其他附加的特徵與優點將會於在此後說明，該說明的內容構成本案申請專利範圍的標的。熟知此技藝人士可以瞭解本案的觀點與實施例可以做為基礎來修改或設計其他結構或製程來實施與本案相同目的。因此熟知此技藝人士應能瞭解相似的結構並未脫提本發明的精神與範疇，本發明的範疇將由後述的申請專利範圍所定義。This Summary describes some embodiments of the invention and is not intended to limit the invention. Additional features and advantages of the invention will be set forth in the description which follows. Those skilled in the art will appreciate that the concepts and embodiments of the present invention can be used as a basis for modifying or designing other structures or processes to achieve the same objectives as the present invention. Therefore, those skilled in the art should be able to understand the structure of the present invention without departing from the spirit and scope of the invention, and the scope of the invention will be defined by the scope of the appended claims.

本發明較佳的實施例的製作與使用方法將詳述如下。本發明所提供的許多發明應用概念可以實施於種類廣泛的特定內容中。以下所討論的特定實施例僅是描述製作與使用本發明的特定方法而非限制本發明的範疇。The method of making and using the preferred embodiment of the present invention will be described in detail below. Many of the inventive application concepts provided by the present invention can be implemented in a wide variety of specific content. The specific embodiments discussed below are merely illustrative of specific ways of making and using the invention, and not limiting the scope of the invention.

第4圖係本發明一實施例，顯示一個8T SRAM位元單元40的電路圖，其中包含了本發明的雙重閘極氧化層的特徵。在第4圖中6T儲存單元部分42具備2個如第1-3圖所示的PMOS上拉電晶體PU1與PU2，以及4個如第1-3圖所示的NMOS電晶體PG1、PG2、PD1與PD2。在此發明中，厚閘極介電層被用於形成這四個NMOS電晶體。藉由厚閘極介電層的使用，SRAM儲存單元部分42的待機電流Isb下降並且穩定度提昇。至於8T SRAM位元單元的讀取埠部分44，則相反地採用薄閘極氧化介電層。薄閘極介電層會使讀取較快並且有較低的Vcc,min。事實上在一個具備邏輯核心部份的積體電路中，讀取部分44可以與該邏輯部分一起生產並且使用該邏輯部分的薄閘極介電層與電力。因此NMOS讀取埠電晶體RPG與RPD有較快的反應時間使讀取週期較快，並且允許較低的Vcc,min使讀取動作時的耗電降低。Figure 4 is a circuit diagram showing an 8T SRAM bit cell 40 incorporating features of the dual gate oxide layer of the present invention, in accordance with an embodiment of the present invention. In Fig. 4, the 6T memory cell portion 42 is provided with two PMOS pull-up transistors PU1 and PU2 as shown in Figs. 1-3, and four NMOS transistors PG1 and PG2 as shown in Figs. PD1 and PD2. In this invention, a thick gate dielectric layer is used to form the four NMOS transistors. With the use of the thick gate dielectric layer, the standby current Isb of the SRAM memory cell portion 42 is lowered and the stability is improved. As for the read buffer portion 44 of the 8T SRAM bit cell, a thin gate oxide dielectric layer is instead used. A thin gate dielectric layer will make reading faster and have a lower Vcc, min. In fact, in an integrated circuit having a logic core portion, the read portion 44 can be produced with the logic portion and use the thin gate dielectric layer and power of the logic portion. Therefore, the NMOS read transistor RPG and the RPD have a faster reaction time to make the read cycle faster, and allow a lower Vcc, min to reduce the power consumption during the read operation.

閘極介電層可以是傳統習知技術所知的矽氧化層、二氧化矽、矽氮化物、矽氮氧化合物與其他包含矽的電介質。高k值的閘極介電層可能會被使用，例如在本發明一些實施例中，電介質包括具備或不具備矽酸鹽及氧的鉿、鋯可被使用。儲存單元部分42的薄閘極介電層厚度與讀取部分44的厚閘極介電層厚度比例可已是在0.75-0.99，較佳的選擇是0.85-0.95，而最好的選擇是0.85-0.90。在一個沒有限制的例子中，厚的閘極介電層在45奈米的半導體製程中由二氧化矽所形成。2.43奈米的閘極介電層厚度在這個例子中是由熱氧化所形成。但本發明應用於任何半導體製程並且有利於現今與規劃中的45奈米、28奈米、22奈米甚至更小尺寸的製程。The gate dielectric layer can be a tantalum oxide layer, cerium oxide, tantalum nitride, niobium oxynitride and other germanium containing dielectrics as is known in the art. High k-value gate dielectric layers may be used, for example, in some embodiments of the invention, the dielectric includes yttrium, zirconium with or without bismuth and oxygen. The thickness of the thin gate dielectric layer of the memory cell portion 42 and the thickness of the thick gate dielectric layer of the read portion 44 may have been between 0.75 and 0.99, preferably 0.85 to 0.95, and the best choice is 0.85. -0.90. In a non-limiting example, a thick gate dielectric layer is formed of hafnium oxide in a 45 nm semiconductor process. The gate dielectric thickness of 2.43 nm is formed by thermal oxidation in this example. However, the present invention is applicable to any semiconductor process and is advantageous for today's and planned 45 nm, 28 nm, 22 nm or even smaller processes.

在SRAM位元單元的實施例中，SRAM位元單元的佈局也會為了更進一步達到本發明雙重閘極氧化層厚度的優點而變更。In an embodiment of the SRAM bit cell, the layout of the SRAM bit cell will also vary in order to further achieve the advantages of the double gate oxide thickness of the present invention.

為了描述這些優點，首先顯示一個傳統具有單閘極介電層厚度的位元單元。第5圖顯示一個SRAM 8T位元單元40的平面佈局圖，其具備閘極介電層厚度為定值。第5圖中，主動區以OD表示，該主動區形成在隔離領域(例如淺層溝渠隔離STI或LOCOS隔離)之間。如同該領域知識者所熟知的，主動區包括擴散區其延伸至半導體基板並且可以摻雜來形成N或P型領域與輕摻雜的汲極領域，而主動區也可包含附加的移植來形成源極或汲極領域。主動區可以位於半導體晶圓片的表面或是位於外延形成於絕緣體(SOI)上的矽層當中。電晶體形成於位元單元區域中，其使用沈積或圖案化在介電材料(覆蓋於主動區上)上的閘極導體來形成。閘極介電層在此平面圖中無法看到，但多晶矽閘極會以PO表示。完整的電晶體會利用PO層將共用閘極端子電性連接在一起，並且會使用金屬層1。金屬層1被標示為M1。在實施例中，金屬層2也被使用並且被標示為M2，根據第5圖中的陰影鍵，金屬層2使用陰影來與其他區域區別。第2圖中每一個電晶體是例如在矽基板上。主動區OD形成MOS電晶體的源極與汲極領域。儲存單元電晶體PG1、PG2、PU1、PU2、PD1、PD2顯示於圖中並組成6T的SRAM位元單元佈局。讀取埠電晶體RPD與RPG也顯示於圖中並且形成第2圖的讀取埠電路。To describe these advantages, a conventional bit cell having a single gate dielectric layer thickness is first shown. Figure 5 shows a plan layout of an SRAM 8T bit cell 40 having a gate dielectric thickness that is constant. In Figure 5, the active region is represented by OD, which is formed between the isolation regions (e.g., shallow trench isolation STI or LOCOS isolation). As is well known to those skilled in the art, the active region includes a diffusion region that extends to the semiconductor substrate and can be doped to form an N or P-type field with a lightly doped bungee region, and the active region can also include additional implants to form Source or bungee field. The active region may be located on the surface of the semiconductor wafer or in a germanium layer epitaxially formed on the insulator (SOI). A transistor is formed in the cell unit region, which is formed using a gate conductor deposited or patterned on a dielectric material (overlying the active region). The gate dielectric layer is not visible in this plan view, but the polysilicon gate is indicated by PO. The complete transistor will electrically connect the common gate terminals together using the PO layer and will use metal layer 1. Metal layer 1 is labeled M1. In the embodiment, the metal layer 2 is also used and is denoted as M2, and according to the shadow key in Fig. 5, the metal layer 2 is shaded to distinguish it from other regions. Each of the transistors in Fig. 2 is, for example, on a germanium substrate. The active region OD forms the source and drain regions of the MOS transistor. The memory cell transistors PG1, PG2, PU1, PU2, PD1, PD2 are shown in the figure and form a 6T SRAM bit cell layout. The read germanium transistors RPD and RPG are also shown in the figure and form the read chirp circuit of FIG.

第6圖顯示第5圖中6-6’線段的剖面圖。主動區OD由隔離領域所分離，閘極介電層61覆蓋在主動區上並且位於電晶體閘極多晶矽PO下。在習知第6圖的剖面構造中，閘極介電層61在讀取部分與在6T的儲存單元皆是相同的厚度。接觸層CO的形成將金屬層1的部分M1連接至多晶矽。金屬層透過一個或多個層間介電層(ILD，未顯示)所形成的隔離體彼此隔離並且也與多晶矽隔離。氧化物、氮化物、氮氧化物與包括層間介電質的碳可以被使用於此。金屬層M1與M2可以使用沈積技術由鋁、鋁合金、銅、或銅合金等形成。當使用銅或銅合金時，如習知技術所熟知的，單鑲嵌或雙鑲嵌與CMP技術可以用來形成導體。同樣在習知技術中，內襯物質(或是所謂的BARC與ARC層)與多層間介電質可以用來形成金屬層與間隔離層。Fig. 6 is a cross-sectional view showing the 6-6' line segment in Fig. 5. The active region OD is separated by the isolation region, and the gate dielectric layer 61 covers the active region and is located under the transistor gate polysilicon PO. In the cross-sectional configuration of the conventional Fig. 6, the gate dielectric layer 61 has the same thickness in both the read portion and the 6T memory cell. The formation of the contact layer CO connects the portion M1 of the metal layer 1 to the polysilicon. The metal layer is isolated from each other by a spacer formed by one or more interlayer dielectric layers (ILD, not shown) and is also isolated from the polysilicon. Oxides, nitrides, oxynitrides, and carbon including interlayer dielectrics can be used herein. The metal layers M1 and M2 may be formed of aluminum, aluminum alloy, copper, or a copper alloy or the like using a deposition technique. When copper or copper alloys are used, single damascene or dual damascene and CMP techniques can be used to form the conductors, as is well known in the art. Also in the prior art, a lining material (either a so-called BARC and ARC layer) and an inter-layer dielectric can be used to form the metal layer and the interlayer.

金屬2的讀取位元線RBL覆蓋在8T位元單元的讀取埠上。當以這樣的傳統佈局配置，需要金屬2、通道(金屬1上的通道V1)、金屬1的部分M1、接觸層CO將讀取位元線RBL連接至位元單元。The read bit line RBL of the metal 2 is overlaid on the read 8 of the 8T bit cell. When configured in such a conventional layout, it is required that the metal 2, the channel (the channel V1 on the metal 1), the portion M1 of the metal 1, and the contact layer CO connect the read bit line RBL to the bit cell.

第7圖顯示一個使用本發明技術特徵的8T的位元單元70的平面佈局圖。第7圖的平面圖是顯示第4圖的電路實施例的一非限定的佈局方式。該電路當然也可使用其他佈局方式，而這些變化的佈局都可視為本發明附加的實施例。第7圖中，6T的儲存單元72與形成於OD層內的主動區一起佈局，單元的範圍由隔離領域如STI所界定。電晶體的閘極以多晶矽形成並且覆蓋在閘極介電層上(圖中無法看出)。NMOS電晶體PG1、PD1、PD2與PG2電性連接至兩個PMOS上拉電晶體PU1與PU2。單元的讀取埠74的配置鄰接與電性連接至6T單元72，如同第4圖的電路圖。讀取埠中的兩個NMOS電晶體分別是讀取下拉電晶體RPD與讀取傳導閘RPG，兩者皆為NMOS電晶體。Figure 7 shows a plan layout of an 8T bit cell 70 using the features of the present invention. The plan view of Fig. 7 is a non-limiting layout showing the circuit embodiment of Fig. 4. Other layouts may of course be used with the circuit, and variations of these variations may be considered as additional embodiments of the invention. In Fig. 7, the storage unit 72 of 6T is laid out together with the active area formed in the OD layer, and the range of the unit is defined by the isolation field such as STI. The gate of the transistor is formed of polysilicon and overlies the gate dielectric (not visible in the figure). The NMOS transistors PG1, PD1, PD2 and PG2 are electrically connected to the two PMOS pull-up transistors PU1 and PU2. The configuration of the read buffer 74 of the unit is contiguous and electrically connected to the 6T unit 72, as in the circuit diagram of FIG. The two NMOS transistors in the read 埠 are the read pull-down transistor RPD and the read transfer gate RPG, both of which are NMOS transistors.

除了兩個不同厚度的閘極介電層的使用(厚的閘極介電層使用於6T的儲存單元72讀NMOS電晶體內，薄的閘極介電層使用於讀取部分74內的讀取埠NMOS電晶體內)，第7圖所示的單元佈局實施例也包括了改善的讀取位元線構造。在這個實施例中，讀取位元線RBL由金屬層1(以M1表示)所形成。如以下即將說明的，藉由限制讀取位元線的金屬化，使其僅為金屬1連接至讀取單元的讀取埠(如同讀取傳導閘電晶體RPG只有一個接觸層，沒有其他介於其間的通道)，讀取位元線RBL的電容與讀取速度比起傳統位元單元的佈局有大幅地改善。In addition to the use of two different thickness gate dielectric layers (a thick gate dielectric layer is used in the 6T memory cell 72 to read the NMOS transistor, a thin gate dielectric layer is used in the read portion 74 for reading The cell layout embodiment shown in Figure 7 also includes an improved read bit line configuration. In this embodiment, the read bit line RBL is formed of a metal layer 1 (indicated by M1). As will be explained below, by limiting the metallization of the read bit line, it is only the read 埠 of the metal 1 connected to the read cell (like reading the conductive gate transistor RPG has only one contact layer, no other media In the channel therebetween, the capacitance and read speed of the read bit line RBL are greatly improved compared to the layout of the conventional bit cell.

第8圖顯示第7圖的佈局圖中8-8’線段的剖面圖。 第8圖中，主動區OD由隔離氧化物所界定。覆蓋在主動區上方6T的位元單元區域內的是具有第1厚度的閘極介電層61。覆蓋在主動區上方的讀取部分內的是閘極介電層62，具有較薄的第2閘極厚度。薄閘極介電層與厚閘極介電層的比例可以有很多種變化，在此視為不同的實施例。薄閘極厚度可以是0.75-0.99倍的厚閘極厚度。較佳的是該比例為0.85-0.99、0.85-0.95、甚至是0.85-0.90倍。其他的範例可包括0.75-0.95、0.75-0.90、0.75-0.80倍。讀取埠中薄的介電層的重要優點是允許讀取埠電晶體以較高的速度切換，並且以較低的Vcc,min操作。這對8T電路的讀取埠而言更為重要。將厚的介電層使用於6T儲存單元部分中對單元的穩定性而言相當重要，並且也提供了SRAM單元(包括儲存節點)的寫入部分的較低待機漏電流Isb。相對於以傳統方法所實行的同樣的單元，結合兩個不同介電層厚度的NMOS電晶體於一個SRAM位元單元提供了明顯的省電與與表現上的優點。另外，相較於薄介電層厚度的電晶體而言，供應至6T的SRAM單元部分的電力可以操作於較高的Vcc,min位準。因為讀取動作比寫入頻繁許多，讀取Vcc,min更為重要。較高的Vcc,min位準供應至6T儲存陣列改善了電路儲存部分的穩定性與可靠性。Figure 8 is a cross-sectional view showing the 8-8' line segment in the layout of Figure 7. In Figure 8, the active region OD is defined by an isolating oxide. Covering the bit cell region 6T above the active region is a gate dielectric layer 61 having a first thickness. Covering the read portion above the active region is a gate dielectric layer 62 having a thinner second gate thickness. The ratio of thin gate dielectric layer to thick gate dielectric layer can vary widely and is considered herein as a different embodiment. The thin gate thickness can be a thick gate thickness of 0.75-0.99 times. Preferably, the ratio is from 0.85 to 0.99, from 0.85 to 0.95, or even from 0.85 to 0.90. Other examples may include 0.75-0.95, 0.75-0.90, 0.75-0.80 times. An important advantage of reading a thin dielectric layer in the crucible is that it allows the read germanium transistor to switch at a higher speed and operates at a lower Vcc, min. This is even more important for the reading of 8T circuits. The use of a thick dielectric layer in the 6T memory cell portion is important for the stability of the cell and also provides a lower standby leakage current Isb for the write portion of the SRAM cell (including the storage node). Combining two different dielectric layer thickness NMOS transistors provides significant power savings and performance advantages over an SRAM cell unit, as opposed to the same cells implemented in conventional methods. In addition, the power supplied to the 6T SRAM cell portion can operate at a higher Vcc,min level than a thin dielectric layer thickness transistor. Because the read action is much more frequent than the write, reading Vcc,min is more important. The higher Vcc, min level supply to the 6T storage array improves the stability and reliability of the circuit storage portion.

而第8圖的剖面圖顯示金屬1讀取位元線RBL覆蓋在電路的讀取部分上。一個單一接觸層CO也位於金屬層1與讀取傳導電晶體RPG的多晶矽閘極之間。The cross-sectional view of Fig. 8 shows that the metal 1 read bit line RBL is overlaid on the read portion of the circuit. A single contact layer CO is also located between the metal layer 1 and the polysilicon gate of the read conduction transistor RPG.

另外一張圖更好地顯示出使用單一金屬層讀取位元線比起傳統8T的位元單元佈局的優點。第9圖顯示了傳統金屬2讀取位元線的佈局剖面圖，並且也顯示了連接至主動區需要將金屬2讀取位元線電性連接至讀取傳導閘的汲極端子。在傳統的配置中金屬2讀取位元線透過通道1(金屬1上的通道)電性連接至金屬層1。接著透過接觸層CO電性連接至主動區，該主動區對應讀取傳導閘(RPG)電晶體的一個端子。因此，電容路徑包括金屬2、V1層的通道、金屬1、接觸層CO、與主動區OD上的接觸阻抗。The other figure better shows the advantage of using a single metal layer to read the bit line compared to the traditional 8T bit cell layout. Figure 9 shows a layout cross-section of a conventional metal 2 read bit line, and also shows that the connection to the active region requires the metal 2 read bit line to be electrically connected to the read terminal of the read conduction gate. In the conventional configuration, the metal 2 read bit line is electrically connected to the metal layer 1 through the channel 1 (the channel on the metal 1). Then, the contact layer CO is electrically connected to the active region, and the active region corresponds to one terminal of the read conduction gate (RPG) transistor. Therefore, the capacitance path includes the metal 2, the V1 layer channel, the metal 1, the contact layer CO, and the contact impedance on the active region OD.

第10圖顯示實施例的讀取位元線構造的剖面圖。第10圖中，金屬層1讀取位元線RBL覆蓋並且接觸單一接觸層CO，接觸層CO接觸主動區OD的表面。因此，阻抗路徑只包括金屬1 M1、單一接觸層CO、與主動區上的接觸阻抗。Fig. 10 is a cross-sectional view showing the configuration of the read bit line of the embodiment. In Fig. 10, the metal layer 1 is read by the bit line RBL and contacts the single contact layer CO, and the contact layer CO contacts the surface of the active region OD. Therefore, the impedance path only includes the metal 1 M1, the single contact layer CO, and the contact impedance on the active region.

第11圖顯示一電性模擬比較的結果，該比較對象為傳統半導體製程形成第9圖金屬2讀取位元線的連接配置與本發明金屬1結構的實施例(例如第10圖所示)。如第11圖所示，實施例的結構相對於傳統方法在電阻的減低上有28%的改善，並且有相對應的讀取速度的增加。Fig. 11 is a view showing the result of an electrical analog comparison, which is a conventional semiconductor process for forming a connection arrangement of the metal 2 read bit line of Fig. 9 and an embodiment of the metal 1 structure of the present invention (for example, Fig. 10). . As shown in Fig. 11, the structure of the embodiment has a 28% improvement in resistance reduction with respect to the conventional method, and there is an increase in the corresponding reading speed.

第12圖顯示將4個8T的位元單元70配置在一起的實施例的佈局圖。如第12圖所示，位元單元70可以透過由左到右垂直地重疊與由上至下水平地重疊來有效封裝在一起。這個配置使得每個單元較薄的閘極介電層裝置RPD與RPG處於陣列中央的共通區域，而6T的儲存單元的較厚的閘極介電層裝置共用主動區OD並且形成在陣列的尾端。當實行介電層沈積步驟的製程時，使用光罩與光阻技術來隔離區塊是較簡易的方法。在一個簡單的實行方法中，製程可以先沈積閘極介電層在一個區域，然後再沈積在另外一個區域，藉此形成不同的閘極介電層厚度。Figure 12 shows a layout of an embodiment in which four 8T bit cells 70 are arranged together. As shown in Fig. 12, the bit cell 70 can be effectively packaged by vertically overlapping from left to right and horizontally overlapping from top to bottom. This configuration allows the thinner gate dielectric devices RPD and RPG of each cell to be in the common region in the center of the array, while the thicker gate dielectric device of the 6T memory cell shares the active region OD and is formed at the end of the array. end. When the process of the dielectric layer deposition step is performed, it is a relatively simple method to use the reticle and photoresist technology to isolate the blocks. In a simple implementation, the process can deposit a gate dielectric layer in one region and then another region, thereby forming different gate dielectric thicknesses.

另外，做為本發明另一個實施例(取代厚的介電層形成於SRAM陣列的一個部分，薄的介電層形成於相同陣列的讀取部分)，兩個不同的閘極介電層可以使用較高及較低的介電常數。較高介電常數的介電層可用於6T的儲存單元來提供高穩定性與低待機漏電流。較低介電常數的介電層可用於位元單元的讀取部分來提供低Vcc,min與較快的讀取速度。使用金屬1讀取位元資料線於讀取部分，再加上使用兩個不同厚度的閘極介電層，形成了相對於傳統技術而言可提供附加表現優點的實施例。In addition, as another embodiment of the present invention (instead of forming a thick dielectric layer formed in one portion of the SRAM array, a thin dielectric layer is formed on the read portion of the same array), two different gate dielectric layers may be used. Use higher and lower dielectric constants. A higher dielectric constant dielectric layer can be used for the 6T memory cell to provide high stability and low standby leakage current. A lower dielectric constant dielectric layer can be used for the read portion of the bit cell to provide low Vcc, min and faster read speed. The use of metal 1 to read the bit data lines to the read portion, coupled with the use of two different thickness gate dielectric layers, provides an embodiment that provides additional performance advantages over conventional techniques.

第13圖顯示10T位元單元60的實施例佈局圖。在第13圖中，佈局部分64的構造與前述6T位元單元的構造相似。10T的單元具有兩個讀取埠，兩者分別位於單元的兩端，且兩者皆與前述的8T的位元儲存單元的讀取埠相似。在部分62中的閘極介電層厚度較部分64內的閘極介電層厚度薄，與先前8T的位元單元相同。因此讀取電晶體比起寫入電晶體具有較快的速度與較低的Vt。Figure 13 shows a layout of an embodiment of a 10T bit cell 60. In Fig. 13, the configuration of the layout portion 64 is similar to that of the aforementioned 6T bit unit. The 10T unit has two read ports, both of which are located at both ends of the unit, and both are similar to the read ports of the aforementioned 8T bit storage unit. The thickness of the gate dielectric layer in portion 62 is thinner than the thickness of the gate dielectric layer in portion 64, which is the same as the previous 8T bit cell. Therefore, reading the transistor has a faster speed and a lower Vt than writing the transistor.

第14圖顯示使用金屬1(M1)於對應第13圖的10T單元的佈局圖。第14圖中，可以看到金屬1(M1)讀取位元線RBL0與RBL1在10T單元的兩端。如上所述，藉由對讀取部分限制金屬1讀取位元線，使其與單元之間僅有一個接觸層間隔並且無其他通道，讀取路徑的電容會降低，SRAM單元的讀取時間也會改善。Fig. 14 is a plan view showing the use of the metal 1 (M1) in the 10T unit corresponding to Fig. 13. In Fig. 14, it can be seen that the metal 1 (M1) read bit lines RBL0 and RBL1 are at both ends of the 10T cell. As described above, by reading the bit line of the read portion metal 1 so that there is only one contact layer interval between the cells and no other channels, the capacitance of the read path is lowered, and the read time of the SRAM cell is reduced. Will also improve.

第15圖顯示一個位元單元的配置，該配置也受益於本發明實施例的使用。內容定址記憶體(content addressable memory,CAM)單元73顯示於第15圖中。CAM單元的選擇是藉由提供資料字元給記憶體，接著記憶體回覆找到配對資料字元的位址來實行。該電路具有6T的電晶體，從電晶體與佈局的觀點來看，與6T的SRAM單元相當相似。在第15圖中，CAM單元具有一對互補的選擇線SL與SL_(其動作類似於SRAM陣列中的讀取位元線RBL)，與一輸出線ML。CAM單元73的兩邊分別有一對反向器，由兩個上拉(PMOS)裝置與兩個下拉(NMOS)裝置形成，其連接用來維持儲存節點的資料。CAM單元73的兩邊也分別有一個讀取下拉電晶體(NMOS M3或M4)及一個選擇閘極電晶體(NMOS M1或M2)。因此，此領域的知識者可以瞭解CAM單元具有與SRAM 10位元單元相同的特徵，其中儲存部分由上拉與下拉電晶體組成，兩者電性連接來鎖存資料，而讀取部分包括串聯在一起的2個NMOS電晶體。因為這些相似點，使用厚的閘極氧化層於儲存反向器部分與使用薄的閘極氧化層於電晶體M1、M2、M3、M4，會獲得與上述SRAM位元單元的應用相似的優點。Figure 15 shows the configuration of a bit cell that also benefits from the use of embodiments of the present invention. A content addressable memory (CAM) unit 73 is shown in Fig. 15. The selection of the CAM unit is performed by providing a data character to the memory, and then the memory replying to find the address of the paired data character. The circuit has a 6T transistor, which is quite similar to a 6T SRAM cell from a transistor and layout point of view. In Fig. 15, the CAM cell has a pair of complementary select lines SL and SL_ (which behaves like the read bit line RBL in the SRAM array), and an output line ML. The CAM unit 73 has a pair of inverters on each side, formed by two pull-up (PMOS) devices and two pull-down (NMOS) devices connected to maintain the data of the storage node. The CAM unit 73 also has a read pull-down transistor (NMOS M3 or M4) and a select gate transistor (NMOS M1 or M2) on each side. Therefore, those skilled in the art can understand that the CAM unit has the same characteristics as the SRAM 10-bit unit, wherein the storage portion is composed of pull-up and pull-down transistors, which are electrically connected to latch data, and the read portion includes series connection. Two NMOS transistors together. Because of these similarities, the use of a thick gate oxide layer in the storage inverter portion and the use of a thin gate oxide layer on the transistors M1, M2, M3, M4 results in similar advantages to the application of the above SRAM bit cell. .

第16圖顯示使用主動區OD、多晶矽導體PO、金屬1 M1與接觸層CO於第15圖的CAM單元的佈局實施例。第15圖中的讀取電晶體M1、M2、M3、M4的閘極導體顯示在右側的部分75。如同前述10T單元與8T單元，在這個實施例中，相對於讀取與儲存部分71的電晶體，讀取部分75的電晶體具備較薄的閘極介電層或較薄的等效氧化物厚度。儲存部分71的NMOS電晶體具備較厚的閘極介電層，或在其他的實施例中具備較厚的等效氧化物厚度。這個配置的優點相當於前述SRAM單元使用此配置的優點：較快取時間、較低待機漏電流、改善的Vcc,min。Figure 16 shows a layout embodiment of the CAM cell of Figure 15 using active region OD, polysilicon conductor PO, metal 1 M1 and contact layer CO. The gate conductors of the read transistors M1, M2, M3, M4 in Fig. 15 are shown on the right portion 75. Like the aforementioned 10T unit and 8T unit, in this embodiment, the transistor of the read portion 75 has a thinner gate dielectric layer or a thinner equivalent oxide with respect to the transistor of the read and storage portion 71. thickness. The NMOS transistor of the storage portion 71 has a thicker gate dielectric layer or, in other embodiments, a thicker equivalent oxide thickness. The advantage of this configuration is equivalent to the advantages of the aforementioned SRAM cell using this configuration: faster cache time, lower standby leakage current, improved Vcc, min.

上述的實施例是關係到SRAM位元單元使用平面MOS電晶體的範疇。在其他也視為本發明一部分的實施例當中，多重閘極電晶體(如finFET)可以使用於上述電路當中。一個三維結構的finFET裝置80顯示於第17圖。FinFET形成在半導體鰭(fin)上，該鰭包括源極、汲極與LDD擴散區，藉此形成MOS裝置的通道與源極、汲極端子。閘極介電層可以形成在垂直面(形成雙閘極裝置)上或在整個暴露的鰭表面(形成三重閘極裝置)上。藉由延伸在鰭的高度或寬度上的閘極寬度，該裝置可以具有較大的寬長比，並且不消耗矽的面積。複數的鰭裝置也可以形成並且連接在一起，藉此增加半導體的尺寸。閘極導體一般以垂直且劃過鰭的方式形成，並且覆蓋在閘極介電層上，藉此完成MOS裝置的閘極結構。The above embodiments are related to the category of SRAM bit cells using planar MOS transistors. In other embodiments that are also considered to be part of the present invention, multiple gate transistors (e.g., finFETs) can be used in the above described circuits. A three-dimensional finFET device 80 is shown in FIG. The FinFET is formed on a semiconductor fin that includes a source, a drain, and an LDD diffusion region, thereby forming a channel and a source, a drain terminal of the MOS device. The gate dielectric layer can be formed on a vertical plane (forming a dual gate device) or over the entire exposed fin surface (forming a triple gate device). By extending the width of the gate over the height or width of the fin, the device can have a large aspect ratio and does not consume the area of the crucible. A plurality of fin devices can also be formed and connected together, thereby increasing the size of the semiconductor. The gate conductor is generally formed vertically and across the fin and overlies the gate dielectric layer, thereby completing the gate structure of the MOS device.

第18圖中，顯示了第17圖的finFET的剖面圖。閘極(多晶矽或其他未知閘極導體材料)具備隔離體側牆SW。鰭包括源極、汲極的植入以及輕摻雜的汲極擴散區，並且在摻雜區的上方具有矽化物。要注意的是當每個矽區域面積所使用的finFET具有比實施例的平面電晶體大的尺寸，閘極介電層可以是相同厚度或是不同厚度。這是因為在相同的矽區域面積下，finFET的表現特性比平面電晶體好。In Fig. 18, a cross-sectional view of the finFET of Fig. 17 is shown. The gate (polysilicon or other unknown gate conductor material) is provided with a spacer side wall SW. The fin includes a source, a drain of the drain, and a lightly doped drain diffusion region, and has a germanide over the doped region. It is to be noted that the finFET used in each of the germanium regions has a larger size than the planar transistor of the embodiment, and the gate dielectric layers may be the same thickness or different thicknesses. This is because the performance of the finFET is better than that of the planar transistor under the same area of the germanium region.

在第19圖中，顯示了雙埠8T位元單元的實施例，並且該圖中表示如何將finFET用來改善位元單元的表現特性。佈局90顯示了前述8T的SRAM單元的主動區與多晶矽閘極。區域91是儲存節點與寫入部分，區域92是讀取埠。在先前的實施例，寫入部分的平面電晶體具備較厚的閘極介電層，讀取部分則是較薄的閘極介電層以獲得快速讀取時間。在本實施例中，讀取埠電晶體RPG與RPD形成finFET裝置95。在這個情況下，一個SRAM位元單元有兩種不同電晶體形式也可以獲得快速讀取時間、低Vcc,min等優點。其中平面MOS形式電晶體93使用於儲存節點電晶體與寫入部分91，finFET電晶體95使用於8T位元單元的讀取埠。In Fig. 19, an embodiment of a double-turn 8T bit cell is shown, and the figure shows how the finFET is used to improve the performance characteristics of the bit cell. Layout 90 shows the active region and polysilicon gate of the aforementioned 8T SRAM cell. The area 91 is a storage node and a write portion, and the area 92 is a read port. In the previous embodiment, the write portion of the planar transistor has a thicker gate dielectric layer and the read portion is a thinner gate dielectric layer to achieve fast read times. In the present embodiment, the germanium transistor RPG and the RPD are read to form the finFET device 95. In this case, an SRAM bit cell can have two different transistor forms and can also obtain fast read time, low Vcc, min and the like. The planar MOS form transistor 93 is used for the storage node transistor and the write portion 91, and the finFET transistor 95 is used for the read 8 of the 8T bit cell.

當然本非限定的實施例也可以延伸應用至前述的10T的SRAM位元單元與CAM位元單元中。finFET的應用可具備均勻的閘極介電層厚度並且使用相同的閘極介電材料做為平面電晶體。而實施例中使用的finFET當形成於SOI層中會較為有利，因為矽鰭會垂直地延伸於表面上且源極與汲極區會形成於鰭本身。Of course, this non-limiting embodiment can also be extended to the aforementioned 10T SRAM bit unit and CAM bit unit. The finFET application can have a uniform gate dielectric thickness and use the same gate dielectric material as a planar transistor. The finFET used in the embodiment, when formed in the SOI layer, is advantageous because the skeletal fins extend perpendicularly to the surface and the source and drain regions are formed on the fin itself.

另外其他的實施例包括使用不同的閘極介電層厚度於finFET裝置當中(相較於平面MOS裝置而言)的情況。其他的實施例包括使用高k介電係數於平面MOS裝置或finFET裝置兩者或其中之一。除此之外，finFET裝置可以是雙重閘極、三重閘極或多重閘極，並且可以包括多個鰭(如第19圖所示)。當然單一鰭的裝置也視為本發明的一個實施例。Still other embodiments include the use of different gate dielectric thicknesses in finFET devices (as compared to planar MOS devices). Other embodiments include the use of a high k dielectric coefficient in either or both of a planar MOS device or a finFET device. In addition, the finFET device can be a double gate, a triple gate, or multiple gates, and can include multiple fins (as shown in Figure 19). Of course, a single fin device is also considered an embodiment of the invention.

在一個實施例中，提出一個具備半導體基板的裝置，其中至少一個8T的SRAM位元單元具備雙重閘極氧化層厚度NMOS電晶體與一個讀取埠。In one embodiment, an apparatus is provided having a semiconductor substrate in which at least one 8T SRAM cell unit is provided with a double gate oxide thickness NMOS transistor and a read NMOS.

在另一個實施例中，提供一個積體電路，包括：一個半導體基板；至少一個8T的SRAM位元單元，其具備雙重閘極氧化層厚度NMOS電晶體與一個讀取埠。該實施例並且提供一個佈局圖，其中讀取埠的讀取位元線被限制在第一階層的金屬化於層間介電層上，並且沒有其他介於其間的通道。因此該實施例提供了結合了雙重閘極‧氧化層SRAM位元單元的附加表現優點。In another embodiment, an integrated circuit is provided comprising: a semiconductor substrate; at least one 8T SRAM bit cell having a double gate oxide thickness NMOS transistor and a read 埠. This embodiment also provides a layout in which the read bit lines of the read defects are confined to the first level of metallization on the interlayer dielectric layer and there are no other intervening channels. This embodiment therefore provides an additional performance advantage of combining a dual gate ‧ oxide SRAM bit cell.

在另一個實施例中，提供一個積體電路，包括：一個半導體基板；至少一個10T的SRAM位元單元，其具備雙重閘極氧化層厚度NMOS電晶體與一個雙讀取埠。雙讀取埠中的NMOS電晶體具有的氧化層厚度比儲存單元電晶體的氧化層厚度薄。In another embodiment, an integrated circuit is provided comprising: a semiconductor substrate; at least one 10T SRAM bit cell having a double gate oxide thickness NMOS transistor and a double read 埠. The NMOS transistor in the double read 埠 has an oxide layer thickness that is thinner than the oxide layer thickness of the memory cell.

在另一個實施例中，一個佈局圖中包括具有雙重閘極氧化層厚度的10T的SRAM位元單元，其中雙讀取埠的讀取位元線被限制在第一層的金屬化於層間介電層上，並且沒有其他介於其間的通道。因此該實施例提供了結合了雙重閘極氧化層10T的SRAM位元單元的附加表現優點。In another embodiment, a layout diagram includes a 10T SRAM cell with a double gate oxide thickness, wherein the double read 埠 read bit line is limited to the first layer of metallization to the interlayer. On the electrical layer, there are no other channels in between. This embodiment therefore provides an additional performance advantage of the SRAM bit cell incorporating the dual gate oxide layer 10T.

在另一個實施例中，提供了一種方法，包括在半導體基板上定義出8T的SRAM位元單元佈局；在SRAM位元單元區域的一個部分形成具備六個電晶體的6T SRAM部分，該部分包括兩個NMOS傳導閘與兩個NMOS下拉電晶體；在位元單元區域的讀取部分形成一個讀取埠，包括一個NMOS傳導閘與一個NMOS下拉電晶體；使6T的位元單元部分的4個NMOS電晶體的閘極氧化層厚度比讀取部分的兩個電晶體的閘極氧化層厚度厚；並且形成第1金屬層讀取位元線覆蓋並且接觸讀取部分，其間沒有任何其他的通道，藉此提供降低的電容與提昇的表現特性。In another embodiment, a method is provided comprising defining an 8T SRAM bit cell layout on a semiconductor substrate; forming a 6T SRAM portion having six transistors in a portion of the SRAM bit cell region, the portion including Two NMOS conduction gates and two NMOS pull-down transistors; forming a read 埠 in the read portion of the bit cell region, including an NMOS conduction gate and an NMOS pull-down transistor; making 4 of the 6T bit cell portions The gate oxide layer thickness of the NMOS transistor is thicker than the gate oxide layer thickness of the two transistors of the read portion; and the first metal layer read bit line is formed to cover and contact the read portion without any other channel therebetween Thereby providing reduced capacitance and improved performance characteristics.

在另一個實施例中，提供了一種方法，包括在半導體基板上定義出10T的SRAM位元單元佈局；在SRAM位元單元區域的一個部分形成具備六個電晶體的6T SRAM儲存單元部分，該部分包括兩個NMOS傳導閘與兩個NMOS下拉電晶體；在位元單元區域的第一讀取部分與第二讀取部分分別形成一個讀取埠，包括一個NMOS傳導閘與一個NMOS下拉電晶體；使6T的位元單元部分的4個NMOS電晶體的閘極氧化層厚度比兩個讀取部分的電晶體的閘極氧化層厚度厚；並且分別形成第1金屬層讀取位元線覆蓋並且接觸兩個讀取部分，其間沒有任何其他的通道，藉此提供降低的電容與提昇的表現特性。In another embodiment, a method is provided comprising defining a 10T SRAM bit cell layout on a semiconductor substrate; forming a 6T SRAM memory cell portion having six transistors in a portion of the SRAM bit cell region, The portion includes two NMOS conduction gates and two NMOS pull-down transistors; a first read portion and a second read portion respectively form a read 埠 in the bit cell region, including an NMOS conductive gate and an NMOS pull-down transistor Making the gate oxide layer thickness of the four NMOS transistors of the 6T bit cell portion thicker than the gate oxide layer thickness of the two read portions of the transistor; and forming the first metal layer read bit line line respectively And the two read portions are contacted without any other channels therebetween, thereby providing reduced capacitance and improved performance characteristics.

在另一個實施例中，提供了一個SRAM位元單元，其具備兩種不同的閘極介電材料。8T的SRAM位元單元中的儲存單元與寫入部分具有第一閘極介電層(等效於第一氧化物厚度)。SRAM位元單元中的讀取部分具有第二閘極介電層(等效於較薄的第二氧化物厚度)。在另一個實施例中，這些閘極介電層其中之一的材料可以是氧化物。在另一個實施例中，這些閘極介電層其中之一的材料是高k介電係數的閘極介電材料。在另外的實施例中，讀取位元線以第1金屬層形成，並且僅以1個接觸層連接至8T的SRAM單元的讀取部分，其間沒有任何其他的通道。In another embodiment, an SRAM bit cell is provided that is provided with two different gate dielectric materials. The memory cell and the write portion of the 8T SRAM cell have a first gate dielectric layer (equivalent to the first oxide thickness). The read portion of the SRAM bit cell has a second gate dielectric layer (equivalent to a thinner second oxide thickness). In another embodiment, the material of one of the gate dielectric layers may be an oxide. In another embodiment, the material of one of the gate dielectric layers is a high-k dielectric gate dielectric material. In a further embodiment, the read bit line is formed with a first metal layer and is connected to the read portion of the 8T SRAM cell with only one contact layer without any other channels therebetween.

在另一個實施例中，提供了一個CAM位元單元，其具備第一儲存節點部分與第二讀取部分。在一個CAM位元單元的實施例中，儲存節點部分包括具有第一較厚閘極介電質的電晶體，讀取部分包括具有第二較薄閘極介電質的電晶體。在另一個實施例中，CAM位元單元具備的讀取位元線以第1金屬層形成，並且透過一個接觸層連接至讀取部分，其間沒有任何其他的通道或其他金屬層。在另一個實施例中，CAM位元單元在讀取部分的電晶體是多重閘極電晶體。在另一個實施例中，CAM位元單元的電晶體具備高k介電係數的閘極介電層與其他介電層。In another embodiment, a CAM bit cell is provided having a first storage node portion and a second read portion. In an embodiment of a CAM cell unit, the storage node portion includes a transistor having a first thicker gate dielectric and the read portion includes a transistor having a second, thinner gate dielectric. In another embodiment, the CAM bit cell has a read bit line formed as a first metal layer and connected to the read portion through a contact layer without any other vias or other metal layers therebetween. In another embodiment, the CAM cell in the read portion of the transistor is a multiple gate transistor. In another embodiment, the transistor of the CAM cell unit has a gate dielectric layer with a high k dielectric coefficient and other dielectric layers.

在另一個高速位元單元的配置當中，8T的SRAM位元單元、10T的SRAM位元單元或CAM單元具有兩個部分：位元單元儲存部分與讀取部分。在儲存部分中，提供了平面CMOS電晶體，在讀取部分中，提供了finFET電晶體。讀取部分的電晶體給讀取部分帶來較高的操作速度的優點。finFET電晶體包括(非限定)：雙重閘極、三重閘極與多重閘極單元。In another configuration of the high speed bit cell, the 8T SRAM bit cell, the 10T SRAM bit cell or the CAM cell has two parts: a bit cell storage portion and a read portion. In the storage portion, a planar CMOS transistor is provided, and in the read portion, a finFET transistor is provided. Reading the portion of the transistor gives the read portion the advantage of a higher operating speed. The finFET transistor includes (non-limiting): a double gate, a triple gate, and a multiple gate unit.

在另一個實施例中，SRAM位元單元(不論8T、10T、其他或CAM位元單元)形成在一外延的絕緣層覆矽(Silicon over insulator,SOI)層上。在這個實施例中，可以沿用任何其他實施例的特徵。也就是說，在一個實施例當中，8T位元單元具備讀取部分(包括儲存節點)與寫入部分形成於SOI層。寫入部分的電晶體具有第一閘極介電層厚度。讀取部分的電晶體具有第二較薄的閘極介電層厚度。在另一個實施例中，寫入部分具有高k介電係數的閘極介電層(等效於第一氧化層厚度)，讀取部分具有高k介電係數的閘極介電層(等效於第二氧化層厚度，較第第一氧化層厚度薄)，在另一個實施例中，讀取部分具有氧化介電層而寫入部分具有高k介電係數的閘極介電層，反之亦然。在另一個實施例中，寫入部分與讀取部分的閘極介電質可以有相同厚度，但以不同材質形成。在另一個實施例中，寫入部分具有第一電晶體形式而讀取部分具有第二電晶體形式。在這個SOI單元非限定的例子中，第二電晶體形式可以是finFET電晶體。In another embodiment, SRAM bit cells (whether 8T, 10T, other or CAM bit cells) are formed on an epitaxial Silicon over insulator (SOI) layer. In this embodiment, the features of any other embodiment can be used. That is, in one embodiment, the 8T bit cell is provided with a read portion (including a storage node) and a write portion formed at the SOI layer. The transistor of the write portion has a first gate dielectric layer thickness. The read portion of the transistor has a second, thinner gate dielectric thickness. In another embodiment, the write portion has a gate dielectric layer of high k dielectric constant (equivalent to the thickness of the first oxide layer), and the read portion has a gate dielectric layer with a high k dielectric constant (etc. In effect, the thickness of the second oxide layer is thinner than the thickness of the first oxide layer. In another embodiment, the read portion has an oxide dielectric layer and the write portion has a gate dielectric layer having a high k dielectric coefficient. vice versa. In another embodiment, the gate dielectric of the write portion and the read portion may have the same thickness but be formed of different materials. In another embodiment, the write portion has a first transistor form and the read portion has a second transistor form. In a non-limiting example of this SOI unit, the second transistor form can be a finFET transistor.

雖然本發明的實施例與其優點已詳術地說明，然而在不脫離本發明如申請專利範圍所定義的精神與範疇下，不同形式的變更、置換與更動皆可實行。例如，熟知本技術領域的人士可輕易地瞭解在本發明的範疇下仍有許多可變動的地方。While the embodiments of the present invention and its advantages have been described in detail, various modifications, substitutions and changes can be made without departing from the spirit and scope of the invention as defined by the appended claims. For example, those skilled in the art will readily appreciate that there are many variations that are possible within the scope of the present invention.

再者，本發明應用的觀點並沒有限制於說明書中所述的特定方法或步驟的實施例。任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程及步驟。Furthermore, the application of the present invention is not limited to the embodiments of the specific methods or steps described in the specification. Any one of ordinary skill in the art can understand the processes and steps that are currently or in the future, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein. In the present invention. Accordingly, the scope of the invention includes the above-described processes and steps.

10、42、72‧‧‧6T的SRAM位元單元10 , SRAM bit unit of 42, 72‧‧‧6T

12、40、70‧‧‧8T的SRAM位元單元12, 40, 70‧‧‧8T SRAM bit cells

14、22、24、44、74‧‧‧讀取埠14, 22, 24, 44, 74‧‧‧ read 埠

20、60‧‧‧10T的SRAM位元單元20, 60‧‧‧10T SRAM bit unit

61、62‧‧‧閘極介電層61, 62‧‧‧ gate dielectric layer

64‧‧‧佈局部分64‧‧‧Layout section

71‧‧‧儲存部分71‧‧‧Storage section

73‧‧‧CAM單元73‧‧‧ CAM unit

75‧‧‧讀取部分75‧‧‧Read section

80‧‧‧三維結構的finFET裝置80‧‧‧Three-dimensional structure of finFET device

91‧‧‧寫入部分91‧‧‧written part

92‧‧‧讀取部分92‧‧‧Read section

93‧‧‧平面MOS形式電晶體93‧‧‧Flat MOS form transistor

95‧‧‧finFET電晶體95‧‧‧finFET transistor

PU1、PU2‧‧‧上拉電晶體PU1, PU2‧‧‧ pull-up crystal

PD1、PD2‧‧‧下拉電晶體PD1, PD2‧‧‧ pull-down transistor

PG1、PG2‧‧‧MOS傳導閘PG1, PG2‧‧‧ MOS conduction gate

BL、BLB、WBL、WBLB‧‧‧位元線BL, BLB, WBL, WBLB‧‧‧ bit line

WL、WWL‧‧‧字元線WL, WWL‧‧‧ character line

RBL‧‧‧讀取位元線RBL‧‧‧Read bit line

RWL‧‧‧讀取字元線RWL‧‧‧Read word line

RPG、RPG1、RPG2‧‧‧讀取埠傳導閘電晶體RPG, RPG1, RPG2‧‧‧ read 埠 conduction gate transistor

RPD、RPD1、RPD2‧‧‧讀取埠下拉電晶體RPD, RPD1, RPD2‧‧‧ read 埠 pull-down transistor

SN1、SN2‧‧‧儲存節點SN1, SN2‧‧‧ storage node

OD‧‧‧主動區OD‧‧‧active area

PO‧‧‧多晶矽閘極PO‧‧‧ polysilicon gate

M1‧‧‧金屬1M1‧‧‧Metal 1

M2‧‧‧僅屬2M2‧‧‧ is only 2

V1、Via‧‧‧通道V1, Via‧‧‧ channel

CO‧‧‧接觸層CO‧‧‧ contact layer

第1圖顯示一習知技術的SRAM位元單元電路。Figure 1 shows a conventional SRAM bit cell circuit.

第2圖顯示一習知技術的8T的SRAM位元單元電路。Figure 2 shows a prior art 8T SRAM bit cell circuit.

第3圖顯示一習知技術的10T的SRAM位元單元電路。Figure 3 shows a 10T SRAM bit cell circuit of a prior art.

第4圖係本發明一實施例，顯示一個包含了本發明特徵的8T SRAM位元單元的電路圖。Figure 4 is a circuit diagram showing an 8T SRAM bit cell incorporating the features of the present invention, in accordance with an embodiment of the present invention.

第5圖顯示一個使用傳統閘極介電層的8T的SRAM位元單元的平面佈局圖。Figure 5 shows a plan layout of an 8T SRAM cell using a conventional gate dielectric layer.

第6圖顯示取自第5圖平面佈局的剖面圖。Figure 6 shows a cross-sectional view taken from the plane layout of Figure 5.

第7圖顯示一個使用本發明雙閘極介電層的8T的SRAM位元單元的平面佈局圖。Figure 7 shows a plan layout of an 8T SRAM bit cell using the dual gate dielectric layer of the present invention.

第8圖顯示取自第7圖實施例的平面佈局的剖面圖。Figure 8 is a cross-sectional view showing the planar layout taken from the embodiment of Figure 7.

第9圖顯示使用傳統電路金屬化技術的讀取位元線連接配置的剖面圖。Figure 9 shows a cross-sectional view of a read bit line connection configuration using conventional circuit metallization techniques.

第10圖顯示本發明實施例的讀取位元線構造的剖面圖。Fig. 10 is a cross-sectional view showing the structure of a read bit line in the embodiment of the present invention.

第11圖顯示一電性模擬比較的結果，該比較對象為第9圖的傳統讀取位元線金屬化與第10圖的本發明實施例。Fig. 11 shows the results of an electrical simulation comparison, which is the conventional read bit line metallization of Fig. 9 and the embodiment of the invention of Fig. 10.

第12圖顯示本發明實施例配置4個8T的位元單元的佈局圖。Figure 12 is a layout diagram showing the arrangement of four 8T bit cells in an embodiment of the present invention.

第13圖顯示本發明實施例的10T位元單元佈局圖。Fig. 13 is a view showing the layout of a 10T bit cell of the embodiment of the present invention.

第14圖顯示使用金屬1於第13圖的實施例的佈局 圖。Figure 14 shows the layout of the embodiment using metal 1 in Figure 13 Figure.

第15圖顯示內容定址記憶位元單元的電路圖。Figure 15 shows a circuit diagram of the content addressed memory bit cell.

第16圖顯示本發明實施例的CAM單元佈局圖。Fig. 16 is a view showing a layout of a CAM unit of an embodiment of the present invention.

第17圖顯示一finFET電晶體裝置的三維結構。Figure 17 shows the three-dimensional structure of a finFET transistor device.

第18圖顯示第17圖的finFET的剖面圖。Figure 18 is a cross-sectional view showing the finFET of Figure 17.

第19圖顯示了雙埠8T的SRAM位元單元具備了使用finFET電晶體的讀取部分以及使用平面電晶體的另一個部分的實施例。Fig. 19 shows an embodiment in which the SRAM cell of the double-turn 8T is provided with a read portion using a finFET transistor and another portion using a planar transistor.

本發明的圖式並非用來限定，而是以範例表示本發明各實施例。各圖式的簡化是為了說明方便，因此沒有按照實際比例。The drawings of the present invention are not intended to be limiting, but rather to illustrate various embodiments of the invention. The simplification of each drawing is for convenience of explanation, and therefore is not in accordance with the actual ratio.

70．．．8T的SRAM位元單元70. . . 8T SRAM bit unit

PU1、PU2．．．上拉電晶體PU1, PU2. . . Pull-up transistor

PD1、PD2．．．下拉電晶體PD1, PD2. . . Pull down transistor

PG1、PG2．．．MOS傳導閘PG1, PG2. . . MOS conduction gate

BL、BLB．．．位元線BL, BLB. . . Bit line

WL．．．字元線WL. . . Word line

RBL．．．讀取位元線RBL. . . Read bit line

RWL‧‧‧讀取字元線RWL‧‧‧Read word line

OD‧‧‧主動區OD‧‧‧active area

PO‧‧‧多晶矽閘極PO‧‧‧ polysilicon gate

M1‧‧‧金屬1M1‧‧‧Metal 1

M2‧‧‧僅屬2M2‧‧‧ is only 2

Via‧‧‧通道Via‧‧‧ channel

CO‧‧‧接觸層CO‧‧‧ contact layer

Claims (9)

一種SRAM位元單元的裝置，包括：一半導體基板；以及至少一個SRAM位元單元，形成於上述半導體基板的一個部分；其中上述至少一個SRAM位元單元包括一6T儲存單元，由具有上述第一閘極介電層厚度的NMOS電晶體所組成，上述SRAM位元單元的裝置更包括一讀取埠，由具有上述較薄的第二閘極介電層厚度的NMOS電晶體所組成，上述較薄的第二閘極介電層厚度在上述第一閘極介電層厚度的75%-99%之間。 An apparatus for an SRAM bit cell, comprising: a semiconductor substrate; and at least one SRAM bit cell formed on a portion of the semiconductor substrate; wherein the at least one SRAM bit cell comprises a 6T memory cell, having the first The NMOS transistor of the thickness of the gate dielectric layer, the device of the SRAM bit cell further comprises a read 埠, which is composed of an NMOS transistor having the thickness of the thin second gate dielectric layer, The thickness of the thin second gate dielectric layer is between 75% and 99% of the thickness of the first gate dielectric layer. 如申請專利範圍第1項所述之SRAM位元單元的裝置，其中上述較薄的第二閘極介電層厚度在上述第一閘極介電層厚度的85%-95%之間。 The device of claim 1 wherein the thinner second gate dielectric layer has a thickness between 85% and 95% of the thickness of the first gate dielectric layer. 如申請專利範圍第1項所述之SRAM位元單元的裝置，其中上述較薄的第二閘極介電層厚度在上述第一閘極介電層厚度的85%-90%之間。 The device of claim 1 wherein the thinner second gate dielectric layer has a thickness between 85% and 90% of the thickness of the first gate dielectric layer. 如申請專利範圍第1項所述之SRAM位元單元的裝置，其中上述SRAM位元單元是8T的SRAM位元單元與10T的SRAM位元單元兩者其中之一者。 The apparatus of the SRAM bit unit of claim 1, wherein the SRAM bit unit is one of an 8T SRAM bit unit and a 10T SRAM bit unit. 如申請專利範圍第1項所述之SRAM位元單元的裝置，更包括：第一與第二金屬層，沈積於上述基板並且被層間介電層隔開，將上述SRAM位元單元的至少一些上述電晶體電性連結在一起；以及 一讀取位元線，以上述第一金屬層形成並且以沒有透過其他金屬層覆蓋在上述基板，上述讀取位元線使用一接觸層而沒有透過其他任何的金屬層通道連接至上述SRAM位元單元的上述讀取埠。 The device of claim 1 , further comprising: first and second metal layers deposited on the substrate and separated by an interlayer dielectric layer, at least some of the SRAM bit cells The above transistors are electrically connected together; a read bit line formed by the first metal layer and overlying the substrate without passing through other metal layers, the read bit line using a contact layer without any other metal layer path connecting to the SRAM bit The above reading of the meta unit. 如申請專利範圍第1項所述之SRAM位元單元的裝置，其中上述SRAM位元單元是8T的SRAM位元單元與10T的SRAM位元單元兩者其中之一者，上述讀取埠包括至少一個finFET電晶體。 The apparatus of the SRAM bit unit of claim 1, wherein the SRAM bit unit is one of an 8T SRAM bit unit and a 10T SRAM bit unit, and the reading includes at least one of A finFET transistor. 一種SRAM位元單元的積體電路，包括：一邏輯部分，形成於半導體基板的第一部分，且具備複數電晶體，上述電晶體的其中一些具有較薄的閘極介電層；一SRAM陣列，具備複數個SRAM位元單元，每個SRAM位元單元形成在上述半導體基板的第二部分，且上述SRAM位元單元更包括：6T儲存單元，由具有上述較厚的閘極介電層厚度的NMOS電晶體所組成；一讀取埠，由具有上述較薄的閘極介電層厚度的NMOS電晶體所組成；其中上述較薄的閘極介電層厚度在上述較厚的閘極介電層厚度的75%-99%之間；第一與第二金屬層，沈積於上述基板並且被層間介電層隔開，將上述SRAM位元單元的至少一些上述電晶體電性連結在一起；以及一讀取位元線，以上述第一金屬層形成並且以沒有 透過其他金屬層覆蓋在上述基板，上述讀取位元線使用一接觸層而沒有透過其他任何的金屬層通道連接至上述SRAM位元單元的上述讀取埠。 An integrated circuit of an SRAM bit cell, comprising: a logic portion formed on a first portion of a semiconductor substrate and having a plurality of transistors, some of the transistors having a thin gate dielectric layer; an SRAM array, Having a plurality of SRAM bit cells, each SRAM cell is formed in a second portion of the semiconductor substrate, and the SRAM cell further includes: a 6T memory cell having a thickness of the thicker gate dielectric layer An NMOS transistor; a read 组成, consisting of an NMOS transistor having the thickness of the thinner gate dielectric layer; wherein the thinner gate dielectric layer is thicker than the thicker gate dielectric Between 75% and 99% of the layer thickness; the first and second metal layers are deposited on the substrate and separated by an interlayer dielectric layer, and at least some of the above-mentioned transistors of the SRAM cell are electrically connected together; And a read bit line formed with the first metal layer described above and without The substrate is covered by another metal layer, and the read bit line uses a contact layer without any other metal layer vias connected to the read gate of the SRAM cell. 一種CAM位元單元的裝置，包括：一半導體基板，具備複數電晶體；以及至少一個CAM位元單元，形成於上述半導體基板的一第一部分；一邏輯部分，形成於上述半導體基板的一第二部分，上述第一部分與上述第二部分不相同，上述電晶體的其中一些具有較薄的閘極介電層厚度；其中上述至少一個CAM位元單元更包括具備第一閘極介電層厚度的電晶體，與具備較薄的第二閘極介電層厚度的附加電晶體，上述較薄的第二閘極介電層厚度等於上述較薄的閘極介電層厚度，上述較薄的第二閘極介電層厚度在上述第一閘極介電層厚度的75%-99%之間。 A device for a CAM bit cell, comprising: a semiconductor substrate having a plurality of transistors; and at least one CAM bit cell formed on a first portion of the semiconductor substrate; and a logic portion formed on a second portion of the semiconductor substrate In part, the first portion is different from the second portion, and some of the transistors have a thin thickness of the gate dielectric layer; wherein the at least one CAM cell further includes a thickness of the first gate dielectric layer a transistor, and an additional transistor having a thinner thickness of the second gate dielectric layer, the thinner second gate dielectric layer having a thickness equal to the thickness of the thinner gate dielectric layer, the thinner The thickness of the second gate dielectric layer is between 75% and 99% of the thickness of the first gate dielectric layer. 如申請專利範圍第8項所述之CAM位元單元的裝置，其中包括上述至少一個CAM位元單元的上述半導體基板的上述部分更包括絕緣體覆矽(SOI)層。 The apparatus of the CAM cell unit of claim 8, wherein the portion of the semiconductor substrate including the at least one CAM cell unit further comprises an insulator-covered (SOI) layer.
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