TWI498980B - Semiconductor wafer and method of forming sacrificial bump pad for wafer probing during wafer sort test - Google Patents

Description

半導體晶圓以及形成用於在晶圓分類測試期間的晶圓探測的犧牲凸塊墊之方法Semiconductor wafer and method of forming sacrificial bump pads for wafer probing during wafer sorting testing

本發明係關於半導體裝置。The present invention relates to a semiconductor device.

半導體裝置通常見於現代電子產品中。半導體裝置之電組件的數目及密度可變化。離散半導體裝置一般含有一種類型之電組件，例如發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器及功率金屬氧化物半導體場效電晶體(MOSFET)。積體半導體裝置典型地含有數百個至數百萬個電組件。積體半導體裝置之實例包括微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池及數位微鏡裝置(DMD)。Semiconductor devices are commonly found in modern electronic products. The number and density of electrical components of a semiconductor device can vary. Discrete semiconductor devices typically contain one type of electrical component, such as a light emitting diode (LED), a small signal transistor, a resistor, a capacitor, an inductor, and a power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charge coupled devices (CCDs), solar cells, and digital micromirror devices (DMDs).

半導體裝置執行許多功能，諸如高速計算、收發電磁信號、控制電子裝置、將日光轉化成電及建立電視顯示器之視像投射。半導體裝置見於娛樂、通信、功率轉換、網路、電腦及消費型產品之領域中。半導體裝置亦見於軍事應用、航空、汽車、工業控制器及辦公設備中。Semiconductor devices perform many functions, such as high speed computing, transceiving electromagnetic signals, controlling electronics, converting daylight into electricity, and establishing a video projection of a television display. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networking, computers, and consumer products. Semiconductor devices are also found in military applications, aerospace, automotive, industrial controllers and office equipment.

半導體裝置係利用半導體材料之電特性。半導體材料之原子結構允許藉由施加電場或經由摻雜製程而操縱其電導率。摻雜係將雜質引入半導體材料中以操縱及控制半導體裝置之電導率。Semiconductor devices utilize the electrical properties of semiconductor materials. The atomic structure of the semiconductor material allows its conductivity to be manipulated by applying an electric field or via a doping process. The doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

半導體裝置含有主動及被動電結構。主動結構(包括雙極電晶體及場效電晶體)控制電流流動。藉由改變摻雜程度及施加電場或基極電流，電晶體促進或限制電流流動。被動結構(包括電阻器、電容器及電感器)在電壓與電流之間建立為執行多種電功能所必需的關係。被動結構與主動結構係電連接以形成電路，從而使半導體裝置能夠執行高速計算及其他有用功能。Semiconductor devices contain active and passive electrical structures. Active structures (including bipolar transistors and field effect transistors) control current flow. The transistor promotes or limits current flow by varying the degree of doping and applying an electric or base current. Passive structures (including resistors, capacitors, and inductors) establish a relationship between voltage and current that is necessary to perform a variety of electrical functions. The passive structure is electrically coupled to the active structure to form a circuit, thereby enabling the semiconductor device to perform high speed calculations and other useful functions.

半導體裝置一般使用兩個複雜製造製程(亦即，前端製造與後端製造)來製造，各製程潛在地包括數百個步驟。前端製造包括在半導體晶圓之表面上形成多個晶粒。各晶粒典型地相同且含有藉由電連接主動組件與被動組件所形成之電路。後端製造包括將成品晶圓單切成個別晶粒且封裝該晶粒以提供結構支撐及環境隔離。Semiconductor devices are typically fabricated using two complex manufacturing processes (i.e., front end manufacturing and back end manufacturing), each of which potentially includes hundreds of steps. Front end fabrication involves forming a plurality of dies on the surface of a semiconductor wafer. Each die is typically identical and contains circuitry formed by electrically connecting the active component to the passive component. Back end manufacturing involves cutting a finished wafer into individual dies and encapsulating the dies to provide structural support and environmental isolation.

半導體製造之一目的在於生產較小半導體裝置。較小裝置典型地消耗較少功率、具有較高效能且可較高效地生產。另外，較小半導體裝置具有較小佔據面積，此為較小終產品所需。較小晶粒尺寸可藉由改良前端製程達成，從而產生具有較小、較高密度之主動及被動組件的晶粒。後端製程可藉由改良電互連及封裝材料來產生具有較小佔據面積之半導體裝置封裝。One of the goals of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, are more efficient, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is required for smaller end products. Smaller grain sizes can be achieved by improved front-end processes, resulting in die with smaller, higher density active and passive components. The backend process can produce a semiconductor device package with a small footprint by modifying electrical interconnects and packaging materials.

圖1說明含有多個半導體晶粒12之習知半導體晶圓10。晶圓10可由諸如矽、鍺、砷化鎵、磷化銦或碳化矽之半導體基材製成。各半導體晶粒12在其主動表面中具有根據晶粒之電設計所形成之主動及被動裝置、導電層及介電層。在一實施例中，半導體晶粒含有基頻類比電路或數位電路，諸如數位信號處理器(DSP)、記憶體或其他信號處理電路。半導體晶粒12亦可含有用於射頻(RF)信號處理之積體被動裝置(IPD)，諸如電感器、電容器及電阻器。FIG. 1 illustrates a conventional semiconductor wafer 10 containing a plurality of semiconductor dies 12. Wafer 10 can be made of a semiconductor substrate such as tantalum, niobium, gallium arsenide, indium phosphide or tantalum carbide. Each of the semiconductor dies 12 has active and passive devices, conductive layers, and dielectric layers formed in accordance with the electrical design of the dies in its active surface. In one embodiment, the semiconductor die contains a fundamental frequency analog circuit or a digital circuit such as a digital signal processor (DSP), memory or other signal processing circuit. Semiconductor die 12 may also contain integrated passive devices (IPD) for radio frequency (RF) signal processing, such as inductors, capacitors, and resistors.

半導體晶粒12係具有凸塊墊14形成於主動表面上之覆晶型半導體裝置。凸塊墊14提供半導體晶粒12內中導電層及主動及被動電路組件之電互連。焊料凸塊典型地形成於凸塊墊14上以在晶圓單切之後使半導體晶粒12與印刷電路板(PCB)及其他電裝置電互連。The semiconductor die 12 has a flip chip type semiconductor device in which a bump pad 14 is formed on an active surface. The bump pads 14 provide electrical interconnections between the conductive layers in the semiconductor die 12 and the active and passive circuit components. Solder bumps are typically formed on the bump pads 14 to electrically interconnect the semiconductor die 12 with printed circuit boards (PCBs) and other electrical devices after the wafer is single cut.

晶圓測試為製造製程之一重要部分以確認半導體晶粒12之連續性、電參數及功能操作。在晶圓級鑑別不良晶粒且自製造製程中移除以免至較高級系統時(例如多晶粒封裝及PCB)發生故障，此故障代價更高昂。Wafer testing is an important part of the manufacturing process to confirm the continuity, electrical parameters, and functional operation of the semiconductor die 12. This failure is more costly when identifying bad grains at the wafer level and removing them from the manufacturing process to avoid failures in higher-level systems, such as multi-die packages and PCBs.

圖2展示半導體晶圓10之習知晶圓探針測試組態。晶圓10固定於晶圓操控器16上，其提供晶圓在x、y及z方向上之移動以達成測試目的。操控晶圓10以使具有觸指或觸針20之測試探頭18電接觸凸塊墊14。電腦測試系統22經由測試探頭18及觸指20對凸塊墊14收發電信號。電腦測試系統22經由凸塊墊14測試半導體晶粒12之連續性、電參數及功能操作。若電腦測試系統22偵測到測試故障，則鑑別為不良半導體晶粒且隨後自製造製程中移除。2 shows a conventional wafer probe test configuration for semiconductor wafer 10. Wafer 10 is affixed to wafer handler 16 which provides movement of the wafer in the x, y, and z directions for testing purposes. The wafer 10 is manipulated such that the test probe 18 with the finger or stylus 20 electrically contacts the bump pad 14. The computer test system 22 transmits and receives electrical signals to the bump pads 14 via the test probes 18 and the fingers 20. Computer test system 22 tests the continuity, electrical parameters, and functional operation of semiconductor die 12 via bump pads 14. If the computer test system 22 detects a test failure, it is identified as a defective semiconductor die and subsequently removed from the manufacturing process.

凸塊墊14具有小面積，直徑約50-500微米(μm)。觸指20典型地具有尖頭以使得可靠地電連接至凸塊墊14。在晶圓探針測試過程中，觸指20已知會穿透表面且損壞凸塊墊14。實際上，晶圓探針測試可包括牽引觸指20橫越凸塊墊14，導致凸塊墊表面上留下擦痕。晶圓探針測試在凸塊墊中留下觸指標記，導致隨後焊料凸塊不易形成。為避免損壞凸塊墊14，已在焊料凸塊24形成之後進行晶圓探針測試，如圖3所示。The bump pad 14 has a small area and is about 50-500 micrometers (μm) in diameter. The finger 20 typically has a pointed tip to enable reliable electrical connection to the bump pad 14. During wafer probe testing, the finger 20 is known to penetrate the surface and damage the bump pads 14. In practice, the wafer probe test can include pulling the finger 20 across the bump pad 14, resulting in scratches on the surface of the bump pad. The wafer probe test leaves a finger mark in the bump pad, resulting in subsequent solder bump formation. To avoid damage to the bump pads 14, wafer probe testing has been performed after the solder bumps 24 are formed, as shown in FIG.

在大多數商務合同中，晶圓代工廠(wafer foundry)被其消費者要求保持對晶圓負責直至完成晶圓分類測試以確保足夠良率。因凸塊墊損壞之潛在性，許多晶圓代工廠在凸塊墊上形成焊料凸塊之後執行晶圓探測。晶圓代工廠直至晶圓分類測試之後方可出售晶圓或以其他方式轉移晶圓責任，且代工廠直至凸塊形成之後方可進行晶圓分類測試。然而，要求晶圓探測在凸塊形成之後進行限制了第三方凸塊形成服務供應商之競爭。若晶圓探測可在凸塊形成之前進行而不損壞凸塊墊，則晶圓代工廠可出售無凸塊之晶圓且其他公司可參與提供凸塊形成服務。In most commercial contracts, the wafer foundry is held by its consumers to remain responsible for the wafer until the wafer classification test is completed to ensure adequate yield. Due to the potential for bump pad damage, many foundries perform wafer probing after solder bumps are formed on the bump pads. Wafers can be sold or wafer transferred after wafer sorting and testing, and wafer sorting tests can be performed until the bumps are formed. However, wafer inspection is required to limit the competition of third-party bump formation service providers after bump formation. If wafer probing can occur prior to bump formation without damaging the bump pads, the foundry can sell bumpless wafers and other companies can participate in providing bump forming services.

需要在凸塊形成之前執行晶圓探針測試而不損壞互連凸塊墊。因此，在一實施例中，本發明為一種製造半導體裝置之方法，其包含以下步驟：提供一含有多個半導體晶粒之半導體晶圓，在半導體晶粒上形成多個互連凸塊墊，在互連凸塊墊鄰近處形成多個犧牲凸塊墊，在各互連凸塊墊與鄰近犧牲凸塊墊之間形成一導電鏈路以及在互連凸塊墊上形成凸塊之前藉由電接觸犧牲凸塊墊進行晶圓探測。Wafer probe testing needs to be performed prior to bump formation without damaging the interconnect bump pads. Accordingly, in one embodiment, the present invention is a method of fabricating a semiconductor device comprising the steps of: providing a semiconductor wafer comprising a plurality of semiconductor dies, forming a plurality of interconnecting bump pads on the semiconductor die, Forming a plurality of sacrificial bump pads adjacent to the interconnect bump pads, forming a conductive link between each interconnect bump pad and the adjacent sacrificial bump pads, and electrically forming the bumps on the interconnect bump pads Contact the sacrificial bump pad for wafer probing.

在另一實施例中，本發明為一種製造半導體裝置之方法，其包含以下步驟：提供一含有多個半導體晶粒之半導體晶圓以及在半導體晶粒上同時地形成多個互連凸塊墊、多個犧牲凸塊墊以及導電鏈路。犧牲凸塊墊安置於互連凸塊墊鄰近處。一導電鏈路使各互連凸塊墊與鄰近犧牲凸塊墊之間電連接。該方法進一步包括藉由電接觸犧牲凸塊墊進行晶圓探測之步驟。In another embodiment, the present invention is a method of fabricating a semiconductor device comprising the steps of: providing a semiconductor wafer comprising a plurality of semiconductor dies and simultaneously forming a plurality of interconnect bump pads on the semiconductor dies , a plurality of sacrificial bump pads and a conductive link. The sacrificial bump pads are disposed adjacent to the interconnect bump pads. A conductive link electrically connects each of the interconnect bump pads to the adjacent sacrificial bump pads. The method further includes the step of wafer probing by electrically contacting the sacrificial bump pads.

在另一實施例中，本發明為一種製造半導體裝置之方法，其包含以下步驟：提供一含有多個半導體晶粒之半導體晶圓，在半導體晶粒上、於一凸塊墊陣列內形成一互連凸塊墊，於該凸塊墊陣列內形成一犧牲凸塊墊，在該互連凸塊墊與該犧牲凸塊墊之間形成一導電鏈路以及藉由電接觸該犧牲凸塊墊進行晶圓探測。In another embodiment, the present invention is a method of fabricating a semiconductor device, comprising the steps of: providing a semiconductor wafer comprising a plurality of semiconductor dies, forming a pattern in a bump pad array on the semiconductor die Interconnecting bump pads, forming a sacrificial bump pad in the bump pad array, forming a conductive link between the interconnect bump pad and the sacrificial bump pad, and electrically contacting the sacrificial bump pad Perform wafer inspection.

在另一實施例中，本發明為一種含有多個半導體晶粒之半導體晶圓，該等晶粒包含一在該等半導體晶粒上於一凸塊墊陣列內形成之互連凸塊墊。一犧牲凸塊墊形成於該凸塊墊陣列內。一導電鏈路形成於該互連凸塊墊與該犧牲凸塊墊之間。In another embodiment, the invention is a semiconductor wafer comprising a plurality of semiconductor dies, the dies comprising an interconnecting bump pads formed on the semiconductor dies in an array of bump pads. A sacrificial bump pad is formed in the bump pad array. A conductive link is formed between the interconnect bump pad and the sacrificial bump pad.

本發明在以下說明中以一或多個實施例參考圖式加以描述，其中相同數字代表相同或類似元件。儘管本發明依據達成本發明目的之最佳方式描述，但熟習此項技術者應瞭解本發明欲涵蓋如隨附申請專利範圍所限定之可包括於本發明之精神及範疇內的替代物、修改及等效物以及如以下揭示內容及圖式所支持之其等效物。The invention is described in the following description with reference to the drawings, in which FIG. Although the present invention has been described in terms of the best mode of the present invention, it is understood that the invention is intended to cover alternatives and modifications as may be included in the spirit and scope of the invention as defined by the appended claims. And equivalents and equivalents thereof as supported by the following disclosure and drawings.

半導體裝置一般使用兩個複雜製造製程來製造：前端製造與後端製造。前端製造包括在半導體晶圓表面上形成多個晶粒。該晶圓上之各晶粒含有主動及被動電組件，其經電連接而形成功能電路。諸如電晶體及二極體之主動電組件具有控制電流流動之能力。諸如電容器、電感器、電阻器及變壓器之被動電組件在電壓與電流之間建立為執行電路功能所必需的關係。Semiconductor devices are typically fabricated using two complex manufacturing processes: front end manufacturing and back end manufacturing. Front end fabrication involves forming a plurality of dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, resistors, and transformers establish a relationship between voltage and current that is necessary to perform circuit functions.

被動及主動組件藉由一系列製程步驟形成於半導體晶圓表面上，包括摻雜、沈積、光微影、蝕刻及平坦化。摻雜係藉由諸如離子植入或熱擴散之技術將雜質引入半導體材料中。摻雜製程改變主動裝置中半導體材料之電導率，從而使該半導體材料轉變成絕緣體、導體，或回應電場或基極電流而動態地改變該半導體材料之電導率。電晶體含有摻雜類型及程度不同之區域，其視需要配置以使該電晶體能夠在施加電場或基極電流時促進或限制電流流動。The passive and active components are formed on the surface of the semiconductor wafer by a series of processing steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process changes the conductivity of the semiconductor material in the active device, thereby converting the semiconductor material into an insulator, a conductor, or dynamically changing the conductivity of the semiconductor material in response to an electric field or base current. The transistor contains regions of varying doping type and extent that are configured as needed to enable the transistor to promote or limit current flow when an electric or base current is applied.

主動及被動組件係由具有不同電特性之材料層形成。該等層可藉由多種沈積技術形成(部分由所沈積之材料類型決定)。舉例而言，薄膜沈積可包括化學氣相沈積(CVD)、物理氣相沈積(PVD)、電解電鍍及無電電鍍製程。各層一般經圖案化以形成主動組件、被動組件或各組件間電連接的部分。Active and passive components are formed from layers of material having different electrical properties. The layers can be formed by a variety of deposition techniques (partly determined by the type of material being deposited). For example, thin film deposition may include chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. The layers are typically patterned to form active components, passive components, or portions of electrical connections between the components.

可使用光微影對層進行圖案化，包括使光敏材料(例如光阻)沈積於待圖案化之層上。使用光將圖案自光罩轉印於光阻上。使用溶劑移除曝光之光阻圖案部分，暴露待圖案化之下層部分。移除光阻之其餘部分，得到其下之圖案化層。或者，有些類型之材料係使用諸如無電電鍍及電解電鍍之技術藉由使材料直接沈積於先前沈積/蝕刻製程所形成的區域或空隙中而加以圖案化。The layer can be patterned using photolithography, including depositing a photosensitive material, such as a photoresist, onto the layer to be patterned. The pattern is transferred from the photomask to the photoresist using light. The portion of the exposed photoresist pattern is removed using a solvent to expose portions of the layer to be patterned. The rest of the photoresist is removed to obtain a patterned layer thereunder. Alternatively, some types of materials are patterned using techniques such as electroless plating and electrolytic plating by depositing materials directly into regions or voids formed by previous deposition/etch processes.

在現有圖案上沈積材料薄膜會放大下面的圖案且產生非均勻平坦表面。生產較小且較密集堆積之主動及被動組件需要均勻平坦表面。可使用平坦化自晶圓表面移除材料且產生均勻平坦表面。平坦化包括用拋光墊拋光晶圓表面。在拋光期間將研磨材料及腐蝕性化學品添加至晶圓表面中。研磨劑機械作用與化學品腐蝕作用組合可移除任何不規則表面構形，從而產生均勻平坦表面。Depositing a thin film of material on an existing pattern magnifies the underlying pattern and creates a non-uniform flat surface. The production of smaller and densely packed active and passive components requires a uniform flat surface. Flattening can be used to remove material from the wafer surface and create a uniform flat surface. Flattening involves polishing the wafer surface with a polishing pad. Abrasive materials and corrosive chemicals are added to the wafer surface during polishing. The abrasive mechanical action in combination with chemical corrosive action removes any irregular surface configuration resulting in a uniform flat surface.

後端製造係指將成品晶圓切割或單切成個別晶粒且接著封裝該晶粒以供結構支撐及環境隔離。致使單切晶粒，沿著晶圓非功能區(稱為切割道或劃線)將晶圓劃痕並切斷。使用雷射切割工具或鋸條單切晶圓。單切之後，將個別晶粒固定於一封裝基板上，該封裝基板包括接腳或接觸墊以供與其他系統組件互連。接著使半導體晶粒上所形成之接觸墊連接至封裝內之接觸墊。電連接可由焊料凸塊、柱形凸塊、導電膏或焊線形成。使密封劑或其他成型材料沈積於封裝上以提供物理支撐及電絕緣。接著將成品封裝***一電系統中且半導體裝置之功能可供其他系統組件利用。Back end manufacturing refers to cutting or simply cutting a finished wafer into individual dies and then encapsulating the dies for structural support and environmental isolation. This results in a single-cut grain that scratches and cuts the wafer along a non-functional area of the wafer (called a scribe line or scribe line). Use a laser cutting tool or saw blade to cut the wafer. After a single cut, the individual die are mounted on a package substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then bonded to contact pads in the package. The electrical connection may be formed by solder bumps, stud bumps, conductive paste or wire bonds. A sealant or other forming material is deposited on the package to provide physical support and electrical insulation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is available to other system components.

圖4說明具有多個黏著於其表面上之半導體封裝的晶片載體基板或PCB 52之電子裝置50。視應用而定，電子裝置50可具有一種類型之半導體封裝或多種類型之半導體封裝。不同類型之半導體封裝展示於圖4中以用於說明之目的。4 illustrates an electronic device 50 having a plurality of wafer carrier substrates or PCBs 52 adhered to a semiconductor package on its surface. Depending on the application, electronic device 50 can have one type of semiconductor package or multiple types of semiconductor packages. Different types of semiconductor packages are shown in Figure 4 for illustrative purposes.

電子裝置50可為一使用半導體封裝執行一或多種電功能之單獨系統。或者，電子裝置50可為一較大系統之子組件。舉例而言，電子裝置50可為一可***電腦中之圖形卡、網路介面卡或其他信號處理卡。半導體封裝可包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散裝置或其他半導體晶粒或電組件。Electronic device 50 can be a separate system that performs one or more electrical functions using a semiconductor package. Alternatively, electronic device 50 can be a sub-assembly of a larger system. For example, the electronic device 50 can be a graphics card, a network interface card, or other signal processing card that can be inserted into a computer. Semiconductor packages may include microprocessors, memories, special application integrated circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components.

在圖4中，PCB 52提供一用於結構支撐之通用基板及固定於PCB上之半導體封裝的電互連。使用蒸鍍、電解電鍍、無電電鍍、網版印刷或其他適合之金屬沈積製程在PCB 52之一表面上或層內形成導電信號跡線54。信號跡線54在半導體封裝、固定組件及其他外部系統組件之每一者之間提供電通信。跡線54亦向各半導體封裝提供電力及接地。In FIG. 4, PCB 52 provides an electrical interconnection for a structurally supported general purpose substrate and a semiconductor package secured to the PCB. Conductive signal traces 54 are formed on or in one of the surfaces of PCB 52 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 54 provide electrical communication between each of the semiconductor package, the fixed components, and other external system components. Trace 54 also provides power and ground to each semiconductor package.

在一些實施例中，一半導體裝置具有兩級封裝。第一級封裝為使半導體晶粒機械附著及電附著至一中間載體之技術。第二級封裝包括使該中間載體機械附著及電附著至PCB。在其他實施例中，一半導體裝置可能僅具有第一級封裝，其中晶粒直接機械黏著及電黏著於PCB上。In some embodiments, a semiconductor device has a two-stage package. The first stage of packaging is a technique for mechanically attaching and electrically attaching semiconductor dies to an intermediate carrier. The second level package includes mechanically attaching and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may only have a first level package in which the die is directly mechanically bonded and electrically bonded to the PCB.

出於說明之目的，在PCB 52上展示數種類型之第一級封裝，包括焊線封裝56及覆晶58。另外，展示固定於PCB 52上之數種類型之第二級封裝，包括球狀柵格陣列(BGA)60、凸塊晶片載體(BCC)62、雙排型封裝(DIP)64、平台柵格陣列(LGA)66、多晶片模組(MCM)68、四邊扁平無引腳封裝(QFN)70及四邊扁平封裝72。視系統要求而定，半導體封裝之任何組合、第一級與第二級封裝類型之任何組合以及其他電子組件的組態可連接至PCB 52。在一些實施例中，電子裝置50包括單個附著之半導體封裝；而其他實施例需要多個互連封裝。藉由在單個基板上組合一或多個半導體封裝，製造商可將預製組件合併於電子裝置及系統中。由於半導體封裝包括複雜功能，因此可使用較便宜組件及流線化製造製程來製造電子裝置。所得裝置不太可能發生故障且製造費用較少，從而降低消費者成本。For purposes of illustration, several types of first level packages, including wire bond packages 56 and flip chips 58, are shown on PCB 52. In addition, several types of second level packages, such as a ball grid array (BGA) 60, a bump wafer carrier (BCC) 62, a dual row package (DIP) 64, and a platform grid, are shown that are fixed to the PCB 52. Array (LGA) 66, multi-chip module (MCM) 68, quad flat no-lead package (QFN) 70, and quad flat pack 72. Depending on system requirements, any combination of semiconductor packages, any combination of first and second level package types, and configurations of other electronic components can be coupled to PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package; while other embodiments require multiple interconnect packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Since semiconductor packages include complex functions, electronic devices can be fabricated using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, thereby reducing consumer costs.

圖5a-5c展示示例性半導體封裝。圖5a進一步詳細說明固定於PCB 52上之DIP 64。半導體晶粒74包括含有類比電路或數位電路之主動區，該等類比電路或數位電路形成於晶粒內執行作為主動裝置、被動裝置、導電層及介電層，並且以根據晶粒之電設計而電互連。舉例而言，電路可包括一或多個電晶體、二極體、電感器、電容器、電阻器及在半導體晶粒74之主動區內所形成之其他電路元件。接觸墊76為諸如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)之導電材料的一或多個層，且電連接至半導體晶粒74內所形成之電路元件。在DIP 64組裝期間，使用金-矽共晶層或諸如熱環氧樹脂之黏合材料將半導體晶粒74固定於中間載體78上。封裝主體包括絕緣封裝材料，諸如聚合物或陶瓷。導線80及焊線82在半導體晶粒74與PCB 52之間提供電互連。密封劑84沈積於封裝上以防止環境濕氣及顆粒進入封裝而污染晶粒74或焊線82。Figures 5a-5c show an exemplary semiconductor package. Figure 5a illustrates in further detail the DIP 64 that is attached to the PCB 52. The semiconductor die 74 includes an active region including an analog circuit or a digital circuit formed in the die to perform as an active device, a passive device, a conductive layer, and a dielectric layer, and is designed according to the electric power of the die. And electrical interconnection. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components formed within the active region of the semiconductor die 74. The contact pad 76 is one or more layers of a conductive material such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and is electrically connected to the semiconductor crystal. Circuit elements formed within the particles 74. During assembly of the DIP 64, the semiconductor die 74 is secured to the intermediate carrier 78 using a gold-germanium eutectic layer or a bonding material such as a thermal epoxy. The package body includes an insulating encapsulation material such as a polymer or ceramic. Conductor 80 and bond wire 82 provide electrical interconnection between semiconductor die 74 and PCB 52. Encapsulant 84 is deposited on the package to prevent ambient moisture and particles from entering the package and contaminating die 74 or bond wire 82.

圖5b進一步詳細說明固定於PCB 52上之BCC 62。使用底膠或環氧樹脂黏合材料92將半導體晶粒88固定於載體90上。焊線94在接觸墊96與98之間提供第一級封裝互連。成型化合物或密封劑100沈積於半導體晶粒88及焊線94上以向裝置提供物理支撐及電絕緣。使用諸如電解電鍍或無電電鍍之適合金屬沈積法在PCB 52之一表面上形成接觸墊102以防止氧化。接觸墊102電連接至PCB 52中之一或多個導電信號跡線54。凸塊104形成於BCC 62之接觸墊98與PCB 52之接觸墊102之間。Figure 5b illustrates in further detail the BCC 62 that is attached to the PCB 52. The semiconductor die 88 is secured to the carrier 90 using a primer or epoxy bonding material 92. Wire bond 94 provides a first level package interconnect between contact pads 96 and 98. A molding compound or encapsulant 100 is deposited over the semiconductor die 88 and bond wires 94 to provide physical support and electrical isolation to the device. Contact pads 102 are formed on one surface of PCB 52 using a suitable metal deposition method such as electrolytic plating or electroless plating to prevent oxidation. Contact pad 102 is electrically coupled to one or more conductive signal traces 54 in PCB 52. Bumps 104 are formed between contact pads 98 of BCC 62 and contact pads 102 of PCB 52.

在圖5c中，半導體晶粒58依覆晶型第一級封裝方式面向下固定於中間載體106上。半導體晶粒58之主動區108含有類比電路或數位電路，其以根據晶粒之電設計所形成之主動裝置、被動裝置、導電層及介電層的形式執行。舉例而言，電路可包括一或多個電晶體、二極體、電感器、電容器、電阻器及主動區108內之其他電路元件。半導體晶粒58經由凸塊110電連接及機械連接至載體106。In FIG. 5c, the semiconductor die 58 is fixed to the intermediate carrier 106 face down in a planar first-level package. The active region 108 of the semiconductor die 58 contains an analog circuit or a digital circuit that is implemented in the form of an active device, a passive device, a conductive layer, and a dielectric layer formed in accordance with the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components within active region 108. Semiconductor die 58 is electrically and mechanically coupled to carrier 106 via bumps 110.

BGA 60係使用凸塊112依BGA型第二級封裝方式電連接及機械連接至PCB 52。半導體晶粒58經由凸塊110、信號線114及凸塊112電連接至PCB 52中之導電信號跡線54。成型化合物或密封劑116沈積於半導體晶粒58及載體106上以向裝置提供物理支撐及電絕緣。覆晶半導體裝置提供半導體晶粒58上之主動裝置至PCB 52上之導電跡線的短導電路徑以縮短信號傳播距離，降低電容且改良總體電路效能。在另一實施例中，在無中間載體106之情況下，可使用覆晶型第一級封裝方式將半導體晶粒58直接機械連接及電連接至PCB 52。The BGA 60 is electrically and mechanically connected to the PCB 52 using bumps 112 in a BGA type second level package. Semiconductor die 58 is electrically coupled to conductive signal traces 54 in PCB 52 via bumps 110, signal lines 114, and bumps 112. A molding compound or encapsulant 116 is deposited over the semiconductor die 58 and carrier 106 to provide physical support and electrical isolation to the device. The flip chip semiconductor device provides a short conductive path from the active device on the semiconductor die 58 to the conductive traces on the PCB 52 to reduce signal propagation distance, reduce capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 can be directly mechanically and electrically connected to the PCB 52 using a flip-chip first level package without the intermediate carrier 106.

圖6說明含有多個半導體晶粒152之半導體晶圓150。晶圓150可由直徑在150-300毫米(mm)範圍內之半導體基材製成，諸如矽、鍺、砷化鎵、磷化銦或碳化矽。各半導體晶粒152在主動表面154中具有根據晶粒之電設計所形成之主動及被動裝置、導電層及介電層。在一實施例中，半導體晶粒152含有基頻類比電路或數位電路，諸如數位信號處理器(DSP)、ASIC、記憶體或其他信號處理電路。半導體晶粒152亦可含有用於RF信號處理之IPD，諸如電感器、電容器及電阻器。FIG. 6 illustrates a semiconductor wafer 150 having a plurality of semiconductor dies 152. Wafer 150 may be fabricated from a semiconductor substrate having a diameter in the range of 150-300 millimeters (mm), such as germanium, antimony, gallium arsenide, indium phosphide or tantalum carbide. Each semiconductor die 152 has active and passive devices, conductive layers, and dielectric layers formed in the active surface 154 in accordance with the electrical design of the die. In one embodiment, semiconductor die 152 includes a baseband analog circuit or a digital circuit, such as a digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die 152 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

在一實施例中，半導體晶粒152為覆晶型半導體裝置，其具有形成於主動表面154上之互連凸塊墊160。凸塊墊160係使用PVD、CVD、濺鍍、電解電鍍、無電電鍍製程或其他適合金屬沈積製程進行圖案化並沈積。凸塊墊160可為一或多個Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料層。凸塊墊160安置於凸塊墊陣列162內以向半導體晶粒152內之導電層以及主動及被動電路組件提供電互連。凸塊墊160面積小，直徑為約50-500微米(μm)。In one embodiment, semiconductor die 152 is a flip chip type semiconductor device having interconnecting bump pads 160 formed on active surface 154. The bump pads 160 are patterned and deposited using PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The bump pads 160 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Bump pads 160 are disposed within bump pad array 162 to provide electrical interconnections to the conductive layers within the semiconductor die 152 as well as the active and passive circuit components. The bump pad 160 is small in area and has a diameter of about 50 to 500 micrometers (μm).

多個犧牲凸塊墊164形成於主動表面154上。凸塊墊164係使用PVD、CVD、濺鍍、電解電鍍、無電電鍍製程或其他適合金屬沈積製程進行圖案化並沈積。凸塊墊164可為一或多個Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料層。犧牲凸塊墊164可具有小於或大於互連凸塊墊160之面積。一般而言，犧牲凸塊墊164直徑約為互連凸塊墊160之直徑或適於晶圓探針測試之直徑。A plurality of sacrificial bump pads 164 are formed on the active surface 154. The bump pads 164 are patterned and deposited using PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The bump pads 164 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. The sacrificial bump pads 164 can have an area that is less than or greater than the interconnect bump pads 160. In general, the sacrificial bump pads 164 are approximately the diameter of the interconnect bump pads 160 or the diameter of the wafer probe test.

圖7a-7b說明半導體晶圓150之一部分的俯視圖及橫截面圖，其進一步詳細展示半導體晶粒152之凸塊墊陣列162。犧牲凸塊墊164與互連凸塊墊160之陣列呈間隙安置。每個互連凸塊墊160存在一個犧牲凸塊墊164。各犧牲凸塊墊164定位於相應互連凸塊墊160鄰近處。在一實施例中，犧牲凸塊墊164安置於相對於相應互連凸塊墊160呈對角偏移之位置，例如一個凸塊墊直徑上方且向右，如圖6所示。7a-7b illustrate top and cross-sectional views of a portion of a semiconductor wafer 150 showing the bump pad array 162 of the semiconductor die 152 in further detail. The sacrificial bump pads 164 are disposed in a gap with the array of interconnect bump pads 160. There is one sacrificial bump pad 164 for each interconnect bump pad 160. Each sacrificial bump pad 164 is positioned adjacent to the respective interconnect bump pad 160. In one embodiment, the sacrificial bump pads 164 are disposed at a diagonal offset relative to the respective interconnect bump pads 160, such as a bump pad diameter above and to the right, as shown in FIG.

導電鏈路166係使用PVD、CVD、濺鍍、電解電鍍、無電電鍍製程或其他適合金屬沈積製程圖案化而形成於主動表面154上介於互連凸塊墊160與犧牲凸塊墊164之間。導電鏈路166可為一或多個Al、Cu、Sn、Ni、Au、Ag或其他適合導電材料層。導電鏈路166使互連凸塊墊160與犧牲凸塊墊164電連接。犧牲凸塊墊164及導電鏈路166可與互連凸塊墊160同時地形成或在凸塊形成期間形成，從而避免各別加工步驟而簡化製造。Conductive link 166 is formed on active surface 154 between PV bump pad 160 and sacrificial bump pad 164 using PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metal deposition process patterning. . Conductive link 166 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive link 166 electrically interconnects interconnect bump pads 160 with sacrificial bump pads 164. Sacrificial bump pads 164 and conductive links 166 may be formed simultaneously with interconnect bump pads 160 or during bump formation, thereby avoiding separate processing steps and simplifying fabrication.

圖8展示半導體晶圓150之晶圓級探針測試組態。在探針測試期間，亦即在單切之前，半導體晶粒152呈晶圓形式。晶圓級測試確認個別半導體晶粒之連續性、電參數及功能性。通過晶圓探測之各半導體晶粒152歸類為良裸晶粒(KGD)。晶圓探測亦可基於測試結果執行修整操作以調整組件值，例如電阻器修整。晶圓探針測試鑑別的不良半導體晶粒可在更高層次組裝(例如多晶粒封裝及PCB)之前自製造製程中移除。FIG. 8 shows a wafer level probe test configuration for semiconductor wafer 150. The semiconductor die 152 is in the form of a wafer during probe testing, that is, prior to single cut. Wafer level testing confirms the continuity, electrical parameters, and functionality of individual semiconductor dies. Each semiconductor die 152 that is probed by the wafer is classified as a good bare die (KGD). Wafer probing can also perform trimming operations based on test results to adjust component values, such as resistor trimming. The defective semiconductor die identified by the wafer probe test can be removed from the fabrication process prior to assembly at a higher level (eg, multi-die package and PCB).

半導體晶圓150在真空壓力下固定於晶圓操控器170上。晶圓操控器170提供晶圓在x、y及z方向上之移動以達成測試目的。在一實施例中，使用晶圓分類來組織及操控晶圓以供測試。將多個半導體晶圓150置放於一晶匣上以供有效處置。The semiconductor wafer 150 is affixed to the wafer handler 170 under vacuum pressure. Wafer manipulator 170 provides wafer movement in the x, y, and z directions for testing purposes. In one embodiment, wafer classification is used to organize and manipulate the wafer for testing. A plurality of semiconductor wafers 150 are placed on a wafer for efficient disposal.

測試探頭172包括PCB，其具有多個自PCB徑向向內延伸的觸指或觸針174以匹配凸塊墊陣列162之緊密的幾何形狀。觸指174典型地由鎢及具有良好電導率及彈性機械特性之其他金屬製成。觸指174具有20-30 μm間距。各觸指174係指向遠端以提供與凸塊墊陣列162上之相關犧牲凸塊墊164的可靠電連接。測試探頭172之PCB包括連接至觸指174之電跡線，觸指174又連接至電腦測試系統176。電腦測試系統176產生並接收半導體晶粒152之測試信號以確認其連續性、電參數及電功能性。測試探頭172可接觸晶圓150上之一或多個半導體晶粒152。在一實施例中，測試探頭172接觸一個半導體晶粒152，隨後移動至下一個晶粒。或者，測試探頭172可接觸所有半導體晶粒152以測試晶圓150之完整性。電腦測試系統176亦控制晶圓操控器170之移動。在晶圓分類期間，將晶圓150自晶匣上負載及卸載且使用自動圖案識別進行比對以供測試。Test probe 172 includes a PCB having a plurality of fingers or styli 174 extending radially inward from the PCB to match the tight geometry of bump pad array 162. The fingers 174 are typically made of tungsten and other metals having good electrical and mechanical properties. The fingers 174 have a pitch of 20-30 μm. Each finger 174 is directed toward the distal end to provide a reliable electrical connection with the associated sacrificial bump pad 164 on the bump pad array 162. The PCB of test probe 172 includes an electrical trace that is connected to finger 174, which in turn is coupled to computer test system 176. Computer test system 176 generates and receives test signals for semiconductor die 152 to confirm its continuity, electrical parameters, and electrical functionality. Test probe 172 can contact one or more semiconductor dies 152 on wafer 150. In one embodiment, test probe 172 contacts a semiconductor die 152 and then moves to the next die. Alternatively, test probe 172 can contact all of semiconductor die 152 to test the integrity of wafer 150. Computer test system 176 also controls the movement of wafer handler 170. During wafer sorting, wafers 150 are loaded and unloaded from the wafer and compared using automated pattern recognition for testing.

為進行晶圓分類測試，由電腦測試系統176操控晶圓操控器170以使觸指174與犧牲凸塊墊164抵壓嚙合。由電腦測試系統176產生電測試信號，其經由測試探頭172及觸指174發送至犧牲凸塊墊164。電測試信號亦由導電鏈路166發送至互連凸塊墊160。視所執行之測試而定，半導體晶粒152在操作溫度範圍內處理電測試信號。測試結果信號經由互連凸塊墊160、導電鏈路166、犧牲凸塊墊164、觸指174及測試探頭172返回電腦測試系統176。視測試結果而定，將各半導體晶粒152歸類為KGD或鑑別為不良。若電腦測試系統176偵測到測試故障，則不良半導體晶粒以墨點標識或記錄於電腦測試系統中以隨後自製造製程中移除。For wafer sorting testing, the wafer handler 170 is manipulated by the computer test system 176 to force the fingers 174 into compression engagement with the sacrificial bump pads 164. An electrical test signal is generated by computer test system 176 that is sent to sacrificial bump pad 164 via test probe 172 and contact fingers 174. The electrical test signal is also sent by conductive link 166 to interconnect bump pad 160. Depending on the tests performed, the semiconductor die 152 processes the electrical test signal over an operating temperature range. The test result signal is returned to computer test system 176 via interconnect bump pad 160, conductive link 166, sacrificial bump pad 164, finger 174, and test probe 172. Depending on the test results, each semiconductor die 152 is classified as KGD or identified as defective. If the computer test system 176 detects a test failure, the defective semiconductor die is identified by ink dots or recorded in a computer test system for subsequent removal from the manufacturing process.

觸指174典型地具有尖頭以便使得可靠地電連接至凸塊墊164。在晶圓探針測試過程中，觸指174已知會穿透表面且可能損壞凸塊墊。實際上，晶圓探針測試可包括牽引觸指174橫越凸塊墊164，導致在凸塊墊表面留下擦痕。然而，由於晶圓探測係在犧牲凸塊墊164上進行，因此互連凸塊墊160保持未損壞的最初狀態以供隨後形成凸塊。The finger 174 typically has a pointed tip to enable reliable electrical connection to the bump pad 164. During wafer probe testing, the fingers 174 are known to penetrate the surface and may damage the bump pads. In effect, the wafer probe test can include pulling the finger 174 across the bump pad 164, resulting in scratches on the surface of the bump pad. However, since the wafer probing is performed on the sacrificial bump pads 164, the interconnect bump pads 160 remain in an undamaged initial state for subsequent bump formation.

在圖9中，犧牲凸塊墊164及導電鏈路166之一部分視情況藉由濕式蝕刻或乾式蝕刻製程移除。在一實施例中，在作為形成互連凸塊墊160之一部分的蝕刻步驟期間移除犧牲凸塊墊164及該部分導電鏈路166。互連凸塊墊160及導電鏈路166之殘餘截短部分可供凸塊製程利用。由於尚未在互連凸塊墊160上進行晶圓探測，因此該等凸塊墊處於最初狀態以供形成凸塊。晶圓代工廠可對無凸塊晶圓執行晶圓分類測試，且出售或以其他方式轉移具有KGD之無凸塊晶圓的責任。任何第三方凸塊形成服務供應商可接著在具有由晶圓分類測試鑑別之KGD的無凸塊晶圓上形成凸塊。In FIG. 9, one portion of the sacrificial bump pads 164 and conductive links 166 are optionally removed by a wet etch or dry etch process. In an embodiment, the sacrificial bump pads 164 and the portion of the conductive links 166 are removed during an etch step that forms part of the interconnect bump pads 160. The interconnected bump pads 160 and the residual truncated portions of the conductive links 166 can be utilized by the bump process. Since wafer probing has not been performed on the interconnect bump pads 160, the bump pads are in an initial state for forming bumps. Wafer foundries can perform wafer sorting tests on bumpless wafers and sell or otherwise transfer responsibility for KGD-free bump-free wafers. Any third party bump forming service provider can then form bumps on bumpless wafers having KGD identified by wafer sorting testing.

導電材料係使用蒸鍍、電解電鍍、無電電鍍、球式滴落(ball drop)或網版印刷製程沈積於互連凸塊墊160上。導電材料可為Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其組合，其視情況含有助熔材料。舉例而言，導電材料可為共晶Sn/Pb、高鉛焊料或無鉛焊料。導電材料係使用適合之附著或焊接製程焊接至互連凸塊墊160。在一實施例中，藉由將導電材料加熱至其熔點以上對該材料進行回焊以形成球形球體或凸塊180。在一些應用中，對凸塊180進行二次回焊以改良與互連凸塊墊160之電接觸。亦可將凸塊壓縮焊接至互連凸塊墊160。凸塊180代表一種類型之互連結構，其可形成於互連凸塊墊160上。互連結構亦可使用焊線、導電膏、柱形凸塊、微凸塊或其他電互連。The conductive material is deposited on the interconnect bump pads 160 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The conductive material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, optionally containing a fluxing material. For example, the conductive material can be eutectic Sn/Pb, high lead solder, or lead free solder. The electrically conductive material is soldered to the interconnect bump pads 160 using a suitable attachment or soldering process. In one embodiment, the material is reflowed by heating the conductive material above its melting point to form a spherical sphere or bump 180. In some applications, the bumps 180 are secondarily reflowed to improve electrical contact with the interconnect bump pads 160. The bumps may also be compression welded to the interconnect bump pads 160. Bumps 180 represent one type of interconnect structure that can be formed on interconnect bump pads 160. The interconnect structure can also use bond wires, conductive pastes, stud bumps, microbumps, or other electrical interconnects.

圖10a-10b說明凸塊180形成於互連凸塊墊160上之半導體晶粒152的俯視圖及橫截面圖。導電鏈路166之殘餘截短部分對凸塊180或互連凸塊墊160無電效應。10a-10b illustrate top and cross-sectional views of semiconductor die 152 with bumps 180 formed on interconnect bump pads 160. The residual truncated portion of the conductive link 166 has no electrical effect on the bump 180 or the interconnect bump pad 160.

儘管已詳細說明本發明之一或多個實施例，但熟習此項技術者應瞭解，可在不違背如以下申請專利範圍中所闡述之本發明範疇的情況下對彼等實施例進行修改及改造。Although one or more embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the embodiments may be modified and modified without departing from the scope of the invention as set forth in the following claims Transformation.

10．．．半導體晶圓10. . . Semiconductor wafer

12．．．半導體晶粒12. . . Semiconductor grain

14．．．凸塊墊14. . . Bump pad

16．．．晶圓操控器16. . . Wafer controller

18．．．測試探頭18. . . Test probe

20．．．觸指或觸針20. . . Finger or stylus

22．．．電腦測試系統twenty two. . . Computer test system

24．．．焊料凸塊twenty four. . . Solder bump

50．．．電子裝置50. . . Electronic device

52．．．PCB52. . . PCB

54．．．跡線54. . . Trace

56．．．焊線封裝56. . . Wire bond package

58．．．覆晶58. . . Flip chip

60．．．球狀柵格陣列60. . . Spherical grid array

62．．．凸塊晶片載體62. . . Bump wafer carrier

64．．．雙排型封裝64. . . Double row package

66．．．平台柵格陣列66. . . Platform grid array

68．．．多晶片模組68. . . Multi-chip module

70．．．四邊扁平無引腳封裝70. . . Quad flat no-lead package

72．．．四邊扁平封裝72. . . Quad flat package

74．．．半導體晶粒74. . . Semiconductor grain

76．．．接觸墊76. . . Contact pad

78．．．中間載體78. . . Intermediate carrier

80．．．導線80. . . wire

82．．．焊線82. . . Welding wire

84．．．密封劑84. . . Sealants

88．．．半導體晶粒88. . . Semiconductor grain

90．．．載體90. . . Carrier

92．．．底膠或環氧樹脂黏合材料92. . . Primer or epoxy bonding material

94．．．焊線94. . . Welding wire

96．．．接觸墊96. . . Contact pad

98．．．接觸墊98. . . Contact pad

100．．．成型化合物或密封劑100. . . Molding compound or sealant

102．．．接觸墊102. . . Contact pad

104．．．凸塊104. . . Bump

106．．．載體106. . . Carrier

108‧‧‧主動區108‧‧‧active area

110‧‧‧凸塊110‧‧‧Bumps

112‧‧‧凸塊112‧‧‧Bumps

114‧‧‧信號線114‧‧‧ signal line

116‧‧‧成型化合物或密封劑116‧‧‧Forming compounds or sealants

150‧‧‧半導體晶圓150‧‧‧Semiconductor Wafer

152‧‧‧半導體晶粒152‧‧‧Semiconductor grains

154‧‧‧主動表面154‧‧‧Active surface

160‧‧‧凸塊墊160‧‧‧Bump pad

162‧‧‧凸塊墊陣列162‧‧‧Bump pad array

164‧‧‧凸塊墊164‧‧‧Bump pad

166‧‧‧導電鏈路166‧‧‧conductive links

170‧‧‧晶圓操控器170‧‧‧Wafer Manipulator

172‧‧‧測試探頭172‧‧‧Test probe

174‧‧‧觸指174‧‧‧ finger

176‧‧‧電腦測試系統176‧‧‧Computer Test System

180‧‧‧球形球體或凸塊180‧‧‧Spherical spheres or bumps

圖1說明一具有多個含有凸塊墊之晶粒的習知半導體晶圓；Figure 1 illustrates a conventional semiconductor wafer having a plurality of dies containing bump pads;

圖2為凸塊墊上之習知晶圓探測測試組態；2 is a conventional wafer probing test configuration on a bump pad;

圖3為焊料凸塊上之習知晶圓探測測試組態；Figure 3 is a conventional wafer probing test configuration on a solder bump;

圖4說明PCB，其中不同類型之封裝黏著於其表面上；Figure 4 illustrates a PCB in which different types of packages are adhered to their surface;

圖5a-5c進一步詳細說明黏著於PCB上之代表性半導體封裝；Figures 5a-5c illustrate in further detail a representative semiconductor package adhered to a PCB;

圖6說明一具有多個晶粒的半導體晶圓，該等晶粒含有經導電鏈路互連之互連凸塊墊與犧牲凸塊墊；6 illustrates a semiconductor wafer having a plurality of dies having interconnected bump pads and sacrificial bump pads interconnected via conductive links;

圖7a-7b進一步詳細說明經導電鏈路互連之互連凸塊墊與犧牲凸塊墊；Figures 7a-7b further illustrate interconnecting bump pads and sacrificial bump pads interconnected via conductive links;

圖8為具有犧牲凸塊墊之半導體晶粒的晶圓探測測試組態；8 is a wafer probing test configuration of a semiconductor die having a sacrificial bump pad;

圖9說明移除犧牲凸塊墊之後的晶圓；及Figure 9 illustrates the wafer after removal of the sacrificial bump pads; and

圖10a-10b說明移除犧牲凸塊墊之後凸塊形成於互連凸塊墊上之晶圓。10a-10b illustrate wafers with bumps formed on interconnect bump pads after the sacrificial bump pads are removed.

150．．．半導體晶圓150. . . Semiconductor wafer

152．．．半導體晶粒152. . . Semiconductor grain

154．．．主動表面154. . . Active surface

160．．．凸塊墊160. . . Bump pad

162．．．凸塊墊陣列162. . . Bump pad array

164．．．凸塊墊164. . . Bump pad

166．．．導電鏈路166. . . Conductive link

Claims (14)

一種製造半導體裝置之方法，其包含：提供一含有多個半導體晶粒之半導體晶圓；在該半導體晶粒上形成多個互連凸塊墊；在該半導體晶粒之主動表面上以及在該等互連凸塊墊鄰近處形成多個犧牲凸塊墊；在各互連凸塊墊與鄰近犧牲凸塊墊之間形成一導電鏈路；在該等互連凸塊墊上形成凸塊之前藉由電接觸該等犧牲凸塊墊進行晶圓探測；及在晶圓探測之後，在無凸塊之情況下將該半導體晶圓轉移至第三方。 A method of fabricating a semiconductor device, comprising: providing a semiconductor wafer including a plurality of semiconductor dies; forming a plurality of interconnect bump pads on the semiconductor die; on an active surface of the semiconductor die and at the Forming a plurality of sacrificial bump pads adjacent to the interconnect bump pads; forming a conductive link between each interconnect bump pad and the adjacent sacrificial bump pads; borrowing before forming the bumps on the interconnect bump pads Wafer detection is performed by electrically contacting the sacrificial bump pads; and after wafer inspection, the semiconductor wafer is transferred to a third party without bumps. 如申請專利範圍第1項之方法，其進一步包括相對於該等互連凸塊墊對角偏移地形成該等犧牲凸塊墊。 The method of claim 1, further comprising forming the sacrificial bump pads diagonally offset relative to the interconnecting bump pads. 如申請專利範圍第1項之方法，其進一步包括同時地形成該等犧牲凸塊墊、互連凸塊墊及導電鏈路。 The method of claim 1, further comprising simultaneously forming the sacrificial bump pads, the interconnect bump pads, and the conductive links. 如申請專利範圍第1項之方法，其進一步包括在晶圓探測之後移除該等犧牲凸塊墊以及該導電鏈路之一部分。 The method of claim 1, further comprising removing the sacrificial bump pads and a portion of the conductive links after wafer inspection. 如申請專利範圍第1項之方法，其中該等犧牲凸塊墊具有不同於該等互連凸塊墊之直徑。 The method of claim 1, wherein the sacrificial bump pads have a different diameter than the interconnecting bump pads. 一種製造半導體裝置之方法，其包含：提供一含有多個半導體晶粒之半導體晶圓；在該半導體晶粒上、於一凸塊墊陣列內形成一互連凸塊墊； 形成一犧牲凸塊墊於該凸塊墊陣列內且電連接至該互連凸塊墊；藉由電接觸未與該互連凸塊墊接觸之該犧牲凸塊墊進行晶圓探測；及藉由蝕刻處理自該半導體晶粒上移除該犧牲凸塊墊。 A method of fabricating a semiconductor device, comprising: providing a semiconductor wafer including a plurality of semiconductor dies; forming an interconnect bump pad on the semiconductor die in an array of bump pads; Forming a sacrificial bump pad in the bump pad array and electrically connecting to the interconnect bump pad; performing wafer detection by electrically contacting the sacrificial bump pad not in contact with the interconnect bump pad; The sacrificial bump pads are removed from the semiconductor die by an etch process. 如申請專利範圍第6項之方法，其進一步包括在晶圓探測之後移除該犧牲凸塊墊。 The method of claim 6, further comprising removing the sacrificial bump pad after wafer inspection. 如申請專利範圍第6項之方法，其進一步包括同時地形成該犧牲凸塊墊及該互連凸塊墊。 The method of claim 6, further comprising simultaneously forming the sacrificial bump pad and the interconnect bump pad. 如申請專利範圍第6項之方法，其進一步包括將該犧牲凸塊墊安置於相對於該互連凸塊墊呈對角偏移之位置。 The method of claim 6, further comprising positioning the sacrificial bump pad at a position that is diagonally offset relative to the interconnecting bump pad. 如申請專利範圍第6項之方法，其進一步包括在無凸塊之情況下探測晶圓後，將該半導體晶圓轉移至第三方。 The method of claim 6, further comprising transferring the semiconductor wafer to a third party after detecting the wafer without bumps. 一種半導體裝置，其包含：一半導體晶粒；一互連凸塊墊，其形成於該半導體晶粒上；一犧牲凸塊墊，其形成於該半導體晶粒之一表面上並且電連接至該互連凸塊墊並且自該互連凸塊墊呈對角偏移；及一晶圓探測，其電接觸未與該互連凸塊墊接觸之該犧牲凸塊墊。 A semiconductor device comprising: a semiconductor die; an interconnect bump pad formed on the semiconductor die; a sacrificial bump pad formed on a surface of the semiconductor die and electrically connected to the Interconnecting the bump pads and diagonally offset from the interconnect bump pads; and a wafer probing electrically contacting the sacrificial bump pads that are not in contact with the interconnect bump pads. 如申請專利範圍第11項之半導體裝置，其進一步包括一被形成在該互連凸塊墊上之凸塊。 The semiconductor device of claim 11, further comprising a bump formed on the interconnect bump pad. 如申請專利範圍第11項之半導體裝置，其中該犧牲 凸塊墊及互連凸塊墊係同時地形成。 Such as the patent device of claim 11 of the semiconductor device, wherein the sacrifice The bump pads and the interconnect bump pads are formed simultaneously. 如申請專利範圍第11項之半導體裝置，其進一步包括一導電鏈路，其形成於該互連凸塊墊與該犧牲凸塊墊之間。 The semiconductor device of claim 11, further comprising a conductive link formed between the interconnect bump pad and the sacrificial bump pad.