TWI498949B - Semiconductor device and methods for forming the same - Google Patents
Semiconductor device and methods for forming the same Download PDFInfo
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Description
本發明係有關於一種半導體技術，特別是有關於一種具有淺溝槽隔離結構(shallow trench isolation，STI)的高壓半導體裝置之製造方法。The present invention relates to a semiconductor technology, and more particularly to a method of fabricating a high voltage semiconductor device having shallow trench isolation (STI).
目前電源管理積體電路(power management integrated circuit，PMIC)最常應用雙極型-互補式金屬氧化物半導體電晶體-橫向擴散金屬氧化物半導體電晶體(bipolar-CMOS(complementary metal oxide semiconductor transistor)-LDMOS(lateral diffused metal oxide semiconductor transistor)，BCD)的結構。互補式金屬氧化物半導體電晶體用於數位電路，雙極型電晶體可驅動高電流，而橫向擴散金屬氧化物半導體電晶體具有高電壓(high voltage，HV)的處理能力。節約電源及高速效能的趨勢影響了橫向擴散金屬氧化物半導體電晶體的結構，半導體產業已製造出低漏電流(leakage)及低導通電阻(on-resistance，RDSon)的橫向擴散金屬氧化物半導體電晶體。導通電阻是影響習知的橫向金屬氧化物半導體場效電晶體(MOS field effect transistor，MOSFET)裝置的電源損耗的重要因素。At present, the power management integrated circuit (PMIC) is most commonly used in a bipolar-CMOS (complementary metal oxide semiconductor transistor)-bipolar-CMOS (complementary metal oxide semiconductor transistor)- Structure of LDMOS (lateral diffused metal oxide semiconductor transistor, BCD). A complementary metal oxide semiconductor transistor is used for a digital circuit, a bipolar transistor can drive a high current, and a laterally diffused metal oxide semiconductor transistor has a high voltage (HV) processing capability. The trend of saving power and high-speed performance affects the structure of laterally diffused metal-oxide-semiconductor transistors. The semiconductor industry has produced low-leakage and low-on-resistance (RDSon) laterally diffused metal oxide semiconductors. Crystal. On-resistance is an important factor affecting the power loss of conventional MOS field effect transistor (MOSFET) devices.
發展低導通電阻的裝置，還需要考量到崩潰電壓 (breakdown voltage)。雖然橫向擴散金屬氧化物半導體電晶體裝置已發展出各種結構或增加元件尺寸，以承受高崩潰電壓，然而元件尺寸增加卻造成導通電阻增加。Devices that develop low on-resistance also need to consider the breakdown voltage (breakdown voltage). Although laterally diffused metal oxide semiconductor transistor devices have developed various structures or increased component sizes to withstand high breakdown voltages, an increase in component size results in an increase in on-resistance.
因此，有必要尋求一種新穎的半導體裝置之製造方法，其能夠解決或改善上述的問題。Therefore, it is necessary to find a novel manufacturing method of a semiconductor device which can solve or ameliorate the above problems.
本發明實施例係提供一種半導體裝置，包括一基板。一隔離結構形成於基板內，以界定出基板的一主動區，其中主動區內具有一場板區。一閘極介電層形成於場板區外側的基板上。一段差閘極介電結構形成於場板區內的基板上，其中段差閘極介電結構的厚度大於閘極介電層的厚度，且小於隔離結構的厚度。Embodiments of the present invention provide a semiconductor device including a substrate. An isolation structure is formed in the substrate to define an active region of the substrate, wherein the active region has a field region. A gate dielectric layer is formed on the substrate outside the field plate region. A differential gate dielectric structure is formed on the substrate in the field plate region, wherein the thickness of the step gate dielectric structure is greater than the thickness of the gate dielectric layer and less than the thickness of the isolation structure.
本發明實施例係提供一種半導體裝置之製造方法，包括提供一基板，其中基板內具有一隔離結構，以界定出基板的一主動區。在主動區內定義一場板區。在場板區外側的基板上形成一閘極介電層，且在場板區內的基板上形成一段差閘極介電結構，其中段差閘極介電結構的厚度大於閘極介電層的厚度，且小於隔離結構的厚度。Embodiments of the present invention provide a method of fabricating a semiconductor device, including providing a substrate having an isolation structure therein to define an active region of the substrate. Define a board area in the active zone. Forming a gate dielectric layer on the substrate outside the field plate region, and forming a differential gate dielectric structure on the substrate in the field plate region, wherein the thickness of the stepped gate dielectric structure is greater than that of the gate dielectric layer Thickness and less than the thickness of the isolation structure.
100‧‧‧基板100‧‧‧Substrate
102、103‧‧‧N型埋藏層102, 103‧‧‧N type buried layer
104‧‧‧N型漂移區104‧‧‧N type drift zone
105‧‧‧P型基體區105‧‧‧P type base area
106‧‧‧氮化矽層106‧‧‧layer of tantalum nitride
108‧‧‧墊氧化層108‧‧‧Mat oxide layer
110‧‧‧隔離結構110‧‧‧Isolation structure
115‧‧‧開口115‧‧‧ openings
120、150‧‧‧罩幕層120, 150‧‧ ‧ cover layer
130、160‧‧‧段差閘極介電結構130, 160‧ ‧ segment differential gate dielectric structure
135‧‧‧閘極介電層135‧‧‧ gate dielectric layer
140‧‧‧氧化層140‧‧‧Oxide layer
145‧‧‧熱氧化層145‧‧‧ Thermal Oxide
200‧‧‧主動區200‧‧‧active area
300‧‧‧場板區300‧‧‧ field area
400‧‧‧磊晶層400‧‧‧ epitaxial layer
第1至4A圖係繪示出本發明一實施例之半導體裝置之製造方法的剖面示意圖。1 to 4A are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
第4B圖係繪示出本發明另一實施例之半導體裝置的剖面示意圖。4B is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.
第5至9A圖係繪示出本發明另一實施例之半導體裝置之製造方法的剖面示意圖。5 to 9A are cross-sectional views showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.
第9B圖係繪示出本發明另一實施例之半導體裝置的剖面示意圖。Figure 9B is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.
以下說明本發明實施例之半導體裝置之製造方法。然而，可輕易瞭解本發明所提供的實施例僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。再者，在本發明實施例之圖式及說明內容中係使用相同的標號來表示相同或相似的部件。Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described. However, the present invention is to be understood as being limited to the details of the present invention. In the drawings and the description of the embodiments of the present invention, the same reference numerals are used to refer to the same or similar parts.
請參照第4A圖，其繪示出本發明一實施例之半導體裝置的剖面示意圖。在本實施例中，半導體裝置可實施於高壓N型金屬氧化物半導體裝置(例如，N型橫向擴散金屬氧化物半導體)，且包括一基板100、一隔離結構110、一閘極介電層135及一段差(step)閘極介電結構130。基板100具有主動區200，主動區200內具有一場板(field plate)區300。在本實施例中，基板100可包括一半導體基材(例如，矽基材)(未繪示)及位於半導體基材上的磊晶層400。在其他實施例中，基板100可僅由半導體基材所構成。Please refer to FIG. 4A, which is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. In this embodiment, the semiconductor device can be implemented in a high voltage N-type metal oxide semiconductor device (eg, an N-type laterally diffused metal oxide semiconductor), and includes a substrate 100, an isolation structure 110, and a gate dielectric layer 135. And a step gate dielectric structure 130. The substrate 100 has an active region 200 having a field plate region 300 therein. In this embodiment, the substrate 100 can include a semiconductor substrate (eg, a germanium substrate) (not shown) and an epitaxial layer 400 on the semiconductor substrate. In other embodiments, substrate 100 can be constructed solely of a semiconductor substrate.
隔離結構110形成於基板100內，以界定基板100的主動區200。在本實施例中，隔離結構110可為淺溝槽隔離結構。The isolation structure 110 is formed within the substrate 100 to define the active region 200 of the substrate 100. In this embodiment, the isolation structure 110 can be a shallow trench isolation structure.
閘極介電層135形成於場板區300外側的基板100上。在本實施例中，閘極介電層135可由氧化物或其他適合的 介電材料所構成。A gate dielectric layer 135 is formed on the substrate 100 outside the field plate region 300. In this embodiment, the gate dielectric layer 135 may be oxide or other suitable Made up of dielectric materials.
段差閘極介電結構130形成於場板區300內的基板100上。在本實施例中，段差閘極介電結構130的厚度大於閘極介電層135的厚度，且小於隔離結構110的厚度。在本實施例中，段差閘極介電結構130更延伸入基板100內，且段差閘極介電結構130的深度小於隔離結構110的深度。在一實施例中，段差閘極介電結構130可為矽局部氧化(local oxidation of silicon，LOCOS)結構。如此一來，基板100同時具有由矽局部氧化結構所構成的段差閘極介電結構130及淺溝槽隔離溝槽所構成的隔離結構110。A stepped gate dielectric structure 130 is formed on the substrate 100 within the field plate region 300. In the present embodiment, the thickness of the stepped gate dielectric structure 130 is greater than the thickness of the gate dielectric layer 135 and less than the thickness of the isolation structure 110. In the present embodiment, the stepped gate dielectric structure 130 extends into the substrate 100, and the depth of the stepped gate dielectric structure 130 is less than the depth of the isolation structure 110. In one embodiment, the stepped gate dielectric structure 130 can be a local oxidation of silicon (LOCOS) structure. In this way, the substrate 100 has an isolation structure 110 composed of a stepped gate dielectric structure 130 and a shallow trench isolation trench formed by a localized oxide structure.
在本實施例中，基板100可為一N型基板，包括一N型漂移(drift)區104，位於場板區300及隔離結構110之間的主動區200內，且包括一N型埋藏層(N-type buried layer，NBL)102，位於半導體材料層與N型漂移區104之間。In this embodiment, the substrate 100 can be an N-type substrate, including an N-type drift region 104, located in the active region 200 between the field plate region 300 and the isolation structure 110, and including an N-type buried layer. An N-type buried layer (NBL) 102 is located between the semiconductor material layer and the N-type drift region 104.
在習知的高壓(例如，大於20伏特)裝置中，多晶矽閘極延伸至場氧化層或任何的隔離結構，以避免高電場。然而，卻反而降低崩潰電壓。在本實施例中，在場板區內形成矽局部氧化結構，取代習知的高壓裝置中作為場氧化層的淺溝槽隔離結構，使半導體基板同時具有由矽局部氧化結構所構成的段差閘極介電結構及淺溝槽隔離溝槽所構成的隔離結構。相較於習知的高壓裝置中作為場氧化層的淺溝槽隔離結構，由於段差閘極介電結構130的厚度小於隔離結構110的厚度，使段差閘極介電結構130延伸入基板100內的深度小於隔離結構110的深度，因而從汲極至源極的電流路徑得以縮短。因此，可降 低導通電阻且維持高崩潰電壓。In conventional high voltage (e.g., greater than 20 volts) devices, the polysilicon gate extends to the field oxide layer or any isolation structure to avoid high electric fields. However, it actually reduces the breakdown voltage. In this embodiment, a tantalum partial oxidation structure is formed in the field plate region to replace the shallow trench isolation structure as a field oxide layer in a conventional high voltage device, so that the semiconductor substrate has a differential gate composed of a localized oxide structure. An isolation structure composed of a dielectric structure and a shallow trench isolation trench. Compared with the shallow trench isolation structure as the field oxide layer in the conventional high voltage device, since the thickness of the step gate dielectric structure 130 is smaller than the thickness of the isolation structure 110, the step gate dielectric structure 130 is extended into the substrate 100. The depth is less than the depth of the isolation structure 110, and thus the current path from the drain to the source is shortened. Therefore, it can be lowered Low on-resistance and maintain high breakdown voltage.
請參照第4B圖，其繪示出本發明另一實施例之半導體裝置的剖面示意圖，其中相同於第4A圖的部件係使用相同的標號並省略其說明。在本實施例中，半導體裝置可實施於高壓P型金屬氧化物半導體裝置(例如，P型橫向擴散金屬氧化物半導體)，且結構類似於第4A圖的實施例，不同之處在於基板100可為一P型基板，包括一P型基體(body)區105，位於場板區300及隔離結構110之間的主動區200內，且包括一N型埋藏層103，位於主動區200內的P型基體區105下方。Referring to FIG. 4B, a cross-sectional view of a semiconductor device according to another embodiment of the present invention is illustrated, wherein components that are the same as those in FIG. 4A are given the same reference numerals and their description is omitted. In the present embodiment, the semiconductor device can be implemented in a high voltage P-type metal oxide semiconductor device (for example, a P-type laterally diffused metal oxide semiconductor), and the structure is similar to the embodiment of FIG. 4A, except that the substrate 100 can be A P-type substrate includes a P-type body region 105, located in the active region 200 between the field plate region 300 and the isolation structure 110, and includes an N-type buried layer 103, which is located in the active region 200. Below the type substrate region 105.
請參照第9A圖，其繪示出本發明另一實施例之半導體裝置的剖面示意圖，其中相同於第4A圖的部件係使用相同的標號並省略其說明。在本實施例中，半導體裝置可實施於高壓N型橫向擴散金屬氧化物半導體裝置，且包括一基板100、一隔離結構110、一閘極介電層135及一段差閘極介電結構160。基板100具有主動區200，主動區200內具有一場板區300。Referring to FIG. 9A, there is shown a cross-sectional view of a semiconductor device according to another embodiment of the present invention, wherein components that are the same as those in FIG. 4A are given the same reference numerals and their description is omitted. In this embodiment, the semiconductor device can be implemented in a high voltage N-type laterally diffused metal oxide semiconductor device, and includes a substrate 100, an isolation structure 110, a gate dielectric layer 135, and a differential gate dielectric structure 160. The substrate 100 has an active region 200 having a field plate region 300 therein.
隔離結構110形成於基板100內，以界定基板100的主動區200。在本實施例中，隔離結構110可為淺溝槽隔離結構。閘極介電層135形成於場板區300外側的基板100上。The isolation structure 110 is formed within the substrate 100 to define the active region 200 of the substrate 100. In this embodiment, the isolation structure 110 can be a shallow trench isolation structure. A gate dielectric layer 135 is formed on the substrate 100 outside the field plate region 300.
段差閘極介電結構160形成於場板區300內的基板100上及閘極介電層135之間。在本實施例中，段差閘極介電結構160的厚度大於閘極介電層135的厚度，且小於隔離結構110的厚度。在一實施例中，段差閘極介電結構160更包括位於底部的一熱氧化層145。The stepped gate dielectric structure 160 is formed on the substrate 100 in the field plate region 300 and between the gate dielectric layers 135. In the present embodiment, the thickness of the stepped gate dielectric structure 160 is greater than the thickness of the gate dielectric layer 135 and less than the thickness of the isolation structure 110. In one embodiment, the stepped gate dielectric structure 160 further includes a thermal oxide layer 145 at the bottom.
在本實施例中，基板100可為一N型基板，包括一N型漂移區104，位於主動區200內的場板區300及隔離結構110之間，且包括一N型埋藏層102，位於隔離結構110及主動區200下方。In this embodiment, the substrate 100 can be an N-type substrate, including an N-type drift region 104, located between the field plate region 300 and the isolation structure 110 in the active region 200, and includes an N-type buried layer 102. The isolation structure 110 and the active area 200 are below.
在本實施例中，在場板區內形成段差閘極介電結構，取代習知的高壓裝置中作為場氧化層的淺溝槽隔離結構。相較於習知的高壓裝置中作為場氧化層的淺溝槽隔離隔離結構，由於段差閘極介電結構160的厚度小於隔離結構110的厚度，且段差閘極介電結構160形成於基板100上方而未延伸入基板100內，因此，相較於前述實施例，可進一步縮短從汲極至源極的電流路徑，以進一步降低導通電阻。In this embodiment, a stepped gate dielectric structure is formed in the field plate region to replace the shallow trench isolation structure as a field oxide layer in a conventional high voltage device. Compared with the shallow trench isolation isolation structure as the field oxide layer in the conventional high voltage device, since the thickness of the step gate dielectric structure 160 is smaller than the thickness of the isolation structure 110, the step gate dielectric structure 160 is formed on the substrate 100. The upper portion does not extend into the substrate 100. Therefore, the current path from the drain to the source can be further shortened to further reduce the on-resistance compared to the foregoing embodiment.
請參照第9B圖，其繪示出本發明另一實施例之半導體裝置的剖面示意圖，其中相同於第9A圖的部件係使用相同的標號並省略其說明。在本實施例中，半導體裝置可實施於高壓P型橫向擴散金屬氧化物半導體裝置，且結構類似於第9A圖的實施例，不同之處在於基板100可為一P型基板，包括一P型基體區105，位於主動區200內的場板區300及隔離結構110之間，且包括一N型埋藏層103，位於主動區200內的P型基體區105下方。Referring to FIG. 9B, a cross-sectional view of a semiconductor device according to another embodiment of the present invention is illustrated, wherein components that are the same as those in FIG. 9A are given the same reference numerals and their description is omitted. In this embodiment, the semiconductor device can be implemented in a high voltage P-type laterally diffused metal oxide semiconductor device, and the structure is similar to the embodiment of FIG. 9A, except that the substrate 100 can be a P-type substrate, including a P-type. The base region 105 is located between the field plate region 300 and the isolation structure 110 in the active region 200 and includes an N-type buried layer 103 below the P-type base region 105 in the active region 200.
第1至4A圖係繪示出本發明一實施例之半導體裝置之製造方法的剖面示意圖。請參照第1圖，提供一基板100，其具有一主動區200，主動區200內具有一場板區300。在本實施例中，基板100可包括一半導體基材(例如，矽基材)(未繪示)及位於半導體基材上的磊晶層400。在其他實施例中，基板 100可僅由半導體基材所構成。1 to 4A are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1, a substrate 100 is provided having an active area 200 having a field plate region 300 therein. In this embodiment, the substrate 100 can include a semiconductor substrate (eg, a germanium substrate) (not shown) and an epitaxial layer 400 on the semiconductor substrate. In other embodiments, the substrate 100 may be composed only of a semiconductor substrate.
首先，在基板100上形成一硬式罩幕層(例如，墊氧化層(pad oxide)106及位於上方的氮化矽層108)，可透過習知的微影及蝕刻製程，圖案化硬式罩幕層而定義出隔離結構區及暴露出基板100，蝕刻暴露出的基板100，以在基板100內形成隔離溝槽(未標示)。接著，可在隔離溝槽的側壁上形成襯層(liner，未繪示)，且進行一高密度電漿化學氣相沉積(high density plasma chemical vapor deposition，HDPCVD)製程，在硬式罩幕層(即，墊氧化層106及氮化矽層108)上形成一高密度電漿氧化層(未繪示)，並填入隔離溝槽，以在基板100內形成隔離結構110(例如，淺溝槽隔離結構)，且界定出基板100的主動區200。接著，進行一化學機械研磨(chemical mechanical polishing，CMP)製程，去除氮化矽層108上多餘的高密度電漿氧化層，以平坦化基板100的表面。First, a hard mask layer (for example, a pad oxide 106 and a tantalum nitride layer 108 above) is formed on the substrate 100, and the hard mask can be patterned by a conventional lithography and etching process. The layers define the isolation structure regions and expose the substrate 100, etching the exposed substrate 100 to form isolation trenches (not labeled) within the substrate 100. Then, a liner (not shown) may be formed on the sidewall of the isolation trench, and a high density plasma chemical vapor deposition (HDPCVD) process is performed on the hard mask layer ( That is, a high-density plasma oxide layer (not shown) is formed on the pad oxide layer 106 and the tantalum nitride layer 108), and the isolation trench is filled to form the isolation structure 110 in the substrate 100 (for example, a shallow trench). The isolation structure) and defines the active region 200 of the substrate 100. Next, a chemical mechanical polishing (CMP) process is performed to remove excess high-density plasma oxide layer on the tantalum nitride layer 108 to planarize the surface of the substrate 100.
在本實施例中，基板100可為一N型基板。在場板區300及隔離結構110之間的主動區200內形成一N型漂移區104，且在半導體材料層與N型漂移區104之間形成一N型埋藏層102。In this embodiment, the substrate 100 can be an N-type substrate. An N-type drift region 104 is formed in the active region 200 between the field plate region 300 and the isolation structure 110, and an N-type buried layer 102 is formed between the semiconductor material layer and the N-type drift region 104.
請參照第2圖，在基板100上形成一罩幕層120(例如，光阻)，並進行習知的微影及蝕刻製程，圖案化基板100上的硬式罩幕層(即，墊氧化層106及氮化矽層108)，以在場板區300內的硬式罩幕層上形成一開口115，且暴露出部分的基板100。Referring to FIG. 2, a mask layer 120 (eg, photoresist) is formed on the substrate 100, and a conventional lithography and etching process is performed to pattern the hard mask layer on the substrate 100 (ie, the pad oxide layer). 106 and the tantalum nitride layer 108) form an opening 115 on the hard mask layer in the field plate region 300 and expose a portion of the substrate 100.
請參照第3圖，在去除罩幕層120後，可進行一 濕式氧化成長(wet oxide growth)製程及緻密化(densification)製程，以在開口115內形成一絕緣結構(例如，矽局部氧化(local oxidation of silicon，LOCOS)結構)，其作為一段差閘極介電結構130。在本實施例中，段差閘極介電結構130延伸入基板100內，且段差閘極介電結構130的深度小於隔離結構110的深度。在本實施例中，基板100同時具有由矽局部氧化結構所構成的段差閘極介電結構130及淺溝槽隔離溝槽所構成的隔離結構110。Referring to FIG. 3, after removing the mask layer 120, one can be performed. A wet oxide growth process and a densification process to form an insulating structure (eg, a local oxidation of silicon (LOCOS) structure) in the opening 115 as a differential gate Dielectric structure 130. In the present embodiment, the stepped gate dielectric structure 130 extends into the substrate 100, and the depth of the stepped gate dielectric structure 130 is less than the depth of the isolation structure 110. In the present embodiment, the substrate 100 has an isolation structure 110 composed of a stepped gate dielectric structure 130 and a shallow trench isolation trench formed by a localized oxide structure.
請參照第4A圖，在形成段差閘極介電結構130後，可進行蝕刻製程，以去除硬式罩幕層(即，墊氧化層106及氮化矽層108)。在上述步驟中，段差閘極介電結構130可作為去除墊氧化層106及氮化矽層108的罩幕層，而不需額外形成另一罩幕層。接著，在場板區300外側的基板100上形成一閘極介電層135，以進行後續之半導體製程步驟。在本實施例中，閘極介電層135可由氧化物或其他適合的介電材料所構成。在本實施例中，段差閘極介電結構130的厚度大於閘極介電層135的厚度，且小於隔離結構110的厚度。Referring to FIG. 4A, after forming the stepped gate dielectric structure 130, an etching process may be performed to remove the hard mask layer (ie, the pad oxide layer 106 and the tantalum nitride layer 108). In the above steps, the stepped gate dielectric structure 130 can serve as a mask layer for removing the pad oxide layer 106 and the tantalum nitride layer 108 without additionally forming another mask layer. Next, a gate dielectric layer 135 is formed on the substrate 100 outside the field plate region 300 for subsequent semiconductor processing steps. In this embodiment, the gate dielectric layer 135 can be formed of an oxide or other suitable dielectric material. In the present embodiment, the thickness of the stepped gate dielectric structure 130 is greater than the thickness of the gate dielectric layer 135 and less than the thickness of the isolation structure 110.
在另一實施例中，基板100可為一P型基板。在場板區300及隔離結構110之間的主動區200內形成一P型基體區105，取代第4A圖中的N型漂移區104，且在主動區200內的P型基體區105下方形成一N型埋藏層103，取代第4A圖中的N型埋藏層102，如第4B圖所示。In another embodiment, the substrate 100 can be a P-type substrate. A P-type base region 105 is formed in the active region 200 between the field plate region 300 and the isolation structure 110, replacing the N-type drift region 104 in FIG. 4A, and is formed under the P-type base region 105 in the active region 200. An N-type buried layer 103 replaces the N-type buried layer 102 in FIG. 4A as shown in FIG. 4B.
習知的半導體製程中，在基板內形成同時形成場氧化層及隔離結構，並進行化學機械研磨製程後，直接將基板 上的硬式罩幕層(例如，墊氧化層及氮化矽層)去除，接著進行後續的製程步驟。根據本發明一實施例，在進行化學機械研磨製程之後及去除硬式罩幕層之前，額外形成定義具有對應場板區的開口的一罩幕層，並透過蝕刻製程及濕式氧化成長製程，在場板區內形成矽局部氧化結構，取代習知的高壓裝置中作為場氧化層的淺溝槽隔離結構，使半導體基板同時具有由矽局部氧化結構所構成的段差閘極介電結構及淺溝槽隔離溝槽所構成的隔離結構。相較於習知的高壓裝置中作為場氧化層的淺溝槽隔離結構，由於段差閘極介電結構130的厚度小於隔離結構110的厚度，且段差閘極介電結構130延伸入基板100內的深度小於隔離結構110的深度，因而從汲極至源極的電流路徑得以縮短。因此，可降低導通電阻且維持高崩潰電壓，進而降低橫向金屬氧化物半導體場效電晶體裝置的電源損耗。In a conventional semiconductor process, a field oxide layer and an isolation structure are simultaneously formed in a substrate, and after a chemical mechanical polishing process, the substrate is directly The upper hard mask layer (eg, the pad oxide layer and the tantalum nitride layer) is removed, followed by subsequent processing steps. According to an embodiment of the present invention, after performing the chemical mechanical polishing process and before removing the hard mask layer, a mask layer defining an opening having a corresponding field plate region is additionally formed, and the etching process and the wet oxidation growth process are performed. A localized oxidation structure is formed in the field plate region to replace the shallow trench isolation structure as a field oxide layer in a conventional high voltage device, so that the semiconductor substrate has a stepped gate dielectric structure and a shallow trench formed by a localized oxide structure. The isolation structure formed by the trench isolation trench. Compared with the shallow trench isolation structure as the field oxide layer in the conventional high voltage device, since the thickness of the step gate dielectric structure 130 is smaller than the thickness of the isolation structure 110, the step gate dielectric structure 130 extends into the substrate 100. The depth is less than the depth of the isolation structure 110, and thus the current path from the drain to the source is shortened. Therefore, the on-resistance can be lowered and a high breakdown voltage can be maintained, thereby reducing the power loss of the lateral metal oxide semiconductor field effect transistor device.
第5至9A圖係繪示出本發明另一實施例之半導體裝置之製造方法的剖面示意圖，其中相同於第1至4A圖的部件係使用相同的標號並省略其說明。請參照第5圖，，提供一基板100，其具有一主動區200，主動區200內具有一場板區300。5 to 9A are cross-sectional views showing a method of manufacturing a semiconductor device according to another embodiment of the present invention, wherein the same components as those of the first to fourth embodiments are denoted by the same reference numerals and the description thereof will be omitted. Referring to FIG. 5, a substrate 100 is provided having an active area 200 having a field plate region 300 therein.
首先，在基板100上形成一硬式罩幕層(例如，墊氧化層106及位於上方的氮化矽層108)，可透過習知的微影及蝕刻製程，圖案化硬式罩幕層而定義出隔離結構區及暴露出基板100，蝕刻暴露出的基板100，以在基板100內形成隔離溝槽(未標示)。接著，可在隔離溝槽的側壁上形成襯層(未繪示)，且進行一高密度電漿化學氣相沉積製程，在硬式罩幕層(即， 墊氧化層106及氮化矽層108)上形成一高密度電漿氧化層(未繪示)，並填入隔離溝槽，以在基板100內形成隔離結構110(例如，淺溝槽隔離結構)，且界定出基板100的主動區200。接著，進行一化學機械研磨製程，去除氮化矽層108上多餘的高密度電漿氧化層，以平坦化基板100的表面。First, a hard mask layer (for example, a pad oxide layer 106 and a tantalum nitride layer 108 above) is formed on the substrate 100, and can be defined by patterning a hard mask layer by a conventional lithography and etching process. The substrate region is isolated and exposed, and the exposed substrate 100 is etched to form isolation trenches (not labeled) within the substrate 100. Then, a liner (not shown) may be formed on the sidewall of the isolation trench, and a high-density plasma chemical vapor deposition process is performed on the hard mask layer (ie, A high-density plasma oxide layer (not shown) is formed on the pad oxide layer 106 and the tantalum nitride layer 108), and is filled in the isolation trench to form the isolation structure 110 in the substrate 100 (for example, a shallow trench isolation structure) And defining the active region 200 of the substrate 100. Next, a chemical mechanical polishing process is performed to remove excess high-density plasma oxide layer on the tantalum nitride layer 108 to planarize the surface of the substrate 100.
在本實施例中，基板100可為一N型基板。在場板區300及隔離結構110之間的主動區200內形成一N型漂移區104，且在半導體材料層與N型漂移區104之間形成一N型埋藏層102。In this embodiment, the substrate 100 can be an N-type substrate. An N-type drift region 104 is formed in the active region 200 between the field plate region 300 and the isolation structure 110, and an N-type buried layer 102 is formed between the semiconductor material layer and the N-type drift region 104.
請參照第6圖，在基板100上形成一罩幕層120，並進行習知的微影及蝕刻製程，圖案化基板100上的硬式罩幕層(即，墊氧化層106及氮化矽層108)，以在場板區300內的硬式罩幕層上形成一開口115，且暴露出部分的基板100。Referring to FIG. 6, a mask layer 120 is formed on the substrate 100, and a conventional lithography and etching process is performed to pattern the hard mask layer on the substrate 100 (ie, the pad oxide layer 106 and the tantalum nitride layer). 108), an opening 115 is formed on the hard mask layer in the field plate region 300, and a portion of the substrate 100 is exposed.
請參照第7圖，在去除罩幕層120後，可進行一高溫氧化(high temperature oxide，HTO)沉積製程及緻密化製程，在硬式罩幕層上全面性地形成一氧化層140，並填入硬式罩幕層內的開口115。在本實施例中，可在形成氧化層140之前，進行一熱氧化(thermal oxide)製程，以在開口115的底部內形成一熱氧化層145，以增加基板100與氧化層140之間的附著力，避免氧化層140自基板100脫離，且可釋放部分的電荷。接著，透過習知的微影製程，在氧化層140上形成一罩幕層150，並進行習知的蝕刻製程，圖案化氧化層140，以在開口115內及其上方形成一絕緣結構，作為一段差閘極介電結構160，且暴露出隔離結構110及硬式罩幕層，如第8圖所示。 在上述步驟中，硬式罩幕層可做為蝕刻終止層，防止過度蝕刻而對下層材料產生嚴重的破壞，且避免降低隔離結構110的隔離效果。Referring to FIG. 7 , after the mask layer 120 is removed, a high temperature oxide (HTO) deposition process and a densification process can be performed, and an oxide layer 140 is formed on the hard mask layer in a comprehensive manner. Into the opening 115 in the hard mask layer. In this embodiment, a thermal oxide process may be performed to form a thermal oxide layer 145 in the bottom of the opening 115 to increase adhesion between the substrate 100 and the oxide layer 140 before forming the oxide layer 140. The force prevents the oxide layer 140 from being detached from the substrate 100 and can release a portion of the charge. Next, a mask layer 150 is formed on the oxide layer 140 by a conventional lithography process, and a conventional etching process is performed to pattern the oxide layer 140 to form an insulating structure in and over the opening 115. A differential gate dielectric structure 160 exposes the isolation structure 110 and the hard mask layer as shown in FIG. In the above steps, the hard mask layer can be used as an etch stop layer to prevent excessive etching from causing severe damage to the underlying material and to avoid reducing the isolation effect of the isolation structure 110.
請參照第9A圖，在形成段差閘極介電結構160後，可進行習知的蝕刻製程，以去除硬式罩幕層(即，墊氧化層106及氮化矽層108)。在上述步驟中，段差閘極介電結構160可作為去除墊氧化層106及氮化矽層108的罩幕層，而不需額外形成另一罩幕層。接著，在場板區300外側的基板100上形成一閘極介電層135，以進行後續之半導體製程步驟。在本實施例中，段差閘極介電結構160的厚度大於閘極介電層135的厚度，且小於隔離結構110的厚度。Referring to FIG. 9A, after forming the stepped gate dielectric structure 160, a conventional etching process can be performed to remove the hard mask layer (ie, the pad oxide layer 106 and the tantalum nitride layer 108). In the above steps, the stepped gate dielectric structure 160 can serve as a mask layer for removing the pad oxide layer 106 and the tantalum nitride layer 108 without additionally forming another mask layer. Next, a gate dielectric layer 135 is formed on the substrate 100 outside the field plate region 300 for subsequent semiconductor processing steps. In the present embodiment, the thickness of the stepped gate dielectric structure 160 is greater than the thickness of the gate dielectric layer 135 and less than the thickness of the isolation structure 110.
在另一實施例中，基板100可為一P型基板。在場板區300及隔離結構110之間的主動區200內形成一P型基體區105，取代第9A圖中的N型漂移區104，且在主動區200內的P型基體區105下方形成一N型埋藏層103，取代第9A圖中的N型埋藏層102，如第9B圖所示。In another embodiment, the substrate 100 can be a P-type substrate. A P-type base region 105 is formed in the active region 200 between the field plate region 300 and the isolation structure 110, replacing the N-type drift region 104 in FIG. 9A, and is formed under the P-type base region 105 in the active region 200. An N-type buried layer 103 replaces the N-type buried layer 102 in FIG. 9A as shown in FIG. 9B.
根據本發明另一實施例，在進行化學機械研磨製程之後及去除硬式罩幕層之前，額外形成具有對應場板區的開口的一罩幕層及定義段差閘極介電結構的另一罩幕層，並透過兩次蝕刻製程及其間的高溫氧化沉積製程，在場板區內形成段差閘極介電結構，取代習知的高壓裝置中作為場氧化層的淺溝槽隔離結構。相較於習知的高壓裝置中作為場氧化層的淺溝槽隔離結構，由於段差閘極介電結構160的厚度小於隔離結構110的厚度，且段差閘極介電結構160形成於基板100上方而 未延伸入基板100內，因此，相較於前述實施例，可進一步縮短從汲極至源極的電流路徑，以進一步降低導通電阻，並維持高崩潰電壓，進而降低橫向金屬氧化物半導體場效電晶體裝置的電源損耗。According to another embodiment of the present invention, a mask layer having an opening corresponding to the field plate region and another mask defining a stepped gate dielectric structure are additionally formed after the chemical mechanical polishing process and before the hard mask layer is removed. The layer, through the two etching processes and the high temperature oxidation deposition process therebetween, forms a stepped gate dielectric structure in the field plate region, replacing the shallow trench isolation structure as a field oxide layer in the conventional high voltage device. Compared to the shallow trench isolation structure as the field oxide layer in the conventional high voltage device, since the thickness of the step gate dielectric structure 160 is smaller than the thickness of the isolation structure 110, the step gate dielectric structure 160 is formed over the substrate 100. and It does not extend into the substrate 100. Therefore, compared with the foregoing embodiment, the current path from the drain to the source can be further shortened to further reduce the on-resistance and maintain a high breakdown voltage, thereby reducing the lateral metal oxide semiconductor field effect. Power loss of the transistor device.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧基板100‧‧‧Substrate
102‧‧‧N型埋藏層102‧‧‧N type buried layer
104‧‧‧N型漂移區104‧‧‧N type drift zone
110‧‧‧隔離結構110‧‧‧Isolation structure
130‧‧‧段差閘極介電結構130‧‧ ‧ differential gate dielectric structure
135‧‧‧閘極介電層135‧‧‧ gate dielectric layer
200‧‧‧主動區200‧‧‧active area
300‧‧‧場板區300‧‧‧ field area
400‧‧‧磊晶層400‧‧‧ epitaxial layer
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| TW201234590A (en) * | 2011-02-11 | 2012-08-16 | Richtek Technology Corp | High voltage device and manufacturing method thereof |
| US20120228704A1 (en) * | 2011-03-07 | 2012-09-13 | Dong-Hyuk Ju | High-Voltage MOSFET with High Breakdown Voltage and Low On-Resistance and Method of Manufacturing the Same |
| TW201304143A (en) * | 2011-07-14 | 2013-01-16 | Richtek Technology Corp | High voltage device and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| TW201430917A (en) | 2014-08-01 |
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