TWI497992B - Image sensors - Google Patents
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Description
本發明係關於一種影像感測器，特別關於一種可有效避免電源電壓降(IR-drop)之影像感測器。The present invention relates to an image sensor, and more particularly to an image sensor that can effectively avoid power drop (IR-drop).
影像感應器(Image Sensor)已成為現今電子產品必備的一部份，從手機照相模組、筆記型電腦網路攝影機、數位相機、攝影機到保全監控系統等，都有其相關應用。Image Sensor has become an integral part of today's electronic products, from mobile camera modules, laptop network cameras, digital cameras, cameras to security monitoring systems.
影像感應器透過像素陣列產生影像。像素陣列係由複數列與複數欄的感光元件所組成，各感光元件用以接收光線並產生與光線強度成比例之電壓(電荷)，用以反映出被拍攝之物體的影像。The image sensor produces an image through the pixel array. The pixel array is composed of a plurality of columns and a plurality of photosensitive elements, each of which receives light and generates a voltage (charge) proportional to the intensity of the light to reflect the image of the object being photographed.
然而，由於影像感應器的解析度需求越來越高，因此像素陣列的列數量與欄數量也隨之提升。當像素陣列的欄數量提升時，用以為耦接至像素陣列之後端讀取電路電源之電源線的長度也必須被延長，進而產生不容忽視的電源電壓降(IR-drop)的問題，使得讀取電路中各個相同的欄放大器可能會產生不同的行為，進而折損所產生的影像品質。However, as the resolution requirements of image sensors are increasing, the number of columns and the number of columns in the pixel array also increase. When the number of columns of the pixel array is increased, the length of the power line for reading the circuit power supply to the rear end of the pixel array must also be extended, thereby generating an IR-drop problem that cannot be ignored, so that reading Taking the same column amplifiers in the circuit may result in different behaviors, which in turn detract from the resulting image quality.
因此，需要一種可有效避免電源電壓降之影像感 測器。Therefore, there is a need for an image sense that can effectively avoid the voltage drop of the power supply. Detector.
根據本發明之一實施例，一種影像感測器，包括像素陣列、讀取電路以及壓降控制電路。像素陣列由複數列與複數欄之感光元件所組成。讀取電路耦接至像素陣列，包括複數欄放大器，其中各欄放大器分別耦接至像素陣列之一欄感光元件，用以產生對應之一感測電壓。壓降控制電路耦接於該讀取電路與一電源線之間，用以為讀取電路隔絕電源線所產生之一電源電壓降，使得讀取電路之各欄放大器均透過壓降控制電路接收到大小相等之區域電壓，其中讀取電路之欄放大器均耦接至壓降控制電路。According to an embodiment of the invention, an image sensor includes a pixel array, a read circuit, and a voltage drop control circuit. The pixel array is composed of photosensitive elements of a plurality of columns and a plurality of columns. The read circuit is coupled to the pixel array, and includes a plurality of column amplifiers, wherein the column amplifiers are respectively coupled to the column photosensitive elements of the pixel array for generating a corresponding one of the sensing voltages. The voltage drop control circuit is coupled between the read circuit and a power line for isolating a power supply voltage drop generated by the read circuit to isolate the power line, so that each column amplifier of the read circuit is received through the voltage drop control circuit. An equal-sized area voltage in which the column amplifiers of the read circuit are coupled to the voltage drop control circuit.
根據本發明之另一實施例，一種影像感測器，包括像素陣列、讀取電路以及壓降控制電路。像素陣列由複數列與複數欄之感光元件所組成。讀取電路耦接至像素陣列，包括複數欄放大器，其中各欄放大器分別耦接至像素陣列之一欄感光元件，用以產生對應之一感測電壓。壓降控制電路包括複數電晶體平行耦接於讀取電路與一電源線之間，用以為讀取電路隔絕電源線所產生之一電源電壓降，使得讀取電路之各欄放大器均透過壓降控制電路接收到大小相等之區域電壓，其中讀取電路之欄放大器均耦接至電晶體之其中一者。In accordance with another embodiment of the present invention, an image sensor includes a pixel array, a read circuit, and a voltage drop control circuit. The pixel array is composed of photosensitive elements of a plurality of columns and a plurality of columns. The read circuit is coupled to the pixel array, and includes a plurality of column amplifiers, wherein the column amplifiers are respectively coupled to the column photosensitive elements of the pixel array for generating a corresponding one of the sensing voltages. The voltage drop control circuit includes a plurality of transistors coupled in parallel between the read circuit and a power line for isolating the power supply voltage drop generated by the read circuit to isolate the power supply line, so that each column of the read circuit has a voltage drop The control circuit receives an equal-sized area voltage, wherein the column amplifier of the read circuit is coupled to one of the transistors.
100‧‧‧影像感測器100‧‧‧Image sensor
110‧‧‧像素陣列110‧‧‧pixel array
120‧‧‧讀取電路120‧‧‧Read circuit
130‧‧‧電源供應電路130‧‧‧Power supply circuit
230、330、430、530‧‧‧壓降控制電路230, 330, 430, 530‧‧‧ voltage drop control circuit
250、350、450、550‧‧‧電源線250, 350, 450, 550‧‧‧ power cords
120-(1)、120-(2)、120-(3)、120-(n-1)、120-(n)、220-(i)、 220-(i+1)、320-(i)、320-(i+1)、420-(i)、420-(i+1)、520-(i)、520-(i+1)‧‧‧欄放大器120-(1), 120-(2), 120-(3), 120-(n-1), 120-(n), 220-(i), 220-(i+1), 320-(i), 320-(i+1), 420-(i), 420-(i+1), 520-(i), 520-(i+1)‧ ‧‧ column amplifier
inp(i)、inn(i)、inp(i+1)、inn(i+1)‧‧‧輸入端Inp(i), inn(i), inp(i+1), inn(i+1)‧‧‧ inputs
Itail(i)、Itail(i+1)‧‧‧電流源Itail(i), Itail(i+1)‧‧‧ current source
out(i)、out(i+1)‧‧‧輸出端Out(i), out(i+1)‧‧‧ output
Np(i)、Np(i+1)‧‧‧端點Np(i), Np(i+1)‧‧‧ endpoints
T(i)、T’(i)、T1(i)、T2(i)、T(i+1)、T1(i+1)、T2(i+1)、T11(i)、T12(i)、T13(i)‧‧‧電晶體T(i), T'(i), T1(i), T2(i), T(i+1), T1(i+1), T2(i+1), T11(i), T12(i ), T13(i)‧‧‧O crystal
VG 、VG1 、VG2 、VG3 ‧‧‧電壓V G , V G1 , V G2 , V G3 ‧‧‧ voltage
第1圖係顯示根據本發明之一實施例所述之影像感測器方塊圖。1 is a block diagram showing an image sensor according to an embodiment of the present invention.
第2圖係顯示根據本發明之一實施例所述之影像感測器之部分電路圖。2 is a partial circuit diagram showing an image sensor according to an embodiment of the present invention.
第3圖係顯示根據本發明之另一實施例所述之影像感測器之部分電路圖。Figure 3 is a partial circuit diagram showing an image sensor according to another embodiment of the present invention.
第4圖係顯示根據本發明之又另一實施例所述之影像感測器之部分電路圖。Figure 4 is a partial circuit diagram showing an image sensor according to still another embodiment of the present invention.
第5圖係顯示根據本發明之又另一實施例所述之影像感測器之部分電路圖。Figure 5 is a partial circuit diagram showing an image sensor according to still another embodiment of the present invention.
為使本發明之製造、操作方法、目標和優點能更明顯易懂，下文特舉幾個較佳實施例，並配合所附圖式，作詳細說明如下：In order to make the manufacturing, operating methods, objects and advantages of the present invention more apparent, the following detailed description of the preferred embodiments and the accompanying drawings
第1圖係顯示根據本發明之一實施例所述之影像感測器方塊圖。值得注意的是，為簡化說明，第1圖中僅顯示與本發明相關之區塊與元件。如同熟習此項技藝者所理解，影像感測器當可包括其它未顯示於第1圖中之區塊與元 件，因此本發明並不限於第1圖所示之內容。1 is a block diagram showing an image sensor according to an embodiment of the present invention. It is to be noted that, in order to simplify the description, only the blocks and elements related to the present invention are shown in FIG. As understood by those skilled in the art, image sensors may include other blocks and elements not shown in FIG. Therefore, the present invention is not limited to the contents shown in Fig. 1.
根據本發明之一實施例，影像感測器100可至少包括像素陣列110、讀取電路120以及電源供應電路130。像素陣列110可由複數欄(column)與複數列(row)之感光元件所組成，用以接收光線並產生與光線強度成比例之電壓(電荷)，用以反映出被拍攝之物體的影像。讀取電路120耦接至像素陣列110，並且包括複數欄放大器(column amplifier)120-(1)、120-(2)、120-(3)…120-(n-1)以及120-(n)，其中各欄放大器具有相同的電路結構，並且分別耦接至像素陣列110之一欄感光元件，用以產生對應之一感測電壓。電源供應電路130耦接至讀取電路120，用以供應電源給讀取電路120，並可避免電源線所產生之電源電壓降(IR-drop)。According to an embodiment of the present invention, the image sensor 100 may include at least a pixel array 110, a read circuit 120, and a power supply circuit 130. The pixel array 110 may be composed of a plurality of columns and a plurality of photosensitive elements for receiving light and generating a voltage (charge) proportional to the intensity of the light to reflect an image of the object being photographed. The read circuit 120 is coupled to the pixel array 110 and includes a plurality of column amplifiers 120-(1), 120-(2), 120-(3)...120-(n-1), and 120-(n The column amplifiers have the same circuit structure and are respectively coupled to the column photosensitive elements of the pixel array 110 for generating a corresponding one of the sensing voltages. The power supply circuit 130 is coupled to the read circuit 120 for supplying power to the read circuit 120 and avoiding a power supply voltage drop (IR-drop) generated by the power line.
讀取電路120之各欄放大器120-(1)、120-(2)、120-(3)…120-(n-1)以及120-(n)均需自電源線接收電源。由於各欄放大器120-(1)、120-(2)、120-(3)…120-(n-1)以及120-(n)具有相同的電路結構且自同一條電源線接收電源，因此理想上，各欄放大器之各節點的電壓必須是相同的，使得各欄放大器可有一致的操作行為。然而，當讀取電路之欄放大器的數量很多(換言之，像素陣列的尺寸很大)時，電源線的長度也必須被延長，進而產生不容忽視的電源電壓降(IR-drop)的問題。舉例而言，距離最遠的兩個欄放大器所接收到的電源電壓大小可能會不一樣。如此一來，讀取電路中各個相同的欄 放大器可能會產生不同的行為，進而折損所產生的影像品質。Each of the column amplifiers 120-(1), 120-(2), 120-(3)...120-(n-1) and 120-(n) of the read circuit 120 is required to receive power from the power line. Since the column amplifiers 120-(1), 120-(2), 120-(3)...120-(n-1) and 120-(n) have the same circuit structure and receive power from the same power line, Ideally, the voltages at each node of each column amplifier must be the same, so that each column amplifier can have consistent operational behavior. However, when the number of amplifiers in the read circuit is large (in other words, the size of the pixel array is large), the length of the power supply line must also be lengthened, thereby causing a problem of an IR-drop that cannot be ignored. For example, the power supply voltages received by the two far-field amplifiers may be different. In this way, read the same column in the circuit Amplifiers can produce different behaviors that can compromise the resulting image quality.
第2圖係顯示根據本發明之一實施例所述之影像感測器之部分電路圖。為了解決電源電壓降(IR-drop)的問題，本發明所提出之影像感測器100的電源供應電路130除了包括電源線以外，進一步包括了壓降控制電路。根據本發明之一實施例，讀取電路120之各欄放大器均耦接至壓降控制電路，用以透過壓降控制電路自電源線接收電源，其中壓降控制電路可隔絕電源線所產生之電源電壓降(IR-drop)。以下段落將透過多個不同實施例對本發明所提出之壓降控制電路作更詳細的介紹。2 is a partial circuit diagram showing an image sensor according to an embodiment of the present invention. In order to solve the problem of power supply voltage drop (IR-drop), the power supply circuit 130 of the image sensor 100 of the present invention further includes a voltage drop control circuit in addition to the power line. According to an embodiment of the present invention, each column amplifier of the reading circuit 120 is coupled to the voltage drop control circuit for receiving power from the power line through the voltage drop control circuit, wherein the voltage drop control circuit can isolate the power line Power supply voltage drop (IR-drop). The following paragraphs will describe the voltage drop control circuit of the present invention in more detail through a number of different embodiments.
根據本發明之一實施例，電源供應電路130可包括壓降控制電路230及電源線250。壓降控制電路230包括n個平行耦接的電晶體，其中電晶體之數量n相等於讀取電路之欄放大器之數量n，n為一正整數。如此一來，讀取電路之欄放大器可各自耦接至一個對應之電晶體，此電晶體用以產生無電源電壓降(IR-drop free)之一區域電壓，並將區域電壓提供給對應之欄放大器。換言之，讀取電路之各欄放大器均可透過壓降控制電路230接收到大小相等之區域電壓。於本發明之較佳實施例中，壓降控制電路230之該等電晶體可以是N型金屬氧化物半導體電晶體。According to an embodiment of the present invention, the power supply circuit 130 may include a voltage drop control circuit 230 and a power line 250. The voltage drop control circuit 230 includes n parallel coupled transistors, wherein the number n of transistors is equal to the number n of columns of the read circuit, n is a positive integer. In this way, the read circuit column amplifiers can each be coupled to a corresponding transistor for generating an area voltage of one of the power supply voltage drop (IR-drop free) and providing the area voltage to the corresponding one. Column amplifier. In other words, each column amplifier of the read circuit can receive an equal-sized area voltage through the voltage drop control circuit 230. In a preferred embodiment of the invention, the transistors of the voltage drop control circuit 230 can be N-type metal oxide semiconductor transistors.
如第2圖所示，電源線250耦接至壓降控制電路230，用以供應系統操作電壓VDD。電晶體T(i)包括一第一極 耦接至電源線250，以及一第二極耦接至欄放大器220-(i)，其中i為一正整數。同樣地，電晶體T(i+1)包括一第一極耦接至電源線250，以及一第二極耦接至欄放大器220-(i+1)。此外，電晶體T(i)與電晶體T(i+1)之一控制極均耦接至參考電壓VG 。欄放大器220-(i)與220-(i+1)具有實質上相同的電路結構，其中欄放大器220-(i)與220-(i+1)可分別包括一運算放大器。運算放大器在此係以差動放大器為例，分別具有一對差動輸入端inp(i)與inn(i)、以及inp(i+1)與inn(i+1)。各對差動輸入端可耦接至像素陣列之其中一欄，用以感測感光元件所產生的電壓大小。運算放大器更分別透過輸出端out(i)與out(i+1)輸出感測電壓至下一級電路(例如，一類比至數位轉換器)。As shown in FIG. 2, the power line 250 is coupled to the voltage drop control circuit 230 for supplying the system operating voltage VDD. The transistor T(i) includes a first pole coupled to the power line 250 and a second pole coupled to the column amplifier 220-(i), where i is a positive integer. Similarly, the transistor T(i+1) includes a first pole coupled to the power line 250 and a second pole coupled to the column amplifier 220-(i+1). In addition, one of the control electrodes of the transistor T(i) and the transistor T(i+1) is coupled to the reference voltage V G . The column amplifier 220-(i) has substantially the same circuit structure as 220-(i+1), wherein the column amplifiers 220-(i) and 220-(i+1) may respectively include an operational amplifier. The operational amplifier here is exemplified by a differential amplifier having a pair of differential input terminals inp(i) and inn(i), and inp(i+1) and inn(i+1), respectively. Each pair of differential input terminals can be coupled to one of the columns of the pixel array for sensing the magnitude of the voltage generated by the photosensitive element. The operational amplifier outputs the sensed voltage to the next stage circuit (for example, an analog to digital converter) through the output terminals out(i) and out(i+1), respectively.
根據本發明之一實施例，壓降控制電路230之各電晶體可根據參考電壓VG 與各欄放大器內的定電流源(例如，Itail(i)與Itail(i+1))於電源電壓供應端點(例如，Np(i)與Np(i+1))產生無電源電壓降(IR-drop free)之一區域電壓。由於參考電壓VG 係直接提供至各電晶體之控制極，因此參考電壓VG 的導線上的電流幾乎為零，因此沒有電流電壓降；而且電源電壓供應端點(例如，Np(i)與Np(i+1))的電壓係為參考電壓減去一閥電壓，因此也沒有電流電壓降的問題，同時，各欄放大器內的電流實質上相同，因此，於電源電壓供應端點(例如，Np(i)與Np(i+1))所產生之區域電壓也會是一定電壓，不會受到電源線250所供應之系統操作電壓VDD之電源電壓降影 響。如此一來，讀取電路之各欄放大器內部之各節點電壓均會一致，操作行為也會一致，有效解決了因系統操作電壓VDD之電源電壓降造成影像品質折損的問題。According to an embodiment of the present invention, each transistor of the voltage drop control circuit 230 can be connected to a constant current source (for example, Itail(i) and Itail(i+1)) in each column amplifier according to the reference voltage V G . The supply endpoints (eg, Np(i) and Np(i+1)) generate one of the region voltages without IR-drop free. Since the reference voltage V G is directly supplied to the gates of the respective transistors, the current on the wires of the reference voltage V G is almost zero, so there is no current voltage drop; and the power supply voltage supply terminal (for example, Np(i) and The voltage of Np(i+1)) is the reference voltage minus one valve voltage, so there is no problem of current voltage drop. At the same time, the currents in each column amplifier are substantially the same, therefore, at the supply voltage supply end point (for example The region voltage generated by Np(i) and Np(i+1)) is also a certain voltage and is not affected by the power supply voltage drop of the system operating voltage VDD supplied from the power line 250. In this way, the voltages of the nodes in each column of the reading circuit are the same, and the operation behavior is also consistent, which effectively solves the problem that the image quality is degraded due to the power supply voltage drop of the system operating voltage VDD.
值得注意的是，於本發明之實施例中，壓降控制電路230之各電晶體之一基極可進一步耦接至源極(如上所述之第一或第二極)或接地點，其中當基極耦接至源極時，可消除電晶體之基體效應(body effect)。此外，於此實施例中，由於讀取電路之各欄放大器僅需額外耦接一個電晶體，電路設計上相當簡單。It should be noted that, in an embodiment of the present invention, one of the bases of each of the transistors of the voltage drop control circuit 230 may be further coupled to a source (the first or second pole as described above) or a ground point, wherein When the base is coupled to the source, the body effect of the transistor can be eliminated. In addition, in this embodiment, since each column amplifier of the read circuit only needs to additionally couple one transistor, the circuit design is quite simple.
值得注意的是，為簡化說明，第2圖中僅顯示出壓降控制電路230之其中兩個電晶體以及兩個對應的欄放大器之電路圖，而熟習此項技藝者當可根據第2圖所揭示之內容輕易推導出壓降控制電路230之其它電晶體之耦接與操作方式。此外，值得注意的是，本發明之欄放大器並不限於第2圖所示之電路結構。如同熟習此項技藝者所理解，讀取電路之各個欄放大器可有多種不同的實施方式，因此第2圖所示之電路僅為輔助說明之範例，並非用以限制本發明之範圍。It should be noted that, in order to simplify the description, only the circuit diagrams of two of the transistors of the voltage drop control circuit 230 and the two corresponding column amplifiers are shown in FIG. 2, and those skilled in the art can use the figure according to FIG. The disclosure reveals easily the coupling and operation of other transistors of the voltage drop control circuit 230. Further, it is to be noted that the column amplifier of the present invention is not limited to the circuit configuration shown in FIG. As will be understood by those skilled in the art, the various column amplifiers of the read circuit can be implemented in a variety of different manners, and thus the circuit shown in FIG. 2 is merely an illustrative example and is not intended to limit the scope of the present invention.
第3圖係顯示根據本發明之另一實施例所述之影像感測器之部分電路圖。於此實施例中，電源供應電路包括了電源線350與壓降控制電路330。壓降控制電路330可包括m個平行耦接的電晶體，其中電晶體之數量m少於讀取電路之欄放大器之數量n。因此，多個欄放大器可共用一個電晶 體，該電晶體用以產生無電源電壓降(IR-drop free)之一區域電壓，並將區域電壓提供給對應之欄放大器。換言之，讀取電路之各欄放大器均可透過壓降控制電路330接收到大小相等之區域電壓。於本發明之較佳實施例中，壓降控制電路330之該等電晶體可以是N型金屬氧化物半導體電晶體。Figure 3 is a partial circuit diagram showing an image sensor according to another embodiment of the present invention. In this embodiment, the power supply circuit includes a power line 350 and a voltage drop control circuit 330. The voltage drop control circuit 330 can include m parallel coupled transistors, wherein the number m of transistors is less than the number n of column amplifiers of the read circuit. Therefore, multiple column amplifiers can share a single crystal The transistor is used to generate a region voltage of no supply-voltage drop (IR-drop free) and supply the region voltage to the corresponding column amplifier. In other words, each of the column amplifiers of the read circuit can receive voltages of equal magnitude through the voltage drop control circuit 330. In a preferred embodiment of the invention, the transistors of the voltage drop control circuit 330 can be N-type metal oxide semiconductor transistors.
第3圖所示之電路與第2圖相似，其差別僅在於電晶體T’(i)之第二極同時耦接至欄放大器320-(i)與320-(i+1)，用以分別於電源電壓供應端點Np(i)與Np(i+1)產生無電源電壓降(IR-drop free)之一區域電壓。由於第3圖所示之電路與第2圖相似，因此電路其它區塊之描述可參考至第2圖，並於此不再贅述。The circuit shown in FIG. 3 is similar to FIG. 2 except that the second pole of the transistor T'(i) is simultaneously coupled to the column amplifiers 320-(i) and 320-(i+1) for One region voltage of the power supply voltage drop (IR-drop free) is generated at the power supply voltage supply terminals Np(i) and Np(i+1), respectively. Since the circuit shown in FIG. 3 is similar to FIG. 2, the description of other blocks of the circuit can be referred to FIG. 2 and will not be described again.
根據本發明之實施例，由於壓降控制電路330之各電晶體可被共用於多個欄放大器之間，因此，相較於第2圖所示之實施例，第3圖所示之實施例可進一步縮減電路面積。此外，於此實施例中，由於參考電壓VG 係直接提供至各電晶體之控制極，，因此參考電壓VG 的導線上的電流幾乎為零，因此沒有電流電壓降；而且電源電壓供應端點(例如，Np(i)與Np(i+1))的電壓係為參考電壓減去一閥電壓，因此也沒有電流電壓降的問題，同時，各欄放大器內的電流實質上相同，因此，於電源電壓供應端點(例如，Np(i)與Np(i+1))所產生之區域電壓也會是一定電壓，不會受到電源線350所供應之系統操作電壓VDD之電源電壓降影響。如此一來，讀取電路之 各欄放大器內部之各節點電壓均會一致，操作行為也會一致，有效解決了因系統操作電壓VDD之電源電壓降造成影像品質折損的問題。According to an embodiment of the present invention, since the transistors of the voltage drop control circuit 330 can be commonly used between a plurality of column amplifiers, the embodiment shown in FIG. 3 is compared to the embodiment shown in FIG. The circuit area can be further reduced. In addition, in this embodiment, since the reference voltage V G is directly supplied to the gates of the respective transistors, the current on the wires of the reference voltage V G is almost zero, so there is no current voltage drop; and the power voltage supply terminal The voltages of the points (for example, Np(i) and Np(i+1)) are the reference voltage minus one valve voltage, so there is no problem of current voltage drop, and the currents in the respective column amplifiers are substantially the same, so The voltage generated in the region of the power supply voltage supply terminal (for example, Np(i) and Np(i+1)) is also a certain voltage, and is not subjected to the power supply voltage drop of the system operating voltage VDD supplied from the power line 350. influences. In this way, the voltages of the nodes in each column of the reading circuit are the same, and the operation behavior is also consistent, which effectively solves the problem that the image quality is degraded due to the power supply voltage drop of the system operating voltage VDD.
得注意的是，為簡化說明，第3圖中僅顯示出壓降控制電路330之其中一個電晶體以及兩個對應的欄放大器之電路圖，而熟習此項技藝者當可根據第3圖所揭示之內容輕易推導出壓降控制電路330之其它電晶體之耦接與操作方式。此外，值得注意的是，於本發明之其它實施例中，亦可由兩個以上欄放大器共用壓降控制電路之同一個電晶體。因此，熟習此項技藝者當可根據第3圖所揭示之內容輕易推導出其它可能的變化，而第3圖所示之電路僅為輔助說明之範例，並非用以限制本發明之範圍。It should be noted that, in order to simplify the description, only one of the transistors of the voltage drop control circuit 330 and two corresponding column amplifiers are shown in FIG. 3, and those skilled in the art can disclose according to FIG. The content easily dictates the coupling and operation of other transistors of the voltage drop control circuit 330. In addition, it should be noted that in other embodiments of the present invention, the same transistor of the voltage drop control circuit may be shared by more than two column amplifiers. Therefore, those skilled in the art can easily derive other possible variations from the disclosure of FIG. 3, and the circuit shown in FIG. 3 is merely an illustrative example and is not intended to limit the scope of the present invention.
此外，值得注意的是，本發明之欄放大器並不限於第3圖所示之電路結構。如同熟習此項技藝者所理解，讀取電路之各個欄放大器可有多種不同的實施方式，因此第3圖所示之電路僅為輔助說明之範例，並非用以限制本發明之範圍。Further, it is to be noted that the column amplifier of the present invention is not limited to the circuit configuration shown in FIG. As will be understood by those skilled in the art, the various column amplifiers of the read circuit can be implemented in a variety of different manners, and the circuit shown in FIG. 3 is merely an example of an aid to the description and is not intended to limit the scope of the present invention.
第4圖係顯示根據本發明之又另一實施例所述之影像感測器之部分電路圖。於此實施例中，電源供應電路包括了電源線450與壓降控制電路430。壓降控制電路430可包括n組平行耦接的電晶體，其中電晶體之群組數量n相等於讀取電路之欄放大器之數量n。如此一來，讀取電路之各欄 放大器可耦接至一組對應之電晶體，該組電晶體用以產生無電源電壓降(IR-drop free)之一區域電壓，並將區域電壓提供給對應之欄放大器。換言之，讀取電路之各欄放大器均可透過壓降控制電路430接收到大小相等之區域電壓。於本發明之較佳實施例中，壓降控制電路430之該等電晶體可以是N型金屬氧化物半導體電晶體。Figure 4 is a partial circuit diagram showing an image sensor according to still another embodiment of the present invention. In this embodiment, the power supply circuit includes a power line 450 and a voltage drop control circuit 430. The voltage drop control circuit 430 can include n sets of parallel coupled transistors, wherein the number n of transistors is equal to the number n of column amplifiers of the read circuit. In this way, read the columns of the circuit The amplifier can be coupled to a corresponding set of transistors for generating a region voltage having no supply-voltage drop (IR-drop free) and supplying the region voltage to the corresponding column amplifier. In other words, each column amplifier of the read circuit can receive an equal-sized area voltage through the voltage drop control circuit 430. In a preferred embodiment of the invention, the transistors of the voltage drop control circuit 430 can be N-type metal oxide semiconductor transistors.
第4圖所示之電路與第2圖相似，其差別僅在於各欄放大器可耦接至兩個疊接之電晶體。舉例而言，電晶體T1(i)之第一極可耦接至電源線450，電晶體T1(i)之第二極可耦接至電晶體T2(i)之第一極，而電晶體T2(i)之第二極可耦接至欄放大器420-(i)。同樣地，電晶體T1(i+1)之第一極可耦接至電源線450，電晶體T1(i+1)之第二極可耦接至電晶體T2(i+1)之第一極，而電晶體T2(i+1)之第二極可耦接至欄放大器420-(i+1)。此外，電晶體T1(i)與電晶體T1(i+1)之一控制極均耦接至參考電壓VG1 ，而電晶體T2(i)與電晶體T2(i+1)之一控制極均耦接至參考電壓VG2 。由於第4圖所示之電路與第2圖相似，因此電路其它區塊之描述可參考至第2圖，並於此不再贅述。The circuit shown in Figure 4 is similar to Figure 2 except that the column amplifiers can be coupled to two stacked transistors. For example, the first pole of the transistor T1(i) can be coupled to the power line 450, and the second pole of the transistor T1(i) can be coupled to the first pole of the transistor T2(i), and the transistor The second pole of T2(i) can be coupled to the column amplifier 420-(i). Similarly, the first pole of the transistor T1(i+1) can be coupled to the power line 450, and the second pole of the transistor T1(i+1) can be coupled to the first of the transistor T2(i+1). The second pole of the transistor T2(i+1) can be coupled to the column amplifier 420-(i+1). In addition, one of the control transistors of the transistor T1(i) and the transistor T1(i+1) is coupled to the reference voltage V G1 , and one of the transistors T2(i) and the transistor T2(i+1) Both are coupled to the reference voltage V G2 . Since the circuit shown in FIG. 4 is similar to FIG. 2, the description of other blocks of the circuit can be referred to FIG. 2 and will not be described again.
根據本發明之實施例，由於參考電壓VG1 與VG2 係直接提供至各電晶體之控制極，且流經各欄放大器內的電流為定值，因此，於電源電壓供應端點(例如，Np(i)與Np(i+1))所產生之區域電壓也會是一定電壓，不會受到電源線450所 供應之系統操作電壓VDD之電源電壓降影響。如此一來，讀取電路之各欄放大器內部之各節點電壓均會一致，操作行為也會一致，有效解決了因系統操作電壓VDD之電源電壓降造成影像品質折損的問題。According to an embodiment of the present invention, since the reference voltages V G1 and V G2 are directly supplied to the gates of the respective transistors, and the current flowing through the respective column amplifiers is constant, the power supply voltage supply terminal (for example, The area voltage generated by Np(i) and Np(i+1)) is also a certain voltage and is not affected by the power supply voltage drop of the system operating voltage VDD supplied from the power line 450. In this way, the voltages of the nodes in each column of the reading circuit are the same, and the operation behavior is also consistent, which effectively solves the problem that the image quality is degraded due to the power supply voltage drop of the system operating voltage VDD.
根據本發明之實施例，透過如第4圖所示之疊接的電晶體，壓降控制電路430可承受的電源線電源電壓降會比僅耦接單一電晶體來得大，因此隔絕電源電壓降的能力會比較好。According to the embodiment of the present invention, through the stacked transistors as shown in FIG. 4, the voltage drop of the power supply line that the voltage drop control circuit 430 can withstand is greater than that of coupling only a single transistor, thereby isolating the power supply voltage. The ability to drop will be better.
值得注意的是，為簡化說明，第4圖中僅顯示出壓降控制電路430之其中兩組電晶體以及兩個對應的欄放大器之電路圖，而熟習此項技藝者當可根據第4圖所揭示之內容輕易推導出壓降控制電路430之其它電晶體之耦接與操作方式。此外，值得注意的是，於本發明之其它實施例中，亦可由如第3圖所示之方式，由兩個或兩個以上欄放大器共用壓降控制電路之同一組電晶體。因此，熟習此項技藝者當可根據第4圖所揭示之內容輕易推導出其它可能的變化，而第4圖所示之電路僅為輔助說明之範例，並非用以限制本發明之範圍。It should be noted that, in order to simplify the description, only the circuit diagrams of two sets of transistors and two corresponding column amplifiers of the voltage drop control circuit 430 are shown in FIG. 4, and those skilled in the art can according to FIG. The disclosure reveals easily the coupling and operation of other transistors of the voltage drop control circuit 430. Moreover, it should be noted that in other embodiments of the present invention, the same set of transistors of the voltage drop control circuit may be shared by two or more column amplifiers as shown in FIG. Therefore, those skilled in the art can easily derive other possible variations from the disclosure of FIG. 4, and the circuit shown in FIG. 4 is merely an illustrative example and is not intended to limit the scope of the present invention.
此外，值得注意的是，於本發明之其它實施例中，壓降控制電路之各組電晶體可更包括兩個以上的電晶體。因此，熟習此項技藝者當可根據第4圖所揭示之內容輕易推導出其它可能的變化，而第4圖所示之電路僅為輔助說 明之範例，並非用以限制本發明之範圍。Moreover, it is noted that in other embodiments of the invention, each set of transistors of the voltage drop control circuit may further comprise more than two transistors. Therefore, those skilled in the art can easily derive other possible changes according to the contents disclosed in FIG. 4, and the circuit shown in FIG. 4 is only auxiliary. The examples are not intended to limit the scope of the invention.
此外，值得注意的是，本發明之欄放大器並不限於第4圖所示之電路結構。如同熟習此項技藝者所理解，讀取電路之各個欄放大器可有多種不同的實施方式，因此第4圖所示之電路僅為輔助說明之範例，並非用以限制本發明之範圍。Further, it is to be noted that the column amplifier of the present invention is not limited to the circuit configuration shown in FIG. As will be understood by those skilled in the art, the various column amplifiers of the read circuit can be implemented in a variety of different manners, and thus the circuit shown in FIG. 4 is merely an illustrative example and is not intended to limit the scope of the present invention.
第5圖係顯示根據本發明之又另一實施例所述之影像感測器之部分電路圖。於此實施例中，電源供應電路包括了電源線550與壓降控制電路530。壓降控制電路530可包括m組平行耦接的電晶體，其中m為一正整數，電晶體之群組數量m少於讀取電路之欄放大器之數量n。因此，多個欄放大器可共用一組電晶體，該組電晶體用以產生無電源電壓降(IR-drop free)之一區域電壓，並將區域電壓提供給對應之欄放大器。換言之，讀取電路之各欄放大器均可透過壓降控制電路530接收到大小相等之區域電壓。於本發明之較佳實施例中，壓降控制電路530之該等電晶體可以是N型金屬氧化物半導體電晶體。Figure 5 is a partial circuit diagram showing an image sensor according to still another embodiment of the present invention. In this embodiment, the power supply circuit includes a power line 550 and a voltage drop control circuit 530. The voltage drop control circuit 530 can include m sets of transistors coupled in parallel, where m is a positive integer, and the number m of groups of transistors is less than the number n of column amplifiers of the read circuit. Thus, a plurality of column amplifiers can share a set of transistors that are used to generate one of the region voltages of the IR-drop free and provide the region voltages to the corresponding column amplifiers. In other words, each column amplifier of the read circuit can receive an equal-sized area voltage through the voltage drop control circuit 530. In a preferred embodiment of the invention, the transistors of the voltage drop control circuit 530 can be N-type metal oxide semiconductor transistors.
第5圖所示之電路與第3圖相似，其差別僅在於各欄放大器可耦接至三個疊接之電晶體。舉例而言，電晶體T11(i)之第一極可耦接至電源線550，電晶體T11(i)之第二極可耦接至電晶體T12(i)之第一極，電晶體T12(i)之第二極可耦接至電晶體T13(i)之第一極，而電晶體T13(i)之第二極可同時 耦接至欄放大器520-(i)與520-(i+1)。此外，電晶體T11(i)、T12(i)與T13(i)之一控制極可分別耦接至不同的參考電壓VG1 、VG2 與VG3 。由於第5圖所示之電路與第3圖相似，因此電路其它區塊之描述可參考至第2圖與第3圖，並於此不再贅述。The circuit shown in Figure 5 is similar to Figure 3 except that the column amplifiers can be coupled to three stacked transistors. For example, the first pole of the transistor T11(i) can be coupled to the power line 550, and the second pole of the transistor T11(i) can be coupled to the first pole of the transistor T12(i), the transistor T12 The second pole of (i) can be coupled to the first pole of the transistor T13(i), and the second pole of the transistor T13(i) can be coupled to the column amplifiers 520-(i) and 520-(i +1). In addition, one of the transistors T11(i), T12(i) and T13(i) may be coupled to different reference voltages V G1 , V G2 and V G3 , respectively . Since the circuit shown in FIG. 5 is similar to FIG. 3, the description of other blocks of the circuit can be referred to FIGS. 2 and 3, and will not be described again.
根據本發明之實施例，各組電晶體之第一電晶體(例如，耦接至電源線之電晶體)之控制極均耦接至參考電壓VG1 、第二電晶體之控制極均耦接至參考電壓VG2 ，且第三電晶體(例如，耦接至欄放大器之電晶體)之控制極均耦接至參考電壓VG3 。由於參考電壓VG1 、VG2 與VG3 係直接提供至各電晶體之控制極，且流經各欄放大器內的電流為定值，因此，於電源電壓供應端點(例如，Np(i)與Np(i+1))所產生之區域電壓也會是一定電壓，不會受到電源線550所供應之系統操作電壓VDD之電源電壓降影響。如此一來，讀取電路之各欄放大器內部之各節點電壓均會一致，操作行為也會一致，有效解決了因系統操作電壓VDD之電源電壓降造成影像品質折損的問題。According to the embodiment of the present invention, the control electrodes of the first transistor (for example, the transistor coupled to the power line) of each group of transistors are coupled to the reference voltage V G1 , and the control electrodes of the second transistor are coupled To the reference voltage V G2 , the control electrode of the third transistor (eg, the transistor coupled to the column amplifier) is coupled to the reference voltage V G3 . Since the reference voltage V G1, V G2 and V G3 line directly to the control electrode of each transistor and the current flowing through the amplifier in each column is constant, therefore, the power supply voltage supply terminal (e.g., Np (i) The voltage generated by the region and Np(i+1)) is also a certain voltage and is not affected by the power supply voltage drop of the system operating voltage VDD supplied from the power line 550. In this way, the voltages of the nodes in each column of the reading circuit are the same, and the operation behavior is also consistent, which effectively solves the problem that the image quality is degraded due to the power supply voltage drop of the system operating voltage VDD.
根據本發明之實施例，透過如第5圖所示之疊接的電晶體，壓降控制電路530可承受的電源線電源電壓降會比僅耦接單一電晶體來得大，因此隔絕電源電壓降的能力會比較好。According to the embodiment of the present invention, the voltage drop of the power supply line that the voltage drop control circuit 530 can withstand is greater than that of coupling only a single transistor through the stacked transistors as shown in FIG. 5, thereby isolating the power supply voltage. The ability to drop will be better.
值得注意的是，為簡化說明，第5圖中僅顯示出 壓降控制電路530之其中一組電晶體以及兩個對應的欄放大器之電路圖，而熟習此項技藝者當可根據第5圖所揭示之內容輕易推導出壓降控制電路530之其它電晶體之耦接與操作方式。It is worth noting that in order to simplify the description, only Figure 5 shows A circuit diagram of one of the transistors of the voltage drop control circuit 530 and two corresponding column amplifiers, and those skilled in the art can easily derive other transistors of the voltage drop control circuit 530 according to the disclosure of FIG. Coupling and operation.
此外，值得注意的是，於本發明之其它實施例中，壓降控制電路之各組電晶體可更包括三個以下或以上的電晶體。因此，熟習此項技藝者當可根據第5圖所揭示之內容輕易推導出其它可能的變化，而第5圖所示之電路僅為輔助說明之範例，並非用以限制本發明之範圍。In addition, it should be noted that in other embodiments of the present invention, each set of transistors of the voltage drop control circuit may further include three or less transistors. Therefore, those skilled in the art can easily derive other possible variations from the disclosure of FIG. 5, and the circuit shown in FIG. 5 is merely an illustrative example and is not intended to limit the scope of the present invention.
此外，值得注意的是，本發明之欄放大器並不限於第5圖所示之電路結構。如同熟習此項技藝者所理解，讀取電路之各個欄放大器可有多種不同的實施方式，因此第5圖所示之電路僅為輔助說明之範例，並非用以限制本發明之範圍。Further, it is to be noted that the column amplifier of the present invention is not limited to the circuit configuration shown in FIG. As will be understood by those skilled in the art, the various column amplifiers of the read circuit can be implemented in a variety of different manners, and the circuit shown in FIG. 5 is merely an example of an aid to the description and is not intended to limit the scope of the present invention.
由以上實施例可看出，由於讀取電路之各欄放大器均改為透過壓降控制電路自電源線接收電源，因此各欄放大器所接收到的電壓不會受到電源線所供應之系統操作電壓VDD之電源電壓降影響。如此一來，各欄放大器內部之各節點電壓均會一致，操作行為也會一致，有效解決了因系統操作電壓VDD之電源電壓降造成影像品質折損的問題。As can be seen from the above embodiment, since each column amplifier of the read circuit is changed to receive power from the power line through the voltage drop control circuit, the voltage received by each column amplifier is not affected by the system operating voltage supplied by the power line. VDD power supply voltage drop effect. In this way, the voltages of the nodes in each column amplifier are consistent, and the operation behavior is also consistent, which effectively solves the problem that the image quality is degraded due to the power supply voltage drop of the system operating voltage VDD.
此外，本發明所提出之壓降控制電路可更為讀取電路隔絕掉電源雜訊，因此訊號-雜訊比可有效提升。此外， 如上述，由於壓降控制電路的電路十分簡單，使用的元件數量也不多，因此不會耗費額外的功率耗損，也不會佔用過多的電路面積，同時兼具功率及電路面積的效率。In addition, the voltage drop control circuit proposed by the present invention can further isolate the circuit from power noise, so the signal-to-noise ratio can be effectively improved. In addition, As described above, since the circuit of the voltage drop control circuit is very simple, the number of components used is not large, so that no additional power consumption is consumed, and excessive circuit area is not occupied, and power and circuit area efficiency are simultaneously achieved.
申請專利範圍中用以修飾元件之“第一”、“第二”、“第三”等序數詞之使用本身未暗示任何優先權、優先次序、各元件之間之先後次序、或方法所執行之步驟之次序，而僅用作標識來區分具有相同名稱(具有不同序數詞)之不同元件。The use of ordinal numbers such as "first," "second," or "third," as used in the <Desc/Clms Page number>> The order of the steps, and only used as an identifier to distinguish different elements having the same name (with different ordinal numbers).
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧影像感測器100‧‧‧Image sensor
110‧‧‧像素陣列110‧‧‧pixel array
120‧‧‧讀取電路120‧‧‧Read circuit
120-(1)、120-(2)、120-(3)、120-(n-1)、120-(n)‧‧‧欄放大器120-(1), 120-(2), 120-(3), 120-(n-1), 120-(n)‧‧‧
130‧‧‧壓降控制電路130‧‧‧voltage drop control circuit
Claims (16)
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| TW102108955A TWI497992B (en) | 2013-03-14 | 2013-03-14 | Image sensors |
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| TW102108955A TWI497992B (en) | 2013-03-14 | 2013-03-14 | Image sensors |
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| TWI497992B true TWI497992B (en) | 2015-08-21 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20060054783A1 (en) * | 2004-09-09 | 2006-03-16 | Transchip, Inc. | Imager flicker compensation systems and methods |
| US20120187936A1 (en) * | 2011-01-24 | 2012-07-26 | Aptina Imaging Corporation | System and method for biasing analog circuitry in a distributed power delivery network for image sensors and other circuit structures |
| TW201436569A (en) * | 2013-03-13 | 2014-09-16 | Himax Imaging Ltd | Image sensors |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20060054783A1 (en) * | 2004-09-09 | 2006-03-16 | Transchip, Inc. | Imager flicker compensation systems and methods |
| US20120187936A1 (en) * | 2011-01-24 | 2012-07-26 | Aptina Imaging Corporation | System and method for biasing analog circuitry in a distributed power delivery network for image sensors and other circuit structures |
| TW201436569A (en) * | 2013-03-13 | 2014-09-16 | Himax Imaging Ltd | Image sensors |
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