TWI496961B - Electrical chemical plating process - Google Patents
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Description
本發明係關於一種電鍍步驟,特別是一種具有預備電鍍步驟的電鍍步驟,有助於提高銅導電層之底部填洞能力。The present invention relates to a plating step, particularly a plating step having a preliminary plating step, which helps to improve the bottom filling ability of the copper conductive layer.
由於元件之線寬尺寸日益縮小,習知用來溝填溝渠以形成內金屬連線之金屬材料由於填洞能力不佳、電阻值較高等因素,已無法滿足目前半導體產業的需要。因此,具有高導電性之金屬銅,便被廣泛地應用於製作低線寬尺寸的內金屬連線。Due to the shrinking of the line width of the components, the metal materials used to fill the trenches to form the inner metal wires are unable to meet the needs of the current semiconductor industry due to factors such as poor hole filling ability and high resistance value. Therefore, metallic copper having high conductivity is widely used for making inner metal wiring of a low line width.
習知形成銅導電層的方法為化學氣相沈積(chemical vapor deposition)製程。化學氣相沈積是使用含有有機物的化學物質作為來源氣體,因此所形成的銅導電層電阻率較高,尤其是當銅層的厚度減少時,電阻率將更增加。此外,在化學氣相沈積後所產生的殘留物,會造成銅層及後續沈積薄膜層間附著性的問題。另一方面,化學氣相沈積的成本也相對高昂,不利於現今半導體流程的生產。Conventionally, a method of forming a copper conductive layer is a chemical vapor deposition process. Chemical vapor deposition uses a chemical substance containing an organic substance as a source gas, and thus the formed copper conductive layer has a high resistivity, and particularly when the thickness of the copper layer is decreased, the resistivity is further increased. In addition, residues generated after chemical vapor deposition cause problems in adhesion between the copper layer and subsequent deposited thin film layers. On the other hand, the cost of chemical vapor deposition is relatively high, which is not conducive to the production of current semiconductor processes.
目前業界多採用電化學電鍍(electrochemical plating,ECP)技術來形成銅導電層,不但成本低廉且不會增加銅層電阻率。在電化學電鍍製程中,是將形成半導體基板浸泡在電解液中,並將電解液中的銅離子還原成金屬銅,銅導電層即可逐漸形成在半導體基板上。然而,習知的電化學電鍍製程常有底部填洞能力(bottom up fill rate)不佳的問題,溝渠無法完全被銅導電層所填滿,進而產生短路而影響元件的品質。因此,各廠商都致力於研究並改良現有的電化學電鍍製程,以獲得較佳填洞能力的銅導電層。At present, electrochemical plating (ECP) technology is widely used in the industry to form a copper conductive layer, which is not only low in cost but also does not increase the resistivity of the copper layer. In the electrochemical plating process, the semiconductor substrate is immersed in the electrolyte, and the copper ions in the electrolyte are reduced to metal copper, and the copper conductive layer can be gradually formed on the semiconductor substrate. However, the conventional electrochemical plating process often has a problem of poor bottom up fill rate, and the trench cannot be completely filled by the copper conductive layer, thereby causing a short circuit and affecting the quality of the component. Therefore, various manufacturers are committed to research and improve the existing electrochemical plating process to obtain a copper conductive layer with better hole filling ability.
本發明於是提出一種電化學電鍍方法,有助於提高銅導電層之底部填洞能力。The invention thus proposes an electrochemical plating method which contributes to the improvement of the bottom filling ability of the copper conductive layer.
本發明所提出之電化學電鍍之方法,首先提供一半導體結構於一電鍍機台中。接著進行一預備電鍍步驟,此預備電鍍步驟是在一固定電壓之環境中進行,並在電流超過電鍍機台之閥值電流後持續0.2至0.5秒。於預備電鍍步驟後,對半導體結構進行一第一電鍍步驟。The method of electrochemical plating proposed by the present invention first provides a semiconductor structure in an electroplating machine. A preliminary plating step is then performed, which is performed in a fixed voltage environment and continues for 0.2 to 0.5 seconds after the current exceeds the threshold current of the plating station. After the preliminary plating step, a first plating step is performed on the semiconductor structure.
本發明之電化學電鍍步驟中,具有一預備電鍍步驟,且此預備電鍍步驟係在一預定電壓環境中進行。本發明提出的預備電鍍步驟,較佳係在0.2秒與0.5秒之間,可在電鍍時間與電鍍品質之間獲得較佳的平衡,進而提高整體生產的品質。In the electrochemical plating step of the present invention, there is a preliminary plating step, and the preliminary plating step is performed in a predetermined voltage environment. The preliminary plating step proposed by the present invention is preferably between 0.2 seconds and 0.5 seconds, which can achieve a better balance between the plating time and the plating quality, thereby improving the overall production quality.
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明,下文特列舉本發明之數個較佳實施例,並配合所附圖式,詳細說明本發明的構成內容及所欲達成之功效。The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.
請參考第1圖至第6圖,所繪示為本發明中電化學電鍍之方法的步驟示意圖。如第1圖所示,首先提供一半導體結構400。於一實施例中,半導體結構400包含有一基底401以及位於基底401上的一絕緣層403。基底401例如是矽基底或者是金屬層間介電層,基底401中則具有一導電區405,例如是摻入離子的源極/汲極(source/drain)區域,或者是金屬內連線圖案(metal interconnection pattern),在後續以電化學電鍍形成的金屬層可和此導電區405電性連接。絕緣層403可以是二氧化矽或是其他低介電常數(low-k)材質。Please refer to FIG. 1 to FIG. 6 , which are schematic diagrams showing the steps of the method for electrochemical plating in the present invention. As shown in FIG. 1, a semiconductor structure 400 is first provided. In one embodiment, the semiconductor structure 400 includes a substrate 401 and an insulating layer 403 on the substrate 401. The substrate 401 is, for example, a germanium substrate or a metal interlayer dielectric layer, and the substrate 401 has a conductive region 405, such as a source/drain region doped with ions, or a metal interconnect pattern ( The metal interconnection pattern can be electrically connected to the conductive layer 405 in a subsequent metal layer formed by electrochemical plating. The insulating layer 403 may be germanium dioxide or other low-k material.
接著如第2圖所示,在此半導體結構400之絕緣層403中形成一溝渠402等之單鑲嵌(single damascene)圖案或雙鑲嵌(dual damascene)圖案。形成溝渠402的方式例如用微影暨蝕刻製程(photo-etching-process,PEP),以暴露出基底401中的導電區405。溝渠402的開口形狀可以是圓孔或其他不規則圖案。於一實施例中,溝渠402的深度約為2000埃至10000埃。Next, as shown in FIG. 2, a single damascene pattern or a dual damascene pattern of the trench 402 or the like is formed in the insulating layer 403 of the semiconductor structure 400. The manner in which the trenches 402 are formed is, for example, photo-etching-process (PEP) to expose the conductive regions 405 in the substrate 401. The shape of the opening of the trench 402 may be a circular hole or other irregular pattern. In one embodiment, the trench 402 has a depth of between about 2,000 angstroms and about 10,000 angstroms.
接著如第3圖所示,在半導體結構400上形成一晶種層(seed layer)404。形成晶種層404的方式例如是物理氣相沈積製程(physical vapor deposition)或化學氣相沈積製程(chemical vapor deposition),其中晶種層404會形成在絕緣層403上,並沿著溝渠402的表面共形地(conformally)形成,其厚度大致上為30埃至200埃之間。晶種層404的材質依後續金屬層的材質而調整,例如金屬層為銅時,晶種層404即為銅晶種層。於另一實施例中,在形成晶種層404之前亦可選擇性的共形地(conformally)形成一阻障層(圖未示),例如是Ti/TiN層或Ta/TaN層。Next, as shown in FIG. 3, a seed layer 404 is formed over the semiconductor structure 400. The manner of forming the seed layer 404 is, for example, a physical vapor deposition or a chemical vapor deposition, wherein the seed layer 404 is formed on the insulating layer 403 and along the trench 402. The surface is conformally formed with a thickness between approximately 30 angstroms and 200 angstroms. The material of the seed layer 404 is adjusted according to the material of the subsequent metal layer. For example, when the metal layer is copper, the seed layer 404 is a copper seed layer. In another embodiment, a barrier layer (not shown) may be selectively formed conformally before forming the seed layer 404, such as a Ti/TiN layer or a Ta/TaN layer.
如第4圖所示,進行一預備電鍍步驟。如上所述,半導體結構400中的溝渠402上已覆蓋有晶種層404。於執行預備電鍍步驟時,須將此半導體結構400置於具有電解液之電鍍機台406中,並以電極408供應電壓至晶種層404以進行預備電鍍步驟。本發明的預備電鍍步驟係正式電鍍步驟之前的準備動作,由於半導體結構400一開始置於電鍍機台406中時無法穩定地進行電鍍,因此進行預備電鍍步驟有助於提升後續正式電鍍步驟的品質。As shown in Fig. 4, a preliminary plating step is performed. As described above, the trench 402 in the semiconductor structure 400 has been covered with a seed layer 404. In performing the preliminary plating step, the semiconductor structure 400 is placed in a plating machine 406 having an electrolyte, and a voltage is supplied to the seed layer 404 with the electrode 408 to perform a preliminary plating step. The preliminary plating step of the present invention is a preparation operation before the formal plating step. Since the semiconductor structure 400 cannot be stably plated when initially placed in the plating machine 406, the preliminary plating step helps to improve the quality of the subsequent formal plating step. .
請參考第7圖,所繪示為本發明電化學電鍍步驟中電壓與電流相對於時間的波形示意圖。如第7圖所示,當電極408通以一預定電壓時,電鍍機台406中的電流即逐步上升。當電流大於電鍍機台406中預設的閥值電流(threshold current,指電鍍機台406能穩定運作時的最低電流值)時,本發明即進入預備電鍍步驟410。本發明的預備電鍍步驟410係在一固定電壓的環境下進行,於本發明之一實施例中,此固定電壓的範圍大體上介於0.6伏特至1.0伏特之間,較佳為0.8伏特。預備電鍍步驟410的時間大體上為0.2至0.5秒,較佳為0.3秒。於本發明之一實施例中,在預備電鍍步驟410中,電流會逐漸上升,最後會停留在一極大值,此極大值電流大致上為8安培至10安培。Please refer to FIG. 7 , which is a schematic diagram showing the waveforms of voltage and current with respect to time in the electrochemical plating step of the present invention. As shown in Fig. 7, when the electrode 408 is passed through a predetermined voltage, the current in the plating machine 406 is gradually increased. When the current is greater than a preset threshold current (the lowest current value at which the plating machine 406 can operate stably) in the plating machine 406, the present invention enters the preliminary plating step 410. The preliminary plating step 410 of the present invention is carried out in a fixed voltage environment. In one embodiment of the invention, the fixed voltage ranges generally between 0.6 volts and 1.0 volts, preferably 0.8 volts. The time for the preliminary plating step 410 is substantially 0.2 to 0.5 seconds, preferably 0.3 seconds. In one embodiment of the invention, in the preliminary plating step 410, the current will gradually rise and eventually stay at a maximum value which is approximately 8 amps to 10 amps.
接著進行一第一電鍍步驟412。如第5圖所示,第一電鍍步驟412即為正式電鍍步驟,金屬層414會在溝渠402表面的晶種層404逐漸形成。且由於在第一電鍍步驟412之前所進行了預備電鍍步驟410,第一電鍍步驟412時金屬層414於溝渠402底部的形成速度會較快,故可以得到較佳的底部填洞能力(bottom up fill rate)。如第7圖所示,於本發明較佳實施例中,第一電鍍步驟412係在一第一固定電流的狀況下進行,此第一固定電流的範圍大約為4.0安培至5.0安培,較佳為4.5安培。A first plating step 412 is then performed. As shown in FIG. 5, the first plating step 412 is a formal plating step, and the metal layer 414 is gradually formed on the seed layer 404 on the surface of the trench 402. And since the preliminary plating step 410 is performed before the first plating step 412, the formation speed of the metal layer 414 at the bottom of the trench 402 at the first plating step 412 is faster, so that a better bottom hole filling capability can be obtained. Fill rate). As shown in FIG. 7, in a preferred embodiment of the present invention, the first plating step 412 is performed under a first fixed current condition, and the first fixed current ranges from about 4.0 amps to 5.0 amps, preferably. It is 4.5 amps.
接著,如第6圖所示,進行一第二電鍍步驟416。在第二電鍍步驟416中,金屬層414即會逐漸填滿溝渠402,最後略高於溝渠402。如第7圖所示,於本發明較佳實施例中,第二電鍍步驟414係在一第二固定電流的狀況下進行,此第二固定電流的值較佳會大於第一固定電流的值,例如介於6.0安培至7.0安培之間,較佳為6.5安培。Next, as shown in FIG. 6, a second plating step 416 is performed. In the second plating step 416, the metal layer 414 gradually fills the trench 402 and is finally slightly above the trench 402. As shown in FIG. 7, in the preferred embodiment of the present invention, the second plating step 414 is performed under a second fixed current, and the value of the second fixed current is preferably greater than the value of the first fixed current. For example, between 6.0 amps and 7.0 amps, preferably 6.5 amps.
在第二電鍍步驟416結束後,金屬層414已形成在半導體結構400之表面且已良好地填滿於溝渠402中。於本發明另一實施例中,依所欲形成金屬層414的厚度不同,亦可在第二電鍍步驟416後選擇性的進行一第三電鍍步驟。第三電鍍步驟較佳亦在一第三固定電流的環境下進行,且此第三固定電流的值會大於第二固定電流的值。最後,在電化學電鍍步驟結束後,可將在半導體結構400上多餘的金屬層414去除,例如進行一化學機械研磨(chemical mechanical polish,CMP)等之平坦化(planarization)步驟,以在溝渠402中形成一填溝良好的金屬層414。After the second plating step 416 is completed, the metal layer 414 has been formed on the surface of the semiconductor structure 400 and has been well filled in the trench 402. In another embodiment of the present invention, a third plating step may be selectively performed after the second plating step 416, depending on the thickness of the metal layer 414 to be formed. Preferably, the third plating step is also performed in a third fixed current environment, and the value of the third fixed current is greater than the value of the second fixed current. Finally, after the electrochemical plating step is completed, the excess metal layer 414 on the semiconductor structure 400 can be removed, for example, a planarization step of a chemical mechanical polish (CMP) or the like is performed in the trench 402. A well-filled metal layer 414 is formed.
本發明之電化學電鍍步驟中,由於具有一預備電鍍步驟,且此預備電鍍步驟係在一預定電壓環境中進行。若預備電鍍步驟時間太短(例如短於0.2秒),後續正式電鍍製程須花較多時間,若預備電鍍步驟時間太長(例如長於0.5秒),會降低金屬層的底部填洞能力,因此本發明提出的預備電鍍步驟,較佳係在0.2秒與0.5秒之間,可在電鍍時間與電鍍品質之間獲得較佳的平衡,進而提高整體生產的品質。In the electrochemical plating step of the present invention, there is a preliminary plating step, and the preliminary plating step is performed in a predetermined voltage environment. If the pre-plating step is too short (for example, less than 0.2 seconds), the subsequent formal electroplating process will take more time. If the pre-plating step is too long (for example, longer than 0.5 seconds), the bottom of the metal layer will be filled, so The preliminary plating step proposed by the present invention is preferably between 0.2 seconds and 0.5 seconds, which can achieve a better balance between the plating time and the plating quality, thereby improving the overall production quality.
請參考第8圖,所繪示為本發明之電鍍步驟之步驟示意圖。首先,提供一半導體結構於一電鍍機台中(步驟300)。接著,進行一預備電鍍步驟,其中該預備電鍍步驟是在一固定電壓之環境中進行,並在電流超過該電鍍機台之閥值電流後持續0.2至0.5秒(步驟302)。最後,對該半導體結構進行一正式電鍍步驟(步驟304)。Please refer to FIG. 8 , which is a schematic diagram showing the steps of the electroplating step of the present invention. First, a semiconductor structure is provided in a plating machine (step 300). Next, a preliminary plating step is performed wherein the preliminary plating step is performed in a fixed voltage environment and continues for 0.2 to 0.5 seconds after the current exceeds the threshold current of the plating station (step 302). Finally, a formal plating step (step 304) is performed on the semiconductor structure.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
300...步驟300. . . step
302...步驟302. . . step
304...步驟304. . . step
400...半導體結構400. . . Semiconductor structure
401...基底401. . . Base
402...溝渠402. . . ditch
403...絕緣層403. . . Insulation
404...晶種層404. . . Seed layer
405...導電區405. . . Conductive zone
406...電鍍機台406. . . Plating machine
408...電極408. . . electrode
410...預備電鍍步驟410. . . Prepare plating step
412...第一電鍍步驟412. . . First plating step
414...金屬層414. . . Metal layer
416...第二電鍍步驟416. . . Second plating step
第1圖至第6圖所繪示為本發明中電化學電鍍之方法的步驟示意圖。1 to 6 are schematic views showing the steps of the method of electrochemical plating in the present invention.
第7圖所繪示為本發明電化學電鍍步驟中電壓與電流的波形示意圖。FIG. 7 is a schematic view showing the waveforms of voltage and current in the electrochemical plating step of the present invention.
第8圖所繪示為本發明之電鍍步驟之步驟示意圖。Figure 8 is a schematic view showing the steps of the electroplating step of the present invention.
300...步驟300. . . step
302...步驟302. . . step
304...步驟304. . . step
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TW564265B (en) * | 1999-11-08 | 2003-12-01 | Ebara Corp | Plating device and method |
CN101956221A (en) * | 2010-09-30 | 2011-01-26 | 深圳市信诺泰创业投资企业(普通合伙) | Continuous plating device for films and method for performing continuous plating on films |
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TW564265B (en) * | 1999-11-08 | 2003-12-01 | Ebara Corp | Plating device and method |
CN101956221A (en) * | 2010-09-30 | 2011-01-26 | 深圳市信诺泰创业投资企业(普通合伙) | Continuous plating device for films and method for performing continuous plating on films |
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