TWI496261B - Electical device package structure and method of fabricating the same - Google Patents
Electical device package structure and method of fabricating the same Download PDFInfo
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- TWI496261B TWI496261B TW101124254A TW101124254A TWI496261B TW I496261 B TWI496261 B TW I496261B TW 101124254 A TW101124254 A TW 101124254A TW 101124254 A TW101124254 A TW 101124254A TW I496261 B TWI496261 B TW I496261B
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- conductive
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- electronic component
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- 238000004519 manufacturing process Methods 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims description 53
- 229910000679 solder Inorganic materials 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 27
- 238000004806 packaging method and process Methods 0.000 claims description 15
- 238000007747 plating Methods 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 80
- 239000000463 material Substances 0.000 description 8
- 239000011241 protective layer Substances 0.000 description 7
- 238000002834 transmittance Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明是有關於一種元件封裝結構及其製作方法，且特別是有關於一種電子元件封裝結構及其製作方法。The present invention relates to an element package structure and a method of fabricating the same, and more particularly to an electronic component package structure and a method of fabricating the same.
近年來，隨著電子技術的日新月異，高科技電子產業的相繼問世，使得更人性化、功能更佳的電子產品不斷地推陳出新。在這些電子產品內通常會配置用來安裝電子元件於其上的線路板。隨著電子產品持續朝向輕、薄、短、小的趨勢設計，線路板的厚度朝向薄型化發展。In recent years, with the rapid development of electronic technology, the high-tech electronics industry has come out one after another, making more humanized and functional electronic products continue to evolve. In these electronic products, a circuit board on which electronic components are mounted is usually disposed. As electronic products continue to be designed toward light, thin, short, and small trends, the thickness of circuit boards is becoming thinner.
然而，在習知技術中，製造者會先分別製作電子元件及用以承載電子元件之線路板。之後，在將電子元件封裝在線路板上，以形成電子元件封裝結構。此作法不但費工費時，且電子元件封裝結構的整體厚度不易降低。承上述，如何開發出一種可製作出薄型化之電子元件封裝結構的方法，實為研發者所欲達成的目標之一。However, in the prior art, the manufacturer will separately fabricate electronic components and circuit boards for carrying the electronic components. Thereafter, the electronic component is packaged on the wiring board to form an electronic component package structure. This method is not only time-consuming, but also the overall thickness of the electronic component package structure is not easily reduced. In view of the above, how to develop a method for manufacturing a thin electronic component package structure is one of the goals that the developer desires to achieve.
本發明提供一種電子元件封裝方法，其可製作出整體厚度小的電子元件封裝結構。The present invention provides an electronic component packaging method which can produce an electronic component package structure having a small overall thickness.
本發明提供一種電子元件封裝結構，其整體厚度小。The present invention provides an electronic component package structure having a small overall thickness.
本發明之一實施例提出一種電子元件封裝方法，其包括下列步驟：提供線路基板，線路基板包括基底以及配置 於基底上的第一導電圖案，將電子元件配置於線路基板上，其中電子元件具有至少一電極，形成介電層於線路基板上，以覆蓋電子元件、電極以及第一導電圖案，其中第一導電圖案在介電層上形成第一凹陷圖案。圖案化介電層，以形成延伸至第一導電圖案的貫孔以及連通貫孔且暴露出電極的第二凹陷圖案。填入導電材料於貫孔以及第二凹陷圖案中，以在貫孔中形成導電通孔且在第二凹陷圖案中形成第二導電圖案，並移除基底。將第一防焊層及第二防焊層分別形成於第一導電圖案以及第二導電圖案上，其中第一防焊層暴露出部分的第一導電圖案，且第二防焊層暴露出部分的第二導電圖案。An embodiment of the present invention provides an electronic component packaging method including the steps of: providing a circuit substrate, the circuit substrate including the substrate, and the configuration a first conductive pattern on the substrate, the electronic component is disposed on the circuit substrate, wherein the electronic component has at least one electrode, and a dielectric layer is formed on the circuit substrate to cover the electronic component, the electrode, and the first conductive pattern, wherein the first The conductive pattern forms a first recess pattern on the dielectric layer. The dielectric layer is patterned to form a via extending to the first conductive pattern and a second recess pattern that communicates through the via and exposes the electrode. A conductive material is filled in the through hole and the second recess pattern to form a conductive via in the via hole and to form a second conductive pattern in the second recess pattern, and to remove the substrate. Forming a first solder resist layer and a second solder resist layer on the first conductive pattern and the second conductive pattern, respectively, wherein the first solder resist layer exposes a portion of the first conductive pattern, and the second solder resist layer exposes a portion The second conductive pattern.
本發明之一實施例提出一種電子元件封裝結構，其包括介電層、電子元件、第一導電圖案、第二導電圖案、導電通孔、第一防焊層以及第二防焊層。介電層具有第一表面、相對於第一表面之第二表面、配置於第一表面上且凹陷於第一表面的第一凹陷圖案、配置於第二表面上且凹陷於第二表面的至少一第二凹陷圖案以及由第一凹陷圖案延伸至第二凹陷圖案的至少一貫孔。電子元件埋在介電層中並具有至少一電極，電極暴露於第二凹陷圖案。第一導電圖案填入第一凹陷圖案，第二導電圖案填入第二凹陷圖案而與電子元件的電極連接，且導電通孔填入貫孔而連接第一導電圖案以及第二導電圖案。第一防焊層配置於介電層的第一表面以及第一導電圖案上，並暴露出部分的第一導電圖案。第二防焊層配置於介電層的第二表面以及第二導電圖案上，並暴露出部分的第二導電圖案。An embodiment of the present invention provides an electronic component package structure including a dielectric layer, an electronic component, a first conductive pattern, a second conductive pattern, a conductive via, a first solder resist layer, and a second solder resist layer. The dielectric layer has a first surface, a second surface opposite to the first surface, a first recess pattern disposed on the first surface and recessed on the first surface, and disposed on the second surface and recessed on the second surface a second recess pattern and at least a consistent aperture extending from the first recess pattern to the second recess pattern. The electronic component is buried in the dielectric layer and has at least one electrode that is exposed to the second recessed pattern. The first conductive pattern fills the first recess pattern, the second conductive pattern fills the second recess pattern to be connected to the electrodes of the electronic component, and the conductive via fills the through hole to connect the first conductive pattern and the second conductive pattern. The first solder resist layer is disposed on the first surface of the dielectric layer and the first conductive pattern, and exposes a portion of the first conductive pattern. The second solder resist layer is disposed on the second surface of the dielectric layer and the second conductive pattern, and exposes a portion of the second conductive pattern.
基於上述，在本發明中，可將電子元件埋入介電層中，以大幅縮減電子元件封裝結構的整體厚度。此外，藉由在介電層的凹陷圖案中填入導電材料以形成導電圖案亦可使電子元件封裝結構的整體厚度更進一步地降低。Based on the above, in the present invention, the electronic component can be buried in the dielectric layer to greatly reduce the overall thickness of the electronic component package structure. In addition, the overall thickness of the electronic component package structure can be further reduced by filling a conductive pattern in the recess pattern of the dielectric layer to form a conductive pattern.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
電子元件封裝方法Electronic component packaging method
圖1A至圖1K為本發明一實施例之電子元件封裝方法的剖面示意圖。請先參照圖1A及圖1B，首先，提供線路基板110(繪於圖1B)，其中線路基板110包括基底112以及配置於基底112上的第一導電圖案114。在本實施例中，基底112包括基材112a以及覆蓋基材112a相對二表面的阻障層112b。基材112a之材質例如為金屬或高分子聚合物，阻障層112b之材質例如為金屬(包括鋁或鎳)或聚合物(polymer)，但本發明不以此為限。1A to 1K are schematic cross-sectional views showing an electronic component packaging method according to an embodiment of the present invention. Referring first to FIG. 1A and FIG. 1B , first, a circuit substrate 110 (shown in FIG. 1B ) is provided. The circuit substrate 110 includes a substrate 112 and a first conductive pattern 114 disposed on the substrate 112 . In the present embodiment, the substrate 112 includes a substrate 112a and a barrier layer 112b covering the opposite surfaces of the substrate 112a. The material of the substrate 112a is, for example, a metal or a polymer, and the material of the barrier layer 112b is, for example, a metal (including aluminum or nickel) or a polymer, but the invention is not limited thereto.
在本實施例中，提供線路基板110的方法包括下列步驟。首先，如圖1A所示，提供基底112以及配置於基底112上的第一導電層116。接著，如圖1B所示，圖案化第一導電層116，以形成電鍍種子層118及位在電鍍種子層118上的第一導電圖案114。進一步而言，在本實施例中，圖案化第一導電層116以形成第一導電圖案114的步驟包括進行半加成工序(Semi-additive Process)。本實施例之 電鍍種子層118及第一導電圖案114的材質可相同，電鍍種子層118及第一導電圖案114的材質例如為銅。In the present embodiment, the method of providing the wiring substrate 110 includes the following steps. First, as shown in FIG. 1A, a substrate 112 and a first conductive layer 116 disposed on the substrate 112 are provided. Next, as shown in FIG. 1B, the first conductive layer 116 is patterned to form a plating seed layer 118 and a first conductive pattern 114 on the plating seed layer 118. Further, in the present embodiment, the step of patterning the first conductive layer 116 to form the first conductive pattern 114 includes performing a semi-additive process. This embodiment The material of the plating seed layer 118 and the first conductive pattern 114 may be the same, and the material of the plating seed layer 118 and the first conductive pattern 114 is, for example, copper.
然而，本發明之提供線路基板的方法並不限於上段所述。圖2A及圖2B繪示本發明另一實施例之提供線路基板的方法。請參照圖2A及圖2B，首先，提供線路基板110A(繪於圖2B)，其中線路基板110包括基底112以及配置於基底112上的第一導電圖案114。特別是，第一導電圖案114暴露出部分的基底112。詳言之，如圖2A所示，可先提供基底112以及配置於基底112上的第一導電層116。接著，如圖2B所示，圖案第一導電層116，以形成第一導電圖案114。在此實施例中，圖案化第一導電層116，以形成第一導電圖案114的步驟包括進行減成工序(Subtractive Process)。簡言之，在其他實施例中，可不形成電鍍種子層118，而形成第一導電圖案114。如此一來，在電子元件封裝方法中，便可省去移除電鍍種子層118的步驟(如圖1H)，而使電子元件封裝方法更為簡單。此外，需說明的是，以圖2A及圖2B所示方法而提供的線路基板亦適用於下述的製程步驟(如圖1C至圖1G以及圖1J、圖1K)，進而形成電子元件封裝結構。此領域具有通常知識者可推知，因此於後續段落中便不再逐一詳述。However, the method of providing a circuit substrate of the present invention is not limited to the above. 2A and 2B illustrate a method of providing a circuit substrate according to another embodiment of the present invention. Referring to FIG. 2A and FIG. 2B , first, a circuit substrate 110A (shown in FIG. 2B ) is provided. The circuit substrate 110 includes a substrate 112 and a first conductive pattern 114 disposed on the substrate 112 . In particular, the first conductive pattern 114 exposes a portion of the substrate 112. In detail, as shown in FIG. 2A, the substrate 112 and the first conductive layer 116 disposed on the substrate 112 may be provided first. Next, as shown in FIG. 2B, the first conductive layer 116 is patterned to form the first conductive pattern 114. In this embodiment, the step of patterning the first conductive layer 116 to form the first conductive pattern 114 includes performing a subtractive process. In short, in other embodiments, the plating seed layer 118 may not be formed to form the first conductive pattern 114. In this way, in the electronic component packaging method, the step of removing the plating seed layer 118 (FIG. 1H) can be omitted, and the electronic component packaging method is simpler. In addition, it should be noted that the circuit substrate provided by the method shown in FIG. 2A and FIG. 2B is also applicable to the following process steps (as shown in FIG. 1C to FIG. 1G and FIG. 1J and FIG. 1K), thereby forming an electronic component package structure. . Those in the field who have the usual knowledge can infer, and therefore will not be detailed one by one in subsequent paragraphs.
請參照圖1C，接著，將電子元件120配置於線路基板110上。電子元件120具有至少一電極122。在本實施例中，在將電子元件120配置於線路基板110上的步驟中，電子元件120可配置於電鍍種子層118上。請參照圖1D， 接著，形成介電層130於線路基板110上，以覆蓋電子元件120、電極122以及第一導電圖案114，其中第一導電圖案114在介電層130上形成第一凹陷圖案132。Referring to FIG. 1C, the electronic component 120 is then disposed on the circuit substrate 110. The electronic component 120 has at least one electrode 122. In the embodiment, in the step of disposing the electronic component 120 on the circuit substrate 110, the electronic component 120 may be disposed on the plating seed layer 118. Please refer to Figure 1D, Next, a dielectric layer 130 is formed on the circuit substrate 110 to cover the electronic component 120, the electrode 122, and the first conductive pattern 114. The first conductive pattern 114 forms a first recess pattern 132 on the dielectric layer 130.
在本實施例中，介電層130可全面性覆蓋電子元件120以及第一導電圖案114。形成介電層130於線路基板110上的目的之一是使電子元件120固定於線路基板110上。在本實施例中，介電層130的材質例如是高分子聚合物。In the embodiment, the dielectric layer 130 can cover the electronic component 120 and the first conductive pattern 114 in a comprehensive manner. One of the purposes of forming the dielectric layer 130 on the circuit substrate 110 is to fix the electronic component 120 on the circuit substrate 110. In the present embodiment, the material of the dielectric layer 130 is, for example, a high molecular polymer.
請參照圖1E，接著，圖案化介電層130，以形成延伸至第一導電圖案114的貫孔134以及連通貫孔134且暴露出電極122的第二凹陷圖案136。在本實施例中，第二凹陷圖案136可具有第一凹陷136a以及位於第一凹陷136a相對二側的二第二凹陷136b，且第二凹陷136b之任一的深度大於第一凹陷136a的深度。在本實施例中，圖案化介電層130的步驟包括將雷射光束(未繪示)照射介電層130，以形成貫孔134以及第二凹陷圖案136。更進一步地說，由於所欲形成之貫孔134與第二凹陷圖案136的凹陷程度不一，在本實施例中，可將雷射光束通過灰階光罩(未繪示)而照射至介電層130，以形成貫孔134以及第二凹陷圖案136。舉例而言，灰階光罩可具有高透光度的第一透光區、中透光度的第二透光區以及低透光度的第三透光區，部份之雷射光束通過具有高透光度的第一透光區後可於介電層130中形成凹陷程度較深之貫孔134，部份之雷射光束通過具有中透光度的第二透光區後可於介電層130中形成凹陷程度次深之第二凹陷136b，而部份之雷射光束 通過具有低透光度的第三透光區後可於介電層130中形成凹陷程度淺之第一凹陷136a。Referring to FIG. 1E, the dielectric layer 130 is patterned to form a through hole 134 extending to the first conductive pattern 114 and a second recess pattern 136 that communicates through the hole 134 and exposes the electrode 122. In this embodiment, the second recess pattern 136 may have a first recess 136a and two second recesses 136b on opposite sides of the first recess 136a, and the depth of any of the second recesses 136b is greater than the depth of the first recess 136a. . In the present embodiment, the step of patterning the dielectric layer 130 includes irradiating a laser beam 130 (not shown) to form the through hole 134 and the second recess pattern 136. Further, since the through holes 134 and the second recess patterns 136 are different in degree of depression, in the embodiment, the laser beam can be irradiated to the medium through a gray scale mask (not shown). The electrical layer 130 is formed to form a through hole 134 and a second recess pattern 136. For example, the gray scale reticle may have a first light transmission area with high transmittance, a second light transmission area with medium transmittance, and a third light transmission area with low transmittance, and part of the laser beam passes through After the first light-transmissive region having high transmittance, a through-hole 134 having a deep recessed depth may be formed in the dielectric layer 130, and a portion of the laser beam passes through the second light-transmitting region having a medium transmittance. A second recess 136b having a second recessed depth is formed in the dielectric layer 130, and a portion of the laser beam is formed. The first recess 136a having a shallow degree of depression may be formed in the dielectric layer 130 by the third light-transmissive region having low transmittance.
請參照圖1F及圖1G，接著，填入導電材料140於貫孔134以及第二凹陷圖案136中，以在貫孔134中形成導電通孔142，且在第二凹陷圖案136中形成第二導電圖案144(繪於圖1G)。詳言之，如圖1F所示，可先形成第二導電層140a於第二凹陷圖案136上，其中第二導電層140a延伸至貫孔134以及第二凹陷圖案136內，且第二導電層140a全面性覆蓋介電層130。在本實施例中，可利用電鍍工序在第二凹陷圖案136上形成第二導電層140a。但本發明不以此為限。接著，如圖1G所示，移除部分的第二導電層140a而留下填入貫孔136的導電通孔142以及填入在第二凹陷圖案136中的第二導電圖案144。Referring to FIG. 1F and FIG. 1G, the conductive material 140 is filled in the through hole 134 and the second recess pattern 136 to form the conductive via 142 in the through hole 134 and form the second in the second recess pattern 136. Conductive pattern 144 (shown in Figure 1G). In detail, as shown in FIG. 1F, the second conductive layer 140a may be formed on the second recess pattern 136, wherein the second conductive layer 140a extends into the through hole 134 and the second recess pattern 136, and the second conductive layer The 140a comprehensively covers the dielectric layer 130. In the present embodiment, the second conductive layer 140a may be formed on the second recess pattern 136 by a plating process. However, the invention is not limited thereto. Next, as shown in FIG. 1G, a portion of the second conductive layer 140a is removed leaving a conductive via 142 filled in the via 136 and a second conductive pattern 144 filled in the second recess pattern 136.
請參照圖1G及圖1H，接著，移除基底112。如圖1H所示，在本實施例中，於移除基底112後，更可進一步地移除電鍍種子層118。在本實施例中，可利用蝕刻工序(Etching Process)移除電鍍種子層118。請參照圖1J，接著，將第一防焊層152及第二防焊層154分別形成於第一導電圖案114以及第二導電圖案144上。第一防焊層152暴露出部分的第一導電圖案114。第二防焊層154暴露出部分的第二導電圖案144。在本實施例中，第二防焊層154可暴露出與導電通孔142連接的部分第二導電圖案144。Referring to FIG. 1G and FIG. 1H, the substrate 112 is removed. As shown in FIG. 1H, in the present embodiment, after the substrate 112 is removed, the plating seed layer 118 can be further removed. In the present embodiment, the plating seed layer 118 can be removed using an etching process. Referring to FIG. 1J , the first solder resist layer 152 and the second solder resist layer 154 are respectively formed on the first conductive pattern 114 and the second conductive pattern 144 . The first solder resist layer 152 exposes a portion of the first conductive pattern 114. The second solder resist layer 154 exposes a portion of the second conductive pattern 144. In the embodiment, the second solder resist layer 154 may expose a portion of the second conductive pattern 144 connected to the conductive via 142.
請參照圖1K，接著，形成保護層160，其中第一防焊層152暴露出的部分第一導電圖案114以及被第二防焊層 154暴露出的部分第二導電圖案114形成多個接墊P，且保護層160覆蓋至少一接墊P。在本實施例中，保護層160之材質例如為金。然後，形成銲料球170，其中銲料球170連接至少一接墊P。於此便完成了本實施例之電子元件封裝結構100。Referring to FIG. 1K, next, a protective layer 160 is formed, wherein a portion of the first conductive pattern 114 exposed by the first solder resist layer 152 and the second solder resist layer are formed. A portion of the second conductive pattern 114 exposed by the 154 forms a plurality of pads P, and the protective layer 160 covers at least one of the pads P. In this embodiment, the material of the protective layer 160 is, for example, gold. Then, a solder ball 170 is formed in which the solder ball 170 is connected to at least one pad P. Thus, the electronic component package structure 100 of the present embodiment is completed.
電子元件封裝結構Electronic component package structure
請參照圖1K，本實施例之電子元件封裝結構100包括介電層130、電子元件120、第一導電圖案114、第二導電圖案144、導電通孔142、第一防焊層152以及第二防焊層154。Referring to FIG. 1K , the electronic component package structure 100 of the present embodiment includes a dielectric layer 130 , an electronic component 120 , a first conductive pattern 114 , a second conductive pattern 144 , a conductive via 142 , a first solder resist layer 152 , and a second Solder mask layer 154.
介電層130具有第一表面130a、相對於第一表面130a之第二表面130b、配置於第一表面130a上且凹陷於第一表面130a的第一凹陷圖案132、配置於第二表面130b上且凹陷於第二表面130b的至少一第二凹陷圖案136以及由第一凹陷圖案132延伸至第二凹陷圖案136的至少一貫孔134。電子元件120埋在介電層130中並具有至少一電極122。電極122暴露於第二凹陷圖案136。The dielectric layer 130 has a first surface 130a, a second surface 130b opposite to the first surface 130a, a first recess pattern 132 disposed on the first surface 130a and recessed on the first surface 130a, and disposed on the second surface 130b. And at least one second recess pattern 136 recessed in the second surface 130b and at least the consistent hole 134 extending from the first recess pattern 132 to the second recess pattern 136. The electronic component 120 is buried in the dielectric layer 130 and has at least one electrode 122. The electrode 122 is exposed to the second recess pattern 136.
第一導電圖案114填入第一凹陷圖案132。第二導電圖案144填入第二凹陷圖案136而與電子元件120的電極122連接。在本實施例中，第一導電圖案114實質上與第一表面130a切齊，而第二導電圖案144實質上與第二表面130b切齊。值得注意的是，在本實施例中，第二凹陷圖案136可具有第一凹陷136a以及位於第一凹陷136a相對二 側的二第二凹陷136b，且第二凹陷136b之任一的深度大於第一凹陷136a的深度。填入第二凹陷136b之部分第二導電圖案144可被填入第一凹陷136a之部分第二導電圖案144所屏蔽。因此，藉由填入第一凹陷136a之部分第二導電圖案144的屏蔽效應，在填入第二凹陷136b之部分第二導電圖案144中傳遞的電訊號被外界雜訊干擾之機率可大幅降低。The first conductive pattern 114 is filled in the first recess pattern 132. The second conductive pattern 144 is filled in the second recess pattern 136 to be connected to the electrode 122 of the electronic component 120. In the present embodiment, the first conductive pattern 114 is substantially aligned with the first surface 130a, and the second conductive pattern 144 is substantially aligned with the second surface 130b. It should be noted that, in this embodiment, the second recess pattern 136 may have a first recess 136a and a second recess 136a opposite to the second The second second recess 136b of the side, and the depth of any of the second recesses 136b is greater than the depth of the first recess 136a. A portion of the second conductive pattern 144 filled in the second recess 136b may be shielded by a portion of the second conductive pattern 144 filled in the first recess 136a. Therefore, by the shielding effect of the portion of the second conductive pattern 144 filled in the first recess 136a, the probability that the electrical signal transmitted in the portion of the second conductive pattern 144 filled in the second recess 136b is disturbed by external noise can be greatly reduced. .
導電通孔142填入貫孔134而連接第一導電圖案114以及第二導電圖案144。第一防焊層152配置於介電層130的第一表面130a以及第一導電圖案114上，並暴露出部分的第一導電圖案114。第二防焊層154配置於介電層130的第二表面130b以及第二導電圖案144上，並暴露出部分的第二導電圖案144。在本實施例中，被第二防焊層154暴露出的部分第二導電圖案114與導電通孔142連接。The conductive via 142 is filled in the via 134 to connect the first conductive pattern 114 and the second conductive pattern 144. The first solder resist layer 152 is disposed on the first surface 130a of the dielectric layer 130 and the first conductive pattern 114, and exposes a portion of the first conductive pattern 114. The second solder resist layer 154 is disposed on the second surface 130b of the dielectric layer 130 and the second conductive pattern 144, and exposes a portion of the second conductive pattern 144. In the present embodiment, a portion of the second conductive pattern 114 exposed by the second solder resist layer 154 is connected to the conductive via 142.
本實施例之電子元件封裝結構100可進一步包括保護層160。被第一防焊層152暴露出的部分第一導電圖案114以及被第二防焊層154暴露出的部分第二導電圖案144形成多個接墊P。保護層160覆蓋至少一接墊P。本實施例之電子元件封裝結構100可選擇性地包括銲料球170。銲料170球連接至少一接墊P。The electronic component package structure 100 of the present embodiment may further include a protective layer 160. A portion of the first conductive pattern 114 exposed by the first solder resist layer 152 and a portion of the second conductive pattern 144 exposed by the second solder resist layer 154 form a plurality of pads P. The protective layer 160 covers at least one pad P. The electronic component package structure 100 of the present embodiment may optionally include a solder ball 170. The solder 170 ball connects at least one pad P.
值得一提的是，在本實施例之電子元件封裝結構100中，由於第一導電圖案114、第二導電圖案144以及電子元件120是內埋在介電層130中，因此電子元件封裝結構100整體的厚度可大幅縮減，進而使得採用電子元件封裝 結構100的電子裝置可具有外型輕薄短小的優勢。It is to be noted that, in the electronic component package structure 100 of the present embodiment, since the first conductive pattern 114, the second conductive pattern 144, and the electronic component 120 are buried in the dielectric layer 130, the electronic component package structure 100 The overall thickness can be greatly reduced, resulting in the use of electronic components The electronic device of the structure 100 can have the advantages of being thin and thin in appearance.
綜上所述，在本發明中，可將電子元件埋入介電層中，以大幅縮減電子元件封裝結構的整體厚度。此外，藉由在介電層的凹陷圖案中填入導電材料以形成導電圖案亦可使電子元件封裝結構的整體厚度更進一步地降低。In summary, in the present invention, the electronic component can be buried in the dielectric layer to greatly reduce the overall thickness of the electronic component package structure. In addition, the overall thickness of the electronic component package structure can be further reduced by filling a conductive pattern in the recess pattern of the dielectric layer to form a conductive pattern.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧電子元件封裝結構100‧‧‧Electronic component packaging structure
110‧‧‧線路基板110‧‧‧Line substrate
112‧‧‧基底112‧‧‧Base
112a‧‧‧基材112a‧‧‧Substrate
112b‧‧‧阻障層112b‧‧‧Barrier layer
114‧‧‧第一導電圖案114‧‧‧First conductive pattern
116‧‧‧第一導電層116‧‧‧First conductive layer
118‧‧‧電鍍種子層118‧‧‧Electroplating seed layer
120‧‧‧電子元件120‧‧‧Electronic components
122‧‧‧電極122‧‧‧ electrodes
130‧‧‧介電層130‧‧‧Dielectric layer
130a‧‧‧第一表面130a‧‧‧ first surface
130b‧‧‧第二表面130b‧‧‧second surface
132‧‧‧第一凹陷圖案132‧‧‧First recessed pattern
134‧‧‧貫孔134‧‧‧through holes
136‧‧‧第二凹陷圖案136‧‧‧second recessed pattern
136a‧‧‧第一凹陷136a‧‧‧first depression
136b‧‧‧第二凹陷136b‧‧‧second depression
140‧‧‧導電材料140‧‧‧Electrical materials
140a‧‧‧第二導電層140a‧‧‧Second conductive layer
142‧‧‧導電通孔142‧‧‧ conductive through holes
144‧‧‧第二導電圖案144‧‧‧Second conductive pattern
152‧‧‧第一防焊層152‧‧‧First solder mask
154‧‧‧第二防焊層154‧‧‧Second solder mask
160‧‧‧保護層160‧‧‧Protective layer
170‧‧‧銲料球170‧‧‧ solder balls
圖1A至圖1K為本發明一實施例之電子元件封裝方法的剖面示意圖。1A to 1K are schematic cross-sectional views showing an electronic component packaging method according to an embodiment of the present invention.
圖2A及圖2B繪示本發明另一實施例之提供線路基板的方法。2A and 2B illustrate a method of providing a circuit substrate according to another embodiment of the present invention.
100‧‧‧電子元件封裝結構100‧‧‧Electronic component packaging structure
114‧‧‧第一導電圖案114‧‧‧First conductive pattern
120‧‧‧電子元件120‧‧‧Electronic components
122‧‧‧電極122‧‧‧ electrodes
130‧‧‧介電層130‧‧‧Dielectric layer
130a‧‧‧第一表面130a‧‧‧ first surface
130b‧‧‧第二表面130b‧‧‧second surface
132‧‧‧第一凹陷圖案132‧‧‧First recessed pattern
134‧‧‧貫孔134‧‧‧through holes
136‧‧‧第二凹陷圖案136‧‧‧second recessed pattern
136a‧‧‧第一凹陷136a‧‧‧first depression
136b‧‧‧第二凹陷136b‧‧‧second depression
140‧‧‧導電材料140‧‧‧Electrical materials
142‧‧‧導電通孔142‧‧‧ conductive through holes
144‧‧‧第二導電圖案144‧‧‧Second conductive pattern
152‧‧‧第一防焊層152‧‧‧First solder mask
154‧‧‧第二防焊層154‧‧‧Second solder mask
160‧‧‧保護層160‧‧‧Protective layer
170‧‧‧銲料球170‧‧‧ solder balls
Claims (6)
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| US20100314352A1 (en) * | 2009-06-12 | 2010-12-16 | Unimicron Technology Corp. | Fabricating method of embedded package structure |
| US8097943B2 (en) * | 2007-12-06 | 2012-01-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming wafer level ground plane and power ring |
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| US8097943B2 (en) * | 2007-12-06 | 2012-01-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming wafer level ground plane and power ring |
| US20100314352A1 (en) * | 2009-06-12 | 2010-12-16 | Unimicron Technology Corp. | Fabricating method of embedded package structure |
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