TWI495267B - Phase locked loop having retiming part for jitter removing of programable frequency divider - Google Patents
Phase locked loop having retiming part for jitter removing of programable frequency divider Download PDFInfo
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本發明系有關一種鎖相環(PLL：Phase Locked Loop)，特別是一種具備用於除去可編程分頻器抖動之重定時部之鎖相環，其重定時(retiming)對電壓控制振盪器輸出信號相位進行分頻之可編程分頻器輸出之後，傳送至相位檢測器進行比較，從而去除分頻器輸出抖動所引起之帶內噪聲。The present invention relates to a phase locked loop (PLL), and more particularly to a phase locked loop having a retiming section for removing programmable frequency divider jitter, which is retiming to a voltage controlled oscillator output. After the signal phase is divided by the programmable divider output, it is sent to the phase detector for comparison to remove the in-band noise caused by the divider output jitter.
通常，鎖相環100為檢測輸入信號和輸出信號之間之相差，控制電壓控制振盪器(VCO：Voltage Controlled Oscillator)，以維持固定輸出信號頻率之電路，如圖1所示，包括：標準分頻器110，提供穩定之標準頻率；相位檢測器120，比較經標準分頻器和主分頻器分頻之輸出頻率相位，輸出脈衝；電荷泵130，按脈衝寬度比例供應電荷；環路濾波器140，根據所聚積之電荷量變化調整電壓；電壓控制振盪器150，根據經調整之電壓輸出特定頻率；適應頻率校準部160，利用標準分頻器之輸出和主分頻器之輸出檢測頻率；及主分頻器170，反饋所述電壓控制振盪器之輸出頻率進行分頻之後，傳送至所述相位檢測器。Generally, the phase-locked loop 100 is a circuit that detects a phase difference between an input signal and an output signal, and controls a voltage controlled oscillator (VCO) to maintain a fixed output signal frequency, as shown in FIG. The frequency converter 110 provides a stable standard frequency; the phase detector 120 compares the output frequency phase divided by the standard frequency divider and the main frequency divider, and outputs a pulse; the charge pump 130 supplies the charge according to the pulse width ratio; the loop filter The controller 140 adjusts the voltage according to the accumulated charge amount change; the voltage controlled oscillator 150 outputs a specific frequency according to the adjusted voltage; the adaptive frequency calibration unit 160 detects the frequency by using the output of the standard frequency divider and the output of the main frequency divider. And a main frequency divider 170 that feeds back the output frequency of the voltage controlled oscillator for frequency division and then transmits to the phase detector.
此時，所述標準分頻器100，由不受外部溫度影響，供應穩定標準頻率(fref )之溫度補償晶體振盪器(TCXO：Temperature Compensated X-tal Oscillator)構成；而所述相位檢測器(PFD：Phase Frequency Detector)120，比較經所述標準分頻器分頻之 TCXO之標準頻率和經主分頻器(main divider)分頻之輸出頻率，輸出對應於其差之脈衝串。At this time, the standard frequency divider 100 is composed of a temperature compensated crystal oscillator (TCXO: Temperature Compensated X-tal Oscillator) that is not affected by external temperature and supplies a stable standard frequency (f ref ); and the phase detector (PFD: Phase Frequency Detector) 120, compares the standard frequency of the TCXO divided by the standard frequency divider and the output frequency divided by the main divider, and outputs a pulse train corresponding to the difference.
所述電荷泵(Charge Pump)130，增加或減少對應於所述相位檢測器所輸出脈衝寬度之電荷量，將電荷聚積在串聯于環路濾波器(Loop Filter)140之電容器後放射，引起電荷量之變化，從而調整所述電壓控制振盪器150之電壓。另外，所述電壓控制振盪器(VCO)150，根據經所述環路濾波器調整之輸入電壓，輸出特定頻率。The charge pump 130 increases or decreases the amount of charge corresponding to the pulse width outputted by the phase detector, and accumulates the charge after being accumulated in a capacitor connected in series with the loop filter 140 to cause a charge. The amount is varied to adjust the voltage of the voltage controlled oscillator 150. In addition, the voltage controlled oscillator (VCO) 150 outputs a specific frequency according to an input voltage adjusted by the loop filter.
所述適應頻率校準部(AFC：Adaptive Frequency Calibration)160，校準所述電壓控制振盪器(VCO)之頻率，包括：頻率比較器163，比較分頻為1/R之161標準分頻器頻率(fR2 )和分頻為1/N之162主分頻器輸出頻率(fN2 )；泵激電壓監控電路165，監控所述電荷泵電壓電平(Vcp )；狀態機164，根據所述頻率比較器比較檢測出之頻率，向所述電壓控制振盪器提供規定比特之頻率(AFCout )，控制電壓控制振盪器(GW1、GW2)。The adaptive frequency calibration unit (AFC) 160 calibrates the frequency of the voltage controlled oscillator (VCO), including: a frequency comparator 163, which compares a frequency divider of 1/R to a standard frequency of 161 ( f R2 ) and 162 main divider output frequency (f N2 ) divided by 1/N; pumping voltage monitoring circuit 165, monitoring the charge pump voltage level (V cp ); state machine 164, according to The frequency comparator compares the detected frequencies, supplies a predetermined bit frequency (AFC out ) to the voltage controlled oscillator, and controls the voltage controlled oscillators (GW1, GW2).
所述主分頻器(Main Divider)170，包括：預定標器171，反饋接收所述電壓控制振盪器之輸出頻率(fout )，預先設置分頻比例；可編程分頻器172，動態調整所述預定標器之分頻比例，根據經調整之分頻比例分頻所述電壓控制振盪器150之輸出頻率(fout )；Σ-△調製器(SDM：Σ-△ Modulator)173，為分頻比例之調整，向所述可編程分頻器提供分頻數據。The main frequency divider (Main Divider) 170 includes: a prescaler 171, feedback receiving an output frequency (f out ) of the voltage controlled oscillator, and setting a frequency division ratio in advance; a programmable frequency divider 172, dynamically adjusting a frequency dividing ratio of the prescaler, dividing an output frequency (f out ) of the voltage controlled oscillator 150 according to the adjusted frequency dividing ratio; a Σ-Δ modulator (SDM: Σ-Δ Modulator) 173, The adjustment of the frequency division ratio provides frequency division data to the programmable frequency divider.
在所述先前技術之鎖相環(PLL)中，所述控制電壓振盪器之輸出信號，從所述主分頻器反饋(feedback)，經可編程分頻 器分頻之後，傳送至所述相位檢測器(FMN2)並與標準頻率(fref )進行相位比較。In the prior art phase locked loop (PLL), an output signal of the control voltage oscillator is fed back from the main frequency divider, divided by a programmable frequency divider, and transmitted to the The phase detector (FMN2) is phase compared to the standard frequency (f ref ).
因此，所述主分頻器，尤其是可編程分頻器之輸出所產生之靜態相位誤差(static phase error)及抖動(jitter)或Σ-△調製器(SDM)之噪聲，將引起電壓控制振盪器(VCO)之帶內噪聲(Inband noise)。Therefore, the static phase error and jitter of the main frequency divider, especially the output of the programmable frequency divider, or the noise of the sigma-delta modulator (SDM) will cause voltage control. Inband noise of the oscillator (VCO).
本發明之目的在於，提供一種具備用於除去可編程分頻器抖動之重定時部之鎖相環，在將經預定標器及可編程分頻器完成分頻之輸出頻率傳送至相位檢測器之前，對其進行重定時之後再進行傳送，以去除控制電壓振盪器之輸出端和可編程分頻器所產生之相位誤差和抖動，降低帶內噪聲。It is an object of the present invention to provide a phase locked loop having a retiming section for removing programmable frequency divider jitter, and transmitting an output frequency that is frequency-divided by a prescaler and a programmable frequency divider to a phase detector Previously, it was retimed and then transmitted to remove the phase error and jitter generated by the output of the control voltage oscillator and the programmable divider, reducing in-band noise.
本發明之目的是這樣實現的：提供一種具備用於除去可編程分頻器抖動之重定時部之鎖相環，在比較電壓控制振盪器的輸出頻率和標準頻率，以維持固定輸出頻率的鎖相環(PLL)中，還包括：主分頻器，反饋所述電壓控制振盪器之輸出頻率(FVCO )進行分頻，並將完成分頻之輸出頻率傳送至重定時部；及重定時部，重定時經所述主分頻器分頻之輸出頻率，並為相位比較將其傳送至所述相位檢測器。The object of the present invention is achieved by providing a phase locked loop having a retiming section for removing programmable frequency divider jitter, and comparing the output frequency of the voltage controlled oscillator with a standard frequency to maintain a fixed output frequency lock The phase loop (PLL) further includes: a main frequency divider that feeds back the output frequency (F VCO ) of the voltage controlled oscillator to divide the frequency, and transmits the output frequency of the divided frequency to the retiming section; and retiming And retime the output frequency divided by the main frequency divider and transmit it to the phase detector for phase comparison.
另外，所述主分頻器之特徵是，包括：預定標器，反饋接收所述電壓控制振盪器之輸出頻率(FVCO )，並將其分頻為可動態調整之分頻比例；可編程分頻器，對經所述預定標器分頻之輸出 頻率進行分頻，並將其傳送至重定時部；及Σ-△調製器，為分頻比例之調整，向所述可編程分頻器提供分頻數據。In addition, the main frequency divider is characterized by comprising: a prescaler, feedback receiving an output frequency (F VCO ) of the voltage controlled oscillator, and dividing the frequency into a dynamically adjustable frequency division ratio; programmable a frequency divider that divides an output frequency divided by the prescaler and transmits it to a retiming section; and a Σ-Δ modulator that adjusts a frequency division ratio to the programmable frequency division The divider provides the crossover data.
另外，所述可編程分頻器之特徵是，包括：第一計數器，將經所述預定標器分頻之輸出頻率作為輸入，按可編程分頻器之分頻比例(1/N)進行分頻，並將經分頻之輸出頻率傳送至重定時部；第二計數器，將經所述預定標器分頻之輸出頻率作為輸入，對脈衝進行計數，並按所述預定標器之分頻比例進行分頻；及控制器，根據所述第一計數器之輸出和第二計數器之輸出，生成用於變更所述預定標器分頻比例之控制信號，並將其輸出至所述預定標器。In addition, the programmable frequency divider is characterized in that the first counter comprises: an output frequency divided by the prescaler as an input, and a frequency division ratio (1/N) of the programmable frequency divider. Dividing, and transmitting the frequency-divided output frequency to the retiming section; the second counter is configured to input the output frequency divided by the prescaler, count the pulse, and divide the pulse according to the prescaler And frequency dividing the frequency division; and the controller generates a control signal for changing the frequency division ratio of the prescaler according to the output of the first counter and the output of the second counter, and outputs the control signal to the predetermined target Device.
另外，所述重定時部之特徵是，包括：第一觸發器，將所述第一計數器之輸出作為輸入；延遲單元，延遲所述電壓控制振盪器之輸出頻率(FVCO )；及第二觸發器，將所述第一觸發器之輸出作為輸入，將所述延遲單元之輸出作為時鐘信號，並將經重定時之信號傳送至所述相位檢測器。Further, the retiming section is characterized by comprising: a first flip-flop having an output of the first counter as an input; a delay unit delaying an output frequency (F VCO ) of the voltage controlled oscillator; and a second A flip-flop takes an output of the first flip-flop as an input, uses an output of the delay unit as a clock signal, and transmits a retimed signal to the phase detector.
另外，所述第一觸發器之特徵是，將所述預定標器之輸出作為時鐘信號，將經所述第一計數器分頻之可編程分頻器之輸出作為輸入信號進行重定時之後，將其輸出至第二觸發器。In addition, the first flip-flop is characterized in that after the output of the prescaler is used as a clock signal, the output of the programmable frequency divider divided by the first counter is used as an input signal for retiming, and then It outputs to the second trigger.
本發明在將經主分頻器分頻之電壓控制振盪器之輸出頻率，與標準頻率進行相位比較之前，對其進行重定時，以去除主分頻器中之抖動，並將去除抖動之信號相位，與標準頻率相位進行比較，從而明顯降低帶內噪聲。The present invention retimes the output frequency of the voltage controlled oscillator divided by the main frequency divider before phase comparison with the standard frequency to remove the jitter in the main frequency divider and remove the jitter signal. Phase, compared to the standard frequency phase, significantly reduces in-band noise.
下面，結合附圖對本發明之具體實施例進行詳細說明。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.
本發明一實施例一種具備用於除去可編程分頻器抖動之重定時部之鎖相環200，如圖2所示，包括：標準分頻器210，提供穩定之標準頻率；相位檢測器220，比較經標準分頻器和主分頻器分頻之輸出頻率相位，輸出脈衝；電荷泵230，按脈衝寬度之比例供應電荷；環路濾波器240，根據所聚積之電荷量變化調整電壓；電壓控制振盪器250，根據經調整之電壓輸出特定頻率；適應頻率校準部260，利用標準分頻器之輸出和主分頻器之輸出，檢測用於控制電壓控制振盪器之頻率；主分頻器270，反饋所述電壓控制振盪器之輸出頻率進行分頻；及重定時部300，重定時經所述主分頻器分頻之電壓控制振盪器之輸出頻率(FVCO )，並將其傳送至所述相位檢測器。An embodiment of the present invention provides a phase locked loop 200 for removing a retiming portion of a programmable frequency divider jitter. As shown in FIG. 2, the method includes a standard frequency divider 210 for providing a stable standard frequency. The phase detector 220 Comparing the output frequency phase divided by the standard frequency divider and the main frequency divider, outputting the pulse; the charge pump 230 supplying the charge according to the ratio of the pulse width; and the loop filter 240 adjusting the voltage according to the accumulated charge amount; The voltage controlled oscillator 250 outputs a specific frequency according to the adjusted voltage; the adaptive frequency calibration unit 260 detects the frequency used to control the voltage controlled oscillator by using the output of the standard frequency divider and the output of the main frequency divider; The controller 270 feeds back the output frequency of the voltage controlled oscillator to perform frequency division; and the retiming unit 300 retimes the output frequency (F VCO ) of the voltage controlled by the main frequency divider to divide the frequency Transfer to the phase detector.
此時，所述標準分頻器210、相位檢測器220、電荷泵230、環路濾波器240、電壓控制振盪器250及適應頻率校準部260，與通常鎖相環中之結構相同，在此不再贅述。下麵，以將經所述主分頻器分頻之輸出頻率傳送至重定時部之可編程分頻器272和重定時部300之結構為中心，說明本發明之構成。At this time, the standard frequency divider 210, the phase detector 220, the charge pump 230, the loop filter 240, the voltage controlled oscillator 250, and the adaptive frequency calibration unit 260 are the same as those in the normal phase locked loop. No longer. Next, the configuration of the present invention will be described focusing on the configuration in which the output frequency divided by the main frequency divider is transmitted to the programmable frequency divider 272 and the retiming unit 300 of the retiming unit.
圖3為本發明可編程分頻器和重定時部之單元結構圖。3 is a block diagram showing the structure of a programmable frequency divider and a retiming section according to the present invention.
如圖3所示，所述主分頻器270，包括：預定標器(Prescaler)271，反饋接收所述電壓控制振盪器之輸出頻率(FVCO )，並根據動態調整之分頻比例(P/P+1)進行分頻；可編程分頻器272，將經所述預定標器分頻之輸出頻率(FVCO )，按分頻比例(1/N) 再次進行分頻；Σ-△調製器(Σ-△ Modulator)273，為分頻比例之調整，向所述可編程分頻器提供分頻數據。As shown in FIG. 3, the main frequency divider 270 includes a prescaler 271 that feedbacks the output frequency (F VCO ) of the voltage controlled oscillator and adjusts the frequency division ratio according to the dynamic adjustment (P). /P+1) is divided; the programmable frequency divider 272 divides the output frequency (F VCO ) divided by the prescaler by a frequency division ratio (1/N); Σ-△ A modulator (Σ-Δ Modulator) 273 is used to adjust the division ratio to provide divided data to the programmable frequency divider.
所述可編程分頻器272，包括：第一計數器(A-Counter)410、第二計數器(B-Counter)420及觸發器(DFF)400，將通過預定標器傳遞之電壓控制振盪器(VCO)250之輸出頻率(FVCO )作為輸入；控制器430，接收所述第一計數器和第二計數器之輸出並通過所述觸發器輸出，以調整所述預定標器之分頻比例。The programmable frequency divider 272 includes: a first counter (A-Counter) 410, a second counter (B-Counter) 420, and a flip-flop (DFF) 400, and a voltage controlled oscillator to be transmitted through the prescaler ( The output frequency of the VCO) 250 (F VCO ) is input; the controller 430 receives the outputs of the first counter and the second counter and outputs through the trigger to adjust the frequency division ratio of the prescaler.
此時，所述預定標器271，對不能用可編程分頻器直接分頻之很高之輸出頻率(FVCO )進行分頻，在可編程分頻器272中進行1/N分頻之前，將按規定分頻比例對所述輸出頻率(FVCO )首先進行分頻。在所述是實例中，較佳地，預定標器271由具備1/P和1/(P+1)之分頻比例之雙模預定標器構成，而將按所述分頻比例分頻之輸出頻率(FVCO )，輸入至第一計數器410和第二計數器420。另外，為同步經分頻之輸出頻率，所述預定標器271之輸出，將輸入至具備於所述可編程分頻器之觸發器(DFF)400和構成重定時部之第一觸發器(DFF1)310之時鐘輸入端子。At this time, the prescaler 271 divides a very high output frequency (F VCO ) that cannot be directly divided by the programmable frequency divider, and performs a 1/N frequency division in the programmable frequency divider 272. The output frequency (F VCO ) is first divided by a prescribed frequency division ratio. In the above example, preferably, the prescaler 271 is composed of a dual mode prescaler having a frequency division ratio of 1/P and 1/(P+1), and is divided by the frequency division ratio. The output frequency (F VCO ) is input to the first counter 410 and the second counter 420. In addition, in order to synchronize the frequency-divided output frequency, the output of the prescaler 271 is input to the flip-flop (DFF) 400 provided in the programmable frequency divider and the first flip-flop constituting the retiming section ( DFF1) 310 clock input terminal.
所述第一計數器(A-Counter)410為可編程計數器，將經所述預定標器按特定分頻比例，例如1/P或1/(P+1)之分頻比例分頻之輸出頻率(FVCO )作為輸入，並按可編程分頻器272之分頻比例(1/N)進行分頻並輸出(現有Nout)。The first counter (A-Counter) 410 is a programmable counter, and the output frequency is divided by the prescaler by a specific frequency division ratio, for example, a division ratio of 1/P or 1/(P+1). (F VCO ) is used as an input and is divided and output (existing Nout) according to the division ratio (1/N) of the programmable frequency divider 272.
另外，所述第二計數器(B-Counter)420為控制預定標器分頻比例之吞脈衝計數器，對一定脈衝進行計數之後，將預定標器之分頻比例調整至1/P和1/(P+1)之間。In addition, the second counter (B-Counter) 420 is a swallow pulse counter that controls the prescaler frequency division ratio. After counting a certain pulse, the division ratio of the prescaler is adjusted to 1/P and 1/( Between P+1).
另外，所述控制器(Control)430利用第一計數器之輸出和第二計數器之輸出，生成將所述預定標器之分頻比例調整至1/P和1/(P+1)之間之控制信號，並將所述控制信號通過具備於所述預定標器之觸發器(DFF)400輸出，加載至預定標器。In addition, the controller (Control) 430 generates an interval between the output of the first counter and the output of the second counter to adjust the frequency division ratio of the prescaler to between 1/P and 1/(P+1). The control signal is output to the prescaler through a flip-flop (DFF) 400 provided at the prescaler.
所述重定時部300，包括：第一觸發器(DFF1)310，將所述第一計數器(A-Counter)410之輸出作為輸入；延遲單元320，延遲所述電壓控制振盪器150之輸出頻率(FVCO )；及第二觸發器330，將所述第一觸發器之輸出作為輸入，將所述延遲單元之輸出作為時鐘信號。The retiming unit 300 includes a first flip-flop (DFF1) 310 that takes an output of the first counter (A-Counter) 410 as an input, and a delay unit 320 that delays an output frequency of the voltage-controlled oscillator 150. (F VCO ); and a second flip-flop 330 that takes the output of the first flip-flop as an input and the output of the delay unit as a clock signal.
此時，所述第一觸發器(DFF1)310，將所述預定標器271之輸出作為時鐘信號，將經所述第一計數器(A-Counter)分頻之可編程分頻器272之輸出作為輸入信號並輸出，從而利用所述預定標器之輸出，重定時所述可編程分頻器之輸出。所述所輸出之第一觸發器(DFF1)310之輸出信號，將輸入至第二觸發器(DFF2)330。At this time, the first flip-flop (DFF1) 310 uses the output of the prescaler 271 as a clock signal to output the programmable frequency divider 272 divided by the first counter (A-Counter). As an input signal and output, the output of the programmable frequency divider is retimed using the output of the prescaler. The output signal of the output first flip-flop (DFF1) 310 is input to the second flip-flop (DFF2) 330.
所述延遲單元(delay cell)320之作用為確保所述第一觸發器之設置或保持時間(setup or hold time)，將從所述電壓控制振盪器(VCO)接收之輸出頻率(FVCO )作為輸入延遲之後，將其傳遞至第二觸發器(DFF2)330。The delay cell 320 functions to ensure a setup or hold time of the first flip-flop, and an output frequency (F VCO ) to be received from the voltage controlled oscillator (VCO). After the input delay, it is passed to the second flip flop (DFF2) 330.
所述第二觸發器(DFF2)330連接至相位檢測器220之一端，將所述第一觸發器310之輸出作為輸入，將經所述延遲單元320延遲之電壓控制振盪器之輸出頻率(FVCO )作為時鐘信號，並將 經重定時之可編程分頻器272之輸出信號(Retiming Nout)，傳送至所述相位檢測器。The second flip-flop (DFF2) 330 is connected to one end of the phase detector 220, takes the output of the first flip-flop 310 as an input, and controls the output frequency of the oscillator by the voltage delayed by the delay unit 320 (F The VCO is transmitted as a clock signal to the phase detector by the output signal (Retiming Nout) of the retimed programmable frequency divider 272.
這樣，利用所述預定標器之輸出，對經可編程分頻器分頻之輸出頻率進行首先之重定時，從而可對加載至相位檢測器之輸出頻率進行整體重定時。因此，在所述相位檢測器中對脈衝進行比較時，防止輸出頻率之脈衝差小而導致的靜態相位誤差(static phase error)或抖動(jitter)增加，或帶內噪聲(Inband noise)增加。Thus, by using the output of the prescaler, the output frequency divided by the programmable frequency divider is first retimed, so that the output frequency loaded to the phase detector can be globally retimed. Therefore, when the pulses are compared in the phase detector, the static phase error or jitter is increased due to the small pulse difference of the output frequency, or the inband noise is increased.
圖4顯示未對可編程分頻器輸出進行重定時之先前帶內相位噪聲(Inband Phase Noise)之檢測結果；圖5顯示對可編程分頻器輸出進行重定時之後之帶內相位噪聲(Inband Phase Noise)之檢測結果。Figure 4 shows the detection of the previous inband phase noise without retiming the programmable divider output; Figure 5 shows the in-band phase noise after the retiming of the programmable divider output (Inband Phase Noise) test results.
從如圖4及圖5所示之圖表可知，未對可編程分頻器輸出進行重定時之情況下(即，圖3之現有Nout)，其帶內相位噪聲約為-70dBc，但根據本發明對所述可編程分頻器輸出進行重定時，去除分頻器輸出之抖動之情況下(即，圖3之Retiming Nout)，其帶內相位噪聲約為-80dBc，通過重定時降低約10dBc，從而改善帶內噪聲性能。As can be seen from the graphs shown in FIGS. 4 and 5, in the case where the programmable frequency divider output is not retimed (ie, the existing Nout of FIG. 3), the in-band phase noise is about -70 dBc, but according to the present example. The invention retimes the programmable frequency divider output to remove the jitter of the frequency divider output (ie, Retiming Nout of FIG. 3), and the in-band phase noise is about -80 dBc, which is reduced by about 10 dBc by retiming. To improve in-band noise performance.
通常，鎖相環100為檢測輸入信號和輸出信號之間之相差，控制電壓控制振盪器(VCO：Voltage Controlled Oscillator)，以維持固定輸出信號頻率之電路，但存在可編程分頻器之輸出所產生之靜態相位誤差(static phase error)及抖動(jitter)或Σ-△調製器(SDM)之噪聲，引起電壓控制振盪器(VCO)帶內噪聲(Inband noise)之問題，但本發明對其進行改善，可應用於各種不同領域。Generally, the phase locked loop 100 is a circuit that detects a phase difference between an input signal and an output signal, and controls a voltage controlled oscillator (VCO: Voltage Controlled Oscillator) to maintain a fixed output signal frequency, but has an output of a programmable frequency divider. Generated static phase error and jitter or sigma-delta modulator (SDM) noise, causing voltage-controlled oscillator (VCO) in-band noise (Inband The problem of noise), but the present invention improves it and can be applied to various fields.
本發明已由所述相關實施例加以描述，然而所述實施例僅為實施本發明之範例。必需指出的是，已揭露之實施例並未限制本發明之範圍。相反地，包含于申請專利範圍之精神及範圍之修改及均等設置均包含於本發明之範圍內。The present invention has been described by the related embodiments, but the embodiments are merely examples for implementing the invention. It must be noted that the disclosed embodiments do not limit the scope of the invention. On the contrary, modifications and equivalents of the spirit and scope of the invention are included in the scope of the invention.
100‧‧‧鎖相環100‧‧‧ phase-locked loop
110‧‧‧標準分頻器110‧‧‧Standard Frequency Divider
120‧‧‧相位檢測器120‧‧‧ phase detector
130‧‧‧電荷泵130‧‧‧Charge pump
140‧‧‧環路濾波器140‧‧‧loop filter
150‧‧‧電壓控制振盪器150‧‧‧Voltage Controlled Oscillator
160‧‧‧適應頻率校準部160‧‧‧Adapted Frequency Calibration Department
170‧‧‧主分頻器170‧‧‧Main divider
161‧‧‧標準分頻器頻率161‧‧‧Standard divider frequency
162‧‧‧主分頻器輸出頻率162‧‧‧Main divider output frequency
163‧‧‧頻率比較器163‧‧‧frequency comparator
164‧‧‧狀態機164‧‧‧ state machine
165‧‧‧泵激電壓監控電路165‧‧‧Pump voltage monitoring circuit
170‧‧‧主分頻器170‧‧‧Main divider
171‧‧‧預定標器171‧‧‧ Prescaler
172‧‧‧可編程分頻器172‧‧‧Programmable Divider
173‧‧‧Σ-△調製器173‧‧‧Σ-Δ modulator
200‧‧‧鎖相環200‧‧‧ phase-locked loop
210‧‧‧標準分頻器210‧‧‧Standard Divider
220‧‧‧相位檢測器220‧‧‧ phase detector
230‧‧‧電荷泵230‧‧‧Charge pump
240‧‧‧環路濾波器240‧‧‧loop filter
250‧‧‧電壓控制振盪器250‧‧‧Voltage Controlled Oscillator
260‧‧‧適應頻率校準部260‧‧‧Adapted Frequency Calibration Department
270‧‧‧主分頻器270‧‧‧main divider
271‧‧‧預定標器271‧‧‧ Prescaler
272‧‧‧可編程分頻器272‧‧‧Programmable Divider
270‧‧‧Σ-△調製器270‧‧‧Σ-Δ modulator
300‧‧‧重定時部300‧‧‧Retimer Department
310‧‧‧第一觸發器310‧‧‧First trigger
320‧‧‧延遲單元320‧‧‧Delay unit
330‧‧‧第二觸發器330‧‧‧second trigger
410‧‧‧第一計數器410‧‧‧First counter
420‧‧‧第二計數器420‧‧‧second counter
430‧‧‧控制器430‧‧‧ Controller
圖1為先前鎖相環結構圖；圖2為本發明具備用於除去可編程分頻器抖動之重定時部之鎖相環結構圖；圖3為本發明重定時部詳細結構圖；圖4為先前鎖相環之帶內噪聲檢測結果波形圖；圖5為根據本發明重定時之鎖相環之帶內噪聲檢測結果波形圖。1 is a structural diagram of a prior phase-locked loop; FIG. 2 is a structural diagram of a phase-locked loop provided with a retiming section for removing jitter of a programmable frequency divider; FIG. 3 is a detailed structural diagram of a retiming section of the present invention; The waveform of the in-band noise detection result of the previous phase-locked loop; FIG. 5 is a waveform diagram of the in-band noise detection result of the phase-locked loop of the retiming according to the present invention.
200‧‧‧鎖相環200‧‧‧ phase-locked loop
210‧‧‧標準分頻器210‧‧‧Standard Divider
220‧‧‧相位檢測器220‧‧‧ phase detector
230‧‧‧電荷泵230‧‧‧Charge pump
240‧‧‧環路濾波器240‧‧‧loop filter
250‧‧‧電壓控制振盪器250‧‧‧Voltage Controlled Oscillator
260‧‧‧適應頻率校準部260‧‧‧Adapted Frequency Calibration Department
270‧‧‧主分頻器270‧‧‧main divider
271‧‧‧預定標器271‧‧‧ Prescaler
272‧‧‧可編程分頻器272‧‧‧Programmable Divider
270‧‧‧Σ-△調製器270‧‧‧Σ-Δ modulator
300‧‧‧重定時部300‧‧‧Retimer Department
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| US20030102928A1 (en) * | 2001-12-03 | 2003-06-05 | D'haene Wesley Calvin | Non-linear phase detector |
| TW200604550A (en) * | 2004-07-29 | 2006-02-01 | Jaeger Ind Co Ltd | Position estimation and control device with high resolution |
| US7315189B2 (en) * | 2004-06-29 | 2008-01-01 | Marvell International, Ltd. | Retiming circuits for phase-locked loops |
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| US20030102928A1 (en) * | 2001-12-03 | 2003-06-05 | D'haene Wesley Calvin | Non-linear phase detector |
| US7315189B2 (en) * | 2004-06-29 | 2008-01-01 | Marvell International, Ltd. | Retiming circuits for phase-locked loops |
| TW200604550A (en) * | 2004-07-29 | 2006-02-01 | Jaeger Ind Co Ltd | Position estimation and control device with high resolution |
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