TWI490862B

TWI490862B - Memory architecture of 3d array with improved uniformity of bit line capacitances

Info

Publication number: TWI490862B
Application number: TW100136822A
Authority: TW
Inventors: Chun Hsiung Hung; Hang Ting Lue; Shih Hung Chen
Original assignee: Macronix Int Co Ltd
Priority date: 2011-01-19
Filing date: 2011-10-11
Publication date: 2015-07-01
Also published as: CN102709269A; TW201232548A; CN102709269B

Description

改良位元線電容單一性之3D陣列記憶體結構Improved bit line capacitance singleness 3D array memory structure

本發明為高密度記憶體裝置，且特別是一種記憶體裝置，其中多個記憶體單元的多平面被用以提供一3D陣列。The present invention is a high density memory device, and more particularly a memory device in which multiple planes of a plurality of memory cells are used to provide a 3D array.

隨著積體電路中的裝置關鍵尺寸縮小至一般記憶體單元技術的極限，設計者一直在尋找堆疊多個記憶體單元平面的技術來達成更大的儲存容量以及更低的位元單位成本。例如，Lai等人在2006年12月11-13號於電機與電子學工程會國際電子裝置會議所發表之「多層可堆疊薄膜電晶體NAND型快閃記憶體」("A Multi-Layer Stackable Thin-Film Transistor(TFT)NAND-Type Flash Memory,”IEEE Int’l Electron Devices Meeting,11-13 Dec. 2006)；以及Jung等人在2006年12月11-13號於電機與電子學工程會國際電子裝置會議所發表之「將ILD及TANOS結構上堆疊單晶矽層用於超過30奈米範圍之節點的3D堆疊NAND快閃記憶體技術」(”Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node”,IEEE Int’l Electron Devices Meeting,11-13 Dec. 2006)，將薄膜電晶體技術應用至電荷設陷(charge trapping)記憶體技術。As device critical dimensions in integrated circuits shrink to the limits of general memory cell technology, designers have been looking for techniques to stack multiple memory cell planes to achieve greater storage capacity and lower bit unit cost. For example, Lai et al., "Multi-Layer Stackable Thin Film NAND Flash Memory", "A Multi-Layer Stackable Thin", December 11-13, 2006, at the International Electron Devices Conference of the Electrical and Electronics Engineering Society. -Film Transistor (TFT) NAND-Type Flash Memory, "IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006); and Jung et al., December 11-13, 2006, at the Electrical and Electronics Engineering Society International "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal", "Electrical Devices Conference, "3D Stacked NAND Flash Memory Technology for Stacking Single Crystal Layers on ILD and TANOS Structures at Nodes Beyond 30 nm" Si Layers on ILD and TANOS Structure for Beyond 30 nm Node", IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006), applying thin film transistor technology to charge trapping memory technology.

並且，Johnson等人在2003年11月於電機與電子學工程會固態電路期刊第38冊第11號發表之「具3D二極體/反熔絲(anti-fuse)記憶體單元陣列的512-Mb PROM」("512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory Cells”IEEE J. of Solid-State Circuits,vol. 38,no. 11,Nov. 2003)，已將交叉點陣列技術應用於反熔絲記憶體。在Johnson等人所描述的設計中，提供了多個字元線與位元線的層，其在交叉點具有記憶體元件。記憶體元件包括了連接至字元線的P+型多晶矽陽極以及連接至位元線的N型多晶矽陰極，其中陽極與陰極是用反熔絲材料來分離。And, in November 2003, Johnson et al., 512-3D with a 3D diode/anti-fuse memory cell array, published in the No. 11 of the Journal of the Solid State Circuits, Electrical and Electronic Engineering Society, November. Mb PROM" ("512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory Cells" IEEE J. of Solid-State Circuits, vol. 38, no. 11, Nov. 2003), has been the intersection Array technology is applied to anti-fuse memory. In the design described by Johnson et al., a plurality of layers of word lines and bit lines are provided that have memory elements at the intersections. The memory component includes a P+ type polycrystalline germanium anode connected to the word line and an N-type polycrystalline germanium cathode connected to the bit line, wherein the anode and the cathode are separated by an antifuse material.

在Lai等人、Jung等人以及Johnson等人所描述的製程中，對於每個記憶體層有數個關鍵的平版印刷(lithography)步驟。因此，製造裝置所需的關鍵平版印刷步驟之數量與所實施的層之數量成正比。所以，雖然使用3D陣列能達成較高密度的好處，但較高的製造成本卻限制了該技術的使用。In the process described by Lai et al, Jung et al. and Johnson et al., there are several critical lithography steps for each memory layer. Therefore, the number of critical lithographic steps required to fabricate the device is directly proportional to the number of layers implemented. Therefore, although the use of 3D arrays can achieve higher density benefits, higher manufacturing costs limit the use of the technology.

另一個提供電荷設陷記憶體技術中垂直NAND單元的結構是敘述於Tanaka等人在2007年6月12-14號於2007 VLSI技術文摘座談會技術文件第14-15頁所發表之「超高密度快閃記憶體具穿孔與插栓製程的位元成本可調節技術」(”Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”,2007 Symposium on VLSI Technology Digest of Technical Papers;12-14 June 2007,pages:14-15)。Tanaka等人所敘述的結構包括了具有像NAND閘一般運作的垂直通道之多閘極場效電晶體結構，使用了矽氧氮氧矽(silicon-oxide-nitride-oxide-silicon,SONOS)電荷設陷技術來在每個閘/垂直通道介面創造儲存場所。該記憶體結構係為了多閘極單元而基於一柱如垂直通道設置的半導體材料，其中較下面的選擇閘極與基板相鄰，而較上面的選擇閘極則在頂端上。複數個水平控制閘極使用與柱交叉的平面電極層而形成。用作控制閘極的平面電極層不需關鍵平版印刷，而因此節省了成本。然而，對於每一個垂直單元仍然需要許多關鍵的平版印刷步驟。並且，可用這種方法堆積成層的控制閘極之數量有限制，其決定於例如垂直通道的導電性以及所使用的編程(program)及抹除(erase)程序等等因素。Another structure for providing vertical NAND cells in charge trapping memory technology is described in Tanaka et al., June 12-14, 2007, on the 14th-15th of the 2007 VLSI Technical Digest Symposium Technical Paper. "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory", 2007 Symposium on VLSI Technology Digest of Technical Papers; 12- 14 June 2007, pages: 14-15). The structure described by Tanaka et al. includes a multi-gate field-effect transistor structure with a vertical channel that operates like a NAND gate, using a silicon-oxide-nitride-oxide-silicon (SONOS) charge design. Technology is used to create storage locations in each gate/vertical channel interface. The memory structure is a semiconductor material disposed on a column, such as a vertical channel, for multiple gate cells, wherein the lower select gate is adjacent to the substrate and the upper select gate is on the top. A plurality of horizontal control gates are formed using a planar electrode layer that intersects the pillars. The planar electrode layer used as a control gate does not require critical lithography, thus saving costs. However, many critical lithographic steps are still required for each vertical unit. Moreover, the number of control gates stacked in layers can be limited by such methods, depending, for example, on the conductivity of the vertical channels and the programming and erase procedures used.

3D芬格垂直閘極NAND(3D Finger VG(vertical gate)NAND)是一種高密度3D可堆疊NAND快閃體系結構。然而，該結構對於陣列的不同位置而言並不對稱，例如陣列的不同平面位置。分別耦接至陣列中不同區塊相同平面位置的位元線，具有不同的位元線電容(bit line capacitance,CBL)。這些不同位元線的不同位元線電容造成了感應儲存於記憶體單元中數值的困難性。3D Finger VG (vertical gate) NAND is a high density 3D stackable NAND flash architecture. However, the structure is asymmetrical for different locations of the array, such as different planar locations of the array. Bit lines respectively coupled to the same planar position of different blocks in the array have different bit line capacitances (CBL). The different bit line capacitances of these different bit lines create difficulties in sensing the values stored in the memory cells.

因此，所提供的3D積體電路記憶體結構最好能具低製造成本，並包括可靠的及非常小的記憶體元件，以及改善的製程視窗(process window)，其中製程視窗指的是與具有閘極結構之記憶體單元串列的相鄰堆疊聯合的製程視窗。Therefore, the provided 3D integrated circuit memory structure preferably has a low manufacturing cost, and includes reliable and very small memory components, and an improved process window, wherein the process window refers to and has A process window in which adjacent stacks of memory cell strings of a gate structure are combined.

多種實施例提供3D記憶體陣列如3D芬格垂直閘極NAND(3D Finger VG(vertical gate)NAND)。Various embodiments provide a 3D memory array such as 3D Finger VG (vertical gate NAND).

多種實施例將位元線耦接於3D記憶體陣列中不同層的序列做變換。舉例來說，在位元線貫穿多個相異記憶體區塊的配置中，位元線在不同記憶體區塊中具有不同序列，這些不同的序列將位元線耦接至3D記憶體陣列中的不同層(of coupling to the different layers of the 3D memory array是修飾誰？)。因為在陣列中不同的平面位置具有不同的電容，而在位元線貫穿多個不同記憶體區塊的配置中，又因在單一區塊中介於不同層之間的電容差異會橫越不同區塊被反覆加總，所以每條耦接陣列中不同區塊的相同平面位置之位元線將具有相異於其他位元線的位元線電容(bit line capacitances,CBL)。不同的序列將不同區塊的不同平面位置耦接於位元線，而該些不同的序列會橫越不同區塊把隨不同平面位置而變化之電容間的差異平均掉。這樣的平均能確保不同位元線的位元線電容一致，促進了從位元線對於儲存於記憶體單元中數值的感應。相對地，在實施例中，每條位元線(例如像位於金屬層3的一金屬位元線)皆具有與其他位元線一致的平均電容(CBL)。Various embodiments convert the bit lines to sequences of different layers in the 3D memory array for transformation. For example, in a configuration in which a bit line runs through a plurality of distinct memory blocks, the bit lines have different sequences in different memory blocks that couple the bit lines to the 3D memory array. The different layers (of coupling to the different layers of the 3D memory array are modified?). Because different plane positions in the array have different capacitances, and in the configuration of bit lines running through multiple different memory blocks, the difference in capacitance between different layers in a single block will traverse different regions. The blocks are summed up in turn, so the bit lines of the same planar position of different blocks in each coupled array will have bit line capacitances (CBL) that are different from the other bit lines. Different sequences couple different plane positions of different blocks to bit lines, and the different sequences traverse different blocks to average the difference between capacitances that vary with different planar positions. Such an average ensures that the bit line capacitances of the different bit lines are uniform, facilitating the sensing of the values from the bit lines for storage in the memory cells. In contrast, in an embodiment, each bit line (eg, like a metal bit line located in metal layer 3) has an average capacitance (CBL) that is consistent with other bit lines.

根據本發明的第一方面，係關於一記憶體裝置，包括一基板、複數個半導體材料帶堆疊、複數條字元線、複數個記憶體元件以及複數個位元線結構。According to a first aspect of the invention, a memory device includes a substrate, a plurality of semiconductor material strip stacks, a plurality of word lines, a plurality of memory elements, and a plurality of bit line structures.

該些半導體材料帶堆疊係位於該基板之上。該些半導體材料帶堆疊係為脊形，且包括至少兩半導體材料帶，該些半導體材料帶係以絕緣材料分隔於複數個平面位置。The strips of semiconductor material are stacked on top of the substrate. The strips of semiconductor material are ridged and comprise at least two strips of semiconductor material separated by an insulating material in a plurality of planar locations.

該些字元線係跨越該些堆疊而設置，且具有與該些堆疊共形(conformal)之表面。The word lines are disposed across the stacks and have a conformal surface with the stacks.

位於介面區域中之記憶體裝置係透過該些半導體材料帶與該些字元線建立一記憶體單元之3D陣列。The memory device located in the interface region establishes a 3D array of memory cells through the strips of semiconductor material and the word lines.

該些位元線結構係位於該些堆疊之末端，該些位元線結構係將該些平面位置耦接於複數條位元線。The bit line structures are located at the ends of the stacks, and the bit line structures are coupled to the plurality of bit lines.

該些位元線的每條位元線係耦接至該些平面位置的至少兩相異平面位置。Each of the bit lines of the bit lines is coupled to at least two different planar positions of the planar positions.

於一實施例中，該些位元線的每條位元線係耦接至該些半導體材料帶堆疊中相異堆疊的至少兩相異平面位置。該至少兩相異平面位置係包括一第一半導體帶堆疊之一第一平面位置以及一第二半導體帶堆疊之一第二平面位置，使得該第一半導體帶堆疊以及該第二半導體帶堆疊係為相異記憶體區塊。In one embodiment, each of the bit lines is coupled to at least two different planar positions of the different stacks of the semiconductor material strip stacks. The at least two-phase different planar position includes a first planar position of a first semiconductor strip stack and a second planar position of a second semiconductor strip stack such that the first semiconductor strip stack and the second semiconductor strip stack It is a block of different memory.

於一實施例中，該些位元線的每條位元線係耦接至該些半導體材料帶堆疊中相異堆疊的至少兩相異平面位置。該至少兩相異平面位置係包括一第一半導體帶堆疊之一第一平面位置以及一第二半導體帶堆疊之一第二平面位置，使得該第一半導體帶堆疊以及該第二半導體帶堆疊得以被該些字元線之相異組字元線所存取。In one embodiment, each of the bit lines is coupled to at least two different planar positions of the different stacks of the semiconductor material strip stacks. The at least two-phase different planar position includes a first planar position of a first semiconductor strip stack and a second planar position of a second semiconductor strip stack such that the first semiconductor strip stack and the second semiconductor strip stack are Accessed by distinct group of character lines of the word lines.

於一實施例中，該些記憶體單元係在NAND串列中沿該些半導體材料帶而設置。In one embodiment, the memory cells are disposed along the strips of semiconductor material in the NAND string.

於一實施例中，該些記憶體單元係沿該些位元線結構以及複數個來源線(source line)結構之間的該些半導體材料帶而設置。In one embodiment, the memory cells are disposed along the bit line structures and the plurality of semiconductor material strips between the plurality of source line structures.

於一實施例中，相異的電容係描繪了該些平面位置之相異平面位置的特徵。In one embodiment, the distinct capacitances characterize the different planar positions of the planar locations.

於一實施例中，該些堆疊係以該些位元線結構分隔為複數個記憶體區塊。In one embodiment, the stacks are separated into a plurality of memory blocks by the bit line structures.

於一實施例中，該些半導體材料帶堆疊之一特定半導體帶以及該些字元線之一條特定字元線的組合選擇，用以識別該記憶體單元3D陣列之一特定記憶體單元。In one embodiment, the semiconductor material strips are stacked with a particular semiconductor strip and a combination of a particular word line of the word lines to identify a particular memory cell of the memory cell 3D array.

於一實施例中，該些記憶體裝置係包括電荷設陷(charge-trapping)結構，該些電荷設陷結構係包括一穿隧層(tunneling layer)、一電荷設陷層以及一阻擋層(blocking layer)。In one embodiment, the memory devices comprise charge-trapping structures, the charge trapping structures comprising a tunneling layer, a charge trapping layer, and a barrier layer ( Blocking layer).

於本發明的另一方面，係關於一記憶體裝置，包括一基板、複數個半導體材料帶堆疊、複數條字元線、複數個記憶體元件以及複數個位元線結構。In another aspect of the invention, a memory device includes a substrate, a plurality of semiconductor material strip stacks, a plurality of word lines, a plurality of memory elements, and a plurality of bit line structures.

該些半導體材料帶堆疊係位於該基板之上。該些堆疊係為脊形，且包括至少兩半導體材料帶，該些半導體材料帶係以絕緣材料分隔於複數個平面位置。The strips of semiconductor material are stacked on top of the substrate. The stacks are ridged and include at least two strips of semiconductor material separated by an insulating material in a plurality of planar locations.

該些字元線係跨越該些堆疊而設置，且具有與該些堆疊共形之平面。The word lines are disposed across the stacks and have planes that are conformal to the stacks.

位於該些介面區域之記憶體裝置，係透過該些半導體材料帶與該些字元線建立一記憶體單元之3D陣列。The memory device located in the interface areas establishes a 3D array of memory cells through the strips of semiconductor material and the word lines.

該些位元線結構係位於該些堆疊之末端。該些位元線結構係將該些平面位置耦接至複數條位元線。該些位元線結構係具有該些平面位置的複數個序列中至少兩相異序列。每個該些序列描繪了該些位元線結構之一位元線結構耦接至該些位元線的該些平面位置的順序特徵。The bit line structures are located at the ends of the stacks. The bit line structures couple the planar locations to a plurality of bit lines. The bit line structures have at least two distinct sequences of the plurality of sequences of the planar positions. Each of the sequences depicts sequential features of the bit line structures of the bit line structures coupled to the planar locations of the bit lines.

於一實施例中，該些記憶體單元係在該些位元線結構與複數個來源線結構之間沿該些半導體材料帶而設置。In one embodiment, the memory cells are disposed along the strips of semiconductor material between the bit line structures and the plurality of source lines.

於一實施例中，該些位元線結構的該些序列之該些相異序列，係平均了描繪耦接於該些位元線的該些平面位置之相異平面位置特徵的該些相異電容。In an embodiment, the different sequences of the sequences of the bit line structures average the phases of the dissimilar planar position features of the planar positions coupled to the bit lines. Different capacitance.

於一實施例中，該位元線結構與該些位元線的該些平面位置耦接的順序，係從該位元線結構之一第一末端橫跨對應至該位元線結構之一第二末端。In one embodiment, the order in which the bit line structure is coupled to the planar positions of the bit lines is from one of the first ends of the bit line structure to one of the bit line structures. The second end.

於一實施例中，該些堆疊係以該些位元結構分隔為複數個記憶體區塊。In an embodiment, the stacks are separated into a plurality of memory blocks by the bit structures.

於一實施例中，該些記憶體裝置係包括電荷設陷結構，該些電荷設陷結構係包括一穿隧層、一電荷設陷層以及一阻擋層。In one embodiment, the memory devices include a charge trapping structure, the charge trapping structures including a tunneling layer, a charge trapping layer, and a barrier layer.

根據本發明的一方面，係關於一記憶體裝置，包括：一3D積體電路記憶體陣列，係具有位於複數個平面位置的複數記憶體單元；複數個位元線結構，係具有複數個平面位置的複數個序列，該些序列至少包括兩相異序列，每個該些序列係描繪了該些位元線結構之一位元線結構耦接至複數條位元線的該些平面位置之順序特徵。According to an aspect of the invention, a memory device includes: a 3D integrated circuit memory array having a plurality of memory cells at a plurality of planar positions; and a plurality of bit line structures having a plurality of planes a plurality of sequences of positions, the sequences comprising at least two distinct sequences, each of the sequences depicting a bit line structure of the bit line structures coupled to the planar positions of the plurality of bit lines Sequential features.

於一實施例中，該陣列的該些記憶體單元係在NAND串列中沿該些半導體材料帶而設置。In one embodiment, the memory cells of the array are disposed along the strips of semiconductor material in a NAND string.

於一實施例中，該陣列的該些記憶體單元係沿該些位元線結構與複數個來源線結構之間的該些半導體材料帶而設置。In one embodiment, the memory cells of the array are disposed along the plurality of semiconductor material strips between the bit line structures and the plurality of source lines.

於一實施例中，相異的電容係描繪了該些平面位置的相異平面位置之特徵。In one embodiment, the distinct capacitances characterize the distinct planar locations of the planar locations.

於一實施例中，該些位元線結構的該些序列之該些相異序列，係平均了描繪該些平面位置之相異平面位置特徵的該些相異電容。In an embodiment, the different sequences of the sequences of the bit line structures average the different capacitances depicting the different planar position features of the planar positions.

於一實施例中，該陣列係以該些位元結構分隔為複數個記憶體區塊。In one embodiment, the array is separated into a plurality of memory blocks by the bit structures.

於一實施例中，該陣列中的該些半導體材料帶堆疊之一特定半導體帶以及該陣列中的該些字元線之一條特定字元線的組合選擇，用以識別該陣列中之一特定記憶體單元。In one embodiment, a combination of one of the plurality of semiconductor material strips in the array and a particular one of the plurality of word lines in the array is selected to identify a particular one of the arrays. Memory unit.

於一實施例中，該陣列的該些記憶體元件係包括電荷設陷結構，該些電荷設陷結構係包括一穿隧層、一電荷設陷層以及一阻擋層。In one embodiment, the memory elements of the array comprise a charge trapping structure, the charge trapping structures comprising a tunneling layer, a charge trapping layer, and a barrier layer.

根據本發明的一方面，係關於一記憶體裝置，包括：一3D積體電路記憶體陣列，係具有位於複數個平面位置中的複數記憶體單元；複數條位元線，每條該些位元線係耦接該些相異平面位置的至少兩相異平面位置，並且於上述至少兩相異平面位置存取該些記憶體單元。According to an aspect of the invention, a memory device includes: a 3D integrated circuit memory array having a plurality of memory cells in a plurality of planar positions; a plurality of bit lines, each of the bits The line system is coupled to at least two different planar positions of the different planar positions, and the memory units are accessed at the at least two different planar positions.

於一實施例中，該陣列係以複數個位元線結構分隔為複數個記憶體區塊。In one embodiment, the array is separated into a plurality of memory blocks by a plurality of bit line structures.

多種實施例具有多種堆疊層編號。舉例來說，對於一八層垂直閘，表示位元線(bit line,BL)耦接至記憶體區塊不同層的順序之序列BL(1)、BL(2)、BL(3)、BL(4)、BL(5)、BL(6)、BL(7)、BL(8)可在不同區塊中被變換，使得每條位元線的位元線電容被平均。這樣可使每條金屬位元線的電容差異最小化，來獲得穩定的感應邊限(sensing margin)。Various embodiments have multiple stacked layer numbers. For example, for an eight-layer vertical gate, the sequence of bit lines (BL) coupled to different layers of the memory block is sequenced BL(1), BL(2), BL(3), BL. (4), BL(5), BL(6), BL(7), BL(8) can be transformed in different blocks such that the bit line capacitance of each bit line is averaged. This minimizes the difference in capacitance of each metal bit line to achieve a stable sensing margin.

關於本發明的其他方面及其優點，可參照於下列之圖式、實施方式以及專利申請範圍。With regard to other aspects of the invention and its advantages, reference is made to the following figures, embodiments, and patent applications.

以下將提供參照附圖的實施例詳細說明。A detailed description of embodiments with reference to the accompanying drawings will be provided below.

圖1為一3D可編程電阻記憶體陣列2x2部分的透視圖，其中填充材料從圖式中被移除，如此方能顯示組成3D陣列的半導體帶堆疊以及垂直字元線。在這張圖式中，僅顯示兩個平面。然而，平面的數量可以擴展到非常大。如圖1所示，記憶體陣列被製造於一具有絕緣層10(insulating layer)的積體電路基板上，其中絕緣層10以半導體或其他結構為基礎(未繪示)。記憶體陣列包括以絕緣材料21、22、23及24分離半導體帶11、12、13及14的複數個堆疊。該些堆疊為延伸於Y軸的脊形，如圖所示，如此半導體帶11-14可被配置為記憶體單元串列。半導體帶11及13可用作第一記憶體平面中的記憶體單元串列。半導體帶12及14可用作第二記憶體平面中的記憶體單元串列。記憶體材料層15，例如為反熔絲材料，在本例中反熔絲材料塗覆於複數個半導體帶堆疊上，而在其他例子中至少塗覆於半導體帶的側壁。複數條字元線16及17垂直跨越複數個半導體帶堆疊而設置。字元線16及17具有與複數個半導體帶堆疊共形的表面，填補了複數個堆疊之邊緣所形成的溝槽(也就是圖中的20)，且使介於堆疊上半導體帶11-14側面以及字元線16及17側面之間交叉點的介面區域之多層陣列成形。矽化物18及19(也就是矽化鎢、矽化鈷、矽化鈦)的層可形成於字元線16及17的頂面上。1 is a perspective view of a portion of a 3D programmable resistive memory array 2x2 in which fill material is removed from the pattern to display a stack of semiconductor strips and vertical word lines that make up the 3D array. In this illustration, only two planes are shown. However, the number of planes can be extended to very large. As shown in FIG. 1, a memory array is fabricated on an integrated circuit substrate having an insulating layer 10, which is based on a semiconductor or other structure (not shown). The memory array includes a plurality of stacks separating the semiconductor strips 11, 12, 13, and 14 with insulating materials 21, 22, 23, and 24. The stacks are ridges extending from the Y-axis, as shown, such that the semiconductor strips 11-14 can be configured as a series of memory cells. The semiconductor strips 11 and 13 can be used as a memory cell string in the first memory plane. Semiconductor strips 12 and 14 can be used as a string of memory cells in the second memory plane. The memory material layer 15, for example, is an anti-fuse material, in this case the anti-fuse material is applied to a plurality of semiconductor strip stacks, and in other examples at least to the sidewalls of the semiconductor strip. A plurality of word line lines 16 and 17 are vertically disposed across a plurality of semiconductor strip stacks. The word lines 16 and 17 have a surface conformal to the plurality of semiconductor strip stacks, filling the trenches formed by the edges of the plurality of stacks (ie, 20 in the figure), and placing the semiconductor strips 11-14 on the stack A multilayer array of side regions and interface regions of intersections between the sides of word lines 16 and 17 are formed. Layers of Tellurides 18 and 19 (i.e., tungsten telluride, cobalt telluride, titanium telluride) may be formed on the top surfaces of word lines 16 and 17.

記憶體材料層15可由反熔絲材料，例如二氧化矽、氮氧化矽或其他矽的氧化物所構成；舉例來說記憶體材料層15的厚度約為1至5奈米。記憶體材料層15也可使用其他反熔絲材料，例如氮化矽。半導體帶11-14可為第一導電類型(也就是P型)的半導體材料。字元線16及17可為第二導電類型(也就是N型)的半導體材料。舉例來說，半導體帶11-14可使用P型多晶矽製造，反之字元線16及17則可使用相對應的重摻雜N+型多晶矽(heavily doped n+-type polysilicon)製造。半導體帶的寬度應提供耗盡層(depletion region)足夠的空間以支持二極體運作。因此，包括以可編程反熔絲層P-N接面(P-N junction)形成之整流器的記憶體單元，係形成於多晶矽帶及線之間的交叉點之3D陣列中。其中可編程反熔絲層係位於陽極與陰極之間。(這是英文的句型結構，中文比較不適合這樣子寫)在其他實施例中，可使用不同的可編程電阻記憶體材料，包括像鎢上的氧化鎢或者摻雜金屬氧化物半導體帶之類的過渡金屬氧化物(transition metal oxide)。這些材料可被編程及抹除，且可被實施於每單元儲存多個位元的作業。The memory material layer 15 may be comprised of an antifuse material, such as cerium oxide, cerium oxynitride or other cerium oxide; for example, the memory material layer 15 has a thickness of about 1 to 5 nanometers. Other antifuse materials, such as tantalum nitride, may also be used for the memory material layer 15. The semiconductor strips 11-14 may be semiconductor materials of a first conductivity type (ie, P-type). Word lines 16 and 17 can be semiconductor materials of the second conductivity type (i.e., N-type). For example, the semiconductor strips 11-14 can be fabricated using P-type polysilicon, whereas the word lines 16 and 17 can be fabricated using the corresponding heavily doped n+-type polysilicon. The width of the semiconductor strip should provide sufficient space in the depletion region to support diode operation. Thus, a memory cell comprising a rectifier formed with a programmable anti-fuse layer P-N junction is formed in a 3D array of intersections between polysilicon ribbons and lines. The programmable anti-fuse layer is between the anode and the cathode. (This is an English sentence structure, which is not suitable for Chinese writing.) In other embodiments, different programmable resistive memory materials can be used, including tungsten oxide on tungsten or doped metal oxide semiconductor strips. Transition metal oxide. These materials can be programmed and erased and can be implemented in jobs that store multiple bits per cell.

圖2顯示了從形成於字元線16及半導體帶14交叉區的記憶體單元之X-Z平面所截取的截面圖。主動區25及26係形成於介於字元線16及帶14之間的兩個邊上。於自然狀態下，反熔絲材料層15具有高電阻。而在編程之後，反熔絲材料分解，致使反熔絲材料中的主動區25及26(active region)兩者或其中之一呈現低電阻狀態。於此描述的實施例中，每個記憶體單元具有兩個主動層25及26，各位於半導體帶14的各個邊緣。圖3顯示形成於字元線16及半導體帶14交叉區的記憶體單元之X-Y平面截面圖。圖3也繪示了從標明為字元線16的字元線通過反熔絲材料層15而達半導體帶14的電流路徑。2 shows a cross-sectional view taken from the X-Z plane of the memory cell formed in the intersection of the word line 16 and the semiconductor strip 14. Active regions 25 and 26 are formed on two sides between word line 16 and strip 14. In the natural state, the antifuse material layer 15 has a high electrical resistance. After programming, the antifuse material decomposes, causing either or both of the active regions 25 and 26 in the antifuse material to exhibit a low resistance state. In the embodiment described herein, each memory cell has two active layers 25 and 26, each located at each edge of the semiconductor strip 14. 3 shows a cross-sectional view of the memory cell formed in the intersection of the word line 16 and the semiconductor strip 14 in an X-Y plane. 3 also illustrates the current path from the word line labeled as word line 16 through the antifuse material layer 15 to the semiconductor strip 14.

如圖3中以實箭頭繪示的電子流，從N+型字元線16流入P型半導體帶，然後沿半導體帶(--箭頭)流至感應放大器(sense amplifier)，於其中該電子流可被量測，以指出選定記憶體單元的狀態。在將約1奈米厚二氧化矽層用作反熔絲材料的典型實施例中(形容詞太長，這樣子讓人獨得很辛苦；試著把這個主詞的補語當成一個句子來講)，編程脈衝係在一晶片上控制電路之控制下運用。其中該編程脈衝可包括具有約1毫秒脈衝寬度的5至7伏特脈衝，而該晶片上控制電路則描述於以下參照於第18圖的部分。讀取脈衝係在一晶片上控制電路之控制下運用。其中該讀取脈衝可包括1至2伏特脈衝，至於脈衝寬度則取決於其配置。該晶片上控制電路係描述於以下參照於第18圖的部分。讀取脈衝可能遠短於編程脈衝。The electron flow, as shown by the solid arrow in FIG. 3, flows from the N+ type word line 16 into the P-type semiconductor strip, and then flows along the semiconductor strip (--arrow) to a sense amplifier, where the electron current can It is measured to indicate the state of the selected memory unit. In a typical embodiment where a layer of about 1 nm thick ruthenium dioxide is used as an antifuse material (the adjective is too long, so that it is very hard to be alone; try to treat the complement of the subject as a sentence), The programming pulse is applied under the control of a control circuit on a wafer. Wherein the programming pulse can include a 5 to 7 volt pulse having a pulse width of about 1 millisecond, and the on-wafer control circuit is described below with reference to the portion of FIG. The read pulse is applied under the control of a control circuit on a wafer. Wherein the read pulse can comprise a pulse of 1 to 2 volts, as the pulse width depends on its configuration. The on-wafer control circuit is described below with reference to the portion of Fig. 18. The read pulse may be much shorter than the programming pulse.

圖4為顯示記憶體單元的2平面概要圖，每個平面具有6個單元。記憶體單元以帶有虛線的二極體符號代表，該虛線代表了介於陽極與陰極之間的反熔絲材料層。位於字元線60及61與半導體帶51及52的第一堆疊、半導體帶53、54的第二堆疊以及半導體帶55及56的第三堆疊之交叉點使兩個平面的記憶體單元成形，其中字元線60及61作為第一字元線(word line,WL)WLn及第二字元線WLn+1，而第一至第三堆疊則在第一層及第二層陣列中，作為記憶單元串列n、n+1及n+2。記憶體單元的第一平面包括了半導體帶52上的記憶體單元30及31、半導體帶54上的記憶體單元32及33以及半導體帶56上的記憶體單元34及35。記憶體單元的第二平面包括了半導體帶51上的記憶體單元40及41、半導體帶53上的記憶體單元42及43以及半導體帶55上的記憶體單元44及45。如圖所示，作為字元線WLn的字元線60，包括垂直延長部分60-1、60-2及60-3，其對應介於堆疊之間而位於如圖1所示的溝槽20中之材料，該些延伸部分乃是為了將字元線60沿所繪示各平面中的3個材料帶耦接於記憶體單元。具有許多層的陣列可如於此所描述的來實施，使得非常高密度記憶體的方法成為可能，或者達到每晶片萬億位元(terabits per chip)。Fig. 4 is a schematic diagram showing a 2-plane of a memory unit, each having 6 cells. The memory cell is represented by a diode symbol with a dashed line representing the layer of antifuse material between the anode and the cathode. The intersection of the word lines 60 and 61 with the first stack of semiconductor strips 51 and 52, the second stack of semiconductor strips 53, 54 and the third stack of semiconductor strips 55 and 56 shape the two planar memory cells, The word lines 60 and 61 are used as the first word line (WL) WLn and the second word line WLn+1, and the first to third stacks are in the first layer and the second layer array. The memory cells are serially n, n+1, and n+2. The first plane of the memory cell includes memory cells 30 and 31 on semiconductor strip 52, memory cells 32 and 33 on semiconductor strip 54, and memory cells 34 and 35 on semiconductor strip 56. The second plane of the memory cell includes memory cells 40 and 41 on the semiconductor strip 51, memory cells 42 and 43 on the semiconductor strip 53, and memory cells 44 and 45 on the semiconductor strip 55. As shown, the word line 60, which is the word line WLn, includes vertical extensions 60-1, 60-2, and 60-3, which are located between the stacks and are located in the trench 20 as shown in FIG. The extensions are for coupling the word lines 60 along the three strips of material in the illustrated plane to the memory unit. Arrays with many layers can be implemented as described herein, making very high density memory methods possible, or reaching terabits per chip.

圖5為一3D電荷設陷記憶體陣列2x2部分的透視圖，其中填充材料從圖式中被移除，如此方能顯示組成3D陣列的半導體帶堆疊以及垂直字元線。在這張圖式中，僅顯示兩個層。然而，層的數量可以擴展到非常大。如圖5所示，記憶體陣列被製造於一具有絕緣層110的積體電路基板上，其中絕緣層110以半導體或其他結構為基礎(未繪示)。記憶體陣列包括以絕緣材料121、122、123及124分離半導體帶111、112、113及114的複數個堆疊。該些堆疊為延伸於Y軸的脊形，如圖所示，如此半導體帶111-114可被配置為記憶體單元串列。半導體帶111及113可用作第一記憶體平面中的記憶體單元串列。半導體帶112及114可用作第二記憶體平面中的記憶體單元串列。Figure 5 is a perspective view of a portion of a 3D charge trap memory array 2x2 in which the fill material is removed from the pattern to enable display of the semiconductor strip stack and vertical word lines that make up the 3D array. In this illustration, only two layers are shown. However, the number of layers can be extended to very large. As shown in FIG. 5, the memory array is fabricated on an integrated circuit substrate having an insulating layer 110 based on a semiconductor or other structure (not shown). The memory array includes a plurality of stacks separating the semiconductor strips 111, 112, 113, and 114 with insulating materials 121, 122, 123, and 124. The stacks are ridges extending over the Y-axis, as shown, such that the semiconductor strips 111-114 can be configured as a series of memory cells. The semiconductor strips 111 and 113 can be used as a memory cell string in the first memory plane. Semiconductor strips 112 and 114 can be used as a string of memory cells in a second memory plane.

在第一堆疊中介於半導體帶111及112之間的絕緣層121以及在第二堆疊中介於半導體帶113及114之間的絕緣層123具有約40奈米或以上的有效氧化層厚度(effective oxide thickness,EOT)，其中有效氧化層厚度是依據二氧化矽的介電常數比率(ratio of the dielectric constant)以及所選擇的絕緣材料之介電常數而正規化(normalized)的絕緣材料厚度。用於此的詞語「約40奈米」是為了估算進約10%左右的可能變動，如同傳統上製造這型結構所產生的。絕緣材料的厚度在減少該結構的鄰近層單元間之干擾可扮演關鍵角色。在某些實施例中，絕緣材料的有效氧化層厚度可小至30奈米並且同時讓層與層之間有足夠的隔離。The insulating layer 121 interposed between the semiconductor strips 111 and 112 in the first stack and the insulating layer 123 interposed between the semiconductor strips 113 and 114 in the second stack have an effective oxide thickness of about 40 nm or more (effective oxide Thickness, EOT), wherein the effective oxide thickness is the thickness of the insulating material normalized according to the ratio of the dielectric constant of the cerium oxide and the dielectric constant of the selected insulating material. The term "about 40 nm" used in this case is intended to estimate a possible change of about 10%, as is conventionally produced for this type of structure. The thickness of the insulating material can play a key role in reducing interference between adjacent layer units of the structure. In some embodiments, the effective oxide thickness of the insulating material can be as small as 30 nanometers while allowing sufficient isolation between the layers.

記憶體材料層115，像是介電電荷設陷結構，在本實施例中塗覆在複數個半導體帶堆疊上。複數條字元線116及117垂直跨越複數個半導體帶堆疊而設置。字元線116及117具有與複數個半導體帶堆疊共形的表面，填補了複數個堆疊所形成的溝槽(也就是圖中的120)，且使介於堆疊上半導體帶111-114的側面以及字元線116及117側面之間交叉點的介面區域之多層陣列成形。矽化物118及119(也就是矽化鎢、矽化鈷、矽化鈦)的層可形成於字元線116及117的頂面上。The memory material layer 115, such as a dielectric charge trapping structure, is coated on a plurality of semiconductor strip stacks in this embodiment. A plurality of word line lines 116 and 117 are vertically disposed across a plurality of semiconductor strip stacks. The word lines 116 and 117 have surfaces conformal to the plurality of semiconductor strip stacks, filling the trenches formed by the plurality of stacks (i.e., 120 in the figure) and causing the sides of the semiconductor strips 111-114 on the stack And a multilayer array of interface regions at the intersections between the sides of word lines 116 and 117. Layers of Tellurides 118 and 119 (i.e., tungsten telluride, cobalt telluride, titanium telluride) may be formed on the top surfaces of word lines 116 and 117.

奈米線金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field effect transistor,MOSFET)單元也可用這種方式來設置，也就是透過在字元線111-114上通道區中提供奈米線或者奈米管結構，如同Paul等人在2007年9月於電機與電子學工程會電子裝置期刊第54冊第9號所發表之「製程變動對於奈米線與奈米管裝置效能之影響」(”Impact of a Process Variation on Nanowire and Nanotube Device Performance”,IEEE Transactions on Electron Devices,Vol. 54,No. 9,September 2007)中所描述的，該文獻在此被納入參考，如同已被充分闡述(which article is incorporated by reference as if fully set forth herein)。(這裡講到的是incorporate by reference，一種美國說明書的一種引入前案內容的撰寫方法。建議***“incorporate by reference”的中文翻譯，並在其後以刮號的方式將原文(incorporate by reference)標示出來，這樣子就會很清楚了)The metal-oxide-semiconductor field effect transistor (MOSFET) unit can also be arranged in such a manner that the nanowire is provided in the channel region on the word line 111-114. Or the structure of the nanotubes, as Paul and others published in September 2007 in the Journal of Electrical and Electronic Engineering, Electronic Devices, Vol.54, No. 9, "Impact of Process Variations on the Performance of Nanowires and Nanotubes" ("Impact of a Process Variation on Nanowire and Nanotube Device Performance", IEEE Transactions on Electron Devices, Vol. 54, No. 9, September 2007), which is incorporated herein by reference. (which article is incorporated by reference as if fully set forth herein). (This is an incorporated by reference, an American manual that describes how to write a pre-case content. It is recommended to translate the Chinese translation of *** "incorporate by reference" and then use the original by reference. Mark it out, it will be very clear.)

如此可製造在NAND快閃陣列中配置的矽氧氮氧矽(silicon-oxide-nitride-oxide-silicon,SONOS)型記憶體單元之3D陣列。源極(source)、汲極(drain)以及通道(channel)形成於矽半導體帶111-114中，記憶體材料層115包括可以二氧化矽形成的穿隧介電層97、可用氮化矽形成的電荷儲存層98、可用二氧化矽形成的阻擋介電層99以及包括字元線116及117的多晶矽之閘極。Thus, a 3D array of silicon-oxide-nitride-oxide-silicon (SONOS) type memory cells arranged in a NAND flash array can be fabricated. A source, a drain, and a channel are formed in the germanium semiconductor strips 111-114. The memory material layer 115 includes a tunneling dielectric layer 97 formed of hafnium oxide, which may be formed of tantalum nitride. The charge storage layer 98, the blocking dielectric layer 99 formed of cerium oxide, and the gate of the polysilicon including the word lines 116 and 117.

半導體帶111-114可為P型半導體材料。字元線116及117可為具相同或相異導電類型(也就是P+型)的半導體材料。舉例來說，半導體帶111-114可使用P型多晶矽或P型磊晶單晶矽製造，反之字元線116及117則可使用相對應的重摻雜P+型多晶矽製造。The semiconductor strips 111-114 can be P-type semiconductor materials. The word lines 116 and 117 can be semiconductor materials having the same or different conductivity types (i.e., P+ type). For example, the semiconductor strips 111-114 can be fabricated using P-type polycrystalline germanium or P-type epitaxial single crystal germanium, whereas the word lines 116 and 117 can be fabricated using corresponding heavily doped P+-type polycrystalline germanium.

另外，半導體帶111-114可為N型半導體材料。字元線116及117可為具相同或相異導電類型(也就是P+型)的半導體材料。這種N型帶設置可達成隱通道(buried-channel)及消耗模式(depletion mode)電荷設陷記憶體單元。舉例來說，半導體帶111-114可使用N型多晶矽或N型磊晶單晶矽(N-type epitaxial single crystal silicon)製造，反之字元線116及117則可使用相對應的重摻雜P+型多晶矽製造。典型的N型半導體帶摻雜濃度可在10¹⁸ /cm³ 附近，以可用的實施例而言約在10¹⁷ /cm³ 至10¹⁹ /cm³ 的範圍內。N型半導體帶的使用在無接面(junction-free)的實施例中特別有利於增進沿NAND串列的導電度且容許較高的讀取電流。Additionally, the semiconductor strips 111-114 can be N-type semiconductor materials. The word lines 116 and 117 can be semiconductor materials having the same or different conductivity types (i.e., P+ type). Such an N-type band arrangement can achieve a buried-channel and depletion mode charge trap memory unit. For example, the semiconductor strips 111-114 can be fabricated using N-type polycrystalline or N-type epitaxial single crystal silicon, whereas the word lines 116 and 117 can be used with corresponding heavily doped P+. Polycrystalline germanium is manufactured. A typical N-type semiconductor strip doping concentration may be in the vicinity of 10 ¹⁸ /cm ³ , and in the range of about 10 ¹⁷ /cm ³ to 10 ¹⁹ /cm ³ in the available embodiment. The use of N-type semiconductor strips is particularly advantageous in junction-free embodiments to promote conductivity along the NAND string and to allow for higher read currents.

如此，包括具有電荷儲存結構的場效電晶體之記憶體單元就被形成於交叉點的3D陣列中。使用約25奈米寬度的半導體帶及字元線，且於其中脊形間的間隙約為25奈米，一個具有幾十個層(也就是32層)的裝置就可在單晶片中達到萬億位元的容量。Thus, a memory cell including a field effect transistor having a charge storage structure is formed in a 3D array of intersections. A semiconductor strip and word line of about 25 nm width are used, and the gap between the ridges is about 25 nm, and a device having tens of layers (ie, 32 layers) can reach 10,000 in a single wafer. The capacity of billions of dollars.

記憶體材料層115可包括其他電荷儲存結構。舉例來說，可使用能隙設計SONOS(bandgap engineered SONOS,BE-SONOS)電荷儲存結構，其包括介電穿隧層97，該介電穿隧層97包括在零偏壓下形成倒「U」形價帶的材料之合成物。在一實施例中，合成穿隧介電層包括稱為孔洞穿隧層(hole tunneling layer)的第一層、稱為帶偏移層(band offset layer)的第二層以及稱為隔離層(isolation layer)的第三層。在此實施例中層115的孔洞穿隧層包括在半導體帶側面上的二氧化矽，其形成舉例來說是使用具選擇性氮化物的原位蒸氣生成法(in-situ steam generation,ISSG)，其在沉積的過程中在周圍環境既可使用後沉積一氧化氮退火(post deposition NO anneal)也可增加一氧化氮的使用。為二氧化矽的第一層之厚度小於20，且更佳地小於等於15。具代表性的實施例之厚度可為10或12。The memory material layer 115 can include other charge storage structures. For example, a band gap engineered SONOS (BE-SONOS) charge storage structure can be used, which includes a dielectric tunneling layer 97 that includes an inverted "U" under zero bias. A composite of materials of a valence band. In an embodiment, the synthetic tunneling dielectric layer includes a first layer called a hole tunneling layer, a second layer called a band offset layer, and an isolation layer ( The third layer of the isolation layer). The hole tunneling layer of layer 115 in this embodiment includes ruthenium dioxide on the side of the semiconductor strip, which is formed, for example, by using an in-situ steam generation (ISSG) with a selective nitride. It can also be used in the surrounding environment to deposit post-deposited NO anneal or increase the use of nitric oxide. The thickness of the first layer of cerium oxide is less than 20 And more preferably less than or equal to 15 . A representative embodiment may have a thickness of 10 Or 12 .

本實施例中的帶偏移層包括平置於孔洞穿隧層上的氮化矽，其形成舉例來說是使用低壓化學氣相沉積法(low-pressure chemical vapor deposition,LPCVD)，例如是在的680℃溫度下使用二氯矽烷(dichlorosilane,DCS)及阿摩尼亞(NH₃ )前驅物。在替代的製程中，帶偏移層包括使用帶有氧化二氮前驅物的相似製程所製造的氮氧化矽。氮化矽帶偏移層的厚度小於30，或更佳地小於等於25。The tape offset layer in this embodiment includes tantalum nitride which is laid flat on the tunnel tunneling layer, and is formed by, for example, low-pressure chemical vapor deposition (LPCVD), for example, The dichlorosilane (DCS) and the ammonia (NH ₃ ) precursor were used at a temperature of 680 °C. In an alternative process, the belt offset layer comprises niobium oxynitride produced using a similar process with a nitrous oxide precursor. The thickness of the tantalum nitride tape offset layer is less than 30 Or, preferably, less than or equal to 25 .

在此實施例中的隔離層包括二氧化矽，其平置於例如使用LPCVD高溫氧化(high temperature oxide,HTO)沉積法而形成之氮化矽帶偏移層上。二氧化矽隔離層的厚度小於35，或更佳地小於等於25。如此的三層穿隧層便可達成倒U形價帶能階(band energy level)。The spacer layer in this embodiment includes germanium dioxide which is placed flat on a tantalum nitride tape offset layer formed, for example, by LPCVD high temperature oxide (HTO) deposition. The thickness of the ceria barrier layer is less than 35 Or, preferably, less than or equal to 25 . Such a three-layer tunneling layer can achieve an inverted U-shaped band energy level.

若價帶能階所在的第一位置能使電場足以在介於帶有半導體本體的介面與第一位置之間的薄區域誘導孔洞穿隧，則價帶能階就足將在第一位置之後的價帶能階提升至能有效地消除第一位置之後的合成穿隧介電質中孔洞穿隧障壁之位階。這樣的結構在三層穿隧介電層中建立了倒U形價帶能階，且使得在高速下電場輔助(electric field assisted)的孔洞穿隧成為可能，並同時有效地在沒有電場或有因其他作業之目的而誘導的小電場時，(例如是在從單元讀取資料或者編程相鄰接的單元時)避免電荷的溢漏(leakage)通過合成穿隧介電質，。If the first position of the valence band energy level enables the electric field to induce hole tunneling in a thin region between the interface with the semiconductor body and the first position, the valence band energy level is sufficient to be after the first position The valence band energy level is raised to effectively eliminate the level of the hole tunneling barrier in the synthetic tunneling dielectric after the first position. Such a structure establishes an inverted U-shaped valence band energy level in the three-layer tunneling dielectric layer, and enables electric field assisted hole tunneling at high speed, and at the same time effectively without an electric field or When a small electric field is induced for the purpose of other operations, such as when reading data from a cell or programming an adjacent cell, leakage of charge is prevented by synthesizing the tunneling dielectric.

在一具代表性的裝置中，記憶體材料層115包括能隙設計合成穿隧介電層，其中包括了一厚度小於2奈米的二氧化矽層、一厚度小於3奈米的氮化矽層以及一厚度小於4奈米的二氧化矽層。在一實施例中，合成穿隧介電層包括了超薄二氧化矽層O1(也就是小於等於15)、超薄氮化矽層N1(也就是小於等於30)以及超薄二氧化矽層O2(也就是小於等於35)，於是在距帶有半導體本體的介面小於等於15的偏移之下增加了約2.6eV的價帶能階。O2層透過較低價帶能階(較高的孔洞穿隧障壁)以及較高傳導帶能階的區域在第二偏移下(也就是距介面約30至45)將N1層從電荷設陷層分離。足以誘導孔洞穿隧的電場將在第二位置之後的價帶能階提升至能有效消除孔洞穿隧障壁的位階，其乃因第二位置距介面較遠。因此，O2層並不明顯干擾電場輔助孔洞穿隧，同時增進了設計穿隧介電質在低場(low field)期間阻擋溢漏的能力。In a representative device, the memory material layer 115 includes an energy gap design synthetic tunneling dielectric layer including a germanium dioxide layer having a thickness of less than 2 nanometers and a tantalum nitride layer having a thickness of less than 3 nanometers. The layer and a layer of ceria having a thickness of less than 4 nm. In one embodiment, the synthetic tunneling dielectric layer includes an ultra-thin yttria layer O1 (ie, less than or equal to 15 ), ultra-thin tantalum nitride layer N1 (that is, less than or equal to 30) ) and the ultra-thin ruthenium dioxide layer O2 (that is, less than or equal to 35) ), then the interface with the semiconductor body is less than or equal to 15 The valence band energy of about 2.6 eV is increased below the offset. The O2 layer passes through the lower valence band energy level (higher hole tunneling barrier) and the higher conduction band energy level region at the second offset (ie, about 30 from the interface) To 45 The N1 layer is separated from the charge trapping layer. An electric field sufficient to induce hole tunneling raises the valence band energy level after the second position to a level effective to eliminate the hole tunneling barrier because the second position is farther from the interface. Therefore, the O2 layer does not significantly interfere with the electric field-assisted hole tunneling, while at the same time improving the ability of the design tunneling dielectric to block the spill during the low field.

在此實施例中的記憶體材料層115中之電荷設陷層包括了厚度大於50的氮化矽，(誰包括?charge trapping layer?? Silicon nitride??)例如是使用LPCVD所形成約70的氮化矽。也可採用其他電荷設陷材料及結構，包括例如氮氧化矽(Si_x O_y N_z )、富矽氮化物(silicon-rich nitride)、富矽氧化物(silicon-rich oxide)以及包括嵌入式奈米微粒(embedded nano-particles)的設陷層等等。The charge trapping layer in the memory material layer 115 in this embodiment includes a thickness greater than 50 The tantalum nitride, (who includes? charge trapping layer?? Silicon nitride??), for example, is formed using LPCVD. Niobium nitride. Other charge trapping materials and structures may also be employed, including, for example, yttrium oxynitride (Si _x O _y N _z ), silicon-rich nitride, silicon-rich oxide, and including embedded The trapping layer of embedded nano-particles and the like.

在此實施例中之記憶體材料層115中的阻擋介電層包括厚度大於50的二氧化矽層，包括例如透過濕爐氧化(wet furnace oxidation)製程從氮化物濕轉換(wet conversion)而形成的約90。在其他實施例中也可使用高溫氧化或LPCVD二氧化矽的方式實施。其他阻擋介電質可包括高κ係數的材料，如氧化鋁。The blocking dielectric layer in the memory material layer 115 in this embodiment includes a thickness greater than 50 The ruthenium dioxide layer includes, for example, about 90 formed by wet conversion of a wet furnace oxidation process. . In other embodiments, high temperature oxidation or LPCVD cerium oxide can also be used. Other barrier dielectrics may include materials with a high Kappa coefficient, such as alumina.

在一具代表性的實施例中，孔洞穿隧層可為13厚的二氧化矽；帶偏移層可為20厚的氮化矽；隔離層可為25厚的二氧化矽；電荷設陷層可為70厚的氮化矽；以及阻擋介電層可為90厚的二氧化矽。使用於字元線116及117中閘極的材料為P+型多晶矽(功函數(work function)約5.1eV)。In a representative embodiment, the tunneling layer can be 13 Thick ruthenium dioxide; with offset layer can be 20 Thick tantalum nitride; the isolation layer can be 25 Thick ceria; charge trapping layer can be 70 Thick tantalum nitride; and the barrier dielectric layer can be 90 Thick cerium oxide. The material used for the gates in word lines 116 and 117 is a P+ type polysilicon (work function of about 5.1 eV).

圖6顯示了從形成於字元線116及半導體帶114介面的電荷設陷記憶體單元之X-Z平面所截取的。主動電荷設陷區域125及126形成於介於字元線116及帶114之間的帶114之兩邊上。在於此描述的實施例中，如圖6所示，每個記憶體單元皆為具主動電荷儲存區域125及126的雙閘極場效電晶體，且位於半導體帶114的各邊上。在圖中以實箭頭所繪示的電子流沿著P形半導體帶而流動至感應放大器，於其中該電子流可被量測，以指出選定記憶體單元的狀態。Figure 6 shows the X-Z plane of the charge trap memory cell formed from the word line 116 and the semiconductor strip 114 interface. Active charge trap regions 125 and 126 are formed on both sides of strip 114 between word line 116 and strip 114. In the embodiment described herein, as shown in FIG. 6, each of the memory cells is a dual gate field effect transistor having active charge storage regions 125 and 126 and is located on each side of the semiconductor strip 114. The flow of electrons depicted by solid arrows in the figure flows along the P-shaped semiconductor strip to a sense amplifier where the flow of electrons can be measured to indicate the state of the selected memory cell.

圖7顯示從形成於字元線116及117與半導體帶114之介面的電荷設陷記憶體單元之X-Y平面所截取的截面圖。順半導體帶114而下的電流路徑也繪示於圖中。即使缺乏具有與字元線下通道區域相對之導電類型的源極與汲極摻雜，介於用作字元線之字元線116及117之間的源極/汲極區域128、129及130也可以是「無接面」的。在無接面的實施例中，電荷設陷場效電晶體可具有P型通道結構。並且，在某些實施例中可在字元線成形之後在自校準植入(self-aligned implant)中實施源極與汲極摻雜。7 shows a cross-sectional view taken from the X-Y plane of the charge trap memory cell formed in the interface between the word lines 116 and 117 and the semiconductor strip 114. The current path down the semiconductor strip 114 is also shown in the figure. Even if there is a lack of source and drain doping with a conductivity type opposite the word line channel region, source/drain regions 128, 129 between the word lines 116 and 117 used as word lines and 130 can also be "no junction". In a junctionless embodiment, the charge trap field effect transistor can have a P-type channel structure. Also, in some embodiments source and drain doping can be performed in a self-aligned implant after word line shaping.

在替代的實施例中，半導體帶111-114可在無接面的設置中使用輕摻雜N型半導體主體來實施，如此便得到可在耗盡模式下運作的隱通道場效電晶體，且其具有電荷設陷單元的自然位移較低閥值分布(naturally shifted lower threshold distribution)。In an alternative embodiment, the semiconductor strips 111-114 can be implemented in a junctionless arrangement using a lightly doped N-type semiconductor body, thus resulting in a hidden channel field effect transistor that can operate in a depletion mode, and It has a naturally shifted lower threshold distribution of the charge trapping unit.

圖8是顯示了具有在NAND配置中設置9個電荷設陷單元的記憶體單元之2平面的概要圖，其代表了可包括很多平面及很多字元線的立方體。記憶體單元的2平面定義於用作字元線WLn-1及WLn的字元線160及161與半導體帶第一堆疊、半導體帶第二堆疊以及半導體帶第三堆疊的交叉點。Figure 8 is a schematic diagram showing a plane of a memory cell having nine charge trapping cells in a NAND configuration, which represents a cube that can include many planes and many word lines. The 2 planes of the memory cells are defined at intersections of word lines 160 and 161 used as word lines WLn-1 and WLn with the first stack of semiconductor strips, the second stack of semiconductor strips, and the third stack of semiconductor strips.

記憶體單元的第一平面包括在半導體帶上的NAND串列中之記憶體單元70及71、在半導體帶上的NAND串列中之記憶體單元73、74以及在半導體帶上的NAND串列中之記憶體單元76、77。每個NAND串列之任一邊連接至接地選擇電晶體(也就是接地選擇電晶體90及72連接至NAND串列70及71的任一邊)。The first plane of the memory cell includes memory cells 70 and 71 in a NAND string on a semiconductor strip, memory cells 73, 74 in a NAND string on a semiconductor strip, and NAND strings on a semiconductor strip Memory unit 76, 77. Either side of each NAND string is coupled to a ground select transistor (i.e., ground select transistors 90 and 72 are coupled to either side of NAND strings 70 and 71).

記憶體單元第二平面在本例中對應至立方體中的底平面，且包括與第一平面類似的方法設置於NAND串列中的記憶體單元(也就是80、82及84)。The second plane of the memory cell corresponds in this example to the bottom plane in the cube and includes memory cells (i.e., 80, 82, and 84) disposed in the NAND string in a similar manner to the first plane.

如圖所示，用作字元線WLn的字元線161包括對應於圖5中介於堆疊之間溝槽120材料的垂直延長部分，這是為了將字元線161耦接至所有平面中介於半導體帶之間溝槽中的介面區域之記憶體單元(在第一平面中的單元71、74以及77)。As shown, the word line 161 used as the word line WLn includes a vertical extension corresponding to the material of the trench 120 between the stacks in FIG. 5, in order to couple the word line 161 to all planes. Memory cells (cells 71, 74, and 77 in the first plane) of the interface regions in the trenches between the semiconductor strips.

在相鄰堆疊中的記憶體單元串列在位元線端-至-來源線端導向(bit line end-to-source line end orientation)與來源線端-至-位元線端導向(source line end-to-bit line end orientation)之間交替。The memory cell string in the adjacent stack is oriented at the bit line end-to-source line end orientation and the source line end-to-bit line end (source line) The end-to-bit line end orientation) alternates.

位元線BL_N 及BL_N-1 (也就是96)為記憶體串列的結尾，其與串列選擇裝置相鄰。舉例來說，在頂部記憶體平面中，位元線BL_N 為具有串列選擇電晶體85及89之記憶體單元串列的結尾。相比之下，位元線並非連接至挽線88(trace)，因為相鄰堆疊的串列在位元線端-至-來源線端導向與來源線端-至-位元線端之間交替。故反而對於此串列，相對應的位元線是連接至串列的其他端。在底部的記憶體平面中，位元線BL_N-1 為具有相對應串列選擇電晶體的記憶體單元串列之結尾。Bit lines BL _N and BL _N-1 (i.e., 96) are the end of the memory string adjacent to the string selection device. For example, in the top memory plane, bit line BL _N is the end of the memory cell string with serial select transistors 85 and 89. In contrast, the bit line is not connected to the trace 88 because the tandem of the adjacent stack is between the bit line end-to-source line end and the source line end-to-bit line end alternately. Instead, for this series, the corresponding bit line is connected to the other end of the string. In the memory plane at the bottom, the bit line BL _N-1 is the end of the memory cell string having the corresponding series of selected transistors.

串列選擇電晶體85及89於此設置中在介於各自的NAND串列與串列選擇線(string select line,SSL)SSL_n-1 及SSL_n 之間連接。同樣地，在立方體中底部平面上類似的串列選擇電晶體於此設置中在介於各自的NAND串列與串列選擇線SSL_n-1 及SSL_n 之間連接。串列選擇線106及108將不同的脊連接至在各個記憶體單元串列中串列選擇電晶體的閘極，以及在此實施例中提供串列選擇訊號SSL_n-1 、SSL_n 及SSL_n+1 。The serial selection transistors 85 and 89 are connected between the respective NAND strings and the string select lines (SSL) SSL _n-1 and SSL _n in this arrangement. Similarly, in the cube on the bottom plane similar series select transistor disposed thereto in series between the respective NAND between the tandem SSL _n-1 and connected to select line SSL _n. Tandem select lines 106 and 108 connect different ridges to the gates of the select transistor in series in each memory cell string, and in this embodiment provide serial select signals SSL _n-1 , SSL _n and SSL _n+1 .

相較之下，串列選擇電晶體並不連接至挽線88，因為相鄰堆疊的串列在介於位元線端-至-來源線端導向與來源線端-至-位元線端導向之間交替。故反而對於此串列，相對應的串列選擇電晶體是連結至串列的其他端。具記憶體單元73及74的NAND串列也在串列的其他端上具有串列選擇裝置(並無繪示於圖中)。挽線88以來源線107做結尾。In contrast, the tandem select transistor is not connected to the puller 88 because the tandem of the adjacent stack is at the end of the bit line-to-source line and the source line end-to-bit line end The orientation alternates. Instead, for this series, the corresponding serial selection transistor is connected to the other end of the string. The NAND string with memory cells 73 and 74 also has a serial selection device (not shown) in the other end of the string. The wire 88 ends with a source line 107.

接地選擇電晶體90-95設置於NAND串列的第一端。接地選擇電晶體72、75、78以及相對應的第二平面接地選擇電晶體設置於NAND串列的第二端。因此，接地選擇電晶體皆在記憶體串列的兩端上。依據記憶體串列特定的端，接地選擇電晶體將記憶體串列耦接至來源線，或耦接至串列選擇裝置以及位元線。Ground selection transistors 90-95 are disposed at the first end of the NAND string. Ground selection transistors 72, 75, 78 and corresponding second planar ground selection transistors are disposed at the second end of the NAND string. Therefore, the ground selection transistors are on both ends of the memory string. The ground selection transistor couples the memory string to the source line or to the string selection device and the bit line, depending on the particular end of the memory string.

於此實施例中的接地選擇訊號GSL 159耦接於接地選擇電晶體90-95的閘極，且可使用如字元線160及161的相同方法來實施(其中159與162同樣都是接地選擇訊號GSL)。串列選擇電晶體以及接地選擇電晶體可如某些實施例中的記憶體單元使用相同的介電堆疊如閘極氧化層(gate oxide)。在其他實例中，就是使用典型的閘極氧化層。並且，通道長度與寬度可依設計者的需求作調校以提供電晶體的開關功能。The ground selection signal GSL 159 in this embodiment is coupled to the gate of the ground selection transistor 90-95 and can be implemented using the same method as the word lines 160 and 161 (where 159 and 162 are both grounded). Signal GSL). The serial selection transistor and the ground selection transistor can use the same dielectric stack as the gate oxide, such as the memory cells in some embodiments. In other examples, a typical gate oxide layer is used. Moreover, the length and width of the channel can be adjusted according to the designer's needs to provide the switching function of the transistor.

圖9為如圖5的替代結構透視圖。在此圖中重複使用相似結構的參考數字，且於此不再重複描述。圖9與圖5的不同之處在於絕緣層110的表面110A以及半導體帶113及114的側面113A及114A是暴露於用作字元線的字元線116之間，此乃形成字元線的蝕刻製程之結果。因此，記憶體材料層115可在不危害運作的情況下，在字元線之間被完全地或部分地蝕刻。然而，類似於此描述地透過記憶體層115蝕刻以形成介電電荷設陷結構在某些結構中並非必要。Figure 9 is a perspective view of an alternative structure as in Figure 5. Reference numerals of similar structures are repeatedly used in this figure, and the description will not be repeated here. 9 is different from FIG. 5 in that the surface 110A of the insulating layer 110 and the sides 113A and 114A of the semiconductor strips 113 and 114 are exposed between the word lines 116 serving as word lines, which form a word line. The result of the etching process. Thus, the memory material layer 115 can be completely or partially etched between the word lines without compromising operation. However, etching through the memory layer 115 to form a dielectric charge trap structure similar to that described herein is not necessary in some constructions.

圖10為類似於圖6在X-Z平面中記憶體單元的截面圖。圖10相同於圖6，繪示了類似於圖9的結構，其可得在此截面中如圖5結構中實施的記憶體單元。圖11為類似於圖7在X-Y平面中記憶體單元的截面圖。圖11與圖7不同的地方在於沿半導體帶114的側面(也就是114A)區域128a、129a以及130a的記憶體材料可以被移除。Figure 10 is a cross-sectional view of the memory cell in the X-Z plane similar to Figure 6. Figure 10 is the same as Figure 6 and depicts a structure similar to that of Figure 9 in which the memory cells implemented in the structure of Figure 5 are available. Figure 11 is a cross-sectional view of the memory cell in the X-Y plane similar to Figure 7. 11 differs from FIG. 7 in that the memory material along the side (ie, 114A) regions 128a, 129a, and 130a of the semiconductor strip 114 can be removed.

圖12-16繪示了如上述實施3D記憶體陣列的基本流程階段，其僅利用為陣列形成之關鍵校準步驟的2個圖型遮罩(pattern masking)步驟。在圖12中，顯示了在例如於晶片陣列區披覆沉積(blanket deposition)中使用摻雜半導體形成之絕緣層210、212、214以及半導體層211及213交替沉積所形成的結構。依據這樣的實施方式，半導體層211及213可使用具有N型或P型摻雜的多晶矽或磊晶單晶矽來實施。跨級(inter-level)絕緣層210、212及214可使用例如二氧化矽、其他氧化矽或氮化矽來實施。這些層可用很多不同方法來形成，包括在所屬技藝中可用的低壓化學氣相沉積製程。Figures 12-16 illustrate the basic flow stages of implementing a 3D memory array as described above, using only two pattern masking steps for the critical calibration steps formed by the array. In Fig. 12, a structure formed by alternately depositing insulating layers 210, 212, 214 formed using a doped semiconductor and semiconductor layers 211 and 213 in, for example, wafer array region blanket deposition is shown. According to such an embodiment, the semiconductor layers 211 and 213 can be implemented using polycrystalline germanium or epitaxial single crystal germanium having N-type or P-type doping. Inter-level insulating layers 210, 212, and 214 can be implemented using, for example, hafnium oxide, other hafnium oxide, or tantalum nitride. These layers can be formed in a number of different ways, including low pressure chemical vapor deposition processes that are useful in the art.

圖13顯示了用於使半導體帶複數個脊形堆疊250成形的第一平板刻紋(lithographic patterning)步驟之結果，其中半導體帶使用半導體層211及213的材料來實施，且被絕緣層212及214分離。深入地，高度高寬比(aspect ratio)且支撐許多層的溝槽可使用運用碳硬遮罩(carbon hard mask)及反應離子蝕刻(reactive ion etching)之平板印刷基礎的製程來形成於堆疊中。Figure 13 shows the result of a first lithographic patterning step for shaping a plurality of ridge stacks 250 of a semiconductor strip, wherein the semiconductor strip is implemented using the materials of the semiconductor layers 211 and 213, and is insulated by the insulating layer 212 and 214 separation. In-depth, a high aspect ratio and a plurality of layers of trenches can be formed in the stack using a lithographic process using carbon hard masks and reactive ion etching. .

雖然圖中沒有顯示，然此步驟中記憶體串列交替的導向係被定義為：位元線端-至-來源線端導向以及來源線端-至-位元線端導向。Although not shown in the figure, in this step, the alternate array of memory strings is defined as: bit line end-to-source line end guidance and source line end-to-bit line end guidance.

圖14A及14B相對地顯示了包括可編程電阻記憶體結構例如為反熔絲單元結構之實施例的下一階段，以及包括可編程電荷設陷記憶體結構如SONOS型記憶體單元結構之實施例的下一階段。14A and 14B relatively show the next stage of an embodiment including a programmable resistive memory structure such as an anti-fuse cell structure, and an embodiment including a programmable charge trap memory structure such as a SONOS-type memory cell structure. The next stage.

圖14A顯示了在一實施例中記憶體材料層215的披覆沉積的結果，於該實施例中，記憶體材料包括了類似於圖一所示的反熔絲結構之單一層。在另一種實施例中，係運用氧化製程而非披覆沉積，來在半導體帶暴露的邊上形成氧化物，其中氧化物係被用作記憶體材料。Figure 14A shows the results of a blanket deposition of memory material layer 215 in one embodiment. In this embodiment, the memory material includes a single layer similar to the anti-fuse structure shown in Figure 1. In another embodiment, an oxide process is used instead of a blanket deposition to form an oxide on the exposed side of the semiconductor strip, wherein the oxide is used as the memory material.

圖14B顯示了層315披覆沉積的結果，包括了包含穿隧層397、電荷設陷層398以及阻擋層399的多層電荷設陷結構，如同上述關於圖4所描述的。如圖14A及14B所示，記憶體層215及315以共形的方式沉積於半導體帶脊形堆疊之上。Figure 14B shows the results of layer 315 cladding deposition, including a multilayer charge trapping structure comprising tunneling layer 397, charge trapping layer 398, and barrier layer 399, as described above with respect to Figure 4. As shown in Figures 14A and 14B, memory layers 215 and 315 are deposited in a conformal manner over the semiconductor strip ridge stack.

圖15顯示了高度寬高比填充步驟的結果，其中使用導電材料沉積形成層225以用作字元線，該導電材料例如為N型或P型摻雜的多晶矽。並且，矽化物層226於利用多晶矽的實施例中可形成於層225之上。如此圖所繪示，係利用於所繪示的實施例中的高度寬高比沉積技術例如多晶矽的低壓化學氣相沉積法來完全填充脊形堆疊間的溝槽220，即使該具高度高寬比並且非常狹窄的溝槽窄至約10奈米。Figure 15 shows the results of a height aspect ratio filling step in which a layer 225 is formed using a conductive material for use as a word line, such as an N-type or P-type doped polysilicon. Also, the telluride layer 226 can be formed over the layer 225 in an embodiment utilizing polysilicon. As shown in this figure, the trench 220 between the ridge stacks is completely filled by a high aspect ratio deposition technique such as polycrystalline germanium low pressure chemical vapor deposition in the illustrated embodiment, even if the height and width are high. The narrower and narrower grooves are as narrow as about 10 nm.

圖16顯示用於使3D記憶體陣列中用作字元線的複數字元線260成形的第二平板刻紋步驟之結果。第二平板刻紋步驟對於陣列關鍵的尺寸係利用單遮罩來在字元線之間蝕刻高度高寬比的溝槽。可使用對多晶矽來說比二氧化矽與氮化矽還具高度選擇性的蝕刻製程來蝕刻多晶矽。因此，使用交替蝕刻製程(alternating etch process)依靠相同的遮罩來蝕穿導電與絕緣層，並止於作為基礎的絕緣層210上。Figure 16 shows the result of a second planar scribing step for shaping complex digital element lines 260 used as word lines in a 3D memory array. The second slab engraving step utilizes a single mask to etch a high aspect ratio trench between the word lines for the critical dimension of the array. The polysilicon can be etched using an etching process that is highly selective to polysilicon and is more selective than ceria and tantalum nitride. Therefore, the alternating etch process is used to etch through the conductive and insulating layers by the same mask and terminates on the insulating layer 210 as a foundation.

於此步驟，也可使接地選擇線成形。於此步驟，也可使被串列選擇線所控制的閘極結構成形，即使閘極結構與個別半導體帶堆疊共形。In this step, the ground selection line can also be formed. In this step, the gate structure controlled by the string selection line can also be formed, even if the gate structure is conformal to the individual semiconductor strip stack.

選擇性的製造步驟包括了在複數字元線上形成硬遮罩，以及在閘極結構上形成硬遮罩。硬遮罩可使用相對薄的氮化矽層或其他可阻擋離子植入程序的材料而形成。在硬遮罩形成之後，可實施植入以增加半導體帶以及階梯結構(stairstep structure)中的摻雜濃度，以減低沿半導體帶電流路徑的電阻。藉由利用控制植入的能量，可致使植入物滲入至半導體帶底部，且各自在堆疊中覆蓋半導體帶。The optional fabrication steps include forming a hard mask on the complex digital line and forming a hard mask on the gate structure. The hard mask can be formed using a relatively thin layer of tantalum nitride or other material that blocks the ion implantation process. After the hard mask is formed, implantation can be performed to increase the doping concentration in the semiconductor strip and the stairstep structure to reduce the resistance along the current path of the semiconductor strip. By utilizing the energy of the implant, it is possible to cause the implant to penetrate into the bottom of the semiconductor strip and each cover the semiconductor strip in the stack.

隨後，移除硬遮罩，暴露沿字元線頂面以及閘極結構上的矽化物層。在陣列頂部上形成一夾層介電質(interlayer dielectric)之後，通孔(via)會被開啟，在通孔中，例如使用鎢填充的接觸栓(contact plug)被形成到達至閘極結構的頂面。覆蓋金屬線被刻紋以如SSL線般連接至列解碼器電路。一個三平面的解碼網路係被建立，其使用一條字元線、一條位元線以及一條SSL線來存取選定單元。請見標題為「平面解碼方法及3D記憶體裝置」(Plane Decoding Method and Device for Three Dimensional Memories)的第6906940號美國專利。Subsequently, the hard mask is removed, exposing the top layer along the word line and the germanide layer on the gate structure. After an interlayer dielectric is formed on top of the array, vias are opened, and in the vias, for example, a tungsten-filled contact plug is formed to reach the top of the gate structure. surface. The overlay metal lines are scribed to connect to the column decoder circuit as an SSL line. A three-plane decoding network is created that uses a word line, a bit line, and an SSL line to access selected cells. See U.S. Patent No. 6,069,940, entitled "Plane Decoding Method and Device for Three Dimensional Memories."

圖17為一張已被模擬及測試過的8層垂直閘、薄膜電晶體以及BE-SONOS電荷設陷NAND裝置的部分TEM剖面圖。該裝置係以75奈米之半節距(half pitch)製造。通道為約18奈米厚的N型多晶矽。不使用額外的接面植入，成為無接面的結構。隔離Z方向通道而介於帶之間的絕緣材料為約40奈米厚的二氧化矽。以P+多晶矽線來提供閘極。SSL與GSL裝置具有較記憶體單元長的通道長度。該測試裝置實施了32條字元線及無接面的NAND串列。因為用於形成該結構的溝槽蝕刻造成具有隨溝槽漸深而漸寬的帶之錐形側牆，且因為錐形側牆具有介於相對於多晶矽被蝕刻較多的帶之間的絕緣材料，所以圖17中的較低帶之寬度大於較高帶的寬度。Figure 17 is a partial TEM cross-sectional view of an 8-layer vertical gate, thin film transistor, and BE-SONOS charge trap NAND device that has been simulated and tested. The device was fabricated at a half pitch of 75 nm. The channel is an N-type polysilicon of about 18 nm thick. Without the use of additional joints, it becomes a jointless structure. The insulating material separating the Z-direction channels between the strips is about 40 nm thick of cerium oxide. The gate is provided by a P+ polysilicon line. The SSL and GSL devices have a longer channel length than the memory cells. The test set implements 32 word lines and a NAND series without junctions. Because the trench used to form the structure etches a tapered sidewall having a strip that tapers as the trench is deeper, and because the tapered sidewall has an insulation between the strips that are more etched relative to the polysilicon Material, so the width of the lower band in Figure 17 is greater than the width of the higher band.

圖17顯示了具有不同側邊尺寸的3D結構之不同層。這種在層之間的不同側邊尺寸是3D結構不同層之間不同電容的來源。Figure 17 shows the different layers of a 3D structure with different side dimensions. This different side dimension between the layers is the source of the different capacitances between the different layers of the 3D structure.

圖18為根據本發明實施例的積體電路簡化方框圖。積體電路線路875包括了如在此描述般實施的3D可編程電阻記憶體陣列860(resisted random-access memory,RRAM)，其位於半導體基板之上，具有位元線端-至-來源線端導向與來源線端-至-位元線端導向的交替記憶體串列導向，且位於在所有其他堆疊之上的串列選擇線閘極結構堆疊之任一端。列解碼器861耦接至複數條字元線862，且沿記憶體陣列860的行而設置。行解碼器863耦接至沿對應於記憶體陣列860中堆疊的行而設置的複數條SSL線864，以從陣列860中的記憶體單元讀取及編程資料。平面解碼器858耦接至位元線859上記憶體陣列860中之複數平面。在匯流排865上提供位址給行解碼器863、列解碼器861以及平面解碼器858。方塊866中的感應放大器及資料輸入(data-in)結構在此實施例中透過資料匯流排867耦接至行解碼器863。資料係從積體電路875上的輸入/輸出埠透過資料輸入線871而提供，或者從其他積體電路875內部或外部的資料來源提供至方塊866中的資料輸入結構。在所繪示的實施例中，積體電路包括了其他的電路系統874，例如一般用途處理器或特定用途應用電路系統，或者是提供可編程電阻單元陣列支援的晶片上系統(system-on-a-chip)功能模組之組合。資料係從方塊866中的感應放大器透過資料輸出(data-out)線872提供至積體電路875上的輸入/輸出埠，或提供至其他積體電路875內部或外部的資料目的地。Figure 18 is a simplified block diagram of an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit line 875 includes a 3D programmable resistive memory array 860 (RRAM) implemented as described herein over a semiconductor substrate having bit line end-to-source line ends The alternate memory is guided in series with the source line end-to-bit line end and is located at either end of the tandem select line gate structure stack over all other stacks. Column decoder 861 is coupled to a plurality of word line lines 862 and is disposed along a row of memory array 860. Row decoder 863 is coupled to a plurality of SSL lines 864 disposed along rows corresponding to stacked in memory array 860 to read and program data from memory cells in array 860. Planar decoder 858 is coupled to the complex planes in memory array 860 on bit line 859. Addresses are provided on bus 865 to row decoder 863, column decoder 861, and plane decoder 858. The sense amplifier and data-in structure in block 866 is coupled to row decoder 863 via data bus 867 in this embodiment. The data is provided from the input/output port on the integrated circuit 875 through the data input line 871, or from a data source internal or external to the other integrated circuit 875 to the data input structure in block 866. In the illustrated embodiment, the integrated circuit includes other circuitry 874, such as a general purpose processor or application specific application circuitry, or a system-on-a-system that provides programmable resistor cell array support (system-on- A-chip) A combination of functional modules. The data is provided from the sense amplifier in block 866 through the data-out line 872 to the input/output ports on the integrated circuit 875 or to the data destinations internal or external to the other integrated circuits 875.

使用偏壓設置狀態機869(bias arrangement state machine)的本實施例中所實施之控制器，是用來控制透過方塊868中一個或多個電壓供應器所產生或提供之偏壓設置供應電壓的應用，例如讀取及編程電壓。控制器可使用熟知技藝中的特定用途邏輯電路系統來實施。在一替代實施例中，控制器包括了一般用途處理器，控制器可在相同的積體電路上實施，而所包括的一般用途處理器則執行電腦程式來控制裝置的運作。又在另一個實施例中，可利用特定用途邏輯電路系統及一般用途處理器的組合以實施其他控制器。A controller implemented in this embodiment using a bias arrangement state machine 869 is used to control the supply voltage of the bias voltage generated or provided by one or more voltage supplies in block 868. Applications such as reading and programming voltages. The controller can be implemented using special purpose logic circuitry in the well-known art. In an alternate embodiment, the controller includes a general purpose processor, the controller can be implemented on the same integrated circuit, and the general purpose processor included executes a computer program to control the operation of the device. In yet another embodiment, a combination of special purpose logic circuitry and general purpose processors can be utilized to implement other controllers.

圖19為依據本發明一實施例之積體電路的簡化方塊圖。積體電路線路975包括了如這裡所描述而實施之半導體基板上具有交替記憶體串列導向的3D NAND快閃記憶體陣列960，且位於具有所有其他堆疊上都有的串列選擇線閘極結構之堆疊的任一端，所謂交替記憶體串列導向為位元線端-至來源線端導向以及來源線端-至-位元線端導向。列解碼器961耦接至複數條字元線962，且沿記憶體陣列960中的列而設置。行解碼器963耦接至沿對應於記憶體陣列960中堆疊的行而設置的複數條SSL線964以從陣列960中的記憶體單元讀取及編程資料。平面解碼器958透過位元線959耦接至記憶體陣列960中的複數個平面。在匯流排965(bus)上提供位址給行解碼器963(column decoder)、列解碼器961(row decoder)以及平面解碼器958(plane decoder)。方塊966中的感應放大器及資料輸入結構在此實施例中透過資料匯流排967耦接至行解碼器963。資料係從積體電路975上的輸入/輸出埠透過資料輸入線971而提供，或者從其他積體電路975內部或外部的資料來源提供至方塊966中的資料輸入結構。在所繪示的實施例中，積體電路包括了其他的電路系統974，例如一般用途處理器或特定用途應用電路系統，或者是提供可編程電阻單元陣列支援的晶片上系統功能模組之組合。資料係從方塊966中的感應放大器透過資料輸出線972提供至積體電路975上的輸入/輸出埠，或提供至其他積體電路975內部或外部的資料目的地。Figure 19 is a simplified block diagram of an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit line 975 includes a 3D NAND flash memory array 960 having alternating memory string alignment on a semiconductor substrate implemented as described herein, and is located in a tandem select line gate having all other stacks. At either end of the stack of structures, the so-called alternate memory string alignment is oriented from the bit line end-to-source line end and the source line end-to-bit line end. Column decoder 961 is coupled to a plurality of word line lines 962 and is disposed along columns in memory array 960. Row decoder 963 is coupled to a plurality of SSL lines 964 disposed along rows corresponding to stacked in memory array 960 to read and program data from memory cells in array 960. Planar decoder 958 is coupled to a plurality of planes in memory array 960 via bit line 959. An address is provided on the bus 965 (bus) to a row decoder 963 (colum decoder), a column decoder 961 (row decoder), and a plane decoder 958 (plane decoder). The sense amplifier and data input structure in block 966 is coupled to row decoder 963 via data bus 967 in this embodiment. The data is provided from the input/output port on the integrated circuit 975 through the data input line 971, or from a data source internal or external to the other integrated circuit 975 to the data input structure in block 966. In the illustrated embodiment, the integrated circuit includes other circuitry 974, such as a general purpose processor or application specific application circuitry, or a combination of on-chip system functional modules that provide programmable resistance cell array support. . The data is provided from the sense amplifier in block 966 through the data output line 972 to the input/output ports on the integrated circuit 975 or to the data destinations internal or external to the other integrated circuit 975.

使用偏壓設置狀態機969的本實施例中所實施之控制器，是用來控制透過方塊968中一個或多個電壓供應器所產生或提供之偏壓設置供應電壓的應用，例如讀取、抹除、編程、抹除驗證(erase verify)以及編程驗證(program verify)電壓。控制器可使用熟知技藝中的特定用途邏輯電路系統來實施。在一替代實施例中，控制器包括了一般用途處理器，控制器可在相同的積體電路上實施，而所包括的一般用途處理器則執行電腦程式來控制裝置的運作。又在另一個實施例中，可利用特定用途邏輯電路系統及一般用途處理器的組合以實施其他控制器。The controller implemented in this embodiment using the bias setting state machine 969 is an application for controlling the supply voltage through the bias voltage generated or provided by one or more voltage supplies in block 968, such as reading, Erase, program, erase verify, and program verify voltage. The controller can be implemented using special purpose logic circuitry in the well-known art. In an alternate embodiment, the controller includes a general purpose processor, the controller can be implemented on the same integrated circuit, and the general purpose processor included executes a computer program to control the operation of the device. In yet another embodiment, a combination of special purpose logic circuitry and general purpose processors can be utilized to implement other controllers.

圖20-22繪示了具有平行於半導體材料帶的縱向導向串列選擇線、平行於字元線的橫向導向串列選擇線以及平行於半導體材料帶的縱向導向位元線之漸高金屬層的第一3D NAND快閃記憶體陣列結構。20-22 illustrate a laterally directed string select line parallel to a strip of semiconductor material, a laterally directed string select line parallel to the word line, and a progressive metal layer parallel to the longitudinal guide bit line of the strip of semiconductor material. The first 3D NAND flash memory array structure.

圖20為第一3D NAND快閃記憶體陣列結構的透視圖。絕緣材料從圖式中被移除以暴露附加的結構。舉例來說，絕緣層在脊形堆疊中的半導體帶間被移除，且在半導體帶的脊形堆疊之間被移除。Figure 20 is a perspective view of the structure of the first 3D NAND flash memory array. The insulating material is removed from the drawing to expose additional structures. For example, the insulating layers are removed between the semiconductor strips in the ridge stack and removed between the ridge stacks of the semiconductor strips.

多層陣列形成於絕緣層之上，且包括了共形於複數個脊形堆疊的複數條字元線425-1、…、425-n-1及425-n，該些條字元線係用作字元線WLn、WLn-1、…WL1。複數個脊形堆疊包括了半導體帶412、413、414及415。在相同平面中的半導體帶與階梯結構電性耦接在一起。The multilayer array is formed on the insulating layer and includes a plurality of word lines 425-1, ..., 425-n-1 and 425-n conformed to the plurality of ridge stacks, wherein the plurality of word lines are used Word lines WLn, WLn-1, ... WL1 are formed. The plurality of ridge stacks include semiconductor strips 412, 413, 414, and 415. The semiconductor strips in the same plane are electrically coupled to the stepped structure.

所示的字元線編號，其從結構之後端到前端依序從1至N漸大，係應用於偶數記憶體頁。對於奇數記憶體頁，字元線編號從結構之後端到前端依序則從N至1漸小。The illustrated word line number, which gradually increases from 1 to N from the rear end to the front end of the structure, is applied to even memory pages. For odd-numbered memory pages, the word line number is gradually reduced from N to 1 from the back end of the structure to the front end.

階梯結構412A、413A、414A及415A為半導體帶之結尾，例如為半導體帶412、413、414及415的結尾。如圖所示，這些階梯結構412A、413A、414A及415A電性連接至不同位元線來將解碼電路系統連接至陣列中的選擇平面。這些階梯結構412A、413A、414A及415A可於使複數個脊形堆疊成形之同時被刻紋。The stepped structures 412A, 413A, 414A, and 415A are the ends of the semiconductor strips, such as the ends of the semiconductor strips 412, 413, 414, and 415. As shown, these ladder structures 412A, 413A, 414A, and 415A are electrically coupled to different bit lines to connect the decoding circuitry to a selection plane in the array. These stepped structures 412A, 413A, 414A, and 415A can be scribed while forming a plurality of ridge stacks.

階梯結構402B、403B、404B及405B為半導體帶的結尾，例如為半導體帶402、403、404及405之結尾。如圖所示，這些階梯結構402B、403B、404B及405B電性連接至不同位元線來將解碼電路系統連接至陣列中的選擇平面。這些階梯結構402B、403B、404B及405B可於使複數個脊形堆疊成形之同時被刻紋。The stepped structures 402B, 403B, 404B, and 405B are the ends of the semiconductor strips, such as the ends of the semiconductor strips 402, 403, 404, and 405. As shown, these ladder structures 402B, 403B, 404B, and 405B are electrically coupled to different bit lines to connect the decoding circuitry to a selection plane in the array. These stepped structures 402B, 403B, 404B, and 405B can be scribed while forming a plurality of ridge stacks.

任何給定的半導體帶堆疊不是被耦接至階梯結構412A、413A、414A及415A，就是被耦接至階梯結構402B、403B、404B及405B，但並不耦接至兩者。半導體帶堆疊具有位元線端-至-來源線端導向或來源線端-至-位元線端導向的兩相對導向其中之一。舉例來說，半導體帶412、413、414及415的堆疊具有位元線端-至-來源線端導向，而半導體帶402、403、404及405的堆疊則具有來源線-至-位元線端導向。Any given semiconductor strip stack is not coupled to the ladder structures 412A, 413A, 414A, and 415A, or to the ladder structures 402B, 403B, 404B, and 405B, but is not coupled to both. The semiconductor strip stack has one of two opposite orientations of the bit line end-to-source line end guide or the source line end-to-bit line end guide. For example, the stack of semiconductor strips 412, 413, 414, and 415 has bit line end-to-source line end guidance, while the stack of semiconductor strips 402, 403, 404, and 405 has source line-to-bit lines. End oriented.

導體帶412、413、414及415的堆疊藉由階梯結構412A、413A、414A及415A在其中一端結尾，通過SSL閘極結構419、閘極選擇線GSL426、從字元線425-1WL至425-N WL、閘極選擇線GSL427，然後透過來源線428結尾於另一端。半導體帶412、413、414及415的堆疊並不到達階梯結構402B、403B、404B及405B。The stack of conductor strips 412, 413, 414, and 415 ends at one end by stepped structures 412A, 413A, 414A, and 415A, through SSL gate structure 419, gate select line GSL426, and word line 425-1WL to 425- N WL, the gate select line GSL427, then ends at the other end through source line 428. The stack of semiconductor strips 412, 413, 414, and 415 does not reach the stepped structures 402B, 403B, 404B, and 405B.

半導體帶402、403、404及405的堆疊藉由階梯結構402B、403B、404B及405B在其中一端結尾，通過SSL閘極結構409、閘極選擇線GSL427、從字元線425-NWL至425-1 WL、閘極選擇線GSL426，然後透過來源線(被圖示的其他部分所遮蓋)結尾於另一端。半導體帶402、403、404及405的堆疊並不到達階梯結構412A、413A、414A及415A。The stack of semiconductor strips 402, 403, 404, and 405 ends at one end by stepped structures 402B, 403B, 404B, and 405B, through SSL gate structure 409, gate select line GSL427, and word line 425-NWL to 425- 1 WL, gate select line GSL426, then end at the other end through the source line (covered by other parts of the illustration). The stack of semiconductor strips 402, 403, 404, and 405 does not reach the stepped structures 412A, 413A, 414A, and 415A.

如前圖所詳細描述的，記憶體材料層從半導體帶412-415以及402-405分離了字元線425-1至425-n。接地選擇線GSL 426及GSL 427共形於複數個脊形堆疊，類似於字元線。As described in detail in the previous figures, the memory material layer separates word lines 425-1 through 425-n from semiconductor strips 412-415 and 402-405. The ground select lines GSL 426 and GSL 427 are conformed to a plurality of ridge stacks, similar to word lines.

半導體帶的每個堆疊的其中一端皆以階梯結構做結尾，並且以來源線做為另一端的結尾。舉例來說，半導體帶412、413、414及415的堆疊透過階梯結構412A、413A、414A及415A結尾於其中一端，並透過來源線428結尾於另一端。在本圖的近端，一部分的半導體帶堆疊透過階梯結構402B、403B、404B及405B結尾，而所有另一部分的半導體帶堆疊則透過來源線結尾。在本圖的遠端，該所有另一部分的半導體帶堆疊透過階梯結構412A、413A、414A及415A，而該一部分的半導體帶堆疊則透過來源線結尾。One end of each stack of semiconductor strips ends with a stepped structure and ends with the source line as the other end. For example, the stack of semiconductor strips 412, 413, 414, and 415 end through one of the stepped structures 412A, 413A, 414A, and 415A and end through the source line 428 at the other end. At the proximal end of the figure, a portion of the semiconductor strip stack ends through the stepped structures 402B, 403B, 404B, and 405B, while all other portions of the semiconductor strip stack end through the source line. At the distal end of the figure, all of the other portions of the semiconductor strip stack are passed through the stepped structures 412A, 413A, 414A, and 415A, and the portion of the semiconductor strip stack is terminated through the source line.

位元線及串列選擇線形成於金屬層ML1、ML2以及ML3，且討論於較明顯的下圖。The bit line and the string selection line are formed in the metal layers ML1, ML2, and ML3, and are discussed in the more obvious lower view.

電晶體於階梯結構412A、413A、414A及字元線425-1之間形成。在電晶體中，半導體帶(也就是413)用作裝置的通道區域。SSL閘極結構(也就是419及409)在使字元線425-1至425-n成形的相同步驟期間被刻紋。矽化物層可沿字元線425-1至425-n與接地選擇線426及427的頂面形成，以及形成於閘極結構409及419之上。記憶體材料415的層可用做電晶體的閘極介電質。這些電晶體用作耦接於解碼電路系統的串列選擇閘極，以選擇陣列中的特定脊形堆疊。The transistor is formed between the stepped structures 412A, 413A, 414A and the word line 425-1. In a transistor, a semiconductor strip (ie, 413) is used as the channel region of the device. The SSL gate structures (i.e., 419 and 409) are scribed during the same steps that shape the word lines 425-1 through 425-n. A telluride layer can be formed along the top surfaces of the word lines 425-1 through 425-n and the ground select lines 426 and 427, and over the gate structures 409 and 419. The layer of memory material 415 can be used as the gate dielectric of the transistor. These transistors are used as a series select gate coupled to the decoding circuitry to select a particular ridge stack in the array.

圖21及22繪示圖20所示的第一3D NAND快閃記憶體陣列結構之側圖。圖21顯示了所有三個金屬層ML1、ML2及ML3。圖22顯示了較低的兩個金屬層ML1及ML2，其中移除了第三金屬層ML3以使其他金屬層較容易檢視。21 and 22 are side views of the first 3D NAND flash memory array structure shown in FIG. Figure 21 shows all three metal layers ML1, ML2 and ML3. Figure 22 shows the lower two metal layers ML1 and ML2 with the third metal layer ML3 removed to make the other metal layers easier to view.

第一金屬層ML1包括了具平行於半導體材料帶之縱向導向的串列選擇線。這些ML1串列選擇線透過短通孔而連接至不同的SSL閘極結構(也就是409及419)。The first metal layer ML1 includes a string selection line having a longitudinal orientation parallel to the strip of semiconductor material. These ML1 serial select lines are connected to different SSL gate structures (ie, 409 and 419) through short vias.

第二金屬層ML2包括了具平行於字元線的橫向導向之串列選擇線。這些ML2串列選擇線透過短通孔而連接至不同的ML1串列選擇線。The second metal layer ML2 includes a string selection line having a lateral orientation parallel to the word line. These ML2 serial select lines are connected to different ML1 string select lines through short vias.

相結合後，這些ML1串列選擇線以及ML2串列選擇線容許了使用串列選擇訊號來選擇半導體帶的特定堆疊。When combined, these ML1 serial select lines and ML2 tandem select lines allow the use of a series select signal to select a particular stack of semiconductor strips.

第一金屬層ML1也包括了兩條具有平行於字元線的橫向導向之來源線。The first metal layer ML1 also includes two source lines having lateral orientations parallel to the word lines.

最後，第三金屬層ML3包括了具有平行於半導體材料帶的縱向導向之位元線。不同位元線電性連接至階梯結構412A、413A、414A及415A及402B、403B、404B及405B的不同階。這些ML3位元線容許了使用位元線訊號來選擇半導體帶的特定水平平面。Finally, the third metal layer ML3 comprises a bit line having a longitudinal orientation parallel to the strip of semiconductor material. The different bit lines are electrically connected to different steps of the step structures 412A, 413A, 414A and 415A and 402B, 403B, 404B and 405B. These ML3 bit lines allow the use of bit line signals to select a particular horizontal plane of the semiconductor strip.

因為特定字元線容許了字元線選擇記憶體單元的特定列平面，字元線訊號、位元線訊號以及串列選擇線訊號的三重組合足以從記憶體單元的3D陣列中選擇特定記憶體單元。Since the specific word line allows the character line to select a particular column plane of the memory cell, the triple combination of the word line signal, the bit line signal, and the serial line signal is sufficient to select a particular memory from the 3D array of memory cells. unit.

圖23-26繪示具有平行於字元線的橫向導向串列選擇線、平行於半導體帶的縱向導向串列選擇線以及平行於半導體材料帶的縱向導向位元線之漸高金屬層的第一3D NAND快閃記憶體陣列結構。23-26 illustrate a laterally directed string select line parallel to the word line, a longitudinal guide string select line parallel to the semiconductor strip, and a progressive metal layer parallel to the longitudinal guide bit line of the strip of semiconductor material. A 3D NAND flash memory array structure.

圖23-26所示的第二3D NAND快閃記憶體陣列大致與圖20-22所示的第一3D NAND快閃記憶體陣列相似。為了更利於檢視，圖26進一步地移除所有的三個金屬層ML1、ML2及ML3。The second 3D NAND flash memory array shown in Figures 23-26 is generally similar to the first 3D NAND flash memory array shown in Figures 20-22. To facilitate viewing, Figure 26 further removes all three metal layers ML1, ML2, and ML3.

然而，圖23-26所示的第二3D NAND快閃記憶體陣列顯示了32條字元線，而圖20-22所示的第一3D NAND快閃記憶體陣列則顯示了8條字元線。而其他的實施例則具有不同數量的字元線、位元線以及串列選擇線，以及相對應不同數量的半導體帶堆疊等等。However, the second 3D NAND flash memory array shown in Figures 23-26 shows 32 word lines, while the first 3D NAND flash memory array shown in Figures 20-22 shows 8 characters. line. Other embodiments have a different number of word lines, bit lines, and tandem select lines, as well as correspondingly different numbers of semiconductor strip stacks and the like.

並且，圖23-26所示的第二3D NAND快閃記憶體陣列顯示了以多晶矽栓將接觸栓連接至階梯結構之不同階，而圖20-22所示的第一3D NAND快閃記憶體陣列則顯示將ML3位元線連接至階梯結構不同階的金屬接觸栓。Moreover, the second 3D NAND flash memory array shown in Figures 23-26 shows the different stages of connecting the contact plugs to the stepped structure with polysilicon plugs, while the first 3D NAND flash memory shown in Figures 20-22 The array shows the metal contact plugs that connect the ML3 bit lines to different stages of the step structure.

進一步地，圖23-26所示的第二3D NAND快閃記憶體陣列具有通往ML1解碼器的串列選擇線以及通往ML2上SSL閘極結構的串列選擇線，而圖20-22所示的第一3D NAND快閃記憶體陣列則具有通往在ML2解碼器的串列選擇線以及通往ML1上SSL閘極結構的串列選擇線。Further, the second 3D NAND flash memory array shown in Figures 23-26 has a tandem select line to the ML1 decoder and a tandem select line to the SSL gate structure on the ML2, and Figures 20-22 The first 3D NAND flash memory array shown has a tandem select line to the ML2 decoder and a serial select line to the SSL gate structure on ML1.

圖27為圖20-22的第一3D NAND快閃記憶體陣列結構設計圖。27 is a structural diagram of the structure of the first 3D NAND flash memory array of FIGS. 20-22.

在圖27的設計圖中，半導體帶堆疊顯示為具點-破折號邊緣的垂直帶。相鄰的半導體帶堆疊在相對的導向之間交替，也就是在位元線端-至-來源線端導向以及來源線端-至-位元線端導向之間交替。一部分的半導體帶堆疊從頂部的位元線結構運行至底部的來源線結構。所有另一部分的半導體帶堆疊則從頂部的來源線結構運行至底部的位元線結構。In the design of Figure 27, the semiconductor strip stack is shown as a vertical strip with a dot-dash edge. Adjacent semiconductor strip stacks alternate between opposing conductors, that is, between bit line end-to-source line end directors and source line end-to-bit line end guides. A portion of the semiconductor strip stack runs from the top bit line structure to the bottom source line structure. All other portions of the semiconductor strip stack run from the top source line structure to the bottom bit line structure.

覆蓋半導體帶堆疊的是水平字元線以及水平接地選擇線GSL(偶)與GSL(奇)。覆蓋半導體帶堆疊的並且為SSL閘極結構。SSL閘極結構在半導體帶頂端覆蓋了一部分半導體帶堆疊，且在半導體帶底端覆蓋了所有其他半導體帶堆疊。在這兩種情況下，SSL閘極結構皆控制任何半導體帶堆疊與對應於堆疊的位元線接觸結構之間的電性連接。Covering the semiconductor strip stack is a horizontal word line and horizontal ground select lines GSL (even) and GSL (odd). The semiconductor strip is stacked and is an SSL gate structure. The SSL gate structure covers a portion of the semiconductor strip stack at the top of the semiconductor strip and covers all other semiconductor strip stacks at the bottom end of the semiconductor strip. In both cases, the SSL gate structure controls the electrical connection between any of the semiconductor strip stacks and the bit line contact structures corresponding to the stack.

所示的字元線編號，其從圖頂至圖底依序從1至N漸大，係應用於偶數記憶體頁。對於奇數記憶體頁，字元線編號從圖頂至圖底依序則從N至1漸小。The character line numbers shown are gradually increased from 1 to N from the top of the figure to the bottom of the figure, and are applied to even memory pages. For odd-numbered memory pages, the word line numbers are gradually reduced from N to 1 from the top of the figure to the bottom of the figure.

覆蓋字元線、接地選擇線以及SSL閘極結構的是垂直運行的ML1 SSL串列選擇線。覆蓋ML1 SSL串列選線的是水平運行的ML2 SSL串列選擇線。雖然ML2 SSL串列選擇線為了能容易檢視結構而顯示為相對應ML1 SSL串列選擇線之結尾，但ML2 SSL串列選擇線的水平運行可以更加延長。ML2 SSL串列選擇線傳送從解碼器來的訊號，而ML1 SSL串列選擇線耦接這些解碼器訊號至特定SSL閘極結構以選擇特定半導體帶堆疊。Overlay word lines, ground select lines, and SSL gate structures are vertically running ML1 SSL serial select lines. Covering the ML1 SSL serial line selection is the horizontally running ML2 SSL serial line selection line. Although the ML2 SSL serial selection line is shown as the end of the corresponding ML1 SSL serial selection line in order to easily view the structure, the horizontal operation of the ML2 SSL serial selection line can be extended. The ML2 SSL serial select line carries the signal from the decoder, and the ML1 SSL serial select line couples these decoder signals to a particular SSL gate structure to select a particular semiconductor strip stack.

覆蓋ML1 SSL串列選擇線的並且是奇數號與偶數號的來源線。The source line that covers the ML1 SSL serial selection line and is an odd number and an even number.

進一步地，覆蓋ML2 SSL串列選擇線的是於頂端及底端連接至階梯接觸結構(stepped contact structure)之ML3位元線(並無顯示於圖中)。透過階梯接觸結構，位元線能選擇半導體帶的特定平面。Further, the ML2 SSL serial selection line is covered by the ML3 bit line connected to the stepped contact structure at the top and bottom ends (not shown in the figure). Through the step contact structure, the bit line can select a particular plane of the semiconductor strip.

圖28為圖23-26第二3D NAND快閃記憶體陣列結構的設計圖。圖28所示的這個第二3D NAND快閃記憶體陣列結構大致與圖27所示的第一3D NAND快閃記憶體結構設計圖相似。然而，圖28所示的第二3D NAND快閃記憶體陣列具有通往ML1解碼器的串列選擇線以及通往ML2上SSL閘極結構的串列選擇線，而圖27顯示的第一3D NAND快閃記憶體結構則具有通往ML2解碼器的串列選擇線以及通往ML1上SSL閘極結構的串列選擇線。28 is a layout diagram of the second 3D NAND flash memory array structure of FIGS. 23-26. The second 3D NAND flash memory array structure shown in FIG. 28 is substantially similar to the first 3D NAND flash memory structure design shown in FIG. However, the second 3D NAND flash memory array shown in FIG. 28 has a tandem select line to the ML1 decoder and a tandem select line to the SSL gate structure on ML2, while the first 3D shown in FIG. The NAND flash memory structure has a serial select line to the ML2 decoder and a tandem select line to the SSL gate structure on ML1.

圖29為3D記憶體陣列的平面圖。在所示的陣列中，Y半節距=32奈米而X半節距=43奈米。在3D VG NAND中有4個記憶體層。陣列中的核心使用率(core efficiency)約為67%(66條WL，與其上的SSL閘極、GSL、SL以及BL接點)。以單階單元(single level cell)運作時(1b/c)其密度為32Gb。晶片大小約為76 mm² 。Figure 29 is a plan view of a 3D memory array. In the array shown, Y half pitch = 32 nm and X half pitch = 43 nm. There are 4 memory layers in 3D VG NAND. The core efficiency in the array is approximately 67% (66 WLs, with SSL gates, GSL, SL, and BL contacts). When operating in a single level cell (1b/c), its density is 32Gb. The wafer size is approximately 76 mm ² .

圖30繪示具有平行於字元線的橫向導向串列選擇線、平行於半導體帶的縱向導向串列選擇線以及平行於半導體材料帶的縱向導向位元線之漸高金屬層的3D NAND快閃記憶體陣列結構。圖30相似於圖23。圖30相較於圖23的更動為將第一組陣列層編號(1)-(4)增加至位元線，以及將第二組陣列層編號(1)-(4)增加至包括階梯結構402B、403B、404B及405B的位元線結構。這些陣列層編號組乃用以顯示特定位元線電性連接至特定陣列層位置。Figure 30 illustrates a 3D NAND fast with a laterally directed string select line parallel to the word line, a longitudinal guide string select line parallel to the semiconductor strip, and a progressive metal layer parallel to the longitudinal guide bit line of the strip of semiconductor material. Flash memory array structure. Figure 30 is similar to Figure 23. Figure 30 is a comparison of the change of Figure 23 to the first set of array layer numbers (1) - (4) to the bit line, and the second set of array layer numbers (1) - (4) to include the step structure Bit line structure of 402B, 403B, 404B, and 405B. These array layer number groups are used to display that a particular bit line is electrically connected to a particular array layer location.

圖30顯示了具有1、2、3及4平面位置序列的記憶體區塊。相對應地，如同位元線結構從第一端橫越至第二端，連續編號的位元線1-4(也就是從左至右、從右至左或其他連續的順序來編號)藉由階梯接觸結構(也可稱之為位元線結構)耦接至平面位置1-4(也就是從頂到底、從底到頂或其他順序來編號)。Figure 30 shows a memory block having a sequence of 1, 2, 3, and 4 planar positions. Correspondingly, as the bit line structure traverses from the first end to the second end, consecutively numbered bit lines 1-4 (that is, numbered from left to right, right to left, or other consecutive order) are borrowed. The step contact structure (also referred to as a bit line structure) is coupled to plane positions 1-4 (ie, numbered from top to bottom, bottom to top, or other order).

圖31為具有以特定位元線存取陣列層之編號標示的位元線之3D NAND快閃記憶體陣列結構設計圖。在所示的範例中，如同依序橫越的4條位元線(也就是從左至右、從右至左或其他順序來編號)，也將位元線以平面位置1、2、3及4來標示。所以如同依序橫越的4條位元線，也將位元線藉由以破折號方框顯示的階梯接觸結構(也可稱之為位元線結構)耦接至平面位置1-4(也就是從頂至底、從底至頂或其他順序來編號)。Figure 31 is a block diagram showing the structure of a 3D NAND flash memory array having bit lines labeled with the number of the access layer arrays in a particular bit line. In the example shown, as with the four bit lines that are traversed sequentially (that is, numbered from left to right, right to left, or other order), the bit lines are also in plane positions 1, 2, and 3. And 4 to mark. Therefore, as with the four bit lines that are sequentially traversed, the bit lines are also coupled to the plane positions 1-4 by a step contact structure (also referred to as a bit line structure) displayed in a dashed box. It is numbered from top to bottom, bottom to top or other order).

圖32為具有以位元線存取之陣列層的編號標示之位元線3DNAND快閃記憶體陣列結構設計圖，顯示了相鄰具有以不同序列耦接至陣列層之位元線的區塊。32 is a block diagram of a bit line 3DNAND flash memory array structure having numbered arrays accessed by bit lines, showing blocks adjacent to bit lines coupled to the array layer in different sequences. .

圖32顯示了不同位元線結構具有平面位置的平移序列。舉例來說，所顯示的不同位元線結構平面位置之不同序列為1、2、3及4；2、3、4及1；以及3、4、1及2。相對應地最左邊從頂運行至底且連接於不同位元線結構的位元線，係連接至平面位置1、2及3(以從頂位元線結構至底位元線結構的順序)。第二左邊從頂運行至底且連接至不同位元線結構的位元線，係連接至平面位置2、3及4(以從頂位元線結構至底位元線結構的順序)。第三左邊從頂運行至底且連接至不同位元線結構的位元線，係連接至平面位置3、4及1(以從頂位元線結構至底位元線結構的順序)。第四左邊從頂運行至底且連接至不同位元線結構的位元線，係連接至平面位置4、1及2(以從頂位元線結構至底位元線結構的順序)。Figure 32 shows a translation sequence with different bit line structures having planar positions. For example, the different sequences of the different bit line structure plane positions shown are 1, 2, 3, and 4; 2, 3, 4, and 1; and 3, 4, 1, and 2. Correspondingly, the bit line running from the top to the bottom and connected to different bit line structures is connected to the plane positions 1, 2 and 3 (in order from the top bit line structure to the bottom bit line structure) . The second left bit runs from top to bottom and is connected to bit lines of different bit line structures, connected to plane positions 2, 3, and 4 (in order from top bit line structure to bottom bit line structure). The third left run from top to bottom and connected to different bit line structures is connected to plane positions 3, 4 and 1 (in order from top bit line structure to bottom bit line structure). The fourth left bit runs from top to bottom and is connected to bit lines of different bit line structures, connected to plane positions 4, 1 and 2 (in order from top bit line structure to bottom bit line structure).

在某些實施例中，選擇位元線結構的編號以及記憶體區塊的編號是為了使每條字元線皆如其他字元線具有相同的所謂之電容，其原因為耦接的為相同於其他位元線之平面位置組合。In some embodiments, the number of the bit line structure and the number of the memory block are selected such that each word line has the same so-called capacitance as other word lines, because the coupling is the same. Combine in the plane position of other bit lines.

多種實施例包括了不同數量的位元線以及不同數量的耦接至位元線之平面位置，例如兩倍或二次方。Various embodiments include a different number of bit lines and a different number of planar positions coupled to the bit lines, such as double or quadratic.

雖本發明已以較佳實施例及範例詳述如上，然需知其乃用以舉例說明而非限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention has been described in detail with reference to the preferred embodiments and examples thereof. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10、110、210、212、214．．．絕緣層10, 110, 210, 212, 214. . . Insulation

11-14、51-56、111-114．．．半導體帶11-14, 51-56, 111-114. . . Semiconductor strip

15、115、215、315．．．記憶體材料層15, 115, 215, 315. . . Memory material layer

16、17、60-61、116、117、160、161、260．．．字元線16, 17, 60-61, 116, 117, 160, 161, 260. . . Word line

18、19、118、119、226．．．矽化物18, 19, 118, 119, 226. . . Telluride

20、120、220．．．溝槽20, 120, 220. . . Trench

21-24、121-124．．．絕緣材料21-24, 121-124. . . Insulation Materials

25、26．．．主動區25, 26. . . Active zone

30-35、40-45．．．記憶體單元30-35, 40-45. . . Memory unit

60-1~60-3．．．字元線延長部分60-1~60-3. . . Character line extension

97、397．．．穿隧介電層97, 397. . . Tunneling dielectric layer

98、398．．．電荷儲存層98, 398. . . Charge storage layer

99、399．．．阻擋介電層99, 399. . . Blocking dielectric layer

125、126．．．電荷設陷區域125, 126. . . Charge trapping area

128-130．．．源極/汲極區域128-130. . . Source/drain region

70、71、73、74、76、77、80、82、84．．．NAND串列中之記憶體單元70, 71, 73, 74, 76, 77, 80, 82, 84. . . Memory unit in NAND string

72、75、78、90-95．．．接地選擇電晶體72, 75, 78, 90-95. . . Ground selection transistor

96．．．位元線96. . . Bit line

85、89．．．串列選擇電晶體85, 89. . . Tandem selection transistor

88．．．挽線88. . . Thread

106、108．．．串列選擇線106, 108. . . Serial selection line

107．．．來源線107. . . Source line

159、162．．．接地選擇訊號159, 162. . . Ground selection signal

113A、114A．．．半導體帶側面113A, 114A. . . Side of semiconductor strip

110A．．．絕緣層表面110A. . . Insulation surface

128a-130a．．．沿半導體帶側面的區域128a-130a. . . Along the side of the semiconductor strip

211、213．．．半導體層211, 213. . . Semiconductor layer

250．．．半導體帶之脊形堆疊250. . . Ridge stacking of semiconductor strips

225．．．層225. . . Floor

858、958．．．平面解碼器858, 958. . . Planar decoder

96、859、959．．．位元線96, 859, 959. . . Bit line

860、960．．．記憶體陣列860, 960. . . Memory array

861、961．．．列解碼器861, 961. . . Column decoder

862、962．．．字元線862, 962. . . Word line

863、963．．．行解碼器863, 963. . . Row decoder

864、964．．．串列選擇線864, 964. . . Serial selection line

865、965．．．匯流排865, 965. . . Busbar

866、966．．．方塊866, 966. . . Square

867、967．．．資料匯流排867, 967. . . Data bus

868、968．．．方塊868, 968. . . Square

869、969．．．偏壓設置狀態機869, 969. . . Bias setting state machine

871、971．．．資料輸入線871, 971. . . Data input line

872、972．．．資料輸出線872, 972. . . Data output line

874、974．．．其他電路系統874, 974. . . Other circuit systems

875、975．．．積體電路875, 975. . . Integrated circuit

402-405、412-415．．．半導體帶402-405, 412-415. . . Semiconductor strip

402B-405B、412A-415A．．．階梯結構402B-405B, 412A-415A. . . Step structure

409、419．．．串列選擇線閘極結構409, 419. . . Tandem selection line gate structure

426、427．．．接地選擇線426, 427. . . Ground selection line

425-1~425-N．．．字元線425-1~425-N. . . Word line

428．．．來源線428. . . Source line

圖1為在此描述的3D記憶體結構透視圖，包括複數個平行於Y軸且設置於複數個脊形堆疊中的半導體材料帶之平面、位於半導體帶側面的記憶體層以及複數條具共形底面且跨越該些脊形堆疊而設置的字元線。1 is a perspective view of a 3D memory structure as described herein, including a plurality of planes of a strip of semiconductor material parallel to the Y-axis and disposed in a plurality of ridge stacks, a memory layer on a side of the semiconductor strip, and a plurality of conformal features. A word line disposed on the bottom surface and spanning the ridge stacks.

圖2為從圖1結構中X-Z平面所擷取的記憶體單元截面。2 is a cross section of a memory cell taken from the X-Z plane of the structure of FIG. 1.

圖3為從圖1結構中X-Y平面所擷取的記憶體單元截面。Figure 3 is a cross section of the memory cell taken from the X-Y plane of the structure of Figure 1.

圖4係繪示具有圖1結構以反熔絲為基礎的記憶體概要圖。4 is a schematic diagram of a memory having an antifuse based on the structure of FIG. 1.

圖5為在此描述的3D NAND快閃記憶體結構透視圖，包括複數個平行於Y軸且設置於複數個脊形堆疊的半導體帶平面、一位於半導體帶側面上的電荷設陷記憶體層以及複數條具共形底面且跨越該些脊形堆疊而設置的字元線。5 is a perspective view of a 3D NAND flash memory structure as described herein, including a plurality of semiconductor strip planes parallel to the Y-axis and disposed in a plurality of ridge stacks, a charge trapping memory layer on a side of the semiconductor strip, and A plurality of word lines having a conformal bottom surface and disposed across the plurality of ridge stacks.

圖6為從圖5結構中X-Z平面所擷取的記憶體單元截面。Figure 6 is a cross section of the memory cell taken from the X-Z plane of the structure of Figure 5.

圖7為從圖5結構中X-Y平面所擷取的記憶體單元截面。Figure 7 is a cross section of the memory cell taken from the X-Y plane of the structure of Figure 5.

圖8係繪示具有圖5及圖23結構的NAND快閃記憶體概要圖。FIG. 8 is a schematic diagram of a NAND flash memory having the structure of FIGS. 5 and 23.

圖9為類似於圖5的3D NAND快閃記憶體結構之另一種實施方式透視圖，其中記憶體層從字元線之間被移除。9 is a perspective view of another embodiment of a 3D NAND flash memory structure similar to that of FIG. 5 with the memory layers removed from between the word lines.

圖10為從圖9結構中X-Z平面所擷取的記憶體單元截面。Figure 10 is a cross section of the memory cell taken from the X-Z plane of the structure of Figure 9.

圖11為從圖9結構中X-Y平面所擷取的記憶體單元截面。Figure 11 is a cross section of the memory cell taken from the X-Y plane of the structure of Figure 9.

圖12係繪示製造類似於圖1、5及9記憶體裝置的程序之第一階段。Figure 12 illustrates the first stage of a process for fabricating a memory device similar to that of Figures 1, 5 and 9.

圖13係繪示製造類似於圖1、5及9記憶體裝置的程序之第二階段。Figure 13 illustrates the second stage of a process for fabricating a memory device similar to that of Figures 1, 5 and 9.

圖14A係繪示製造類似於圖1記憶體裝置的程序之第三階段。Figure 14A illustrates a third stage of making a program similar to the memory device of Figure 1.

圖14B係繪示製造類似於圖5記憶體裝置的程序之第三階段。Figure 14B is a diagram showing the third stage of manufacturing a program similar to the memory device of Figure 5.

圖15係繪示製造類似於圖1、5及9記憶體裝置的程序之第三階段。Figure 15 is a diagram showing the third stage of manufacturing a program similar to the memory devices of Figures 1, 5 and 9.

圖16係繪示製造類似於圖1、5及9記憶體裝置的程序之第四階段，緊接著的為一硬掩膜以及一選擇性植入步驟之另一個階段。Figure 16 illustrates the fourth stage of a process for fabricating a memory device similar to that of Figures 1, 5, and 9, followed by another stage of a hard mask and a selective implantation step.

圖17為一張3D NAND快閃記憶體陣列部分的透射電子顯微鏡(transmission electron microscope,TEM)影像。Figure 17 is a transmission electron microscope (TEM) image of a 3D NAND flash memory array portion.

圖18為包括具有行、列及平面解碼電路系統的3D可編程電阻記憶體陣列的積體電路之概要圖。Figure 18 is a schematic diagram of an integrated circuit including a 3D programmable resistive memory array having row, column and planar decoding circuitry.

圖19為包括具有行、列及平面解碼電路系統的3D NAND快閃記憶體陣列的積體電路之概要圖。Figure 19 is a schematic diagram of an integrated circuit including a 3D NAND flash memory array having row, column and planar decoding circuitry.

圖20-22係繪示第一個具縱向平行於半導體材料帶之串列選擇線的遞高金屬層之3D NAND快閃記憶體陣列結構、橫向平行於字元線的串列選擇線以及具縱向平行於半導體材料帶的位元線。20-22 illustrate a first 3D NAND flash memory array structure having a raised metal layer longitudinally parallel to the tandem select lines of the strip of semiconductor material, a tandem select line laterally parallel to the word line, and The longitudinal direction is parallel to the bit line of the strip of semiconductor material.

圖23-26係繪示第二個具縱向平行於半導體材料帶之串列選擇線的遞高金屬層之3D NAND快閃記憶體陣列結構、橫向平行於字元線的串列選擇線以及具縱向平行於半導體材料帶的位元線。23-26 illustrates a second 3D NAND flash memory array structure having a raised metal layer longitudinally parallel to the tandem select lines of the semiconductor material strip, a tandem select line laterally parallel to the word line, and The longitudinal direction is parallel to the bit line of the strip of semiconductor material.

圖27為圖20-22之該第一3D NAND快閃記憶體陣列結構的設計圖。FIG. 27 is a layout diagram of the first 3D NAND flash memory array structure of FIGS. 20-22.

圖28為圖23-26之該第二3D NAND快閃記憶體陣列結構的設計圖。28 is a layout diagram of the second 3D NAND flash memory array structure of FIGS. 23-26.

圖29為一3D記憶體陣列的平面圖。Figure 29 is a plan view of a 3D memory array.

圖30係繪示被位元線存取並且具有陣列層編號標示的位元線之3D NAND快閃記憶體陣列結構。Figure 30 is a diagram showing a 3D NAND flash memory array structure accessed by bit lines and having bit lines labeled by array layer numbers.

圖31為被位元線存取並且具有陣列層編號標示之3D NAND快閃記憶體陣列結構之設計圖。Figure 31 is a block diagram of a 3D NAND flash memory array structure accessed by bit lines and having an array layer number designation.

圖32為被位元線存取並且具有陣列層編號標示之3D NAND快閃記憶體陣列結構之設計圖，並展示了具有在不同序列中耦接於陣列層之位元線的相鄰區塊。32 is a design diagram of a 3D NAND flash memory array structure accessed by bit lines and having an array layer number designation, and showing adjacent blocks having bit lines coupled to the array layers in different sequences. .

ML1-3．．．金屬層ML1-3. . . Metal layer

412A~415A、402B~405B．．．階梯結構412A~415A, 402B~405B. . . Step structure

402~405、412~415．．．半導體帶402~405, 412~415. . . Semiconductor strip

419．．．串列選擇線閘極結構419. . . Tandem selection line gate structure

426、427．．．接地選擇線426, 427. . . Ground selection line

425-1~425-N．．．字元線425-1~425-N. . . Word line

428．．．來源線428. . . Source line

Claims

一記憶體裝置，包括：一記憶體陣列，係具有位於複數個平面位置的複數記憶體單元；複數個階梯接觸結構，係具有複數個平面位置的複數個序列，該些序列至少包括兩相異序列，每個該些序列係描繪了該些階梯接觸結構之一階梯接觸結構耦接至複數條位元線的該些平面位置之順序特徵；其中，位於該些階梯接觸結構之相鄰兩階梯接觸結構中的部分該記憶體陣列中的該些位元線之一者，耦接至位於該些平面位置之一者上的該些記憶體單元，並且不會和位於該些平面位置之其他者上的該些記憶體單元耦接。 A memory device comprising: a memory array having a plurality of memory cells at a plurality of planar positions; and a plurality of step contact structures having a plurality of sequences having a plurality of planar positions, the sequences comprising at least two different a sequence, each of the sequences depicting sequential features of the planar contact locations of the step contact structures coupled to the plurality of bit lines; wherein the adjacent two steps of the step contact structures And a portion of the plurality of bit lines in the memory array in the contact structure, coupled to the memory cells located on one of the planar locations, and not in other locations located at the planar locations The memory units on the device are coupled.

如申請專利範圍第1項所述之記憶體裝置，其中該陣列的該些記憶體單元係在NAND串列中沿複數個半導體材料帶而設置。 The memory device of claim 1, wherein the memory cells of the array are disposed along a plurality of strips of semiconductor material in a NAND string.

如申請專利範圍第1項所述之記憶體裝置，其中該記憶體陣列的該些記憶體單元係沿該些階梯接觸結構與複數個來源線結構之間的複數個半導體材料帶而設置。 The memory device of claim 1, wherein the memory cells of the memory array are disposed along a plurality of semiconductor material strips between the step contact structures and the plurality of source lines.

如申請專利範圍第1項所述之記憶體裝置，其中相異的電容係描繪了該些平面位置的相異平面位置之特徵。 The memory device of claim 1, wherein the different capacitances characterize the different planar positions of the planar locations.

如申請專利範圍第1項所述之記憶體裝置，其中該些階梯接觸結構的該些序列之該些相異序列，係平均了描繪該些平面位置之相異平面位置特徵的相異電容。 The memory device of claim 1, wherein the different sequences of the sequences of the step contact structures are flat The distinct capacitances depicting the different planar positional features of the planar locations are all described.

如申請專利範圍第1項所述之記憶體裝置，其中該些階梯接觸結構之該階梯接觸結構與該些位元線的該些平面位置耦接的順序，係從該些階梯接觸結構之該階梯接觸結構之一第一末端橫跨對應至該階梯接觸結構之一第二末端。 The memory device of claim 1, wherein the step contact structure of the step contact structures is coupled to the planar positions of the bit lines from the step contact structures A first end of the step contact structure spans a second end corresponding to one of the step contact structures.

如申請專利範圍第1項所述之記憶體裝置，其中該記憶體陣列係以該些階梯接觸結構分隔為複數個記憶體區塊。 The memory device of claim 1, wherein the memory array is divided into a plurality of memory blocks by the step contact structures.

如申請專利範圍第1項所述之記憶體裝置，其中該記憶體陣列中的複數個半導體材料帶堆疊之一特定半導體帶以及該記憶體陣列中的複數條字元線之一條特定字元線的組合選擇，係用以識別該記憶體陣列中之一特定記憶體單元。 The memory device of claim 1, wherein the plurality of semiconductor material strips in the memory array are stacked in a specific semiconductor strip and one of a plurality of word lines in the memory array is a specific word line The combined selection is used to identify a particular memory unit in the memory array.

如申請專利範圍第1項所述之記憶體裝置，其中該記憶體陣列的該些記憶體單元係包括複數個電荷設陷結構，該些電荷設陷結構係包括一穿隧層、一電荷設陷層以及一阻擋層。 The memory device of claim 1, wherein the memory cells of the memory array comprise a plurality of charge trapping structures, the charge trapping structures comprising a tunneling layer and a charge a trap layer and a barrier layer.

如申請專利範圍第1項所述之記憶體裝置，包括：一基板；複數個半導體材料帶堆疊，係為脊形，且包括至少兩個半導體材料帶，該些半導體材料帶係以絕緣材料分隔於複數個平面位置；複數條字元線，該些字元線係跨越該些堆疊而設置，且具有與該些堆疊共形(conformal)之表面；以及位於一介面區域中之複數個記憶體元件，該些記憶體元件係透過該些半導體材料帶與該些字元線建立該些記憶體單元的記憶體陣列；其中該些階梯接觸結構係位於該些堆疊之末端。 The memory device of claim 1, comprising: a substrate; a plurality of semiconductor material strips stacked in a ridge shape, and comprising at least two strips of semiconductor material separated by an insulating material In a plurality of plane positions; a plurality of word lines disposed across the stacks and having a conformal surface with the stacks; and a plurality of memory elements located in an interface region, the memories The component establishes a memory array of the memory cells through the strips of semiconductor material and the word lines; wherein the step contact structures are located at the ends of the stacks.

一記憶體裝置，包括：一記憶體陣列，係具有位於複數個平面位置中的複數個記憶體單元；以及複數條位元線，每條該些位元線係耦接至該些平面位置的至少兩相異平面位置，並且於上述至少兩相異平面位置存取該些記憶體單元；其中，在部分該記憶體陣列中的該些位元線之一者，耦接至位於該些平面位置之一者上的該些記憶體單元，並且不會和位於該些平面位置之其他者上的該些記憶體單元耦接。 A memory device includes: a memory array having a plurality of memory cells in a plurality of planar positions; and a plurality of bit lines, each of the bit lines being coupled to the planar positions Having at least two different planar positions, and accessing the memory cells at the at least two different planar positions; wherein, one of the bit lines in the portion of the memory array is coupled to the planes The memory cells on one of the locations are not coupled to the memory cells located on the other of the planar locations.

如申請專利範圍第11項所述之記憶體裝置，其中該記憶體陣列的該些記憶體單元係在NAND串列中沿複數個半導體材料帶而設置。 The memory device of claim 11, wherein the memory cells of the memory array are disposed along a plurality of semiconductor material strips in a NAND string.

如申請專利範圍第11項所述之記憶體裝置，其中該記憶體陣列的該些記憶體單元係沿複數個階梯接觸結構與複數個來源線結構之間的複數個半導體材料帶而設置。 The memory device of claim 11, wherein the memory cells of the memory array are disposed along a plurality of semiconductor material strips between the plurality of step contact structures and the plurality of source lines.

如申請專利範圍第11項所述之記憶體裝置，其中相異的電容係描繪了該些平面位置的相異平面位置之特徵。 The memory device of claim 11, wherein the different capacitances describe different planar positions of the planar positions. Characteristics.

如申請專利範圍第13項所述之記憶體裝置，其中該記憶體陣列係以該些階梯接觸結構分隔為複數個記憶體區塊。 The memory device of claim 13, wherein the memory array is divided into a plurality of memory blocks by the step contact structures.

如申請專利範圍第11項所述之記憶體裝置，其中該陣列中的複數個半導體材料帶堆疊之一特定半導體帶以及該記憶體陣列中的該些字元線之一條特定字元線的組合選擇，係用以識別該記憶體陣列中之一特定記憶體單元。 The memory device of claim 11, wherein a plurality of semiconductor material strips in the array are associated with a specific semiconductor strip and a combination of a plurality of word lines of the word lines in the memory array The selection is used to identify a particular memory unit in the array of memory.

如申請專利範圍第11項所述之記憶體裝置，其中該記憶體陣列的該些記憶體單元係包括複數個電荷設陷結構，該些電荷設陷結構係包括一穿隧層、一電荷設陷層以及一阻擋層。 The memory device of claim 11, wherein the memory cells of the memory array comprise a plurality of charge trapping structures, the charge trapping structures comprising a tunneling layer and a charge a trap layer and a barrier layer.

如申請專利範圍第13項所述之記憶體裝置，包括：一基板；複數個半導體材料帶堆疊，係為脊形，且包括至少兩個半導體材料帶，該些半導體材料帶係以絕緣材料分隔於複數個平面位置；複數條字元線，該些字元線係跨越該些堆疊而設置，且具有與該些堆疊共形(conformal)之表面；以及位於一介面區域中之複數個記憶體元件，該些記憶體元件係透過該些半導體材料帶與該些字元線建立該些記憶體單元的記憶體陣列；其中該些階梯接觸結構係位於該些堆疊之末端。 The memory device of claim 13, comprising: a substrate; a plurality of semiconductor material strips stacked in a ridge shape, and comprising at least two strips of semiconductor material separated by an insulating material a plurality of plane positions; a plurality of word lines disposed across the stacks and having a conformal surface with the stacks; and a plurality of memories located in an interface region And a memory device that establishes a memory array of the memory cells through the strips of semiconductor material and the word lines; wherein the step contact structures are located at ends of the stacks.

如申請專利範圍第18項所述之記憶體裝置，其中該些位元線的每條位元線係耦接至該些半導體材料帶堆疊中相異堆疊的至少兩相異平面位置，其中上述之兩相異平面位置係包括一第一半導體帶堆疊之一第一平面位置以及一第二半導體帶堆疊之一第二平面位置，使得該第一半導體帶堆疊以及該第二半導體帶堆疊為相異記憶體區塊。 The memory device of claim 18, wherein each of the bit lines is coupled to at least two different planar positions of the different stacked stacks of semiconductor material strips, wherein The two different planar positions include a first planar position of a first semiconductor strip stack and a second planar position of a second semiconductor strip stack such that the first semiconductor strip stack and the second semiconductor strip stack are phased Different memory blocks.

如申請專利範圍第18項所述之記憶體裝置，其中該些位元線的每條位元線耦接該些半導體材料帶堆疊中相異堆疊的至少兩相異平面位置，其中上述之兩相異平面位置係包括該第一半導體帶堆疊之該第一平面位置以及該第二半導體帶堆疊之該第二平面位置，使得該第一半導體帶堆疊以及該第二半導體帶堆疊得以被該些字元線之相異組字元線所存取。 The memory device of claim 18, wherein each of the bit lines is coupled to at least two different planar positions of the different stacked stacks of semiconductor material strips, wherein the two The dissimilar planar position includes the first planar position of the first semiconductor strip stack and the second planar position of the second semiconductor strip stack such that the first semiconductor strip stack and the second semiconductor strip stack are The different group of character lines of the word line are accessed.