TWI489465B - Low voltage programming in nand flash with two stage source side bias - Google Patents
Low voltage programming in nand flash with two stage source side bias Download PDFInfo
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本發明係關於快閃記憶體技術，特別是關於在反及閘組態中合適作為低電壓程式化及抹除操作的快閃記憶體。This invention relates to flash memory technology, and more particularly to flash memory suitable for low voltage stylization and erase operations in an anti-gate configuration.
快閃記憶體是非揮發積體電路記憶體技術的一類。傳統的快閃記憶體使用浮動閘極記憶胞。隨著記憶裝置之密度提升，浮動閘極記憶胞之間逾加靠近，儲存在相鄰浮動閘極中的電荷交互影響即造成問題，因此形成限制，使得採用浮動閘極之快閃記憶體密度無法提升。另一種快閃記憶體所使用之記憶胞稱為電荷捕捉記憶胞，其採用電荷捕捉層取代浮動閘極。電荷捕捉記憶胞係利用電荷捕捉材料，不會如浮動閘極造成個別記憶胞之間的相互影響，並且可以應用於高密度的快閃記憶體。Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory uses floating gate memory cells. As the density of the memory device increases, the floating gate memory cells are closer together, and the charge interaction stored in the adjacent floating gates causes a problem, thus forming a limitation, so that the floating gate density of the floating gate is used. Unable to upgrade. Another type of memory cell used in flash memory is called a charge trapping memory cell, which uses a charge trapping layer instead of a floating gate. The charge trapping memory cell utilizes a charge trapping material that does not cause interaction between individual memory cells as a floating gate, and can be applied to high density flash memory.
典型的電荷儲存記憶胞包含一場效電晶體(FET)結構，其中包含由通道所分隔之源極與汲極，以及藉由一電荷儲存結構而與通道分離的閘極，其中該電荷儲存結構包含穿隧介電層、電荷儲存層(浮動閘極或介電層)、與阻障介電層。較早的傳統設計如SONOS裝置，其中源極、汲極與通道形成於矽基材(S)上，穿隧介電層則由氧化矽(O)之上，電荷儲存層由氮化矽形成(N)，阻障介電層由氧化矽(O)形成，而閘極則為多晶矽(S)。A typical charge storage memory cell includes a field effect transistor (FET) structure including a source and a drain separated by a channel, and a gate separated from the channel by a charge storage structure, wherein the charge storage structure comprises A tunneling dielectric layer, a charge storage layer (floating gate or dielectric layer), and a barrier dielectric layer. Earlier conventional designs, such as SONOS devices, in which the source, drain and channel are formed on the germanium substrate (S), the tunneling dielectric layer is over the germanium oxide (O), and the charge storage layer is formed of tantalum nitride. (N), the barrier dielectric layer is formed of ruthenium oxide (O), and the gate is polycrystalline germanium (S).
快閃記憶體裝置通常可以使用反及閘(NAND)或是反或閘(NOR)架構來施作，但也可以是其他的架構，包括及閘(AND)架構。此反及閘(NAND)架構特別因為其在資料儲存應用方面的高密度及高速的優點而受到青睞。而反或閘(NOR)架構則是適合於例如是程式法儲存等其他應用上，因為隨機存取是重要的功能需求。在一反及閘(NAND)架構中，程式化過程通常是依賴富勒-諾得漢(FN)穿隧，且需要高電壓，通常是在20伏特數量級，且需要高電壓電晶體來處理。此額外的高電壓電晶體及搭配使用於邏輯和其他資料流的電晶體於同一積體電路中，會造成製程的複雜性增加。如此則會增加此裝置的製造成本。Flash memory devices can typically be implemented using either a NAND or a NOR architecture, but can be other architectures, including an AND architecture. This NAND architecture is favored especially for its high density and high speed advantages in data storage applications. The inverse OR gate (NOR) architecture is suitable for other applications such as program storage, because random access is an important functional requirement. In a NAND architecture, the stylization process typically relies on Fuller-Nordheim (FN) tunneling and requires high voltages, typically on the order of 20 volts, and requires high voltage transistors for processing. This extra high-voltage transistor and the transistors used in logic and other data streams are in the same integrated circuit, which increases the complexity of the process. This will increase the manufacturing cost of the device.
因此，需要提供一種新的記憶體技術，其可以在反及閘(NAND)架構中利用低電壓即可程式化操作。Therefore, there is a need to provide a new memory technology that can be programmed with low voltage in a NAND architecture.
此處所描述之記憶裝置，組態為低電壓操作，其包含複數個記憶胞串聯安排於一半導體主體中，例如可以被應用於反及閘陣列的反及閘串列中，具有複數條字元線與對應的記憶胞耦接。控制電路與該複數條位元線及半導體主體耦接，以適合藉由熱載子注入對一所選取記憶胞進行程式化，這些熱載子是使用控制的字元線電壓於一目標記憶胞上，在此稱為切換電壓V-SW。一源極端電壓施加於此串列的一側，其是共同接地或是其他特定電壓以作為源極端電壓。所選取記憶胞在程式化時施加源極端電壓的一側在此稱為"等效源極端"或是"等效源極"。一汲源極端電壓VD 施加於此串列的另一側，其是施加一供應電位在此業界通常稱為VDD 或VCC ，或是其他特定電壓以作為汲極端電壓。所選取記憶胞在程式化時施加汲極端電壓的一側在此稱為"等效汲極端"或是"等效汲極"。為了控制切換記憶胞的電導，在程式化區間的一部分時V-SW設置至一偏壓條件在鄰接目標記憶胞的主體建立一條件以支援足夠熱電場(汲極至源極電壓)且足夠的通道電流於此目標記憶胞中，其中程式化電壓施加至此目標記憶胞，以誘發熱載子注入。使用此程序的熱載子注入可以應用控制電路實施，其於程式化區間實施加一程式化電壓至所選取字元線(與該目標記憶胞對應)，其施加切換電壓V-SW至所選取字元線之等效源極側的鄰接字元線，其施加導通電壓至其他的字元線。The memory device described herein is configured for low voltage operation, and includes a plurality of memory cells arranged in series in a semiconductor body, for example, can be applied to a reverse gate array of an anti-gate array, having a plurality of characters. The line is coupled to the corresponding memory cell. The control circuit is coupled to the plurality of bit lines and the semiconductor body to be programmed to program a selected memory cell by hot carrier injection using a controlled word line voltage to a target memory cell Above, this is referred to as the switching voltage V-SW. A source extreme voltage is applied to one side of the string, which is commonly grounded or other specific voltage as the source terminal voltage. The side of the selected memory cell that applies the source extreme voltage during programming is referred to herein as the "equivalent source terminal" or "equivalent source." A source extreme voltage V D is applied to the other side of the string, which is to apply a supply potential commonly referred to herein as V DD or V CC , or other specific voltages as the 汲 extreme voltage. The side of the selected memory cell that applies the extreme voltage during programming is referred to herein as the "equivalent 汲 extreme" or "equivalent 汲". In order to control the switching of the conductance of the memory cell, the V-SW is set to a bias condition during a portion of the stylized interval to establish a condition in the body adjacent to the target memory cell to support a sufficient thermal field (bungee-to-source voltage) and sufficient The channel current is in the target memory cell, wherein a stylized voltage is applied to the target memory cell to induce hot carrier injection. The hot carrier injection using this program can be implemented by applying a control circuit that applies a programmed voltage to the selected word line (corresponding to the target memory cell) in the stylized interval, which applies the switching voltage V-SW to the selected An adjacent word line on the equivalent source side of the word line that applies a turn-on voltage to the other word line.
在程式化區間時，此選取字元線藉由一程式化電壓偏壓，其足以克服通道熱載子能障階級。然而，此程式化電壓可以遠小於典型FN程式化所需的電壓。與複數個記憶胞所對應的字元線接收一導通電壓，其是低於程式化電壓以抑制其他記憶胞的干擾。於程式化區間的切換電壓也類似地低於程式化電壓以抑制此切換記憶胞的干擾。In the stylized interval, the selected word line is biased by a stylized voltage that is sufficient to overcome the channel hot carrier barrier class. However, this stylized voltage can be much smaller than the voltage required for typical FN stylization. The word line corresponding to the plurality of memory cells receives a turn-on voltage that is lower than the stylized voltage to suppress interference of other memory cells. The switching voltage in the stylized interval is also similarly lower than the stylized voltage to suppress the interference of the switching memory cell.
對一反及閘串列實施例，一第一切換開關(接地選擇切換開關或底位元線切換開關)提供於複數個電晶體的一第一端，且一第二切換開關(串列選擇切換開關或頂位元線切換開關)提供於複數個電晶體的一第二端。在此實施例中，控制電路於程式化區間時操作以開啟汲極端的第一及第二切換開關之一且於此程式化區間的一初始部份(此時發生源極端升壓)關閉源極端的第一及第二切換開關之另一者，隨後開啟源極端的切換開關以致能電流於半導體主體中流動。經由選擇線(例如串列選擇線SSL或接地選擇線GSL)源極端的切換開關接收一閘極電壓，而與切換開關連接的位元線或參考線最初設置至小於臨界電壓的一電壓使得該切換開關保持關閉，該臨界電壓高於或低於閘極電壓，且隨後此位元線或參考線的電壓快速減少超過該小於該閘極電壓之臨界電壓至一源極端電位以致能電流流動。For a reverse gate sequence embodiment, a first switch (ground selection switch or bottom bit line switch) is provided at a first end of the plurality of transistors, and a second switch (serial selection) A switch or a top bit line switch is provided at a second end of the plurality of transistors. In this embodiment, the control circuit operates in the stylized interval to turn on one of the first and second switches of the 汲 extreme and an initial portion of the stylized interval (in which case the source is boosted) The other of the extreme first and second switching switches then turns on the switching switch of the source terminal to cause current to flow in the semiconductor body. The switch of the source terminal is received via a select line (eg, tandem select line SSL or ground select line GSL) to receive a gate voltage, and the bit line or reference line connected to the switch is initially set to a voltage less than the threshold voltage such that The switch remains off, the threshold voltage is above or below the gate voltage, and then the voltage of the bit line or reference line rapidly decreases beyond the threshold voltage less than the gate voltage to a source extreme potential to cause current flow.
與此複數條字元線平行的選擇線(例如串列選擇線SSL或接地選擇線GSL)可以耦接至第一及第二切換開關。當所選取記憶胞與這些選擇線之一鄰接時，則切換電壓V-SW可以施加至切換開關，而不是記憶胞。替代地，一假字元線可以被加至此串列中，其操作以接收V-SW來對此反及閘串列中的第一或最後記憶胞進行程式化。A selection line parallel to the plurality of word lines (eg, the serial selection line SSL or the ground selection line GSL) may be coupled to the first and second switching switches. When the selected memory cell is adjacent to one of the select lines, the switching voltage V-SW can be applied to the switch instead of the memory cell. Alternatively, a dummy word line can be added to the string, which operates to receive the V-SW to program the first or last memory cell in the reverse gate sequence.
在第二複數個記憶胞與相同的複數條字元線耦接，例如一未選取位元線上的一平行反及閘串列，此控制電路可以操作以抑制或防止在未選取串列上的熱載子注入。The control circuit is operable to suppress or prevent on the unselected series when the second plurality of memory cells are coupled to the same plurality of word lines, such as a parallel reverse gate sequence on an unselected bit line Hot carrier injection.
本發明也提供一種誘發一反及閘陣列的反及閘串列中之一選取記憶胞熱載子注入以進行程式化的方法，其係根據使用V-SW鄰接所選取記憶胞以造成載子的流動及熱電場。一高於熱載子注入能障階級的程式化電位施加於所選取記憶胞，且然後汲極至源極電壓通過所選取記憶胞且所選取記憶胞中的載子流動到達一足以支持熱載子注入的階級。The invention also provides a method for inducing a memory cell hot carrier injection to be programmed in one of the inverse gate arrays of the reverse gate array, which is based on using the V-SW adjacent to the selected memory cells to cause carriers. Flow and thermal fields. A stylized potential higher than the hot carrier injection barrier is applied to the selected memory cell, and then the drain-to-source voltage passes through the selected memory cell and the carrier flow in the selected memory cell reaches a sufficient temperature to support the hot load. Sub-injected class.
本發明還提供一種誘發熱載子注入於一反及閘陣列的一反及閘串列中之一選取記憶胞的方法，以阻擋載子於該反及閘串列的一選取記憶胞的一第一側之一第一半導體主體區域與該反及閘串列的該選取記憶胞的一第二側之一第二半導體主體區域之間流動；於一程式化區間的一初始部分時藉由電容性耦合將該第一半導體主體區域升壓至一升壓電壓階級；及偏壓該第二半導體主體區域至一汲極端電壓階級。於該程式化區間中施加一大於一熱載子注入能障階級的程式化電位至該所選取記憶胞；然後於一程式化區間的一後續部分時藉由將該第二半導體主體區域與一源極端電壓耦接，致能載子自該第二半導體主體區域流動至該所選取記憶胞以導致熱載子產生。The invention also provides a method for inducing a hot carrier to be injected into one of the reverse gate arrays and selecting one of the memory cells to block a carrier from the selected memory cell of the reverse gate sequence. Flowing between a first semiconductor body region of one of the first sides and a second semiconductor body region of a second side of the selected memory cell of the reverse gate sequence; by an initial portion of a stylized interval Capacitive coupling boosts the first semiconductor body region to a boost voltage level; and biases the second semiconductor body region to an extreme voltage level. Applying a programmed potential of greater than one hot carrier injection barrier to the selected memory cell in the stylized interval; and then by using the second semiconductor body region with a subsequent portion of a stylized interval The source extreme voltage is coupled, and the enabling carrier flows from the second semiconductor body region to the selected memory cell to cause hot carrier generation.
此處所描述之一種創新的程式化機制可以使用熱載子注入以有效地降低程式化電壓。此外，此技術對於記憶一胞閘極的耦合比例(GCR)並不敏感。因此，其可以解決因為記憶胞持續縮小尺寸及密度增加所產生的低閘極耦合比例(GCR)問題。此外，可以使用相對低的字元線電壓，而未選取記憶包的干擾可以被抑制。再者，因為傳統FN操作所需的高電壓可以被消除或是或是使用於較不需要嚴格條件的應用中，在某些實施例中製程也可以被簡化。An innovative stylization mechanism described here can use hot carrier injection to effectively reduce the stylized voltage. In addition, this technique is not sensitive to the coupling ratio (GCR) of the memory cell gate. Therefore, it can solve the problem of low gate coupling ratio (GCR) caused by the continued shrinking of the memory cell and the increase in density. In addition, a relatively low word line voltage can be used, and interference of unselected memory packets can be suppressed. Moreover, because the high voltages required for conventional FN operation can be eliminated or used in applications where less stringent conditions are required, the process can be simplified in some embodiments.
本發明之目的，特徵，和實施例，會在下列實施方式的章節中搭配圖式被描述。The objects, features, and embodiments of the present invention will be described in the accompanying drawings.
本發明實施例搭配以下第1到10圖進行詳細描述。The embodiments of the present invention are described in detail with reference to the following figures 1 to 10.
第1A和1B圖顯示一習知技術反及閘(NAND)架構快閃記憶體的剖面圖，其中顯示複數個介電電荷捕捉快閃記憶胞串聯安排以形成反及閘串列及偏壓供FN穿隧程式化之用。第1A圖顯示一反及閘串列的偏壓，其包括一選取位元線上的目標記憶胞，而第1B圖顯示一反及閘串列上未被選取位元線的偏壓。使用能隙工程SONOS電荷捕捉技術以實施反及閘快閃記憶體的一技術可參閱Lue之美國專利第7315474號，其在此引為參考資料。反及閘串列可以使用許多不同的組態實施，包括鰭形場效電晶體技術、淺溝渠隔離技術、垂直反及閘技術等等。某些垂直反及閘結構的範例，請參閱Kim等人標題為"Non-volatile memory device,method of operating same and method of fabricating the same"的歐洲專利第EP 2048709號。另一種類似的結構係用於浮動閘極記憶胞，使用導電的浮動閘極。1A and 1B are cross-sectional views showing a conventional technique of a NAND architecture flash memory in which a plurality of dielectric charge trapping flash memory cells are arranged in series to form a reverse gate series and a bias supply. FN tunneling is used for stylization. Figure 1A shows a bias voltage for a reverse gate train comprising a target memory cell on a selected bit line, and Figure 1B shows a bias voltage for an unselected bit line on the gate sequence. A technique for implementing a backlash flash memory using an energy gap engineering SONOS charge trapping technique can be found in U.S. Patent No. 7,315,474, issued toU.S. The reverse gate series can be implemented using a number of different configurations, including fin field effect transistor technology, shallow trench isolation technology, vertical reverse gate technology, and the like. For an example of certain vertical reversal gate structures, see European Patent No. EP 2048709 to Kim et al., entitled "Non-volatile memory device, method of operating same and method of fabricating the same." Another similar structure is used for floating gate memory cells, using conductive floating gates.
請參閱第1A圖，此記憶胞示形成於一半導體主體10之上。對於n通道記憶胞而言，半導體主體10可以是一隔離之p井，其位於一半導體晶片的深n井區內。替代地，此半導體主體10可以由介電層或是其他材料隔離。某些實施例中也可以使用p通道記憶胞，其中半導體主體的摻雜材料是n型。Referring to FIG. 1A, the memory cell is formed on a semiconductor body 10. For an n-channel memory cell, the semiconductor body 10 can be an isolated p-well located in a deep n-well region of a semiconductor wafer. Alternatively, the semiconductor body 10 can be isolated by a dielectric layer or other material. A p-channel memory cell can also be used in some embodiments, wherein the doping material of the semiconductor body is n-type.
複數個快閃記憶胞可以安排成沿著一個與字元線方向正交的位元線方向排列之串列。字元線22-27沿伸通過一些平行的反及閘串列。節點12-18是由半導體主體中的n型區域(對n通道裝置而言)，且作為記憶胞的源/汲極區域。一個由金氧半電晶體形成的第一切換開關具有一閘極於接地選擇線GSL 21中，其連接於具有第一字元線22的對應記憶胞與由半導體主體10中的n型區域形成之一接點11之間。此接點11與共同源極線CS 30連接。一個由金氧半電晶體形成的第二切換開關具有一閘極於串列選擇線SSL 28中，其連接於具有最後字元線27的對應記憶胞與由半導體主體10中的n型區域形成之一接點19之間。此接點19與位元線BL 31連接。在此例示實施例中的第一及第二切換開關是金氧半電晶體，此範例中具有二氧化矽的閘介電層7和8。The plurality of flash memory cells can be arranged in a series of bit line directions that are orthogonal to the direction of the word line. The word lines 22-27 extend through a number of parallel anti-gate trains. Nodes 12-18 are n-type regions (for n-channel devices) in the semiconductor body and serve as source/drain regions for the memory cells. A first switch formed of a MOS transistor has a gate in the ground select line GSL 21 coupled to the corresponding memory cell having the first word line 22 and formed by the n-type region in the semiconductor body 10. One of the contacts 11 between. This contact 11 is connected to the common source line CS 30. A second switch formed by the MOS transistor has a gate in the string select line SSL 28 coupled to the corresponding memory cell having the last word line 27 and formed by the n-type region in the semiconductor body 10. One of the contacts 19 is between. This contact 19 is connected to the bit line BL 31. The first and second switching switches in this exemplary embodiment are MOS transistors, in this example thyristor dielectric layers 7 and 8.
在此例示中，為了簡化起見此串列中具有六個記憶胞。在典型的組態中，一個反及閘串列可以包含16、32或更多個記憶胞串聯安排。這些記憶胞所對應的字元線22-27具有電荷捕捉結構9於字元線與半導體主體10中通道區域之間。此記憶胞中的電荷捕捉結構9可以是介電電荷捕捉結構、浮動閘極電荷捕捉結構、或是其他合適作為使用此處所描述技術來程式化的快閃記憶體結構。此外，反及閘快閃結構的實施例中已經開發出沒有接面的樣態，其中節點13-17，且選擇性地包括節點12和18可以自此結構中省略。In this illustration, there are six memory cells in this series for the sake of simplicity. In a typical configuration, an inverse gate sequence can contain 16, 32 or more memory bank arrangements. The word lines 22-27 corresponding to these memory cells have a charge trapping structure 9 between the word lines and the channel regions in the semiconductor body 10. The charge trapping structure 9 in this memory cell can be a dielectric charge trapping structure, a floating gate charge trapping structure, or other suitable flash memory structure suitable for programming using the techniques described herein. In addition, no junctions have been developed in embodiments that are inverse gate flash structures in which nodes 13-17, and optionally nodes 12 and 18, may be omitted from this configuration.
第1A圖顯示一習知技術反及閘(NAND)架構快閃記憶體的剖面圖，其中誘發FN穿隧以對與字元線24(目標記憶胞)對應之記憶胞進行程式化的偏壓示意圖。根據此處所顯示的偏壓，接地選擇線GSL偏壓至大約為0V而共同源極線接地，使得與接地選擇線GSL 21對應之第一切換開關是關閉的，且串列選擇線SSL偏壓至約VCC 而所選取位元線也是接地，使得與串列選擇線SSL 28對應之第二切換開關是開啟的。在這些條件下，與反及閘串列相關的區域33中的半導體主體是預充電至約0V。此選取字元線24被偏壓至一高電壓程式化階級V-PGM，在某些實施例中可以高達20伏特的數量級。未選取字元線22、23、25~27被偏壓至一導通電壓V-PASS，其係比V-PGM還小於一個可以抑制此串列中未選取細胞的程式化之電壓。其結果是，電子穿隧進入所選取記憶胞的電荷捕捉結構中。Figure 1A shows a cross-sectional view of a conventional technique NAND architecture flash memory in which FN tunneling is induced to program bias the memory cells corresponding to word line 24 (target memory cell). schematic diagram. According to the bias voltage shown here, the ground select line GSL is biased to approximately 0V and the common source line is grounded such that the first switch corresponding to the ground select line GSL 21 is off and the tandem select line SSL bias To about V CC and the selected bit line is also grounded, so that the second switch corresponding to the serial select line SSL 28 is turned on. Under these conditions, the semiconductor body in region 33 associated with the gate series is precharged to about 0V. The selected word line 24 is biased to a high voltage stylized class V-PGM, which in some embodiments can be on the order of 20 volts. The unselected word lines 22, 23, 25-27 are biased to a turn-on voltage V-PASS which is less than a V-PGM that is less than a stylized voltage that can suppress unselected cells in the series. As a result, electrons tunnel into the charge trapping structure of the selected memory cell.
第1B圖顯示一習知技術反及閘(NAND)架構快閃記憶體的剖面圖，其係對分享第1A圖中字元線22~27之反及閘串列未選取位元線的偏壓示意圖。由圖中可以發現，所有字元線的接地選擇線GSL與串列選擇線SSL皆與第1A圖所示的偏壓相同。類似地，共同源極線30也是接地。然而，未選取的位元線偏壓至約為VCC 的階級。如此會將第二切換開關關閉，其與串列選擇線SSL對應，且將區域35中的半導體主體與未選取的位元線BL 32解除耦接。其結果是，區域35中的半導體主體會由施加至字元線22~27電壓所產生的電容耦合自我壓升，其可以防止足以干擾未選取反及閘串列之記憶胞中電荷捕捉結構的電場形成。根據電容性自我壓升之所謂的遞增步進脈衝程式化(ISSP)操作是業界所熟知的。FIG. 1B is a cross-sectional view showing a conventional flash memory (NAND) architecture flash memory, which shares the bias of the uncharacterized bit lines of the gate lines 22 to 27 and the gate series of the gate array. schematic diagram. As can be seen from the figure, the ground selection line GSL and the string selection line SSL of all the word lines are the same as those shown in FIG. 1A. Similarly, the common source line 30 is also grounded. However, the unselected bit lines are biased to a level of approximately V CC . This will turn off the second switch, which corresponds to the string select line SSL, and decouples the semiconductor body in region 35 from the unselected bit line BL32. As a result, the semiconductor body in region 35 will self-pressurize by the capacitive coupling generated by the voltage applied to word lines 22-27, which can prevent the charge trapping structure in the memory cells of the unselected inverse gate series from being sufficiently disturbed. The electric field is formed. The so-called incremental step pulse programming (ISSP) operation based on capacitive self-pressure is well known in the art.
第2圖顯示一選取反及閘(NAND)串列的程式化偏壓，其係使用習知技藝之熱載子程式化。Figure 2 shows a stylized bias for selecting a NAND string, which is programmed using the hot carrier of the prior art.
在第2圖中，共同源極線CS 30是接地，且選取的位元線31也是與VD 耦接。接地選擇線GSL 21是耦接到一通過電壓以開啟第一切換開關42，將半導體主體與共同源極線CS30耦接。串列選擇線SSL 28偏壓至一通過電壓而開啟第二切換開關43，且將半導體主體與所選取的位元線31耦接，其係與VD 或是一位元線程式化偏壓耦接。與目標記憶胞40對應的字元線接收程式化脈衝V-PGM。由於此程式化偏壓的結果，一通道電流IPGM在此串列中的半導體主體流動，其完全開啟時是由軌跡55表示。此外，通過目標記憶胞的汲極至源極電壓(區間56)是很小的，沿著此串列的電壓下降分佈由VD 至地顯示於VCHANNEL 圖中的軌跡57。其結果是，此目標記憶胞在程式化區間中與汲極至源極電壓對應的加熱電場是很小的，所以即使此操作方式下的通道電流是足夠高的，但總結下來其熱載子注入卻是緩慢而沒有效率的。因此，對反及閘程式化而言熱載子注入並無法達到一重要程度。In FIG. 2, the common source line CS 30 is grounded, and the selected bit line 31 is also coupled to V D . The ground selection line GSL 21 is coupled to a pass voltage to turn on the first switch 42 to couple the semiconductor body to the common source line CS30. The serial select line SSL 28 is biased to a pass voltage to turn on the second switch 43 and couple the semiconductor body to the selected bit line 31, which is tied to V D or a bit threaded bias Coupling. The word line corresponding to the target memory cell 40 receives the stylized pulse V-PGM. As a result of this stylized bias, a channel current IPGM flows in the semiconductor body in the series, which is indicated by trace 55 when fully turned on. Furthermore, the drain-to-source voltage (interval 56) through the target memory cell is small, and the voltage drop distribution along this series is shown by V D to the trace 57 in the V CHANNEL diagram. As a result, the heating electric field corresponding to the drain-to-source voltage in the stylized section of the target memory cell is small, so even if the channel current in this mode of operation is sufficiently high, the hot carrier is summarized. Injection is slow and inefficient. Therefore, hot carrier injection cannot be achieved to an important degree in the anti-gate stylization.
第3圖顯示此處所描述之熱載子注入的程式化偏壓。必須注意的是，對n通道實施例，此熱載子包括電子。對p通道實施例，可以施加類似的偏壓技術以誘發熱電洞注入，其中熱載子包括電洞。此處所描述的實施例係為n通道，但是替代的p通道實施例也可稱為熱載子注入。Figure 3 shows the programmed bias of the hot carrier injection described herein. It must be noted that for the n-channel embodiment, this hot carrier includes electrons. For p-channel embodiments, a similar biasing technique can be applied to induce thermowell injection, where the hot carrier includes a hole. The embodiments described herein are n-channels, but alternative p-channel embodiments may also be referred to as hot carrier injection.
在與目標記憶胞40共同源極線CS 30端鄰接之記憶胞41耦接的字元線接收一兩階段切換電壓V-SW，其安排成在程式化區間的一段時導致足以產生有效熱載子注入的條件。在一程式化區間的偏壓條件下，半導體主體10中的區域51藉由將共同源極電壓VCS 至一汲極電壓VD 而被預充電以響應介於接收V-PGM的目標字元線與第一切換開關42之間的所有字元線上之導通電壓V-PASS(汲極端)。半導體主體10中的區域50於此程式化區間的一初始部分時藉由電容性自我壓升及將第二切換開關43關閉被偏壓，且隨後於此程式化區間的一後續部分時經由位元線31施加一源極端電壓且將第二切換開關開啟。在此範例中，此程式化區間的一初始部分及後續部分時施加於汲極端的偏壓藉由於此程式化區間時設定第二切換開關的閘極電壓至VCC ，且施加一變動電壓至位元線31而達成。在此實施例中的變動電壓包括將位元線31電壓設定為約VCC 或是其他小於切換電晶體43臨界電壓VCC 的電壓準位，或是於此程式化區間的一初始部分時高於VCC ，於其間由於導通電壓V-PASS被施加於記憶胞的汲極端造成第二切換電晶體43關閉而半導體主體10中的區域50被升壓。因此，在此程式化區間的後續部分時，位元線31電壓被降低至例如是地的等效源極電壓VS ，其係低於VD ，其開啟第二切換電晶體43而電壓V-PASS(源極端)被耦接至介於目標記憶胞40與第二切換開關43之間的字元線上。此V-PASS(源極端)可以是與V-PASS(汲極端)相同的電壓，或是不同的電壓，端視一特定應用或程式化條件所需。此外，此導通電壓V-PASS可以根據在串列上的位置而改變。The word line coupled to the memory cell 41 adjacent to the common source line CS 30 end of the target memory cell 40 receives a two-stage switching voltage V-SW that is arranged to cause an effective hot load during a period of the stylized interval. Sub-injection conditions. Under a biasing condition of a stylized section, the region 51 in the semiconductor body 10 is precharged in response to a target word received in the V-PGM by a common source voltage V CS to a drain voltage V D . The turn-on voltage V-PASS (汲 extreme) of all the word lines between the line and the first changeover switch 42. The region 50 in the semiconductor body 10 is biased by capacitive self-voltage rise and closing of the second switch 43 during an initial portion of the stylized section, and then passes through a bit of a subsequent portion of the stylized interval The source line 31 applies a source extreme voltage and turns the second toggle switch on. In this example, the bias applied to the 汲 extreme during an initial portion and the subsequent portion of the stylized interval is set by the gate voltage of the second switch to V CC during the stylized interval, and a varying voltage is applied to The bit line 31 is achieved. The varying voltage in this embodiment includes setting the voltage of the bit line 31 to about V CC or other voltage level less than the threshold voltage V CC of the switching transistor 43 or a high portion of the initial portion of the stylized interval. At V CC , the second switching transistor 43 is turned off and the region 50 in the semiconductor body 10 is boosted because the turn-on voltage V-PASS is applied to the drain terminal of the memory cell. Therefore, at a subsequent portion of this stylized interval, the voltage of the bit line 31 is lowered to, for example, the ground source equivalent source voltage V S , which is lower than V D , which turns on the second switching transistor 43 and the voltage V The -PASS (source terminal) is coupled to a word line between the target memory cell 40 and the second switch 43. This V-PASS can be the same voltage as the V-PASS or a different voltage, depending on a particular application or stylized condition. Furthermore, this turn-on voltage V-PASS can be varied depending on the position on the string.
第3圖中也有一示意圖顯示於此程式化區間中電壓準位與沿著串列中位置的關係圖。在此範例中，於此程式化區間中在介於第一切換開關接觸窗11與目標記憶胞40之間的等效汲極區域51之電壓準位，藉由自共同源極線CS 30端經過第一切換開關所施加的電壓VCS ，被設定為約VD 。在此範例中，因為電容性升壓的緣故，於此程式化區間之初始部分(可參考其大致為第3圖中線65的左側)中在介於第二切換電晶體43的接觸窗19與切換記憶胞41之間的等效源極區域50之電壓準位，具有由軌跡63A所代表的電壓準位。因為第二切換開關是關閉的且通過次串列的電壓變動很小，於此程式化區間之初始部分時僅有非常小或是沒有電流通過。因為施加至位元線31電壓下降以及第二切換開關開啟的結果，於此程式化區間之後續部分(可參考其大致為第3圖中線65的右側)中的等效源極區域50之電壓準位，具有由軌跡63B所代表的電壓準位。於此程式化區間之後續部分時，相對較大的壓降通過切換記憶胞41底下的通道區域52。此半導體主體中的電流增加至一程式化電流階級足以有效地支持熱載子注入，其階級由軌跡62所代表，係在完全開啟通道電流階級61與完全關閉通道電流階級60之間。此外，通過切換記憶胞41的通道區域52之壓降，如圖中區域64的VCHANNEL 圖示，吸收了大部分介於程式化之位元線電壓與共同源極線電壓間的壓降，於目標記憶胞40附近產生了熱電場，其支持熱載子注入。Figure 3 also shows a diagram showing the relationship between the voltage level and the position along the string in this stylized interval. In this example, the voltage level of the equivalent drain region 51 between the first switch contact window 11 and the target memory cell 40 in this stylized interval is obtained from the common source line CS 30 terminal. The voltage V CS applied through the first changeover switch is set to about V D . In this example, due to the capacitive boosting, the initial portion of the stylized section (which may be referred to as the left side of the line 65 in FIG. 3) is in the contact window 19 of the second switching transistor 43. The voltage level of the equivalent source region 50 between the switching memory cells 41 has a voltage level represented by the track 63A. Since the second switch is off and the voltage variation through the sub-column is small, only the initial portion of the stylized interval has very little or no current. Because of the voltage drop applied to the bit line 31 and the result of the second switch being turned on, the equivalent source region 50 in the subsequent portion of the stylized interval (referring to the right side of the line 65 in FIG. 3) The voltage level has a voltage level represented by track 63B. At a subsequent portion of this stylized interval, a relatively large pressure drop is achieved by switching the channel region 52 underneath the memory cell 41. The current in the semiconductor body is increased to a stylized current level sufficient to effectively support hot carrier injection, the class of which is represented by trace 62 between the fully open channel current class 61 and the fully closed channel current class 60. In addition, by switching the voltage drop of the channel region 52 of the memory cell 41, the V CHANNEL diagram of the region 64 in the figure absorbs most of the voltage drop between the stylized bit line voltage and the common source line voltage. A thermal electric field is generated near the target memory cell 40, which supports hot carrier injection.
在此範例中，如同此處所示所有的範例反及閘串列，第一及第二切換開關(例如切換電晶體42，43)是利用與此串列中記憶胞串聯的場效電晶體實施。當然也可以視需要而使用其他的切換電路。在第3圖中所示的範例中，此場效電晶體的閘介電層是單層結構，且通常包括氧化矽或是氮摻雜之氧化矽。在其他的實施例中，如圖中所示之串列中切換開關(例如42，43)的場效電晶體，可以使用多層閘介電層，包括與此串列中所有用的電荷捕捉結構相同的閘介電層。此方案可以簡化記憶胞的製程。在如此的實施例中，第一及第二切換開關可以被特性化為"記憶胞"。有需要的話，作為切換開關之場效電晶體的通道長度可以較記憶胞的通道長度更長。因為，與傅勒-諾德漢(FN)穿隧相較，使用此處所描述技術相對低的操作電壓，於程式化一目標記憶胞時此陣列中記憶胞的干擾可以被抑制。此外，因為使用此程式化的方法字元線電壓相較於傳統使用傅勒-諾德漢(FN)穿隧為基礎記憶裝置的反及閘快閃記憶體亦是較低，通過穿隧氧化層的垂直電場也是較小。因為此原因，並不需要使用高電壓驅動裝置，且可靠性也會變得更好。此外，使用浮動閘極裝置，即使記憶胞因元件微縮造成具有較低的閘極耦合率，也不會因為如此低的閘極耦合率而大幅降低程式化速度。同時，因為使用低電壓裝置的結果，製程可以省略非常高電壓裝置而變得簡化。In this example, as with all of the examples shown herein, the first and second switching switches (e.g., switching transistors 42, 43) utilize field effect transistors in series with the memory cells in the series. Implementation. Of course, other switching circuits can be used as needed. In the example shown in FIG. 3, the gate dielectric layer of the field effect transistor is a single layer structure and typically includes hafnium oxide or nitrogen doped antimony oxide. In other embodiments, as shown in the series of field effect transistors of the switching switches (eg, 42, 43), a multilayer gate dielectric layer can be used, including all of the charge trapping structures used in the series. The same gate dielectric layer. This scheme can simplify the process of memory cells. In such an embodiment, the first and second switchers can be characterized as "memory cells." If necessary, the channel length of the field effect transistor as the switch can be longer than the channel length of the memory cell. Because, compared to the Fourier-Nordheim (FN) tunneling, using the relatively low operating voltages of the techniques described herein, the interference of memory cells in the array can be suppressed when the target cell is programmed. In addition, because the stylized line voltage used in this stylized method is lower than that of the conventional FN-based tunneling-based memory device, the anti-gate flash memory is also low. The vertical electric field of the layer is also small. For this reason, it is not necessary to use a high voltage drive and the reliability will be better. In addition, with the floating gate device, even if the memory cell has a lower gate coupling ratio due to component miniaturization, the stylized speed is not greatly reduced due to such a low gate coupling ratio. At the same time, because of the use of low voltage devices, the process can be simplified by omitting very high voltage devices.
一種在操作時誘發熱載子注入一目標記憶胞中的方法係藉由施加一切換字元線電壓以控制於目標記憶胞源極端切換記憶胞電導。此電導被控制使得足以關閉切換記憶胞中的電流而可以將反及閘串列分隔成兩個區域，包括一等效源極區域及一等效汲極區域。在等效源極區域及等效汲極區域的電壓降是很小的。其結果是，所施加的位元線電壓大部份通過此切換記憶胞。此外，電導足以開啟此小量但是足夠的電流可以流經過此切換記憶胞和目標記憶胞，其中載子被加熱且注入此目標記憶胞的電荷捕捉結構中。A method of inducing hot carrier injection into a target memory cell during operation is to switch memory cell conductance by applying a switching word line voltage to control the target memory source terminal. The conductance is controlled such that it is sufficient to turn off the current in the switching memory cell and the reverse gate sequence can be divided into two regions, including an equivalent source region and an equivalent drain region. The voltage drop in the equivalent source region and the equivalent drain region is small. As a result, the applied bit line voltage mostly switches the memory cells through this. In addition, the conductance is sufficient to turn on this small amount but sufficient current can flow through the switching memory cell and the target memory cell, wherein the carrier is heated and injected into the charge trapping structure of the target memory cell.
於程式化區間當電流需要在串列上被致能時，在選取位元線及共同源極線上的電壓應該高到足以誘發目標記憶胞中的熱載子加熱電場。施加在接地選擇線及串列選擇線上的電壓應該高到足以完全導通選取位元線及共同源極線的電壓。施加在接地選擇線及串列選擇線上的電壓可以是不同的。類似地，施加在未選取字元線上的電壓應該高到足以完全導通施加在選取位元線及共同源極線的電壓。必須注意的是在等效源極端的導通電壓與在等效汲極端的導通電壓可以是不同的。類似地，假如有必要的話其可以在沿著串列長度上改變。對與即將被程式化記憶胞對應的字元線而言，所施加的程式化電壓應該高到足以導致電子注入。於程式化操作時，在切換字元線上的電壓應該落在一操作範圍內使得目標記憶胞中的汲極至源極電壓和程式化電流高到足以產生熱載子注入。在一特定應用時的電壓範圍可以由實驗或是模擬技術來決定。In the stylized interval, when the current needs to be enabled on the series, the voltage on the selected bit line and the common source line should be high enough to induce the hot carrier heating electric field in the target memory cell. The voltage applied to the ground select line and the string select line should be high enough to fully turn on the voltage of the selected bit line and the common source line. The voltages applied to the ground select line and the string select line can be different. Similarly, the voltage applied to the unselected word line should be high enough to fully turn on the voltage applied to the selected bit line and the common source line. It must be noted that the turn-on voltage at the equivalent source terminal and the turn-on voltage at the equivalent 汲 terminal can be different. Similarly, it can vary along the length of the string if necessary. For word lines corresponding to the memory cells to be programmed, the applied stylized voltage should be high enough to cause electron injection. During the stylization operation, the voltage on the switching word line should fall within an operating range such that the drain-to-source voltage and stylized current in the target memory cell are high enough to generate hot carrier injection. The voltage range for a particular application can be determined by experimental or analog techniques.
第4圖顯示四個反及閘串列101、102、103、104的佈局圖，其分別經由串列選擇電晶體(如112)和接地選擇電晶體(如111)而與各自的位元線BL-1到BL-4和一個共同源極線CS 105耦接。為了說明的目的起見，此處所示之偏壓電壓係程式化此反及閘串列101對應字元線WL(i)的一目標記憶胞100。第一切換開關電晶體111由接地選擇線GSL上的導通偏壓例如V-GSL以經過共同源極線CS 105將反及閘串列等效源極端預充電至地。第二切換開關電晶體112被偏壓至例如約為VCC 的閘極電壓，而位元線電壓在此程式化區間之初始及後續部分時被偏壓至之前所描述過的一般。對應字元線WL(i-1)的切換記憶胞113係鄰接目標記憶胞100。因此，字元線WL(i-1)於程式化區間時接收V-SW。Figure 4 shows a layout of four inverted gate trains 101, 102, 103, 104, which are respectively connected to the respective bit lines via a serial selection transistor (e.g., 112) and a ground selection transistor (e.g., 111). BL-1 to BL-4 are coupled to a common source line CS 105. For purposes of illustration, the bias voltage shown herein stunts a target memory cell 100 corresponding to the word line WL(i) of the gate sequence 101. The first changeover switch transistor 111 is precharged to ground by the common source line CS 105 via an on-bias bias voltage, such as V-GSL, on the ground select line GSL. The second switch transistor 112 is biased to a gate voltage of, for example, about V CC , and the bit line voltage is biased to the level previously described during the initial and subsequent portions of the stylized interval. The switching memory cell 113 corresponding to the word line WL(i-1) is adjacent to the target memory cell 100. Therefore, the word line WL(i-1) receives the V-SW in the stylized section.
也可以使用替代地偏壓安排及陣列組態。第4圖顯示代表性地實施方式，其牽涉到偏壓使得此反及閘陣列中的電流流動是自所選取記憶胞(低電壓)至共同源極線(較高電壓)。或是替代地，此等效源極和等效汲極端偏壓可以被交換。Alternative bias arrangements and array configurations can also be used. Figure 4 shows a representative implementation involving biasing such that the current flow in the gate array is from the selected memory cell (low voltage) to the common source line (higher voltage). Alternatively, the equivalent source and equivalent 汲 extreme bias can be swapped.
根據一種抑制未選取記憶胞干擾的技術，此未選取位元線被設定於一接地或是接近地的位元線電壓，使得在此未選取位元線上的電流流動是有限的且不足以將分享具有目標記憶胞的字元線WL(i)之記憶胞程式化。必須注意的是，當一目標記憶胞於第一字元線WL(1)上，此串列選擇線SSL可以用來施加一切換電壓V-SW，其是適合作為切換電晶體112而不是記憶胞操作之用。替代地，可以使用如圖中所示的一假字元線放置於字元線WL(0)與切換電晶體112之間。According to a technique for suppressing unselected memory cell interference, the unselected bit line is set to a ground or near ground bit line voltage, so that current flow on the unselected bit line is limited and insufficient The memory cell stylization of the word line WL(i) with the target memory cell is shared. It should be noted that when a target memory cell is on the first word line WL(1), the string selection line SSL can be used to apply a switching voltage V-SW, which is suitable as the switching transistor 112 instead of the memory. For cell manipulation. Alternatively, a dummy word line as shown in the figure can be placed between the word line WL(0) and the switching transistor 112.
第5圖顯示第4圖操作時偏壓電壓的一範例時序示意圖。未選取位元線(例如BL-2)及共同源極線CS在此區間中被偏壓至地。接地選擇線GSL與大約10V耦接。此外，在此範例中未選取字元線的等效源極和等效汲極端兩者與大約10V耦接。源極選擇字元線SSL與大約VCC 的一電壓耦接。選取位元線(BL-1)在此程式化區間初始部分中與VCC 或是接近的一個電壓階級(例如源極選擇字元線SSL的階級)耦接，而隨後於此程式化區間後續部分中快速降至約為地的電位(例如線500的右側)。選取字元線在此範例的程式化區間中接收一約為14V的程式化脈衝。切換電壓V-SW則設定為足以提供電流的準位而同時維持一熱電場。Figure 5 is a diagram showing an example timing diagram of the bias voltage during operation of Figure 4. The unselected bit line (e.g., BL-2) and the common source line CS are biased to ground in this interval. The ground selection line GSL is coupled to approximately 10V. Moreover, both the equivalent source and the equivalent 汲 extreme of the unselected word line in this example are coupled to approximately 10V. The source select word line SSL is coupled to a voltage of approximately V CC . The selected bit line (BL-1) is coupled to V CC or a nearby voltage class (eg, the class of the source select word line SSL) in the initial portion of the stylized interval, and subsequently followed by the stylized interval The portion quickly drops to a potential of approximately ground (eg, to the right of line 500). The selected word line receives a stylized pulse of approximately 14V in the stylized section of this example. The switching voltage V-SW is set to a level sufficient to provide current while maintaining a thermal field.
當位元線的電壓準位下降足夠可以導致源極選擇SSL切換開關開啟時，電流開始在此反及閘串列中流動且隨後抵達由施加於此切換記憶胞上的電壓V-SWL調變的準位，且其足夠誘發熱載子注入。When the voltage level of the bit line drops enough to cause the source select SSL switch to be turned on, the current begins to flow in the reverse gate train and then arrives at the voltage V-SWL modulated by the switching memory cell. The level is sufficient and it induces hot carrier injection.
請參考以下的表格為抹除操作的代表性偏壓準位範圍。Please refer to the table below for the representative bias level range of the erase operation.
第6圖顯示根據本發明之一第二替代實施技術以抑制未選取串列上記憶胞干擾的偏壓條件。因此，第6圖是一電路示意圖，其顯示兩個反及閘串列101、102分別經由串列選擇電晶體和接地選擇電晶體而與各自的位元線BL-1、BL-2和一個共同源極線CS 105耦接的佈局圖。此處所示的偏壓條件是對反及閘串列101中一對應字元線WL(i)的目標記憶胞100程式化。第一切換開關電晶體111經過共同源極線CS 105偏壓至一汲極端電壓準位(即VCS 設定為VD )而與反及閘串列耦合。第二切換開關電晶體112由串列選擇線上的串列選擇線上的VCC 及選取位元線BL-1上的兩階段電壓，將反及閘串列的頂端與所選取位元線BL-1耦合。對應字元線WL(i-1)的切換記憶胞113係鄰接目標記憶胞100的等效源極端。因此，字元線WL(i-1)於程式化區間時接收V-SW以支持此熱載子注入程式化區間。未選取位元線與低於VCC 的VCS 耦接，使得等效源極和等效汲極區域兩者經由未選取位元線BL-2及共同源極線CS 105被偏壓至一共同電壓。Figure 6 shows a bias condition for suppressing memory cell interference on unselected strings in accordance with a second alternative embodiment of the present invention. Therefore, FIG. 6 is a circuit diagram showing two inverted gate series 101, 102 via respective tandem selection transistors and ground selection transistors and respective bit lines BL-1, BL-2 and one A layout diagram of the common source line CS 105 coupled. The bias conditions shown here are stylized for the target memory cell 100 of a corresponding word line WL(i) in the gate sequence 101. The first change-over switching transistor 111 is biased to a maximum voltage level (ie, V CS is set to V D ) via a common source line CS 105 and coupled to the anti-gate series. The second switch transistor 112 is composed of V CC on the tandem selection line on the tandem selection line and the two-stage voltage on the selected bit line BL-1, and the top of the gate sequence and the selected bit line BL- 1 coupled. The switching memory cell 113 corresponding to the word line WL(i-1) is adjacent to the equivalent source terminal of the target memory cell 100. Therefore, the word line WL(i-1) receives the V-SW during the stylized interval to support the hot carrier injection stylized interval. The unselected bit line is coupled to V CS lower than V CC such that both the equivalent source and the equivalent drain region are biased to one via unselected bit line BL-2 and common source line CS 105 Common voltage.
第7圖顯示根據本發明之一第三替代實施技術以抑制未選取串列上記憶胞干擾的偏壓條件。與字元線WL(i)對應的目標記憶胞接收此程式化電位。切換電壓被施加於反及閘串列位元線端的字元線WL(i-1)。來自選取位元線之偏壓電壓用來在此程式化區間的第二部分時建立反及閘串列介於串列選擇切換開關(例如切換電晶體112)與目標記憶胞100之間的等效源極區域。切換記憶胞113接收切換電壓其供應切換記憶胞的電導以產生之前所描述的熱載子注入條件。未選取位元線接收供應電位，例如是VCC ，其於程式化區間中保持一個定值以防止電流流動，且導致反及閘串列的等效源極端的自我壓升，因此，抑制此未選取串列的干擾。Figure 7 shows a bias condition for suppressing memory cell interference on unselected strings in accordance with a third alternative embodiment of the present invention. The target memory cell corresponding to the word line WL(i) receives the stylized potential. The switching voltage is applied to the word line WL(i-1) opposite to the terminal line of the gate string. The bias voltage from the selected bit line is used to establish the reverse gate sequence between the serial selection switch (eg, switching transistor 112) and the target memory cell 100 during the second portion of the stylized interval. Source area. The switching memory cell 113 receives the switching voltage whose supply switches the conductance of the memory cell to produce the previously described hot carrier injection conditions. The unselected bit line receives the supply potential, such as V CC , which maintains a constant value in the stylized interval to prevent current flow and causes self-pressure rise of the equivalent source terminal of the gate series, thus suppressing this The interference of the series is not selected.
當此進行程式化的目標記憶胞是反及閘串列中的第一個記憶胞時，與接地選擇線相鄰，造成沒有記憶胞鄰接於目標記憶胞之等效源極端而可以作為切換記憶胞。相對的，當此進行程式化的目標記憶胞是反及閘串列中的最後一個記憶胞時，與串列選擇線相鄰，且此串列偏壓以使得等效源極端在上方，再次造成沒有記憶胞鄰接於目標記憶胞之等效源極端而可以作為切換記憶胞。在這些情況下，串列選擇線或接地選擇線可以在合適偏壓下以作為記憶胞的方式來控制半導體主體的電導。在替代實施例中，可以使用假字元線。When the programmed target memory cell is the first memory cell in the gate sequence, adjacent to the ground selection line, causing no memory cell adjacent to the equivalent source terminal of the target memory cell can be used as the switching memory. Cell. In contrast, when the programmed target memory cell is the last memory cell in the gate sequence, adjacent to the string selection line, and the string is biased such that the equivalent source terminal is above, again It causes the memory cell to be adjacent to the equivalent source end of the target memory cell and can be used as a switching memory cell. In these cases, the tandem select line or ground select line can control the conductance of the semiconductor body in a manner that acts as a memory cell at a suitable bias voltage. In an alternate embodiment, a dummy word line can be used.
第8圖顯示類似於第3圖之字元線和一反及閘陣列源-汲極串列的簡要佈局圖，除此之外還額外加上頂部假字元線TDWL鄰接串列選擇線SSL。如圖所示，源汲極串列500~503是垂直延伸於頁面上。水平導線位於源汲極串列500~503之上。這些水平導線包括串列選擇線SSL、頂部假字元線TDWL及字元線WL(0)到WL(N-1)。此外水平導線還包括接地選擇線GSL和共同源極線CS。在串列上端的假字元線可以如同之前所描述的在熱載子注入程式化時作為控制一假記憶胞之用。Figure 8 shows a schematic layout similar to the word line of Figure 3 and the source-drain series of the gate array, in addition to the top dummy word line TDWL adjacent column select line SSL. . As shown, the source drain series 500-503 are vertically extending on the page. The horizontal wires are located above the source drain series 500-503. These horizontal wires include a serial selection line SSL, a top dummy word line TDWL, and word lines WL(0) through WL(N-1). In addition, the horizontal wire further includes a ground selection line GSL and a common source line CS. The dummy word line at the top of the series can be used as a control for a dummy memory cell when the hot carrier injection is programmed as previously described.
第9圖顯示安排成虛擬接地反及閘架構中七個反及閘串列201~207的佈局圖。在此處所描述的虛擬接地反及閘架構中，位元線同時作為與感測放大器耦接的位元線及與參考電壓源耦接的參考線，係取決於所存取的行位置。此反及閘串列由頂位元線選擇電晶體BLT及底位元線選擇電晶體BLB而與對應的一組位元線BL-1到BL-8耦接。為了說明起見，圖中所示的偏壓為將反及閘串列204中與字元線WL(i)對應的一目標記憶胞300程式化之偏壓。第一切換開關電晶體301由底位元線選擇電晶體BLB上的VCC 偏壓以致能兩階段的操作，其會經由位元線BL-5將兩階段位元線電壓施加至反及閘串列204。第二切換開關電晶體302由頂位元線選擇電晶體BLT上的V-PASS偏壓以將反及閘串列204與位元線BL-4耦接，BL-4是偏壓至如同上述般的共同源極電壓VCS (例如一源極端電壓VD )。於反及閘串列204左側的所有位元線BL-1到BL-3皆被偏壓至VCS 。於反及閘串列204右側的所有位元線BL-6到BL-8皆被偏壓至地。對應字元線WL(i+1)的切換記憶胞304係鄰接目標記憶胞300。因此，字元線WL(i+1)接收V-SW。半導體主體中的區域310被偏壓至等效汲極電壓(例如第4、6及7圖實施例中的VCS )，因此設置反及閘串列204的等效汲極區域。在右側未選取的位元線上，等效汲極區域和源極區域312和313藉由位元線BL-5到BL-8被偏壓至地以避免此串列上的記憶胞受到干擾。在左側未選取的位元線上，區域314和315被耦接至相對高的電壓(例如位元線BL-1到BL-3上的VCS )以避免此串列上的記憶胞受到干擾。因此，當此切換記憶胞304接收一切換電壓且位元線BL-5上的位元線電壓在程式化區間的一部分時降低以致產生熱載子注入，目標記憶胞300會由熱載子注入程式化，而此陣列中的其他記憶胞不會受到干擾。Figure 9 shows a layout of the seven reverse gate series 201-207 arranged in a virtual ground and gate structure. In the virtual grounded anti-gate architecture described herein, the bit line is simultaneously a bit line coupled to the sense amplifier and a reference line coupled to the reference voltage source, depending on the row position being accessed. The reverse gate sequence is coupled to the corresponding set of bit lines BL-1 to BL-8 by the top bit line selection transistor BLT and the bottom bit line selection transistor BLB. For the sake of explanation, the bias voltage shown in the figure is a bias voltage that stylizes a target memory cell 300 corresponding to the word line WL(i) in the gate sequence 204. The first changeover switch transistor 301 is biased by the V CC on the bottom bit line select transistor BLB to enable a two-stage operation that applies a two-stage bit line voltage to the anti-gate via the bit line BL-5. Tandem 204. The second switch transistor 302 is coupled to the V-PASS bias on the transistor BLT by the top bit line to couple the AND gate sequence 204 to the bit line BL-4, and the BL-4 is biased as described above. Common source voltage V CS (eg, a source extreme voltage V D ). All of the bit lines BL-1 to BL-3 on the left side of the gate series 204 are biased to V CS . All of the bit lines BL-6 to BL-8 on the right side of the reverse gate train 204 are biased to ground. The switched memory cell 304 corresponding to the word line WL(i+1) is adjacent to the target memory cell 300. Therefore, the word line WL(i+1) receives the V-SW. The region 310 in the semiconductor body is biased to an equivalent gate voltage (e.g., V CS in the fourth, sixth, and seventh embodiment), thus providing an equivalent drain region opposite the gate string 204. On the unselected bit lines on the right side, the equivalent drain and source regions 312 and 313 are biased to ground by bit lines BL-5 through BL-8 to avoid interference with the memory cells on the series. On the unselected bit lines on the left side, regions 314 and 315 are coupled to relatively high voltages (e.g., V CS on bit lines BL-1 through BL-3) to avoid interference of memory cells on the series. Therefore, when the switching memory cell 304 receives a switching voltage and the bit line voltage on the bit line BL-5 is lowered during a portion of the stylized interval to cause hot carrier injection, the target memory cell 300 is injected by the hot carrier. Stylized, and other memory cells in this array are not disturbed.
第10圖顯示積體電路的簡化示意圖，其使用此處所描述之熱載子注入程式化的反及閘快閃記憶體。此積體電路810包括使用電荷捕捉或是浮動閘極記憶胞的一記憶體陣列812，其形成於舉例而言，一半導體基板之上。字元線(列)接地選擇及串列選擇解碼器(包括合適的驅動器)814與複數條字元線816、串列選擇線、和接地選擇線耦接且電性溝通，且沿著記憶陣列812的列方向排列。位元線(行)解碼器及驅動器818與複數條位元線820電性溝通且沿著記憶陣列812的行方向排列，以自陣列812的記憶胞讀取資料或寫入資料至其中。選擇性地，提供一共同源極線解碼器819以支援一個分享字元線及位元線安排，其可使用於例如是三維記憶體架構中。位址係由匯流排822提供給字元線及串列選擇解碼器814與位元線解碼器818。方塊824中的感測放大器與資料輸入結構，包括讀取、程式化及抹除模式的電流源，經由資料匯流排826與位元線解碼器818耦接。資料由積體電路810上的輸入/輸出埠提供給資料輸入線828，或者由積體電路810其他內部/外部的資料源，輸入至方塊824中的資料輸入結構。其他電路830係包含於積體電路810之內，例如泛用目的處理器或特殊目的應用電路，或是模組組合以提供由陣列所支援的系統單晶片功能。資料由方塊824中的感測放大器，經由資料輸出線832，提供至積體電路810，或提供至積體電路810內部/外部的其他資料終端。Figure 10 shows a simplified schematic of an integrated circuit that uses a hot carrier as described herein to inject a programmed anti-gate flash memory. The integrated circuit 810 includes a memory array 812 that uses charge trapping or floating gate memory cells, which are formed, for example, on a semiconductor substrate. A word line (column) ground selection and serial selection decoder (including a suitable driver) 814 is coupled to and electrically coupled to the plurality of word lines 816, the string selection lines, and the ground selection line, and along the memory array The column direction of 812 is arranged. The bit line (row) decoder and driver 818 is in electrical communication with the plurality of bit lines 820 and arranged along the row direction of the memory array 812 to read data or write data from the memory cells of the array 812. Optionally, a common source line decoder 819 is provided to support a shared word line and bit line arrangement that can be used, for example, in a three dimensional memory architecture. The address is provided by bus 822 to word line and tandem select decoder 814 and bit line decoder 818. The sense amplifier and data input structures in block 824, including current sources for read, program, and erase modes, are coupled to bit line decoder 818 via data bus 826. The data is supplied to the data input line 828 by the input/output ports on the integrated circuit 810, or is input to the data input structure in block 824 by other internal/external data sources of the integrated circuit 810. Other circuitry 830 is included within integrated circuitry 810, such as a general purpose processor or special purpose application circuitry, or a combination of modules to provide system single chip functionality supported by the array. The data is provided by the sense amplifier in block 824, via the data output line 832, to the integrated circuit 810, or to other data terminals internal/external to the integrated circuit 810.
在本實施例中所使用的控制器834，使用了偏壓調整狀態機構，控制了偏壓調整供應電壓及電流源836的應用，例如讀取、程式化、抹除、抹除確認以及程式化確認電壓或電流施加於字元線或位元線上，並使用存取控制流程控制了字元線/源極線的操作。該控制器也應用切換序列來誘發此處所描述之熱載子程式化。控制器834可以使用業界所熟知的特殊功能邏輯電路來實施。在替代實施例中，該控制器834包括了通用目的處理器，其可使於同一積體電路，以執行一電腦程式而控制裝置的操作。在又一實施例中，該控制器834係由特殊目的邏輯電路與通用目的處理器組合而成。此控制器834可以組態為實施一種誘發熱載子注入於一反及閘陣列的一反及閘串列中之一選取記憶胞的方法，包含：藉由施加一切換電壓至鄰接該所選取字元線的一字元線控制該反及閘串列的電導，以誘發等效源極於該反及閘串列的一選取記憶胞的一側之一第一半導體主體區域中及誘發等效汲極於該反及閘串列的該選取記憶胞的另一側之一第二半導體主體區域中；於一程式化區間的一初始部分時浮接該第一半導體主體區域，且於該程式化區間的一後續部分時偏壓該第一半導體主體區域至一源極端電壓；偏壓該第二半導體主體區域至一汲極端電壓；以及於該程式化區間時施加一大於一熱載子注入能障階級的程式化電位至該所選取記憶胞。The controller 834 used in this embodiment uses a bias adjustment state mechanism to control the application of bias voltage adjustment supply voltage and current source 836, such as reading, programming, erasing, erasing confirmation, and stylization. Verify that the voltage or current is applied to the word line or bit line and control the operation of the word line/source line using the access control flow. The controller also applies a switching sequence to induce the hot carrier stylization described herein. Controller 834 can be implemented using special function logic circuitry well known in the art. In an alternate embodiment, the controller 834 includes a general purpose processor that can be used in the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller 834 is a combination of special purpose logic circuitry and a general purpose processor. The controller 834 can be configured to implement a method for inducing a hot carrier to be injected into one of the reverse and gate arrays of the gate array to select a memory cell, comprising: applying a switching voltage to the adjacent one of the selected cells A word line of the word line controls the conductance of the anti-gate sequence to induce an equivalent source in the first semiconductor body region of one side of the selected memory cell of the anti-gate sequence and induce The effect is extremely high in one of the second semiconductor body regions of the other side of the selected memory cell of the gate sequence; the first semiconductor body region is floated at an initial portion of a stylized interval, and a subsequent portion of the stylized section biases the first semiconductor body region to a source terminal voltage; biases the second semiconductor body region to a terminal voltage; and applies a greater than one hot carrier during the stylized interval The stylized potential of the energy barrier is injected into the selected memory cell.
其中反及閘陣列中的反及閘串列實施例包括一第一切換開關介於此反及閘串列的一第一端與位元線或參考線之間，及一第二切換開關介於此反及閘串列的一第二端與位元線或參考線之間，其中該偏壓包括開啟包括此反及閘串列的選取記憶胞之第一切換開關，及經由此第一切換開關施加汲極端電壓至此第一半導體主體區域，且開啟包括此反及閘串列的選取記憶胞之第二切換開關，及經由此第二切換開關施加源極端電壓至此第二半導體主體區域。The embodiment of the anti-gate array in the anti-gate array includes a first switch between the first end of the anti-gate string and the bit line or the reference line, and a second switch In this case, a second end of the gate string is connected to the bit line or the reference line, wherein the biasing comprises: turning on the first switching switch of the selected memory cell including the reverse gate sequence, and The switch applies a drain voltage to the first semiconductor body region, and turns on a second switch including the selected memory cell of the gate sequence, and applies a source terminal voltage to the second semiconductor body region via the second switch.
替代地，其中反及閘陣列中的反及閘串列實施例包括一第一切換開關介於此反及閘串列的一第一端與位元線或參考線之間，及一第二切換開關介於此反及閘串列的一第二端與位元線或參考線之間，其中該偏壓包括開啟包括此反及閘串列的選取記憶胞之第一切換開關，及經由此第一切換開關施加源極端電壓至此第一半導體主體區域，且開啟包括此反及閘串列的選取記憶胞之第二切換開關，及經由此第二切換開關施加汲極端電壓至此第二半導體主體區域。Alternatively, the embodiment of the anti-gate array in the anti-gate array includes a first switch between the first end of the anti-gate string and the bit line or the reference line, and a second The switch is between the second end of the reverse gate sequence and the bit line or the reference line, wherein the bias comprises: turning on the first switch of the selected memory cell including the reverse gate sequence, and The first switching switch applies a source terminal voltage to the first semiconductor body region, and turns on a second switching switch including the selected memory cell of the reverse gate sequence, and applies a threshold voltage to the second semiconductor via the second switching switch Body area.
此控制器834可以組態為藉由關閉至少一未選取反及閘串列上的第一或第二切換開關之一者實施一偏壓操作以防止程式化干擾。此外，此控制器834也可以組態為藉由開啟至少一未選取反及閘串列上的第一及第二切換開關實施一偏壓操作以防止程式化干擾。The controller 834 can be configured to perform a biasing operation to prevent stylized interference by turning off one of the first or second switches on the at least one unselected AND gate train. In addition, the controller 834 can also be configured to perform a biasing operation by turning on the first and second switching switches on at least one of the unselected reverse gate trains to prevent stylized interference.
在與本發明相關的美國專利申請案12/898,979和12/797,994的描述中，在此引為參考資料，描述了此反及閘串列熱載子注入操作之其他的偏壓方案，其係根據切換記憶胞的使用及通道電流的調變。某些方案中也使用以建立等效源極和汲極電壓。某些方案則使用直接施加的源極和汲極電壓。某些方案則使用動態或掃描電壓V-SW施加至切換記憶胞。In the descriptions of U.S. Patent Application Serial Nos. 12/8,98,979 and 12/797,994, the disclosure of each of which is incorporated herein by reference in its entirety in its entirety in According to the use of switching memory cells and modulation of channel current. It is also used in some scenarios to establish equivalent source and drain voltages. Some solutions use directly applied source and drain voltages. Some solutions apply dynamic or scan voltage V-SW to the switching memory cell.
此處所描述之程式化方法包括使用共同源極架構應用至傳統的反及閘陣列中，及具有虛擬接地型態架構之修改後的反及閘陣列中。對每一種陣列型態，程式化可以藉由電流在第一及第二方向流動而達成。根據第一電流方向，等效汲極係位於反及閘串列的上方部分，且等效源極係位於下方部分。對於第二電流方向，等效源極係位於反及閘串列的上方部分，且等效汲極係位於下方部分。The stylized methods described herein include application to a conventional anti-gate array using a common source architecture, and a modified anti-gate array with a virtual ground-type architecture. For each array type, stylization can be achieved by current flowing in the first and second directions. According to the first current direction, the equivalent drain is located in the upper portion of the reverse gate train, and the equivalent source is located in the lower portion. For the second current direction, the equivalent source is located in the upper portion of the reverse gate train, and the equivalent drain is located in the lower portion.
一種新的反極閘快閃記憶體程式化方法被提供，其因為較低操作電壓而抑制程式化干擾。一種新的程式化根據使用切換電位以達成熱載子注入而可使用較低的操作電壓。此較低操作電壓的結果是，此積體電路上的驅動電路可以僅使用單一MOSFET製程來實施，而不需要額外的高電壓MOSFET製程。A new anti-polar gate flash memory stylization method is provided that suppresses stylized interference due to lower operating voltages. A new stylization can use a lower operating voltage depending on the use of switching potentials to achieve hot carrier injection. As a result of this lower operating voltage, the driver circuitry on this integrated circuit can be implemented using only a single MOSFET process without the need for an additional high voltage MOSFET process.
此外，此程式化方法的字元線電壓也使低於傳統反及閘快閃記憶體FN程式化所需。因此，也不需要非常高電壓的驅動裝置。此外，此通過反及閘快閃記憶體中穿隧氧化層的垂直電場也小於FN程式化所需。因為所需的較低電場，裝置的可靠性也被提升。In addition, the word line voltage of this stylized method is also required to be lower than that of the conventional anti-gate flash memory FN. Therefore, a very high voltage drive is also not required. In addition, the vertical electric field passing through the tunneling oxide layer in the gate flash memory is also less than that required for FN stylization. The reliability of the device is also improved because of the lower electric field required.
更進一步，較傳統FN操作所需為低的程式化及導通VPASS電壓導致字元線層間介電層的電壓降低，且因此減少了字元線層間介電層因為字元線間距縮小而產生的崩潰問題。Furthermore, the lower programming and turn-on VPASS voltage required for conventional FN operation results in a lower voltage of the inter-layer dielectric layer of the word line, and thus reduces the dielectric layer of the word line due to the narrowing of the word line spacing. Crash problem.
雖然本發明係已參照實施例來加以描述，然本發明創作並未受限於其詳細描述內容。替換方式及修改樣式係已於先前描述中所建議，且其他替換方式及修改樣式將為熟習此項技藝之人士所思及。特別是，所有具有實質上相同於本發明之構件結合而達成與本發明實質上相同結果者，皆不脫離本發明之精神範疇。因此，所有此等替換方式及修改樣式係意欲落在本發明於隨附申請專利範圍及其均等物所界定的範疇之中。Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.
7、8．．．閘介電層7, 8. . . Gate dielectric layer
9．．．電荷捕捉結構9. . . Charge trapping structure
10．．．半導體主體10. . . Semiconductor body
11、19．．．接點11, 19. . . contact
12~18．．．節點12~18. . . node
21．．．接地選擇線GSLtwenty one. . . Ground selection line GSL
22~27．．．字元線22~27. . . Word line
28．．．串列選擇線SSL28. . . Serial selection line SSL
30、105．．．共同源極線CS30, 105. . . Common source line CS
31．．．位元線31. . . Bit line
32．．．未選取位元線32. . . Unselected bit line
33、35．．．與反及閘串列相關的半導體主體區域33, 35. . . Semiconductor body region associated with the gate series
100、156、300、320、400、420．．．目標記憶胞100, 156, 300, 320, 400, 420. . . Target memory cell
113、114、155、304、324．．．切換記憶胞113, 114, 155, 304, 324. . . Switch memory cells
42．．．第一切換開關42. . . First switch
43．．．第二切換開關43. . . Second switch
50．．．等效源極區域50. . . Equivalent source region
51．．．等效汲極區域51. . . Equivalent bungee region
52．．．通道區域52. . . Channel area
101、102、103、104、201~207．．．反及閘串列101, 102, 103, 104, 201~207. . . Reverse gate train
105．．．共同源極線CS105. . . Common source line CS
111．．．接地選擇電晶體111. . . Ground selection transistor
112．．．串列選擇電晶體112. . . Tandem selection transistor
301、321．．．第一切換電晶體301, 321. . . First switching transistor
302、322．．．第二切換電晶體302, 322. . . Second switching transistor
310、314、315．．．半導體主體中的區域310, 314, 315. . . Area in the semiconductor body
312．．．等效源極區域312. . . Equivalent source region
313．．．等效汲極區域313. . . Equivalent bungee region
500~503．．．源/汲極串列500~503. . . Source/bungee string
810．．．積體電路810. . . Integrated circuit
812．．．反及閘快閃記憶體(例如三維)812. . . Reverse gate flash memory (eg 3D)
814．．．字元線/串列選擇及接地選擇解碼器與驅動器814. . . Word line/serial selection and ground selection decoder and driver
816．．．字元線816. . . Word line
818．．．位元線解碼器818. . . Bit line decoder
819．．．共同源極線解碼器819. . . Common source line decoder
820．．．位元線820. . . Bit line
822、826．．．匯流排822, 826. . . Busbar
824．．．感測放大器/資料輸入結構824. . . Sense amplifier / data input structure
830．．．其他電路830. . . Other circuit
834．．．熱載子注入程式化及FN抹除控制器834. . . Hot carrier injection stylization and FN erase controller
836．．．偏壓調整供應電壓836. . . Bias adjustment supply voltage
828．．．資料輸入線828. . . Data input line
832．．．資料輸出線832. . . Data output line
本發明係由申請專利範圍所界定。這些和其它目的，特徵，和實施例，會在下列實施方式的章節中搭配圖式被描述，其中：The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:
第1A和1B圖顯示一習知FN穿隧程式化技術之一選取反及閘串列及一非選取反及閘串列的簡要剖面圖。Figures 1A and 1B show a schematic cross-sectional view of one of the conventional FN tunneling stylization techniques for selecting a reverse gate train and a non-selected reverse gate train.
第2圖顯示一選取反及閘(NAND)串列的簡要剖面圖及其通道電流與程式化偏壓關係圖，顯示使用習知技藝方案在反及閘(NAND)串列中嘗試誘發熱載子注入程式化所遭遇的問題。Figure 2 shows a simplified cross-sectional view of a selected NAND string and its channel current vs. stylized bias relationship, showing the attempt to induce a hot load in a NAND string using conventional techniques. Subinjection stylized problems.
第3圖顯示一選取反及閘(NAND)串列的簡要剖面圖及其通道電流與程式化偏壓關係圖，顯示此處所描述之於一反及閘串列中誘發熱載子注入的程式化偏壓條件。Figure 3 shows a simplified cross-sectional view of a selected NAND string and its channel current versus programmed bias voltage, showing the program described herein for inducing hot carrier injection in a gate series. Bias conditions.
第4圖顯示使用此處所描述之程式化偏壓操作的一共同源極型態的反及閘型態記憶陣列之佈局圖，其具有第一種偏壓條件以抑制干擾。Figure 4 shows a layout of a common source type of inverted gate mode memory array using the programmed bias operation described herein with a first bias condition to suppress interference.
第5圖顯示此處所描述之熱載子注入程式化操作時位元線及字元線偏壓電壓的一範例時序示意圖。Figure 5 shows an example timing diagram of the bit line and word line bias voltages for the hot carrier injection stylization operation described herein.
第6圖顯示使用此處所描述之程式化偏壓操作的一共同源極型態的反及閘型態記憶陣列之佈局圖，其具有第二種偏壓條件以抑制干擾。Figure 6 shows a layout of a common source type of inverted gate mode memory array using the programmed bias operation described herein with a second bias condition to suppress interference.
第7圖顯示使用此處所描述之程式化偏壓操作的一共同源極型態的反及閘型態記憶陣列之佈局圖，其具有第三種偏壓條件以抑制干擾。Figure 7 shows a layout of a common source-type inverted gate mode memory array using the programmed bias operation described herein with a third bias condition to suppress interference.
第8圖顯示具有假字元線鄰接反及閘串列兩端之一反及閘陣列的簡化佈局示意圖。Figure 8 shows a simplified layout of a gate array with one of the opposite ends of the dummy word line and the gate array.
第9圖顯示虛擬接地反及閘型態記憶陣列進行程式化操作時的示意圖，其使用此處所描述之程式化偏壓條件。Figure 9 shows a schematic diagram of the virtual ground and gate type memory array for stylized operation using the programmed bias conditions described herein.
第10圖顯示積體電路的方塊示意圖，其使用本發明實施例的記憶胞及偏壓電路。Fig. 10 is a block diagram showing an integrated circuit using the memory cell and the bias circuit of the embodiment of the present invention.
11、19．．．接點11, 19. . . contact
21．．．接地選擇線GSLtwenty one. . . Ground selection line GSL
28．．．串列選擇線SSL28. . . Serial selection line SSL
30．．．共同源極線CS30. . . Common source line CS
31．．．位元線31. . . Bit line
40．．．目標記憶胞40. . . Target memory cell
41．．．切換記憶胞41. . . Switch memory cells
42．．．第一切換開關42. . . First switch
43．．．第二切換開關43. . . Second switch
50．．．等效源極區域50. . . Equivalent source region
51．．．等效汲極區域51. . . Equivalent bungee region
52．．．通道區域52. . . Channel area
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20090086542A1 (en) * | 2007-09-28 | 2009-04-02 | Dana Lee | High Voltage Generation and Control in Source-Side Injection Programming of Non-Volatile Memory |
| US20100097863A1 (en) * | 2008-10-21 | 2010-04-22 | Samsung Electronics Co., Ltd. | Method of programming non-volatile memory device and non-volatile memory device using the same |
| US7944752B2 (en) * | 2006-09-29 | 2011-05-17 | Hynix Semiconductor Inc. | Method for programming a flash memory device |
| US7957191B2 (en) * | 2007-12-27 | 2011-06-07 | Hynix Semiconductor Inc. | Method of programming non-volatile memory device |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7944752B2 (en) * | 2006-09-29 | 2011-05-17 | Hynix Semiconductor Inc. | Method for programming a flash memory device |
| US20090086542A1 (en) * | 2007-09-28 | 2009-04-02 | Dana Lee | High Voltage Generation and Control in Source-Side Injection Programming of Non-Volatile Memory |
| US7957191B2 (en) * | 2007-12-27 | 2011-06-07 | Hynix Semiconductor Inc. | Method of programming non-volatile memory device |
| US20100097863A1 (en) * | 2008-10-21 | 2010-04-22 | Samsung Electronics Co., Ltd. | Method of programming non-volatile memory device and non-volatile memory device using the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI722755B (en) * | 2020-01-07 | 2021-03-21 | 旺宏電子股份有限公司 | Non-volatile memory and operating method thereof |
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