TWI486964B - High-performance flash memory data transfer method and device - Google Patents

High-performance flash memory data transfer method and device Download PDF

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TWI486964B
TWI486964B TW096114457A TW96114457A TWI486964B TW I486964 B TWI486964 B TW I486964B TW 096114457 A TW096114457 A TW 096114457A TW 96114457 A TW96114457 A TW 96114457A TW I486964 B TWI486964 B TW I486964B
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data
controller
flash memory
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TW200818206A (en
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Yishai Kagan
Rizwan Ahmed
Farookh Moogat
Jason Lin
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Sandisk Technologies Inc
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Priority claimed from US11/424,573 external-priority patent/US7525855B2/en
Priority claimed from US11/458,422 external-priority patent/US7499369B2/en
Priority claimed from US11/458,431 external-priority patent/US7499339B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Description

高效能快閃記憶體資料傳送方法及裝置High-efficiency flash memory data transmission method and device

本發明係關於快閃記憶體裝置領域，並且具體而言，本發明係針對在電子系統中介於快閃記憶體裝置與記憶體控制器之間的資料通信。This invention relates to the field of flash memory devices and, in particular, to data communication between a flash memory device and a memory controller in an electronic system.

如此項技術所熟知，"快閃"記憶體係電可擦除半導體記憶體裝置，其可以相對小區塊為單位進行擦除與重寫，而非如在先前電可擦除可程式唯讀記憶體(EEPROM)裝置中以全晶片或大區塊為基礎進行擦除與重寫。就其本身而論，快閃記憶體已變成特別流行用於經儲存資料之非揮發性(即，在未供電之後的資料保留)係基本要點、但重寫頻率相對低的應用中。快閃記憶體之流行應用的實例包括攜帶型音訊播放器、在計數器電話手機中儲存電話號碼與通話記錄的"SIM"卡、用於電腦與工作站之"thumbkey"可卸除式儲存裝置、用於數位攝影機之儲存裝置與類似物。As is well known in the art, "flash" memory systems electrically erasable semiconductor memory devices that can be erased and rewritten in units of cell blocks rather than as previously erasable programmable read only memory. The (EEPROM) device performs erasing and rewriting on the basis of a full wafer or a large block. For its part, flash memory has become particularly popular in applications where non-volatile (ie, data retention after unpowered) data is stored, but the rewriting frequency is relatively low. Examples of popular applications for flash memory include portable audio players, "SIM" cards that store phone numbers and call logs in counter phone handsets, "thumbkey" removable storage devices for computers and workstations, Storage devices and the like for digital cameras.

在半導體非揮發性記憶體技術中之一項重要新近進展係：將快閃記憶體單元配置為"NAND"記憶體，而非配置為"NOR"記憶體。如此項技術已知，NOR快閃記憶體意指介於一位元線與一源極線之間並聯一行記憶體單元的習知配置。存取一NOR行中的一特定記憶體單元的方式係：驅動該記憶體單元之字線(控制閘極)成為作用中狀態，同時保持該行中的其他記憶體單元，使得介於位元線與源極線之間的電流係由該所存取之記憶體單元的狀態予以決定。另一方面，在一行NAND記憶體中的記憶體單元係串聯連接於位元線與源極線之間。因此，存取一NAND行中的一特定記憶體單元需要：以作用中字線位準開啟該行中的所有記憶體單元；以及施加一中間字線位準至待存取之記憶體單元，使得介於位元線與源極線之間的電流再次係由該所存取之記憶體單元的狀態予以決定。如此項技術所熟知，NAND快閃記憶體之每位元所需的面積大幅小於NOR快閃記憶體之每位元所需的面積，主要原因在於相對於NOR記憶體，一行NAND記憶體需要較少的導體(並且因此需要較少的接點)，此外，在NAND配置中大量記憶體單元之間可共用存取電晶體。此外，可輕易地連續存取習知NAND快閃記憶體，舉例而言，藉由沿行相繼存取記憶體單元，而非如NOR記憶體之情況中的隨機存取記憶體。因此，NAND記憶體尤其極適用於音樂與視訊儲存應用。An important recent development in semiconductor non-volatile memory technology is the configuration of flash memory cells as "NAND" memory rather than "NOR" memory. As is known in the art, a NOR flash memory means a conventional configuration in which a row of memory cells is connected in parallel between a bit line and a source line. Accessing a particular memory cell in a NOR row by driving a word line (control gate) of the memory cell to an active state while maintaining other memory cells in the row, such that the bit is located The current between the line and the source line is determined by the state of the memory cell being accessed. On the other hand, a memory cell in a row of NAND memory is connected in series between the bit line and the source line. Therefore, accessing a particular memory cell in a NAND row requires: turning on all of the memory cells in the row with the active wordline level; and applying an intermediate wordline level to the memory cell to be accessed, such that The current between the bit line and the source line is again determined by the state of the accessed memory cell. As is well known in the art, the area required for each bit of the NAND flash memory is substantially smaller than the area required for each bit of the NOR flash memory. The main reason is that a row of NAND memory needs to be compared to the NOR memory. There are fewer conductors (and therefore fewer contacts), and in addition, access transistors can be shared between a large number of memory cells in a NAND configuration. In addition, conventional NAND flash memory can be easily accessed continuously, for example, by successively accessing memory cells along a row, rather than random access memory as in the case of NOR memory. Therefore, NAND memory is especially suitable for music and video storage applications.

在快閃記憶體領域中之另一項重要新近進展在此項技術稱為多位準程式化記憶體單元(multilevel program cell；MLC)。根據此項做法，僅僅藉由更精巧地控制記憶體單元之程式化，使每一記憶體單元可能有兩種以上狀態。在習知二進制資料儲存器中，每一記憶體單元被程式化成為"0"或"1"狀態。達成讀取此類二進制記憶體單元之方式為：施加單個控制電壓至經位址記憶體單元的控制閘極，使得若程式化至"1"狀態則使電晶體導通，但是若處於"0"狀態則使電晶體關閉；因此，對透過經位址記憶體單元傳導之感測傳回該記憶體的經程式化狀態。相比之下，根據MLC做法的典型實例，對於每一記憶體單元定義四種可能之狀態，典型相對應於二進制值00、01、10、11。效用上，兩種中間狀態對應於介於經完全擦除狀態與經完全程式化狀態之間的記憶體單元局部程式化的兩種位準。已知具有每記憶體單元至多八種狀態或三個二進制位元的MLC快閃記憶體之一些實施方案。在每一記憶體單元上儲存資料之兩個或三個位元直接使記憶體單元晶片的資料容量加雙倍或加三倍。MLC快閃記憶體單元與包括此類MLC記憶體單元之記憶體的實例描述於美國專利第5,172,338號與美國專利第6,747,892 B2號，彼兩項美國專利案茲此共同讓渡且以引用方式併入本文中。Another important recent advance in the field of flash memory is called multilevel program cell (MLC) in this technology. According to this approach, each memory unit may have more than two states by merely more subtly controlling the staging of the memory cells. In the conventional binary data storage, each memory unit is programmed to a "0" or "1" state. The way to read such a binary memory unit is to apply a single control voltage to the control gate of the address memory unit so that if it is programmed to the "1" state, the transistor is turned on, but if it is at "0" The state causes the transistor to turn off; therefore, the stylized state of the memory is passed back through sensing through the address memory unit. In contrast, according to a typical example of an MLC approach, four possible states are defined for each memory cell, typically corresponding to binary values 00, 01, 10, 11. In effect, the two intermediate states correspond to two levels of partial stylization of the memory cells between the fully erased state and the fully programmed state. Some embodiments of MLC flash memory with up to eight states or three binary bits per memory cell are known. Two or three bits of data stored on each memory unit directly double or triple the data capacity of the memory unit wafer. Examples of MLC flash memory cells and memories including such MLC memory cells are described in U.S. Patent No. 5,172,338 and U.S. Patent No. 6,747,892, the entire disclosure of each of which is hereby incorporated by reference. Into this article.

MLC技術與NAND快閃記憶體架構之效率的組合已導致顯著減少對於半導體非揮發性儲存器的每位元成本，並且導致改良的系統可靠度，以及對於既定外形因數的較高資料容量與系統功能。但是，儘管這些重要改良，往返於習知快閃記憶體裝置的資料傳送速率尚未齊步並進。某些現代化快閃記憶體應用特別易受資料傳送速率之影響，特別係隨著資料容量增大。舉例而言，高效能專業級數位靜物攝影機的解析度現今可超過10百萬像素，對於此等攝影機的MLCNAND快閃記憶體之進展受到歡迎。但是，介於連續影像攝取之間的"快門遲滯"(shutter lag)取決於自感測器至快閃記憶體的影像資料之資料傳送速率。此項介於影像之間的延遲時間(對於攝影機使用者，延遲時間被視為獨立之參數，而非取決於影像解析度)正變成彼等攝影機中的一項關鍵因素。尤其隨著影像解析度持續增大，已觀察到習知資料傳送時間不足以達成所要的影像間延遲時間。出入習知快閃記憶體的資料傳送時間亦無法與現代磁碟機之資料傳送時間競爭，當然這是關於快閃記憶體的另一所要新應用。據此，為了使快閃記憶體滿足現代高效能數位靜物攝影機的需求，或使快閃記憶體當作現代高效能電子系統中的固態大量儲存器，這將使快閃記憶體變成必須達成往返於快閃記憶體裝置的更高資料傳送速率。The combination of MLC technology and the efficiency of NAND flash memory architecture has resulted in a significant reduction in cost per bit for semiconductor non-volatile memory, and has led to improved system reliability, as well as higher data capacity and system for a given form factor. Features. However, despite these important improvements, the data transfer rate to and from conventional flash memory devices has not yet progressed. Some modern flash memory applications are particularly susceptible to data transfer rates, especially as data capacity increases. For example, the resolution of high-performance professional-grade digital still cameras can now exceed 10 megapixels, and the progress of MLCNAND flash memory for these cameras is welcome. However, the "shutter lag" between successive image ingestions depends on the data transfer rate of the image data from the sensor to the flash memory. This delay between images (for camera users, latency is considered an independent parameter, not depending on image resolution) is becoming a key factor in their cameras. In particular, as image resolution continues to increase, it has been observed that conventional data transfer times are not sufficient to achieve the desired inter-image delay time. The data transfer time of the conventional flash memory cannot compete with the data transfer time of the modern disk drive. Of course, this is another new application for flash memory. Accordingly, in order for the flash memory to meet the needs of modern high-performance digital still cameras, or to make the flash memory a solid mass storage in modern high-performance electronic systems, this will make the flash memory necessary to achieve a round trip. Higher data transfer rate for flash memory devices.

一項用於快閃記憶體的習知資料傳送做法之實例描述於資料工作表2 GBIT(256 M×8 BITS)CMOS NAND E2 PROM中，零件號碼TH58NVG1S3AFT05(Toshiba，2003年)。此項習知做法涉及一種八位元式資料匯流排，其中以一讀取啟用時脈之每循環，以同步於該讀取啟用時脈之下降邊緣方式，在每一資料輸出上提供一個位元。再者，如在該資料工作表中之描述，此項習知做法涉及一項3.3伏邏輯標準，使得最小高邏輯位準輸出電壓(VOH )係2.4伏，並且最大低邏輯位準輸出電壓(VOL )係0.4伏。此裝置之最大資料速率係20 MHz。據信，此資料速率不是符合個人電腦系統中之大量儲存器所需的資料速率，使得此等習知快閃記憶體不適合作為磁碟機替代品。An example of a conventional data transfer practice for flash memory is described in Data Sheet 2 GBIT (256 M x 8 BITS) CMOS NAND E 2 PROM, part number TH58NVG1S3AFT05 (Toshiba, 2003). This conventional practice involves an octet data bus in which each bit of the enabled clock is synchronized to the falling edge of the read enabled clock to provide a bit on each data output. yuan. Furthermore, as described in the data sheet, this conventional practice involves a 3.3 volt logic standard such that the minimum high logic level output voltage (V OH ) is 2.4 volts and the maximum low logic level output voltage (V OL ) is 0.4 volts. The maximum data rate for this device is 20 MHz. It is believed that this data rate is not a data rate required for a large number of storage devices in a personal computer system, making such conventional flash memory unsuitable as a replacement for a disk drive.

藉由背景資料，一些習知動態隨機存取記憶體(RAM)實施所謂的"雙倍資料速率"(double data rate；DDR)的資料傳送技術。如此項技術已知，DDR資料傳送涉及以同步於相對應之資料選通或時脈之上升邊緣與下降邊緣兩者方式傳送一或多個資料位元(取決於匯流排線數)。因此，DDR資料傳送以習知同步資料傳送(其同步於僅其中一個時脈邊緣(上升邊緣或下降邊緣))之資料速率的兩倍傳達資料。此外，習知DDR動態RAM利用來源同步資料選通，其中RAM裝置本身產生用於讀取自記憶體的資料選通(而外部電路產生用於寫至記憶體的資料選通)。但是，此加倍的輸入/輸出切換速率增大資料傳送之功率消耗，接近單資料速率通信之功率消耗的兩倍。With background information, some conventional dynamic random access memories (RAMs) implement a so-called "double data rate (DDR) data transfer technique. As is known in the art, DDR data transfer involves transmitting one or more data bits (depending on the number of bus bars) in synchronization with both the rising and falling edges of the corresponding data strobe or clock. Thus, DDR data transfer conveys data at twice the data rate of conventional synchronous data transfer (which is synchronized to only one of the clock edges (rising edge or falling edge)). In addition, conventional DDR dynamic RAM utilizes source synchronous data strobe, wherein the RAM device itself generates data strobes for reading from memory (and external circuitry generates data strobes for writing to memory). However, this doubling of the input/output switching rate increases the power consumption of the data transfer, which is close to twice the power consumption of the single data rate communication.

但是，在現代電子系統中，功率消耗係一項重大關切事項，並且在系統中的積體電路裝置之間傳送資料過程中對匯流排與導體之驅動係整體系統功率消耗的重大功率消耗者。依此項技術之基礎，用於驅動外部導體的輸出驅動器的功率消耗直接相關於待驅動之數位訊號的切換速率。因此，如上文所述，增大資料傳送至接近現代磁碟機之資料傳送需要相對應增大此類資料傳送所消耗的功率，所有其他參數維持相等。此增大的功率消耗需要較大的驅動器與接收器裝置，改良系統應用中的散熱及類似項，這些皆使整體系統成本增加。即使進行彼等變更，對於攜帶型電子系統(諸如數位攝影機、膝上型電腦與工作站、無線電話手機、個人數位音訊播放器及類似電池供電之裝置)，來自高速資料傳送的增大功率消耗係非所要的。However, in modern electronic systems, power consumption is a significant concern and a significant power consumer of the overall system power consumption of the busbars and conductors during the transfer of data between integrated circuit devices in the system. Based on the technology, the power consumption of the output driver used to drive the external conductor is directly related to the switching rate of the digital signal to be driven. Therefore, as described above, increasing the transfer of data to a data transfer close to a modern disk drive requires a corresponding increase in the power consumed by such data transfer, all other parameters remaining equal. This increased power consumption requires larger drivers and receiver devices, improved heat dissipation and similarities in system applications, all of which increase overall system cost. Even with these changes, for portable electronic systems (such as digital cameras, laptops and workstations, wireless telephone handsets, personal digital audio players, and similar battery-powered devices), increased power consumption from high-speed data transmission Unwanted.

藉由進一步背景資料，此項技術中已知一種稱為Ultra DMA Mode的通信協定，用於往返於快閃記憶體卡(諸如COMPACT FLASH或CF＋快閃記憶體卡)之通信。圖1繪示按照熟知之標準CF＋與CompactFlash規格書版本3.0(2004年CompactFlash Association)建構與運作之此類習知快閃記憶體卡。如圖1所示，快閃記憶體卡2(在此實例中，快閃記憶體卡係按照此標準建構為COMPACT FLASH儲存器)包含一或多個快閃記憶體模組4及單晶片記憶體控制器6。快閃記憶體模組4透過匯流排data_I/O以往返於記憶體控制器6傳達資料且透過匯流排ctrl以往返於記憶體控制器6發佈控制訊號。在此實例中，前文引用之Toshiba資料工作表中描述的資料傳送做法對應於介於快閃記憶體模組4與記憶體控制器6之間透過data_I/O匯流排與ctrl匯流排之通信。記憶體控制器6透過主機介面HOST_IF與一主機裝置(例如，數位攝影機、數位音訊播放器、個人電腦等等)通訊。前文引用之CF＋與CompactFlaSh規格書描述透過主機介面HOST_IF通信，包括按照Ultra DMA Mode("UDMA")。如同此份規格書中之描述，UDMA通信係以特殊操作模式予以實行，其係藉由要求此類通信的代理(主機或記憶體卡2)於一控制線(UDMARQ)上驅動一訊號予以起始。亦如同此份規格書中之描述，UDMA資料傳送係來源同步，原因在於正在將資料置於匯流排HOST_IF上的代理(記憶體卡2或主機系統)亦發佈資料選通訊號。此外，亦如同此份規格書中之描述，在UDMA操作模式下，在資料傳送中使用該選通訊號之上升邊沿與下降邊沿兩者。With further background information, a communication protocol known as Ultra DMA Mode is known in the art for communication to and from a flash memory card, such as a COMPACT FLASH or CF+ flash memory card. Figure 1 illustrates such a conventional flash memory card constructed and operated in accordance with the well-known standard CF+ and CompactFlash Specification Version 3.0 (CompactFlash Association 2004). As shown in FIG. 1, the flash memory card 2 (in this example, the flash memory card is constructed as a COMPACT FLASH memory according to this standard) includes one or more flash memory modules 4 and single chip memory. Body controller 6. The flash memory module 4 transmits data to and from the memory controller 6 through the bus data_I/O and transmits control signals to and from the memory controller 6 through the bus bar ctrl. In this example, the data transfer method described in the Toshiba data worksheet cited above corresponds to communication between the flash memory module 4 and the memory controller 6 through the data_I/O bus and the ctrl bus. The memory controller 6 communicates with a host device (for example, a digital camera, a digital audio player, a personal computer, etc.) through the host interface HOST_IF. The CF+ and CompactFlaSh specifications described above describe communication through the host interface HOST_IF, including according to the Ultra DMA Mode ("UDMA"). As described in this specification, UDMA communication is carried out in a special mode of operation, which is initiated by a proxy (host or memory card 2) requiring such communication to drive a signal on a control line (UDMARQ). beginning. As described in this specification, the UDMA data transfer source is synchronized because the agent (memory card 2 or host system) that is placing the data on the bus HOST_IF also publishes the data selection communication number. In addition, as described in this specification, in the UDMA mode of operation, both the rising edge and the falling edge of the selected communication number are used in data transfer.

但是，經觀察，結合本發明，即使對於圖1之快閃記憶體卡中的主機介面運用UDMA模式，介於記憶體模組4與記憶體控制器6之間的資料傳送速率仍然將限制記憶體卡2的整體效能。但是，按照習知技術之介面的資料傳送加速亦將大幅增加記憶體卡2內的功率消耗。此外，此項技術已知對記憶體積體電路之輸入/輸出介面的修改將大幅限制此等積體電路的可用性，增加存貨控制與設定常態費用方面的成本。However, it has been observed that, in conjunction with the present invention, even if the UDMA mode is used for the host interface in the flash memory card of FIG. 1, the data transfer rate between the memory module 4 and the memory controller 6 will still limit the memory. The overall performance of the body card 2. However, data transfer acceleration in accordance with the interface of the prior art will also substantially increase the power consumption in the memory card 2. In addition, it is known in the art that modifications to the input/output interface of the memory volume circuit will substantially limit the availability of such integrated circuits, increasing the cost of inventory control and setting normal cost.

因此，本發明的目的旨在提供一種具有高效能資料傳送模式運作之快閃記憶體模組的用於往返於一記憶體控制器進行資料傳送之方法。SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method for data transfer to and from a memory controller of a flash memory module operating in a high performance data transfer mode.

本發明的進一步目的旨在提供一種按照高效能模式進行資料傳送之方法，其消耗功率之速率實質上不大於習知資料傳送消耗功率之速率。It is a further object of the present invention to provide a method of data transfer in a high performance mode in which the rate of power consumption is substantially no greater than the rate at which conventional data transfer power is consumed.

本發明的進一步目的旨在提供一種方法，其中亦可實施"舊型"資料通信，以提供對習知資料傳送標準的回溯相容性。It is a further object of the present invention to provide a method in which "old" data communication can also be implemented to provide backward compatibility with conventional data transfer standards.

本發明的進一步目的旨在提供一種最小化高效能資料傳送模式中資料扭曲之方法。It is a further object of the present invention to provide a method of minimizing data distortion in a high performance data transfer mode.

已參考本份說明書連同其圖式之熟悉此項技術者將明白本發明的其他目的及優點。Other objects and advantages of the present invention will become apparent to those skilled in the <RTIgt;

本發明之一第一態樣可實施於一種具有一多模式資料介面的快閃記憶體裝置中。在一舊型模式中，該資料介面以同步於外部產生之資料選通之方式提供或接收資料，其中在該選通之每一循環中傳達每導體一個位元。在一進階模式中，該資料介面係來源同步，其中一資料位元或字同步於兩種極性之選通邊沿(上升與下降)。對於該進階模式提供一減小之電壓擺動，藉以減小功率消耗。在引動用於資料傳送之該進階模式中，對於命令與控制通信繼續使用該舊型操作模式；對於該進階操作模式提供資料逾時與其他自動化控制功能。A first aspect of the present invention can be implemented in a flash memory device having a multi-mode data interface. In an old mode, the data interface provides or receives data in synchronization with externally generated data strobes, wherein one bit per conductor is communicated in each cycle of the strobe. In an advanced mode, the data interface is source synchronized, with one data bit or word being synchronized to the strobe edges (rising and falling) of the two polarities. A reduced voltage swing is provided for the advanced mode to reduce power consumption. In the advanced mode for priming data transfer, the old mode of operation is continued for command and control communication; data timeout and other automated control functions are provided for the advanced mode of operation.

本發明之一第二態樣可實施於一種具有一多模式資料介面的快閃記憶體裝置中。在一舊型模式中，該資料介面以同步於外部產生之資料選通之方式提供或接收資料，其中在該選通之每一循環中傳達每導體一個位元。在一進階模式中，該資料介面係來源同步，其中一資料位元或字同步於一選通訊號之一上升與下降邊沿中任一者，其頻率係該舊型操作模式之頻率的兩倍。對於該進階模式提供一減小之電壓擺動，藉以減小功率消耗。在引動用於資料傳送之該進階模式中，對於命令與控制通信繼續使用該舊型操作模式；對於該進階操作模式提供資料逾時與其他自動化控制功能。A second aspect of the present invention can be implemented in a flash memory device having a multi-mode data interface. In an old mode, the data interface provides or receives data in synchronization with externally generated data strobes, wherein one bit per conductor is communicated in each cycle of the strobe. In an advanced mode, the data interface is synchronized, wherein a data bit or word is synchronized to any one of the rising and falling edges of one of the selected communication numbers, and the frequency is two of the frequencies of the old operating mode. Times. A reduced voltage swing is provided for the advanced mode to reduce power consumption. In the advanced mode for priming data transfer, the old mode of operation is continued for command and control communication; data timeout and other automated control functions are provided for the advanced mode of operation.

本發明之一第三態樣可實施於一種具有一多模式資料介面的快閃記憶體裝置中。在一舊型模式中，該資料介面以同步於外部產生之資料選通之方式提供或接收資料，其中在該選通之每一循環中傳達每導體一個位元。在該舊型模式中之一寫入操作中，由一控制器發佈至該記憶體的一寫入啟用選通訊號計時該控制器提供至該快閃記憶體的每一資料字；在該舊型模式中之一讀取操作中，由該控制器發佈至該記憶體的一讀取啟用選通訊號計時該快閃記憶體提供至該控制器的每一資料字。在一進階模式中，該資料介面係來源同步，其中一資料位元或字同步於該讀取啟用選通與該寫入啟用選通兩個之選通邊沿。在該進階模式中之一讀取操作中，該快閃記憶體裝置發佈相位彼此不同的讀取選通與寫入選通，以計時交替的輸出資料字。在該進階模式中之一寫入操作中，該控制器發佈相位彼此不同的讀取選通與寫入選通，以計時至該記憶體中的交替之輸入資料字。對於該進階模式提供一減小之電壓擺動，藉以減小功率消耗。在引動用於資料傳送之該進階模式中，對於命令與控制通信繼續使用該舊型操作模式；對於該進階操作模式提供資料逾時與其他自動化控制功能。A third aspect of the present invention can be implemented in a flash memory device having a multi-mode data interface. In an old mode, the data interface provides or receives data in synchronization with externally generated data strobes, wherein one bit per conductor is communicated in each cycle of the strobe. In one of the old mode write operations, a write enable select communication number issued by a controller to the memory is clocked by the controller to each data word of the flash memory; In one of the read modes, a read enable communication number issued by the controller to the memory counts each data word provided by the flash memory to the controller. In an advanced mode, the data interface is source synchronized, wherein a data bit or word is synchronized to the strobe edge of the read enable strobe and the write enable strobe. In one of the read modes of the advanced mode, the flash memory device issues read strobes and write strobes that are different in phase from each other to time the alternate output data words. In one of the write operations in the advanced mode, the controller issues read strobes and write strobes that are different in phase from each other to time the alternate input data words in the memory. A reduced voltage swing is provided for the advanced mode to reduce power consumption. In the advanced mode for priming data transfer, the old mode of operation is continued for command and control communication; data timeout and other automated control functions are provided for the advanced mode of operation.

將結合本發明較佳具體實施例之描述本發明，即，實施為快閃記憶體模組、包括此種快閃記憶體模組之子系統及操作此種快閃記憶體模組之方法。具體而言，此示範性快閃記憶體模組係描述為NAND型多位準記憶體單元(multi－level cell；MLC)快閃記憶體，原因在於預期本發明特別適用於結合此類快閃記憶體，致使實現在電腦系統中之大量資料儲存器中使用固態非揮發性記憶體。但是，預期本發明將適用於且有益於涉及各種類型之非揮發性固態記憶體的其他應用中。據此，應明白，下文說明內容僅藉由實例而提供，並且非意欲來限制如申請專利範圍之本發明的真實範疇。The invention will be described in connection with a preferred embodiment of the invention, that is, as a flash memory module, a subsystem including such a flash memory module, and a method of operating such a flash memory module. In particular, the exemplary flash memory module is described as a NAND type multi-level cell (MLC) flash memory because the invention is expected to be particularly suitable for incorporating such flashes. Memory, which enables the use of solid non-volatile memory in a large data store in a computer system. However, it is contemplated that the present invention will be applicable to and useful in other applications involving various types of non-volatile solid state memories. Accordingly, it should be understood that the following description is provided by way of example only, and is not intended to limit the true scope of the invention as claimed.

圖2繪示一種根據本發明較佳具體實施例建構之快閃記憶體裝置(或模組)10的示範性建構。預期典型地將快閃記憶體裝置10建構於單個積體電路中，並且其身可介接若干記憶體控制器或記憶體控制器邏輯之任一者，如同下文進一步詳細描述所述。亦預期圖2所示之快閃記憶體裝置10的架構僅僅係為了理解本發明目的而提出的實例，並且已參考本份說明書之熟悉此項技術者可輕易地結合不同於圖2所示之快閃記憶體裝置架構的快閃記憶體裝置架構來實現本發明。2 illustrates an exemplary construction of a flash memory device (or module) 10 constructed in accordance with a preferred embodiment of the present invention. It is contemplated that the flash memory device 10 is typically constructed in a single integrated circuit and that it can interface with any of a number of memory controllers or memory controller logic, as described in further detail below. It is also contemplated that the architecture of the flash memory device 10 shown in FIG. 2 is merely an example presented for the purpose of understanding the present invention, and those skilled in the art having reference to this specification can easily combine the differences from those shown in FIG. The flash memory device architecture of the flash memory device architecture implements the present invention.

快閃記憶體裝置10的儲存容量駐存於快閃記憶體陣列12中。陣列12包括以列與行排列之電可程式化且可擦除記憶體單元，如此項技術所熟知。雖然圖2中繪示單個陣列12，但是當然預期陣列12可被實現為多個子陣列，每一子陣列各具有周邊積體電路之一個別例項(instance)，諸如，下文關於圖2之實例進一步詳細描述之位址、資料或控制電路之部分或全部。預期已參考本份說明書之熟悉此項技術者將能夠輕易地結合此種多子陣列架構來實現本發明。在此實例中，陣列12的記憶體單元係浮動閘極金屬氧化物半導體(MOS)電晶體，其經建構使得每一此種電晶體(相對應於一個記憶體單元)可予以電程式化且亦可予以電擦除。根據本發明之較佳具體實施例，陣列12之記憶體單元係多位準記憶體單元(MLC)，原因在於彼等記憶體單元可被程式化至兩種以上資料狀態(即，程式化至兩種以上臨限電壓中之任一者)，使得每一此種記憶體單元儲存一多位元數位值。再者，根據本發明之此項較佳具體實施例，如同將從下文說明內容明瞭，彼等記憶體單元較佳係以熟知NAND方式予以排列，使得典型地非以隨機方式存取而是以序列方式存取彼等記憶體單元，原因在於有助於大量儲存應用。當然，亦可結合二元記憶體單元(即，僅儲存單個數位位元)，且結合NOR配置之記憶體單元來運用本發明。The storage capacity of the flash memory device 10 resides in the flash memory array 12. Array 12 includes electrically programmable and erasable memory cells arranged in columns and rows, as is well known in the art. Although a single array 12 is illustrated in FIG. 2, it is of course contemplated that array 12 can be implemented as a plurality of sub-arrays, each having an individual instance of a peripheral integrated circuit, such as the example below with respect to FIG. Part or all of the address, data or control circuitry is described in further detail. It is expected that those skilled in the art having reference to this specification will be able to readily implement the present invention in conjunction with such a multi-subarray architecture. In this example, the memory cells of array 12 are floating gate metal oxide semiconductor (MOS) transistors that are constructed such that each such transistor (corresponding to a memory cell) can be electrically programmed and It can also be electrically erased. In accordance with a preferred embodiment of the present invention, the memory cells of array 12 are multi-level memory cells (MLCs) because their memory cells can be programmed to more than two data states (ie, programmed to Either of the two or more threshold voltages, such that each such memory cell stores a multi-bit digit value. Furthermore, in accordance with this preferred embodiment of the present invention, as will be apparent from the following description, their memory cells are preferably arranged in a well-known NAND manner such that they are typically accessed not in a random manner but in Serial access to their memory units is due to the large number of storage applications. Of course, the present invention can also be applied in conjunction with a binary memory unit (ie, storing only a single digit bit) in conjunction with a memory unit of a NOR configuration.

根據本發明之此項較佳具體實施例，共同輸入/輸出終端I/O1至I/On經提供且連接至輸入/輸出控制電路20。如同NAND型快閃記憶體技術已知，快閃記憶體裝置10之操作大部分受控於命令之接收與執行，彼等命令係透過輸入/輸出終端I/O1至I/On作為數位字予以達成且由控制邏輯18予以執行。就其本身而論，輸入/輸出控制電路20接收控制命令、位址值及輸入資料，並且經由其與輸入/輸出終端I/O1至I/On通信的驅動器與接收器電路來呈現狀態資訊與輸出資料。預期輸入/輸出終端I/O1至I/On之數量n通常係8或16，然而，當然可提供任何數量之此等終端。此外，輸入/輸出控制電路20接收電源供應電壓Vcc－R 且以基於該電壓的邏輯位準來驅動輸入/輸出終端I/O1至I/On。將於下文詳細描述根據本發明之此項較佳具體實施例，此電源供應電壓Vcc－R 處於低於習知快閃記憶體裝置中使用的電壓，使得減少起因於在輸入/輸出終端I/O1至I/On處之資料傳送的功率消耗，甚至以較高之切換速率。控制邏輯18亦接收此電源供應電壓Vcc－R ，其基於該電壓自讀取啟用終端RE＿驅動較低電壓之輸出控制訊號，等等。According to this preferred embodiment of the invention, the common input/output terminals I/O1 to I/On are provided and connected to the input/output control circuit 20. As is known in the NAND type flash memory technology, the operation of the flash memory device 10 is mostly controlled by the reception and execution of commands, and the commands are transmitted as digital words through the input/output terminals I/O1 to I/On. This is achieved and executed by control logic 18. For its part, the input/output control circuit 20 receives control commands, address values, and input data, and presents status information via the driver and receiver circuits that communicate with the input/output terminals I/O1 through I/On. Output data. It is expected that the number n of input/output terminals I/O1 to I/On is usually 8 or 16, however, any number of such terminals may of course be provided. Further, the input/output control circuit 20 receives the power supply voltage V cc-R and drives the input/output terminals I/O1 to I/On based on the logic level of the voltage. In accordance with this preferred embodiment of the present invention, the power supply voltage V cc-R is at a lower voltage than that used in conventional flash memory devices, such that the reduction is due to the input/output terminal I. The power consumption of data transmission at /O1 to I/On is even higher at the switching rate. The control logic 18 also receives the power supply voltage Vcc-R , which is based on the voltage from the read enable terminal RE_ to drive the lower voltage output control signal, and the like.

輸入/輸出控制電路20轉遞命令資訊至命令暫存器24，以藉由控制邏輯18進行解碼與執行，原因在於該控制邏輯18控制快閃記憶體裝置10之操作。在習知方式中，由控制邏輯18將狀態資訊儲存於狀態暫存器23中。在習知方式中，由輸入/輸出控制電路20在輸入/輸出終端I/O1至I/On處接收之位址值係於位址暫存器22中予以緩衝；此等位址之列部分係由列解碼器11予以解碼且行部分係由行解碼器15予以解碼(每一解碼器典型包括一位址緩衝器)，以實現對在陣列12之一或多個所要記憶體單元之選擇。輸入/輸出控制電路20亦經由匯流排DATA_BUS與資料暫存器14進行雙向通信，用以依據待執行之資料傳送方向，轉遞待寫入之資料至資料暫存器14，且自資料暫存器14輸出資料。控制邏輯18亦接收來自外部至快閃記憶體裝置10的各種直接控制訊號，包括(舉例而言)下列訊號線：晶片啟用CE＿、命令鎖存啟用CLE、位址鎖存啟用ALE、寫入啟用WE＿、讀取啟用RE＿及寫入保護線WP＿。如同此項技術已知，命令鎖存啟用訊號CLE及位址鎖存啟用訊號ALE指示出輸入/輸出終端I/O1至I/On上是否有一命令或位址存在，而寫入啟用訊號WE＿及讀取啟用訊號RE＿分別用作為寫入操作與讀取操作中的資料選通。The input/output control circuit 20 forwards the command information to the command register 24 for decoding and execution by the control logic 18 because the control logic 18 controls the operation of the flash memory device 10. In the conventional manner, status information is stored by the control logic 18 in the status register 23. In the conventional manner, the address values received by the input/output control circuit 20 at the input/output terminals I/O1 to I/On are buffered in the address register 22; the address portion of these addresses It is decoded by column decoder 11 and the line portion is decoded by row decoder 15 (each decoder typically includes a bit address buffer) to effect selection of one or more desired memory cells in array 12. The input/output control circuit 20 also performs bidirectional communication with the data register 14 via the bus DATA_BUS, and transfers the data to be written to the data register 14 according to the data transmission direction to be executed, and the data is temporarily stored. The device 14 outputs the data. Control logic 18 also receives various direct control signals from external to flash memory device 10, including, for example, the following signal lines: Wafer Enable CE_, Command Latch Enable CLE, Address Latch Enable ALE, Write Enable WE_, read enable RE_ and write protection line WP_. As is known in the art, the command latch enable signal CLE and the address latch enable signal ALE indicate whether a command or address exists on the input/output terminals I/O1 to I/On, and the enable signal WE_ and The read enable signal RE_ is used as a data strobe in the write operation and the read operation, respectively.

根據本發明之此項具體實施例，寫入啟用WE＿訊號係一至快閃記憶體裝置10之輸入。據此，對於經由輸入/輸出終端I/O1至I/On傳送資料至快閃記憶體裝置10中，作為寫入啟用WE＿訊號載運的寫入資料選通總是源自於在快閃記憶體裝置10外部的裝置，典型源自於傳送資料本身的來源。但是，亦根據本發明之此項較佳具體實施例且如同下文進一步詳細描述所述，讀取啟用RE＿訊號係雙向。在常態操作模式中，外部裝置(即係正在自快閃記憶體陣列12讀取資料之目的地)係讀取資料選通的來源，接著作為一至快閃記憶體裝置10的輸入來載運該讀取資料選通以作為讀取啟用RE＿訊號。在根據本發明之較佳具體實施例的進階操作模式中，如同下文進一步詳細描述所述，控制邏輯18發佈讀取資料選通以作為讀取啟用RE＿訊號，其同步於自快閃記憶體陣列12讀取資料且經由資料暫存器14、I/O控制電路20與輸入/輸出終端I/O1至I/On傳達資料。In accordance with this embodiment of the invention, the input enable WE_signal is coupled to the input of flash memory device 10. Accordingly, for transmitting data to the flash memory device 10 via the input/output terminals I/O1 to I/On, the write data strobe as the write enable WE_signal is always derived from the flash memory. The device external to device 10 is typically derived from the source of the transmitted material itself. However, also in accordance with this preferred embodiment of the present invention and as described in further detail below, the read enable RE_signal is bidirectional. In the normal mode of operation, the external device (i.e., the destination from which data is being read from the flash memory array 12) is the source of the read data strobe, and the input is a input to the flash memory device 10 to carry the read. Take the data strobe to enable the RE_ signal as a read. In an advanced mode of operation in accordance with a preferred embodiment of the present invention, control logic 18 issues a read data strobe as a read enable RE_signal, which is synchronized to the self-flash memory, as described in further detail below. The array 12 reads the data and communicates the data via the data register 14, the I/O control circuit 20, and the input/output terminals I/O1 through I/On.

圖3繪示根據本發明較佳具體實施例於快閃記憶體卡25中之快閃記憶體裝置(或模組)10之實施。如圖3所示，快閃記憶體卡25包括至少快閃記憶體裝置10本身且亦包括控制器30。控制器30提供且管理一至主機系統(諸如高效能數位攝影機、個人電腦，或諸如數位音訊播放器或行動電話手機之類的攜帶型裝置或類似物)之外部介面HOST_IF；介面HOST_IF亦可對應於快閃記憶體卡25(其建構為可***於各式各樣主機系統中之任一種中的一般用途之卡)的一組外部終端，如此項技術中所已知。預期介面HOST_IF可按照如此項技術中所已知的習知標準介面運作，或可結合未來快閃記憶體介面標準或專屬介面協定予以開發。如上文所述，預期本發明特別有利於提供高速資料傳送，諸如在高效能數位靜物攝影機之資料傳送速率關鍵應用中。進一步預期本發明所提供的高資料傳送速率亦可實現使用快閃記憶體來作為個人電腦中的固態大量儲存裝置，以取代磁碟機。預期介面HOST_IF本身將最佳地具有高速資料傳送能力，舉例而言，如前文[先前技術]中提及之UDMA標準所預期的高速資料傳送能力。3 illustrates the implementation of a flash memory device (or module) 10 in a flash memory card 25 in accordance with a preferred embodiment of the present invention. As shown in FIG. 3, the flash memory card 25 includes at least the flash memory device 10 itself and also includes a controller 30. The controller 30 provides and manages an external interface HOST_IF to a host system (such as a high-performance digital camera, a personal computer, or a portable device such as a digital audio player or a mobile phone handset or the like); the interface HOST_IF may also correspond to A set of external terminals of flash memory card 25, which is constructed as a general purpose card that can be inserted into any of a wide variety of host systems, is known in the art. The interface HOST_IF is expected to operate in accordance with conventional standard interfaces known in the art, or may be developed in conjunction with future flash memory interface standards or proprietary interface protocols. As described above, the present invention is expected to be particularly advantageous for providing high speed data transfer, such as in data transfer rate critical applications for high performance digital still cameras. It is further contemplated that the high data transfer rates provided by the present invention may also enable the use of flash memory as a solid state mass storage device in a personal computer in place of a magnetic disk drive. It is expected that the interface HOST_IF itself will optimally have high speed data transfer capabilities, for example, the high speed data transfer capabilities as expected by the UDMA standard mentioned in the [Prior Art] above.

如圖3所示，快閃記憶體裝置10係以與圖2所示之終端一致之方式耦接至控制器30。就這一點而言，一輸入/輸出匯流排係藉由訊號線I/O1至I/On(相對應於快閃記憶體裝置10之同名之終端)所形成。一控制匯流排CTRL使控制器30耦接至快閃記憶體裝置10，並且包括經連接至圖2所示之ALE、CLE、WP＿與CE＿終端的訊號線。預期亦可提供其他控制線與終端以用於介於快閃記憶體裝置10與控制器30之間的通信，並且控制匯流排CTRL係繪示為雙向匯流排，雖然圖2所示之ALE、CLE、WP＿與CE＿終端係作為至快閃記憶體裝置10的輸入。As shown in FIG. 3, the flash memory device 10 is coupled to the controller 30 in a manner consistent with the terminal shown in FIG. In this regard, an input/output bus is formed by signal lines I/O1 to I/On (corresponding to the terminal of the same name of the flash memory device 10). A control bus CTRL couples the controller 30 to the flash memory device 10 and includes signal lines connected to the ALE, CLE, WP_ and CE_ terminals shown in FIG. It is contemplated that other control lines and terminals may be provided for communication between the flash memory device 10 and the controller 30, and that the control bus CTRL is depicted as a two-way bus, although the ALE shown in FIG. The CLE, WP_, and CE_ terminals are used as inputs to the flash memory device 10.

為了使此份說明書更明確，圖3繪示與控制匯流排CTRL分開的兩個控制線RE＿與WE＿。根據本發明之此項具體實施例，線WE＿在寫入操作(自控制器30寫入資料至快閃記憶體裝置10)中載送資料選通，並且其本身係連接至快閃記憶體裝置1之終端WE＿(圖2)。根據本發明之較佳具體實施例，在每一操作模式中，線WE＿之資料選通係源自於控制器30。線RE＿載送用於讀取操作(自快閃記憶體裝置10讀取資料且將資料傳達至控制器30)之資料選通，並且其本身係連接至快閃記憶體裝置10之終端RE＿(圖2)。如上文所述，根據本發明之此項較佳具體實施例，控制線RE＿為雙向，而讀取資料選通之來源取決於快閃記憶體裝置10之現行操作模式。在常態操作模式中，控制器30發佈讀取資料選通，快閃記憶體裝置10回應其而維持作為存在於訊號線I/O1至I/On上的有效資料。在根據本發明之較佳具體實施例的進階操作模式中，快閃記憶體裝置10係在線RE＿上發佈讀取資料選通，以用於將資料自快閃記憶體裝置10傳送至控制器30。如同下文進一步詳細描述所述，控制器30透過訊號線I/O1至I/On所傳達之命令同步於訊號線RE＿上的讀取資料選通來源，而不顧慮快閃記憶體裝置10正在傳送資料至控制器30的操作模式。In order to make this description clearer, FIG. 3 shows two control lines RE_ and WE_ separated from the control bus CTRL. In accordance with this embodiment of the invention, line WE_ carries a data strobe in a write operation (writing data from controller 30 to flash memory device 10) and is itself coupled to the flash memory device 1 terminal WE_ (Figure 2). In accordance with a preferred embodiment of the present invention, the data gating of line WE_ is derived from controller 30 in each mode of operation. The line RE_ carries a data strobe for a read operation (reading data from the flash memory device 10 and communicating the data to the controller 30), and is itself connected to the terminal RE_ of the flash memory device 10 ( figure 2). As described above, in accordance with this preferred embodiment of the present invention, the control line RE_ is bidirectional, and the source of the read data strobe depends on the current mode of operation of the flash memory device 10. In the normal mode of operation, the controller 30 issues a read data strobe that the flash memory device 10 maintains as valid data present on the signal lines I/O1 to I/On. In an advanced mode of operation in accordance with a preferred embodiment of the present invention, the flash memory device 10 issues a read data strobe on the line RE_ for transmitting data from the flash memory device 10 to the controller. 30. As described in further detail below, the command communicated by controller 30 via signal lines I/O1 through I/On is synchronized to the read data strobe source on signal line RE_, regardless of the flash memory device 10 being transmitted. The data is sent to the operating mode of the controller 30.

預期將實質上按照如此項技術所已知的習知快閃記憶體控制器架構來建構控制器30，按需要予以修改，以實現本份說明書中結合根據本發明較佳具體實施例之快閃記憶體裝置10之進階操作模式中讀取操作之起始、操作與終止所描述的操作。亦預期已參閱本份說明書之熟悉此項技術者將明瞭用於實施彼等進階操作模式的邏輯硬體、程式指令或其組合。進一步預期熟悉此項技術之讀者將輕易地能夠實施控制器30之修改，以最佳地適合用於特定實現，而不需要過度的實驗。It is contemplated that the controller 30 will be constructed in substantial accordance with the conventional flash memory controller architecture known in the art, as needed to achieve flashing in accordance with a preferred embodiment of the present invention. The operations described in the start, operation, and termination of the read operation in the advanced mode of operation of the memory device 10. It is also contemplated that those skilled in the art having access to this specification will be aware of logical hardware, program instructions, or combinations thereof for implementing their advanced modes of operation. It is further contemplated that those skilled in the art will readily be able to implement modifications of controller 30 to best suit a particular implementation without undue experimentation.

並且，亦如圖3所示，電源供應電壓Vcc－R 連接至且加偏壓於快閃記憶體裝置10與控制器30之每一者。此電源供應電壓Vcc－R 處於低於習知快閃記憶體裝置與控制器中使用的電壓，使得減少起因於在輸入/輸出終端I/O1至I/On及各種控制線處之資料傳送與轉變的功率消耗，甚至以較高之切換速率，如下文所述。如下文結合特定實例的詳細說明所述，此電源供應電壓可能係約1.80伏之標稱電壓(範圍為約1.60伏至2.00伏)，其實質上小於習知的3.30伏標稱電源供應電壓(範圍為約2.70伏至3.60伏)。Also, as shown in FIG. 3, the power supply voltage Vcc-R is coupled to and biased to each of the flash memory device 10 and the controller 30. The power supply voltage V cc-R is lower than the voltage used in the conventional flash memory device and controller, so that the data transfer caused by the input/output terminals I/O1 to I/On and various control lines is reduced. With the power consumption of the transition, even at a higher switching rate, as described below. As described in detail below in conjunction with the specific examples, this power supply voltage may be a nominal voltage of about 1.80 volts (ranging from about 1.60 volts to 2.00 volts), which is substantially less than the conventional 3.30 volt nominal power supply voltage ( The range is from about 2.70 volts to 3.60 volts).

現在參考圖4a至圖4e，現在將按照一常態操作模式且亦按照一命令傳達模式描述記憶體卡25中快閃記憶體裝置10組合控制器30之操作。預期彼等操作模式將大致上對應於用於現代快閃記憶體裝置的習知快閃記憶體介面協定，並且彼等操作模式本身將用作用於根據本發明較佳具體實施例之快閃記憶體裝置10之一"舊型"輸入/輸出協定。Referring now to Figures 4a through 4e, the operation of the combination controller 30 of the flash memory device 10 in the memory card 25 will now be described in a normal mode of operation and also in a command communication mode. It is contemplated that their modes of operation will generally correspond to conventional flash memory interface protocols for modern flash memory devices, and that their operational modes will themselves be used as flash memory for use in accordance with preferred embodiments of the present invention. One of the "old" input/output protocols of the body device 10.

圖4a繪示自控制器30至快閃記憶體裝置10之一命令之傳達。如此項技術所已知，且如下文中更詳細說明將描述，現代快閃記憶體裝置操作以回應控制器所發佈之特定命令及透過資料輸入/輸出線傳達之特定命令。就其本身而論，在此實例中，實現一命令CMD之傳達之方式為：控制器30驅動命令鎖存啟用訊號CLE至一高作用中狀態，以及位址鎖存啟用訊號ALE至一低非作用中狀態，其代表將在輸入/輸出線I/O1至I/On上傳達一命令(而非一位址)。在習知方式中使晶片啟用訊號CE＿成為作用中低狀態而啟用快閃記憶體裝置10；如此項技術所已知，如果在卡25內提供多個快閃記憶體裝置10，則當控制器30選擇該等快閃記憶體裝置10中用於通信之所要快閃記憶體裝置時，其可使用個別晶片啟用訊號CE＿。控制器30在寫入啟用線WE＿上發佈一作用中低脈衝而選通輸入/輸出線I/O1至I/On上由控制器30所提供的數位字(相對應於如圖4a所示之命令CMD)；寫入啟用線WE＿上之脈衝的上升邊沿促使I/O控制電路20接收與鎖存於該命令CMD中，最終到達命令暫存器24(圖2)。接著，控制器30可使命令鎖存啟用訊號CLE返回一非作用低狀態，終止命令操作。當然，如此項技術所已知，可以此方式循序傳達多字命令或多個單字命令。FIG. 4a illustrates the communication of commands from controller 30 to flash memory device 10. As is known in the art, and as will be described in more detail below, modern flash memory devices operate in response to specific commands issued by the controller and specific commands communicated through the data input/output lines. In its own right, in this example, the implementation of a command CMD is implemented by the controller 30 driving the command latch enable signal CLE to a high active state, and the address latch enable signal ALE to a low The active state, which represents a command (not an address) on the input/output lines I/O1 to I/On. In the conventional manner, the wafer enable signal CE_ is enabled to be in an active low state to enable the flash memory device 10; as is known in the art, if a plurality of flash memory devices 10 are provided within the card 25, then the controller When the desired flash memory device for communication in the flash memory device 10 is selected, it can use the individual chip enable signal CE_. Controller 30 issues an active low pulse on write enable line WE_ and strobes the digits provided by controller 30 on input/output lines I/O1 through I/On (corresponding to Figure 4a). Command CMD); the rising edge of the pulse on the write enable line WE_ causes the I/O control circuit 20 to receive and latch in the command CMD, and finally to the command register 24 (FIG. 2). Next, the controller 30 can cause the command latch enable signal CLE to return to a non-active low state to terminate the command operation. Of course, as is known from such techniques, multi-word commands or multiple single-word commands can be sequentially transmitted in this manner.

以圖4a所示之方式傳達之命令係用以指示控制器30將傳達記憶體位址至快閃記憶體裝置10的命令(例如，用於讀取操作的命令00H；用於序列資料輸入程式化或寫入操作之命令10H)。圖4b繪示根據本發明較佳具體實施例在常態與命令操作模式中控制器30傳達位址至快閃記憶體裝置的時序。就其本身而論，圖4b所示之操作沿循按照圖4a所示之序列傳達命令00H，其指示出在下一訊號序列中即將傳輸記憶體位址。The command communicated in the manner shown in Figure 4a is used to instruct the controller 30 to communicate a memory address to the flash memory device 10 (e.g., command 00H for a read operation; stylized for sequence data entry) Or write the command 10H). 4b illustrates the timing at which controller 30 communicates an address to a flash memory device in a normal and command mode of operation in accordance with a preferred embodiment of the present invention. For its part, the operation shown in Figure 4b conveys a command 00H along the sequence shown in Figure 4a, which indicates that the memory address is about to be transmitted in the next sequence of signals.

在此常態操作模式中，控制器30可傳達相對廣泛的命令至快閃記憶體裝置10。下列表格中列出在本發明之此項較佳具體實施例中之示範性命令集。In this normal mode of operation, controller 30 can communicate a relatively wide range of commands to flash memory device 10. An exemplary set of commands in this preferred embodiment of the invention is set forth in the following table.

現在請參考圖4b，將描述根據本發明之此項較佳具體實施例自控制器30傳輸記憶體位址至快閃記憶體裝置10。在此操作中，控制器30驅動命令鎖存啟用訊號CLE至非作用中低狀態以及位址鎖存啟用訊號ALE至高狀態，其向快閃記憶體裝置10指示出將在輸入/輸出線I/O1至I/On上傳達位址值(而非命令值)。晶片啟用訊號CE＿亦被驅動成為作用中低狀態，其指示出控制器30正在選擇快閃記憶體裝置10作為此位址資訊的收件者。在此操作中，控制器30發佈寫入啟用訊號WE＿之作用中低脈衝，每一脈衝指示出當時控制器30在輸入/輸出線I/O1至I/On上提供的位址值之一部分。在本發明之此項具體實施例中，此位址資訊同步於寫入啟用訊號WE＿之上升邊沿(即，作用中低脈衝之結尾)，使得快閃記憶體10可使用此邊沿將輸入/輸出線I/O1至I/On之當前狀態鎖存於位址暫存器22(圖2)中以作為所要記憶體位址之一部分。如圖4b之實例中所示，記憶體位址延伸跨越多個字(其寬度係按輸入/輸出線I/O1至I/On之數量n予以定義)。在此情況中，記憶體位址包括四個位址字ADD0至ADD3，其係同步於WE＿的作用中低脈衝予以提供。Referring now to Figure 4b, the transfer of a memory address from the controller 30 to the flash memory device 10 in accordance with this preferred embodiment of the present invention will now be described. In this operation, the controller 30 drives the command latch enable signal CLE to the inactive low state and the address latch enable signal ALE to the high state, which indicates to the flash memory device 10 that it will be on the input/output line I/. The address value (not the command value) is conveyed on O1 to I/On. The wafer enable signal CE_ is also driven to an active low state indicating that the controller 30 is selecting the flash memory device 10 as the recipient of the address information. In this operation, the controller 30 issues an active low pulse for the write enable signal WE_, each pulse indicating a portion of the address value provided by the controller 30 on the input/output lines I/O1 to I/On. In this embodiment of the invention, the address information is synchronized to the rising edge of the write enable signal WE_ (ie, the end of the active low pulse), so that the flash memory 10 can use the edge to input/output. The current state of lines I/O1 through I/On is latched in address register 22 (Fig. 2) as part of the desired memory address. As shown in the example of Figure 4b, the memory address extends across multiple words (the width of which is defined by the number n of input/output lines I/O1 to I/On). In this case, the memory address includes four address words ADD0 to ADD3, which are provided in synchronization with the active low pulse of WE_.

繼傳達位址值(如圖4b所示)後，控制器30可實行寫入資料至快閃記憶體裝置10或自快閃記憶體裝置10讀取資料。圖4c繪示根據本發明之此項較佳具體實施例且在常態操作模式(即，"舊型"模式)中為實現寫入操作所傳達之訊號。根據圖2之架構，此項資料寫入操作係將資料寫入至資料暫存器14。就其本身而論，根據本發明之較佳具體實施例，以圖4a所示之方法來實現寫入命令(例如，命令值80H)至資料暫存器，其後由控制器30傳達在快閃記憶體裝置10內的目的地記憶體位址，兩者皆係在現在將參考圖4c描述的寫入操作之前。為了實現資料寫入操作，控制器30驅動命令鎖存啟用訊號CLE及位址鎖存啟用訊號ALE兩者至非作用中低狀態，其向快閃記憶體裝置10指示出將在輸入/輸出線I/O1至I/On上傳達的待寫入之輸入資料(即，不是命令，也不是位址值)。當然，對於此操作，晶片啟用訊號CE＿亦被驅動至作用中低狀態。接著，控制器30發佈寫入啟用訊號WE＿之作用中低脈衝連同在輸入/輸出線I/O1至I/On上提供的每一位元組或字之資料。在本發明之此項具體實施例中，如同命令與位址傳輸之情況中，以在每一脈衝結尾時同步於寫入啟用訊號WE＿之上升邊沿方式提供有效之輸入資料。回應此邊沿，快閃記憶體裝置10將輸入/輸出線I/O1至I/On之當現狀態(相對應於輸入資料之一字或位元組)鎖存至I/O控制電路20的資料暫存器內，或透過匯流排DATA_BUS間接(或最後按可能之情況)鎖存至資料暫存器14。圖4c繪示以同步於寫入啟用訊號WE＿之四個脈衝方式透過輸入/輸出線I/O1至I/On傳達四個字Din (0)至Din (3)。Following the transmission of the address value (as shown in FIG. 4b), controller 30 can perform writing of data to flash memory device 10 or reading data from flash memory device 10. Figure 4c illustrates the signal conveyed in accordance with this preferred embodiment of the present invention and in a normal mode of operation (i.e., "legacy" mode) for implementing a write operation. According to the architecture of FIG. 2, this data write operation writes data to the data register 14. As such, in accordance with a preferred embodiment of the present invention, a write command (e.g., command value 80H) is implemented to the data register in the manner illustrated in Figure 4a, and thereafter communicated by controller 30 in a fast manner. The destination memory address within flash memory device 10, both before the write operation now described with reference to Figure 4c. In order to implement the data write operation, the controller 30 drives both the command latch enable signal CLE and the address latch enable signal ALE to the inactive low state, which indicates to the flash memory device 10 that it will be on the input/output line. Input data to be written on I/O1 to I/On (ie, not a command, nor an address value). Of course, for this operation, the wafer enable signal CE_ is also driven to the active low state. Next, the controller 30 issues the active low pulse of the write enable signal WE_ along with the data of each byte or word provided on the input/output lines I/O1 to I/On. In this particular embodiment of the invention, as in the case of command and address transmission, valid input data is provided in synchronization with the rising edge of the write enable signal WE_ at the end of each pulse. In response to this edge, the flash memory device 10 latches the present state of the input/output lines I/O1 to I/On (corresponding to a word or a byte of the input data) to the I/O control circuit 20. The data register is latched into the data register 14 either indirectly through the bus DATA_BUS (or finally as the case may be). 4c illustrates four words D in (0) through D in (3) transmitted through the input/output lines I/O1 to I/On in a manner of four pulses synchronized with the write enable signal WE_.

圖4d繪示根據本發明較佳具體實施例在常態操作模式(即，"舊型"模式)中控制器30與快閃記憶體裝置10在實行資料讀取操作(自快閃記憶體裝置10至控制器30)中之操作。如同在資料寫入操作之情況中，在此讀取操作之前，先前已實行一命令序列(即，如圖4a所示)及一位址序列(即，如圖4b所示)。在此讀取之前亦可先前已實行一或多項寫入操作(即，如果對相同於剛剛已寫入之位址進行讀取的情況中，此項讀取將用作為對先前寫入的驗證)，或可在此讀取操作之後實行寫入操作(例如，如圖4c所示)，其形式為對相同記憶體位址的讀取－修改－寫入序列。在讀取之前回應於傳達之位址，相對應於該位址的記憶體單元之內容經感測且轉遞至資料暫存器14。就其本身而論，圖4d之讀取操作係對資料暫存器14之目前註解進行讀取。並且為了實現此項讀取操作，控制器30以前文參考圖4a之描述的方式在命令操作中發佈適當命令(例如，命令E0h)。4d illustrates the controller 30 and the flash memory device 10 performing a data read operation (from the flash memory device 10) in a normal mode of operation (ie, "old" mode) in accordance with a preferred embodiment of the present invention. To the operation in controller 30). As in the case of a data write operation, a sequence of commands (i.e., as shown in Figure 4a) and an address sequence (i.e., as shown in Figure 4b) have been previously executed prior to the read operation. One or more write operations may have been previously performed prior to this read (ie, if the same is true for the address just written, the read will be used as the verification of the previous write) The write operation (e.g., as shown in Figure 4c) may be performed after this read operation in the form of a read-modify-write sequence to the same memory address. In response to the communicated address prior to reading, the contents of the memory unit corresponding to the address are sensed and forwarded to the data register 14. For its part, the read operation of Figure 4d reads the current annotation of data register 14. And to implement this read operation, the controller 30 issues the appropriate command (e.g., command E0h) in the command operation in the manner previously described with reference to Figure 4a.

在此操作中，如同資料寫入操作中，控制器30已驅動命令鎖存啟用訊號CLE及位址鎖存啟用訊號ALE兩者至非作用中低狀態，並且已驅動晶片啟用訊號CE＿至作用中低狀態。控制器30藉由使寫入啟用訊號WE＿成為非作用中高狀態來指示出所要之讀取操作。在此資料讀取操作中，快閃記憶體裝置10回應如控制器30所產生之讀取啟用訊號RE＿之下降邊沿而輸出資料字Dout 。因此，在此常態操作模式中，控制器30能夠藉由下列方式來同步化自快閃記憶體裝置10接收資料：發佈讀取啟用訊號RE＿之作用中低脈衝，並且接收等待一段指定之存取時間(准許快閃記憶體裝置10實現涉及感測其記憶體單元之狀態的一些或所有操作)，並且將所感測之狀態轉遞至其資料暫存器14中且轉出至輸入/輸出線I/O1至I/On。接著，控制器30可將輸入/輸出線I/O1至I/On之資料狀態鎖存至其輸入緩衝器中，以接收來自快閃記憶體裝置10之資料。在圖4d之實例中，循序讀取四個資料字Dout (0)至Dout (3)；晶片啟用訊號CE＿之上升邊沿結束此讀取操作，其後快閃記憶體裝置10促使在I/O控制電路20中的輸出驅動器將輸入/輸出終端I/O1至I/On置於高阻抗("高－Z")狀態。In this operation, as in the data write operation, the controller 30 has driven both the command latch enable signal CLE and the address latch enable signal ALE to the inactive low state, and has driven the wafer enable signal CE_ to the active state. Low state. The controller 30 indicates the desired read operation by making the write enable signal WE_ inactive. In this data reading operation, the flash memory device 10 outputs the material word D out in response to the falling edge of the read enable signal RE_ generated by the controller 30. Therefore, in this normal mode of operation, the controller 30 can synchronize the data received from the flash memory device 10 by issuing the low pulse of the read enable signal RE_ and receiving a specified access. Time (permits flash memory device 10 to implement some or all of the operations involved in sensing the state of its memory cells) and forwards the sensed state to its data register 14 and out to the input/output line I/O1 to I/On. Controller 30 can then latch the data status of input/output lines I/O1 through I/On into its input buffer to receive data from flash memory device 10. In the example of Figure 4d, four data words D out (0) through D out (3) are sequentially read; the rising edge of the wafer enable signal CE_ ends the read operation, after which the flash memory device 10 causes the I The output driver in the /O control circuit 20 places the input/output terminals I/O1 to I/On in a high impedance ("high-Z") state.

根據此項常態操作模式(即，"舊型"模式)之其他操作亦較佳地可用，此等操作係如此項技術所已知。舉例而言，在此項常態操作模式中，控制器30可藉由下列方式讀取狀態暫存器24之內容：沿循圖4a之時序發佈指定之狀態命令(例如，命令碼70H)，並且回應於讀取啟用訊號RE＿之作用中低脈衝之發佈，透過輸入/輸出線I/O1至I/On接收讀取狀態暫存器24之內容。Other operations in accordance with this normal mode of operation (i.e., "old" mode) are also preferably available, and such operations are known in the art. For example, in this normal mode of operation, the controller 30 can read the contents of the state register 24 by issuing the specified state command (eg, command code 70H) along the timing of FIG. 4a, and In response to the release of the low pulse generated by the read enable signal RE_, the contents of the read status register 24 are received through the input/output lines I/O1 to I/On.

如圖4c與4d所示，對於寫入啟用訊號WE＿或讀取啟用訊號RE＿之每一循環傳達一個資料字或位元組(在此說明書中稱為"資料字")，如同許多情況。並且如圖所示及前文說明內容所述，在此項常態操作模式中，控制器30控制寫入啟用訊號WE＿與讀取啟用訊號RE＿。具體而言，根據習知快閃記憶體時序需求與效能，在讀取操作中，因為對於讀取啟用訊號RE＿之每一完整循環僅讀取一個資料字，所以控制器30有充分的時間自行發佈其讀取資料選通(寫入啟用訊號WE＿)以及接收且鎖存該讀取資料。但是，此效能等級對於高速使用之快閃記憶體裝置10未必足夠，諸如當使用快閃記憶體卡25作為個人電腦系統中之大量儲存器。此外，亦預期此"舊型"操作模式無法跟上自控制器30至主機系統的高速外部介面模式，諸如依據上文提及之UDMA介面協定。As shown in Figures 4c and 4d, a data word or byte (referred to as "data word" in this specification) is conveyed for each cycle of the write enable signal WE_ or the read enable signal RE_, as is the case. And as shown in the above and in the foregoing description, in this normal mode of operation, the controller 30 controls the write enable signal WE_ and the read enable signal RE_. Specifically, according to the conventional flash memory timing requirement and performance, in the read operation, since only one data word is read for each complete cycle of the read enable signal RE_, the controller 30 has sufficient time to self. Publish its read data strobe (write enable signal WE_) and receive and latch the read data. However, this level of performance is not necessarily sufficient for the flash memory device 10 for high speed use, such as when using the flash memory card 25 as a large amount of storage in a personal computer system. In addition, it is also contemplated that this "legacy" mode of operation cannot keep up with the high speed external interface mode from controller 30 to the host system, such as in accordance with the UDMA interface protocol mentioned above.

根據本發明之較佳具體實施例，因此，快閃記憶體裝置10提供進階較高效能之讀取與寫入操作模式，並且控制器30經建構以利用該進階模式。現在將參考圖5a與5b之流程圖以及圖6a至6e之時序圖來詳細描述快閃記憶體裝置10與控制器30利用此進階模式之操作。In accordance with a preferred embodiment of the present invention, therefore, flash memory device 10 provides an advanced higher performance read and write mode of operation, and controller 30 is configured to utilize the advanced mode. The operation of the flash memory device 10 and controller 30 to utilize this advanced mode will now be described in detail with reference to the flowcharts of Figures 5a and 5b and the timing diagrams of Figures 6a through 6e.

圖5a以及圖6a至6c繪示快閃記憶體裝置10在實行資料讀取操作(即，在快閃記憶體卡25中，自快閃記憶體裝置10至控制器30)過程中之操作。在圖5a之處理程序40中，供電給快閃記憶體裝置10與控制器30，使該兩個裝置進入常態操作模式中(處理程序42)，如上文關於圖4a至4d之描述所述。在處理程序44中，在此常態操作模式(即，"舊型"模式)中，實行在此常態模式中的讀取操作與寫入操作(若有的話)。5a and 6a through 6c illustrate the operation of the flash memory device 10 during the data reading operation (i.e., in the flash memory card 25 from the flash memory device 10 to the controller 30). In the process 40 of Figure 5a, power is supplied to the flash memory device 10 and controller 30 to bring the two devices into a normal mode of operation (process 42) as described above with respect to Figures 4a through 4d. In the processing program 44, in this normal mode of operation (i.e., "old" mode), read operations and write operations (if any) in this normal mode are performed.

進入進階讀取操作模式開始於處理程序46，其中控制器30按照常態操作模式發佈記憶體位址值至快閃記憶體裝置10，如上文關於圖4b之描述所述。在處理程序46中由控制器30所發佈之記憶體位址係在此進階操作模式中將自該處讀取資料的起始記憶體位址，並且較佳係繼傳輸相對應之讀取位址輸入命令之後，如上文所述。在處理程序48中，控制器30發佈"起始資料傳送"或"IDT"命令序列至快閃記憶體裝置10。圖6a進一步詳細繪示此項操作。Entering the advanced read mode of operation begins with a process 46 in which the controller 30 issues a memory address value to the flash memory device 10 in accordance with the normal mode of operation, as described above with respect to FIG. 4b. The memory address issued by the controller 30 in the processing program 46 is the starting memory address from which the data will be read in this advanced mode of operation, and preferably the corresponding read address is transmitted. After entering the command, as described above. In the processing program 48, the controller 30 issues a "start data transfer" or "IDT" command sequence to the flash memory device 10. This operation is illustrated in further detail in Figure 6a.

根據本發明之較佳具體實施例，在處理程序48中，控制器30發佈"IDT"命令至快閃記憶體裝置10，以起始進階資料傳送模式。以類似於上文關於圖4a之描述所述之方式發佈此命令，其中控制器30驅動晶片啟用訊號CE＿至作用中低狀態、驅動位址鎖存啟用訊號ALE至非作用中低狀態及驅動命令鎖存啟用訊號CLE至作用中高狀態。寫入啟用訊號WE＿之作用中低脈衝之上升邊沿係用作為用於由控制器30驅動至輸入/輸出線I/O1至I/On上之IDT命令值IDT_CMD(其係二進位字且值不同於其他指派之命令值)的資料選通。繼寫入啟用訊號WE＿正處於高狀態之後的一特定時間之後，控制器30使輸入/輸出線I/O1至I/On成為高阻抗狀態。並且，繼寫入啟用訊號WE＿之上升邊沿之後的另一歷時時間trel 之後，當選通IDT命令時，接著控制器30亦釋放其對讀取啟用訊號RE＿之控制，准許快閃記憶體裝置10之控制邏輯18驅動相對應於線RE＿之狀態(無與控制器30發生資料競爭之風險)。In accordance with a preferred embodiment of the present invention, in processing 48, controller 30 issues an "IDT" command to flash memory device 10 to initiate an advanced data transfer mode. This command is issued in a manner similar to that described above with respect to FIG. 4a, in which controller 30 drives wafer enable signal CE_ to active low state, drive address latch enable signal ALE to inactive low state, and drive command. The enable signal CLE is latched to the active high state. The rising edge of the low-pulse pulse applied to the enable signal WE_ is used as the IDT command value IDT_CMD for driving to the input/output lines I/O1 to I/On by the controller 30 (the binary word is different in value) Data strobes for other assigned command values). After a certain time after the write enable signal WE_ is in the high state, the controller 30 causes the input/output lines I/O1 to I/On to be in a high impedance state. Moreover, after another duration t rel after the rising edge of the enable signal WE_ is written, when the IDT command is gated, the controller 30 also releases its control of the read enable signal RE_, permitting the flash memory device 10 The control logic 18 drives the state corresponding to the line RE_ (there is no risk of data competition with the controller 30).

一旦IDT命令已被鎖存於快閃記憶體裝置10中且由快閃記憶體裝置10予以執行，接著快閃記憶體裝置10開始執行高速模式讀取資料傳送處理程序50。如圖6a所示，繼寫入啟用訊號WE＿之上升邊沿之後歷時非零存取時間之後，此讀取資料傳送處理程序開始於快閃記憶體裝置10發佈第一有效輸出資料字Dout (0)。一旦快閃記憶體裝置10提供此第一輸出資料字Dout (0)，接著其以同步於額外輸出資料字Dout (1)以及下列等等之方式開始發佈讀取啟用訊號RE＿之作用中脈衝。根據本發明之此項較佳具體實施例，以同步於快閃記憶體裝置10本身所驅動的讀取啟用訊號RE＿之每一邊沿(下降邊沿與上升邊沿)方式發佈一個資料字Dout (k)。在圖6a之實例中，每一輸出資料字Dout (k)係接在其選通邊沿之後相差非零存取時間；替代做法為，可於相對應的有效資料字Dout (k)內發佈(或延遲發佈)每一讀取啟用訊號RE＿邊沿至控制器30。Once the IDT command has been latched into the flash memory device 10 and executed by the flash memory device 10, then the flash memory device 10 begins executing the high speed mode read data transfer processing routine 50. As shown in FIG. 6a, after reading the rising edge of the enable signal WE_ for a non-zero access time, the read data transfer processing program begins with the flash memory device 10 issuing the first valid output data word Dout (0). ). Once the flash memory device 10 provides the first output material word D out (0), it then begins to issue the read enable signal RE_ in synchronization with the additional output data word D out (1) and the like. pulse. According to this preferred embodiment of the present invention, a data word D out (k) is issued in synchronization with each edge (falling edge and rising edge) of the read enable signal RE_ driven by the flash memory device 10 itself. ). In the example of Figure 6a, each output data word D out (k) is tied to its non-zero access time after its strobe edge; alternatively, it can be within the corresponding valid data word D out (k) Each read enable signal RE_ edge is issued (or delayed) to the controller 30.

根據本發明之較佳具體實施例，因此，對於快閃記憶體裝置10經由輸入/輸出線I/O1至I/On提供資料至控制器30的速率：在此進階模式中的速率實質上快於常態操作模式(圖4d)中的速率，大約係典型實現中之資料速率的兩倍。在某種程度上，實現此較高資料速率之方式為：准許快閃記憶體裝置10發佈讀取啟用訊號RE＿之讀取資料選通邊沿，其排除若控制器30發佈彼等讀取資料選通邊沿情況下所涉及的傳播延遲與必然的時序窗。In accordance with a preferred embodiment of the present invention, therefore, the rate at which the flash memory device 10 provides data to the controller 30 via input/output lines I/O1 through I/On: the rate in this advanced mode is substantially The rate in the normal mode of operation (Fig. 4d) is approximately twice the data rate in a typical implementation. To some extent, the higher data rate is achieved by allowing the flash memory device 10 to issue a read data strobe edge of the read enable signal RE_, which excludes if the controller 30 issues their read data. The propagation delay involved in the case of the edge and the inevitable timing window.

然而，熟悉此項技術者應明白，在所有其他因數相等之情況下，在輸入/輸出線I/O1至I/On上提供輸出資料的增大速率實質上增大快閃記憶體卡25內的功率消耗，在此讀取操作中，功率消耗主要源自於快閃記憶體裝置10之I/O控制電路20內的輸出驅動電路。隨著資料字寬度(即，輸入/輸出線I/O1至I/On之數量n)增大(此為現代趨勢)，使此功率消耗惡化。根據本發明之較佳具體實施例，現在將描述藉由減小輸入/輸出線I/O1至I/On上之輸出訊號的電壓擺動而使此功率消耗大幅減小。However, those skilled in the art will appreciate that the rate of increase in the output data provided on input/output lines I/O1 through I/On substantially increases the amount of memory within flash memory card 25, with all other factors being equal. The power consumption, in this read operation, is primarily derived from the output drive circuitry within the I/O control circuitry 20 of the flash memory device 10. As the data word width (i.e., the number n of input/output lines I/O1 to I/On) increases (this is a modern trend), this power consumption is deteriorated. In accordance with a preferred embodiment of the present invention, it will now be described that this power consumption is substantially reduced by reducing the voltage swing of the output signals on input/output lines I/O1 through I/On.

習知快閃記憶體裝置利用熟知的3.3伏匯流排標準，其中使得最小高位準輸出電壓(VOH )係2.4伏並且最大低位準輸出電壓(VOL )係0.4伏，並且其標稱電壓擺動係約3.3伏。如此項技術所已知，根據此標準，彼等電壓係以標稱上為3.30伏的電源供應電壓為基礎，並且其規格範圍係在2.70伏與3.60伏之間。根據現代快閃記憶體裝置之習知常態操作模式，輸出資料速率係25 MHz(即，每40奈秒一次資料轉變)，在一既定輸入/輸出線I/Ok在每一循環進行一次資料轉變的最壞情況中，將需要快閃記憶體裝置10以12.5 MHz之頻率對輸入/輸出線I/Ok之電容進行充電。假設輸入/輸出線I/Ok的典型線電容係65 pF，則可從下式計算一個輸入/輸出線I/Ok的電流消耗(以毫安培為單位)：Ik ＝f*C(VOH －VOL )對於此實例，結果為：Ik ＝12.5*0.065(3.3)＝2.681毫安培上式使用介於高資料位準與低資料位準之間典型的3.3伏擺動。在驅動讀取啟用訊號RE＿過程中消耗之電流將係電流Ik 的兩倍，此乃因其必須在每次轉變對其相對應之導體進行充電。假設有8條輸入/輸出線I/O1至I/O8，因此，在此項實例之習知常態操作模式中所消耗之總電流將係：Itotal ＝8(2.681)＋2(2.681)＝26.81毫安培Conventional flash memory devices utilize the well-known 3.3 volt busbar standard in which the minimum high level output voltage (V OH ) is 2.4 volts and the maximum low level output voltage (V OL ) is 0.4 volts, and its nominal voltage swing It is about 3.3 volts. As is known in the art, according to this standard, their voltages are based on a nominal supply voltage of 3.30 volts and are specified between 2.70 volts and 3.60 volts. According to the conventional normal mode of operation of modern flash memory devices, the output data rate is 25 MHz (ie, a data transition every 40 nanoseconds), and a data transition is performed in each cycle at a given input/output line I/Ok. In the worst case, the flash memory device 10 will be required to charge the capacitance of the input/output line I/Ok at a frequency of 12.5 MHz. Assuming a typical line capacitance of the input/output line I/Ok is 65 pF, the current consumption of an input/output line I/Ok (in milliamps) can be calculated from: I k =f*C(V OH -V OL ) For this example, the result is: I k =12.5*0.065 (3.3) = 2.681 mA The above equation uses a typical 3.3 volt swing between the high data level and the low data level. The current consumed in driving the read enable signal RE_ will be twice the current I k because it must charge its corresponding conductor at each transition. Suppose there are 8 input/output lines I/O1 to I/O8, so the total current consumed in the conventional normal mode of operation of this example would be: I total = 8 (2.681) + 2 (2.681) = 26.81 Milliamper

根據本發明之較佳具體實施例，匯流排電壓從此習知3.3伏匯流排位準實質上減小(例如)至約1.8伏之匯流排電壓，其定義標稱電壓擺動為1.8伏。在此情況中，最小輸出高位準電壓VOH－R 限制之實例可係約1.44伏(標稱電源供應電壓之80%)，並且最大低輸出位準電壓VOL－R 之實例可係約0.36伏(標稱電源供應電壓之20%)。在此減小電壓操作中，彼等電壓係以標稱上為1.80伏的電源供應電壓為基礎，並且所准許之範圍係從約1.60伏至約2.0伏。假設最佳情況(對於資料傳送；對於電流消耗之最壞情況)的資料速率為50 MHz，輸入/輸出線I/O1至I/On的充電頻率將係25 MHz。因此，可利用下式計算單個輸入/輸出線I/Ok所消耗的電流Ik ：Ik ＝25*0.065(1.8)＝2.925毫安培上式使用介於高資料位準與低資料位準之間典型的1.8伏擺動。因此，對於進階操作模式，此每輸入/輸出線之電流消耗的差異不大，然而提供兩倍之資料速率。但是，讀取啟用訊號RE＿係以相同於常態操作模式的頻率操作(但是以每一邊沿(而非僅以上升邊沿)計時一個資料字)。但是，當然亦減小其電壓擺動，此乃因其亦以1.8伏匯流排電壓運作；就其本身而論，其消耗之電流相同於該等輸入/輸出線中之一者消耗之電流。再次假設有8條輸入/輸出線I/O1至I/O8，因此，在此項實例之進階操作模式中所消耗之總電流將係：Itotal ＝8(2.925)＋1(2.925)＝26.33毫安培其稍微小於以3.3伏匯流排電壓運作之習知快閃記憶體卡消耗之總電流。並且，因為此稍低之電流消耗係以對於輸入/輸出訊號的較低電壓擺動(1.8伏相對於3.3伏)予以達成，所以在此進階操作模式中消耗之功率實質上小於習知快閃記憶體卡中消耗之功率。根據彼等實例，在常態操作模式中之習知8 I/O快閃記憶體中消耗之功率將係約88毫瓦特(3.3伏乘26.81毫安培)，然而上文所述之本發明較佳具體實施例之實例消耗之功率將係約47毫瓦特(1.8伏乘26.33毫安培)。此實質減小之功率消耗係結合實質改良之資料傳送速率(約大型叢發之資料速率的兩倍)予以達成。In accordance with a preferred embodiment of the present invention, the busbar voltage is substantially reduced from the conventional 3.3 volt busbar level, for example, to a busbar voltage of about 1.8 volts, which defines a nominal voltage swing of 1.8 volts. In this case, the example of the minimum output high level voltage V OH-R limit may be about 1.44 volts (80% of the nominal power supply voltage), and the example of the maximum low output level voltage V OL-R may be about 0.36. Volts (20% of the nominal power supply voltage). In this reduced voltage operation, these voltages are based on a nominal supply voltage of 1.80 volts and are permitted to range from about 1.60 volts to about 2.0 volts. Assuming a best case (for data transfer; worst case for current consumption) at a data rate of 50 MHz, the input/output lines I/O1 to I/On will have a charging frequency of 25 MHz. Therefore, the current I k consumed by a single input/output line I/Ok can be calculated by the following equation: I k =25*0.065(1.8)=2.925 mA. The above formula uses a high data level and a low data level. A typical 1.8 volt swing. Therefore, for the advanced mode of operation, this difference in current consumption per input/output line is small, but provides twice the data rate. However, the read enable signal RE_ operates at the same frequency as the normal mode of operation (but with one edge per clock (rather than just rising edges)). However, of course, its voltage swing is also reduced because it also operates at a 1.8 volt bus voltage; as such, it consumes the same current as one of the input/output lines. Again assume that there are eight input/output lines I/O1 to I/O8, so the total current consumed in the advanced mode of operation of this example would be: I total = 8 (2.925) +1 (2.925) = 26.33 The milliamperes are slightly less than the total current consumed by conventional flash memory cards operating at 3.3 volts busbar voltage. Also, since this slightly lower current draw is achieved with a lower voltage swing (1.8 volts versus 3.3 volts) for the input/output signal, the power consumed in this advanced mode of operation is substantially less than the conventional flash. The power consumed in the memory card. According to these examples, the power consumed in conventional 8 I/O flash memory in the normal mode of operation will be about 88 milliwatts (3.3 volts by 26.81 milliamps), although the invention described above is preferred. The power consumed by the example of a particular embodiment would be about 47 milliwatts (1.8 volts by 26.33 milliamperes). This substantially reduced power consumption is achieved in conjunction with a substantially improved data transfer rate (about twice the data rate of a large burst).

因此，根據本發明之較佳具體實施例，其中以較低匯流排電壓(相對於習知快閃記憶體裝置)執行進階讀取資料傳送，在進階模式中消耗之電流不會比習知快閃記憶體裝置在常態操作模式中消耗之電流更槽。並且，在根據本發明之此項較佳具體實施例中，其中快閃記憶體裝置10亦具有以常態操作模式運作之能力，進階模式與常態操作模式運作兩者中使用較低之匯流排電壓，並且亦對於包括命令與位址值之傳達的其他操作使用較低之匯流排電壓。就其本身而論，快閃記憶體裝置10在傳送資料中消耗之功率低於習知快閃記憶體裝置。Therefore, in accordance with a preferred embodiment of the present invention in which advanced read data transfer is performed with a lower bus voltage (relative to conventional flash memory devices), the current consumed in the advanced mode is not It is known that the flash memory device consumes more current in the normal mode of operation. Moreover, in the preferred embodiment of the present invention, the flash memory device 10 also has the ability to operate in a normal mode of operation, and the lower bus is used in both the advanced mode and the normal mode of operation. The voltage, and also the lower bus voltage, is used for other operations including the transmission of commands and address values. For its part, the flash memory device 10 consumes less power in transmitting data than conventional flash memory devices.

如前文所述，在常態操作模式中傳達命令訊號與位址訊號。為了易於實施，較佳方式為，用於傳達彼等訊號之匯流排電壓亦維持在較低匯流排電壓(例如，1.8伏)，其提供額外減小快閃記憶體卡25之功率消耗。As described above, the command signal and the address signal are conveyed in the normal mode of operation. For ease of implementation, it is preferred that the busbar voltages used to communicate their signals are also maintained at a lower busbar voltage (e.g., 1.8 volts), which provides additional reduction in power consumption of the flash memory card 25.

請重新參考圖5a，根據本發明之此項具體實施例之快閃記憶體裝置10能夠回應來自控制器30的暫停請求。根據本發明，預期控制器30為了若干原因中任一者(例如，其內部接收資料緩衝器已滿)而認為必須暫停讀取資料傳送。就其本身而論，圖5a之決策51決定是否需要此一暫停。若否，則以上文關於圖6a之描述所述的方式，於處理程序56中繼續進行高速讀取資料傳送。Referring again to FIG. 5a, the flash memory device 10 in accordance with this embodiment of the present invention is capable of responding to a suspend request from the controller 30. In accordance with the present invention, controller 30 is expected to consider having to suspend reading data transfer for any of a number of reasons (e.g., its internal receive data buffer is full). For its part, decision 51 of Figure 5a determines whether this suspension is required. If not, the high speed read data transfer continues in processing 56 in the manner described above with respect to the description of FIG. 6a.

如果控制器30需要暫停讀取資料傳送(決策51決定"是")，則其於處理程序52中發佈暫停請求。在此項示範性實施中，控制器30於讀取傳送操作期間藉由確證(assert)位址鎖存啟用訊號ALE上之作用中高位準而提出此項請求。圖6b繪示此暫停操作，其發生於進階模式中之讀取資料傳送期間(即，已調用進階模式並且已開始資料傳送)。在圖6b之實例中，於自快閃記憶體裝置10至控制器30之資料傳送期間，控制器30藉由確證位址鎖存啟用訊號ALE而請求資料傳送暫停。作為回應，快閃記憶體裝置10暫停讀取啟用訊號RE＿(當在低位準(如圖所示)或在高位準時)，並且在暫停讀取啟用訊號RE＿之後延遲發佈下一資料字。假定在此進階模式中讀取啟用訊號RE＿與輸入/輸出線I/O1至I/On之迅速切換速率，預期在位址鎖存啟用訊號ALE被驅動至作用中高狀態以請求暫停之後，快閃記憶體裝置10可驅動一個或兩個額外資料字以及讀取啟用訊號RE＿之相對應邊沿。在此實例中，於輸出資料字Dout (4)期間，控制器30已確證位址鎖存啟用訊號ALE，並且於輸出資料字Dout (6)期間，快閃記憶體裝置10藉由保持讀取啟用訊號RE＿及輸入/輸出線I/O1至I/On之進一步轉變而作出回應。If the controller 30 needs to suspend the read data transfer (decision 51 decides "Yes"), it issues a pause request in the processing program 52. In this exemplary implementation, the controller 30 makes this request during the read transfer operation by asserting the address latch to enable the mid-high level on the enable signal ALE. Figure 6b illustrates this pause operation, which occurs during the read data transfer in the advanced mode (i.e., the advanced mode has been invoked and data transfer has begun). In the example of FIG. 6b, during data transfer from the flash memory device 10 to the controller 30, the controller 30 requests a data transfer pause by confirming the address latch enable signal ALE. In response, the flash memory device 10 suspends the read enable signal RE_ (when at the low level (as shown) or at the high level) and delays the release of the next data word after the read enable signal RE_ is suspended. Assuming that the fast switching rate of the enable signal RE_ and the input/output lines I/O1 to I/On is read in this advanced mode, it is expected that after the address latch enable signal ALE is driven to the active high state to request the pause, the fast The flash memory device 10 can drive one or two additional data words and read the corresponding edge of the enable signal RE_. In this example, during output of the data word D out (4), the controller 30 has confirmed the address latch enable signal ALE, and during the output of the material word D out (6), the flash memory device 10 is maintained. A response is made by reading the enable signal RE_ and the further transition of the input/output lines I/O1 to I/On.

此暫停進一步資料傳送持續，直到控制器30執行處理程序54以撤銷啟動位址鎖存啟用訊號ALE，因此結束暫停。如圖6b所示，在控制器30使位址鎖存啟用訊號ALE成為非作用中低狀態後隨即結束此暫停狀態。根據本發明之此項具體實施例，位址鎖存啟用訊號ALE之此轉變係用作為來自快閃記憶體裝置10之下一輸出資料字(在此實例中係資料字Dout (7))的讀取資料選通。在此起始暫停後之資料字之後，快閃記憶體裝置10藉由確證讀取啟用訊號RE_之轉變而再次產生讀取選通訊號，如圖所示。在此實例中，讀取啟用訊號RE＿之下一轉變係用於繼暫停時期結束之後的第二輸出資料字Dout (8)的選通。於處理程序56中繼續進行進階模式讀取資料傳送，如圖6b所示。This pause further data transfer continues until controller 30 executes processing 54 to deactivate the enable address latch enable signal ALE, thus ending the pause. As shown in FIG. 6b, the pause state is terminated immediately after the controller 30 causes the address latch enable signal ALE to become the inactive low state. According to this embodiment of the invention, the transition of the address latch enable signal ALE is used as an output data word from the underlying flash memory device 10 (in this example, the data word D out (7)) Read data strobe. After the start of the suspended data word, the flash memory device 10 reproduces the read selection communication number by confirming the transition of the read enable signal RE_ as shown. In this example, the read enable signal RE_next transition is for gating of the second output material word Dout (8) after the end of the pause period. The advanced mode read data transfer continues in the processing program 56, as shown in Figure 6b.

請重新參考圖5a，繼續進行進階模式讀取資料傳送直到控制器30想要終止傳送之時，其在處理程序58、59中向快閃記憶體裝置10指示出其想要終止傳送。典型地，在控制器30決定正在抵達快閃記憶體裝置10內之頁尾後隨即終止此傳送，然而控制器30亦可為了其他原因(例如，在接收到用於操作的全部所要資料之後)終止傳送。Referring again to Figure 5a, proceeding with the advanced mode read data transfer until the controller 30 wants to terminate the transfer, it indicates to the flash memory device 10 in the processing program 58, 59 that it wants to terminate the transfer. Typically, the transfer is terminated immediately after the controller 30 determines that it is reaching the end of the flash memory device 10, however the controller 30 may also be for other reasons (eg, after receiving all of the desired material for operation) Termination of the transfer.

根據此項實例，為了終止此資料傳送，控制器30首先於處理程序58中發佈暫停，例如，藉由確證位址鎖存啟用訊號ALE之作用中高位準，如上文所述。圖6c繪示終止處理程序58、59之實例，圖中繪示在進階讀取資料傳送操作期間位址鎖存啟用訊號ALE之轉變。控制器30於暫停操作期間實行處理程序59，使處理程序58之暫停操作變換至終止進階讀取資料傳送。替代做法為，可於快閃記憶體裝置10本身決定其輸出資料已抵達頁尾之後實行處理程序59，在此情況中，快閃記憶體裝置10本身使讀取啟用訊號RE＿維持在其最後位準，並且在輸入/輸出線I/O1至I/On上維持現行(即，最後的)輸出資料字；在此情況中，位址鎖存啟用訊號ALE仍是維持非作用中低狀態。在圖6c所示之此實例中，控制器30在位址鎖存啟用訊號ALE係處於作用中高位準時確證命令鎖存啟用訊號CLE上之作用中高位準，而終止此資料傳送。回應於此命令鎖存啟用訊號CLE之轉變，快閃記憶體裝置10控制其輸出驅動器以將輸入/輸出線I/O1至I/On置於高阻抗狀態，並且亦釋放其對相對應於讀取啟用訊號RE＿的導體之控制，在彼兩種情況中，准許控制器30在適當時取得對彼等線路之控制，同時避免資料競爭問題。如圖6c之實例中所示，因為暫停操作與終止操作發生於讀取啟用訊號RE＿處於低位準，所以一旦控制器30取得對讀取啟用訊號RE＿之控制，隨即驅動相對應之線路上之非作用中高位準，導致如圖所示之轉變；如果暫停操作與終止操作發生於讀取啟用訊號RE＿已處於高位準，則當然在此線路上無任何轉變。In accordance with this example, to terminate this data transfer, the controller 30 first issues a pause in the handler 58, for example, by verifying that the address latch enables the high level of the enable signal ALE, as described above. Figure 6c illustrates an example of termination handlers 58, 59, which illustrate the transition of the address latch enable signal ALE during an advanced read data transfer operation. Controller 30 executes processing routine 59 during the suspend operation to cause the suspend operation of handler 58 to transition to terminate the advanced read data transfer. Alternatively, the processing program 59 can be executed after the flash memory device 10 itself determines that its output data has reached the end of the page, in which case the flash memory device 10 itself maintains the read enable signal RE_ at its last bit. The current (ie, last) output data word is maintained on the input/output lines I/O1 to I/On; in this case, the address latch enable signal ALE remains in the inactive low state. In the example shown in FIG. 6c, the controller 30 terminates the data transfer when the address latch enable signal ALE is at the active high level to confirm the high level of the command latch enable signal CLE. In response to the transition of the command latch enable signal CLE, the flash memory device 10 controls its output driver to place the input/output lines I/O1 to I/On in a high impedance state, and also releases its pair corresponding to the read. Control of the conductors that enable the signal RE_, in both cases, permits the controller 30 to gain control of its lines when appropriate, while avoiding data contention issues. As shown in the example of FIG. 6c, since the suspend operation and the termination operation occur when the read enable signal RE_ is at a low level, once the controller 30 obtains control of the read enable signal RE_, the corresponding line is driven. The high level of action results in a transition as shown; if the pause and terminate operations occur when the read enable signal RE_ is already at a high level, then of course there is no transition on this line.

接著，快閃記憶體裝置10返回常態操作模式("舊型"模式)，將控制傳回至圖5a之流程圖中的處理程序44。根據本發明之此項較佳具體實施例，新的進階模式讀取資料傳送將需要起始處理程序48之另一執行個體(instance)。Next, the flash memory device 10 returns to the normal mode of operation ("old mode" mode), and control is passed back to the process 44 in the flow chart of Figure 5a. In accordance with this preferred embodiment of the present invention, a new advanced mode read data transfer would require another execution entity of the start process 48.

進一步，在替代做法中，如果控制器30撤銷確證晶片啟用訊號CE＿，則將發生無條件終止。但是，預期此項無條件終止可導致在快閃記憶體裝置10及控制器30之內部與外部發生"差錯"及其他假性且未指定的事件。Further, in the alternative, if the controller 30 revokes the verification wafer enable signal CE_, an unconditional termination will occur. However, it is contemplated that this unconditional termination can result in "errors" and other false and unspecified events occurring inside and outside of flash memory device 10 and controller 30.

根據本發明之此項較佳具體實施例，對於自控制器30至快閃記憶體裝置10之資料傳送(換言之，對於寫入資料傳送操作)亦提供進階高效能模式。圖5b之流程圖連同圖6a與6d至6e之時序圖繪示此項操作，現在將予以描述。In accordance with this preferred embodiment of the present invention, an advanced high performance mode is also provided for data transfer from controller 30 to flash memory device 10 (in other words, for write data transfer operations). The flow chart of Figure 5b, together with the timing diagrams of Figures 6a and 6d through 6e, illustrates this operation and will now be described.

為了實現進階模式寫入資料傳送，快閃記憶體裝置10自常態操作模式開始，進入處理程序60。如同讀取資料傳送之情況，在處理程序62中首先實行此常態模式操作(若有的話)。在處理程序64中，在此常態操作模式中，控制器30發佈位址值至快閃記憶體裝置10，如上文關於圖4b之描述所述。並且於處理程序66中，控制器30以類似於上文關於圖6a描述之進階讀取資料傳送所述的實行方式起始進階資料傳送模式。預期於處理程序66中將於此進階模式中執行的寫入資料傳送實質上完全相同於讀取資料傳送。就其本身而論，舉例而言，預期於處理程序66中發佈之命令值IDT_CMD對於讀取資料傳送操作與寫入資料傳送操作皆相同。替代做法為，可對於該兩種操作指派彼此不同的命令值。In order to implement the advanced mode write data transfer, the flash memory device 10 enters the processing program 60 from the normal mode of operation. This normal mode operation (if any) is first implemented in the processing program 62 as is the case with the read data transfer. In the process 64, in this normal mode of operation, the controller 30 issues an address value to the flash memory device 10 as described above with respect to Figure 4b. And in processing 66, controller 30 initiates an advanced data transfer mode in an implementation similar to that described above with respect to FIG. 6a. It is contemplated that the write data transfer performed in this advanced mode in processing 66 is substantially identical to the read data transfer. For its part, for example, the command value IDT_CMD issued in the processing program 66 is expected to be the same for both the read data transfer operation and the write data transfer operation. Alternatively, different command values may be assigned to each of the two operations.

在處理程序68中，控制器30與快閃記憶體裝置10實行進階寫入資料傳送。圖6d繪示此項操作(包括處理程序66)之實例中的訊號時序，其中由控制器30發佈命令值IDT_CMD、命令鎖存啟用訊號CLE之作用中高位準與寫入啟用訊號WE＿之作用中低脈衝的組合至快閃記憶體裝置10，因此起始進階模式資料傳送。如同先前之實例，使位址鎖存啟用訊號ALE維持在非作用中低位準，以及使晶片啟用訊號CE維持在作用中低位準。並且因為此項操作將係一項資料寫入操作，所以控制器30使讀取啟用訊號RE＿(圖中6d未繪示)始終保持在非作用中高狀態。在本發明之此項具體實施例中，因為寫入資料傳送處理程序68仍是在控制器30之完全控制下，所以介於發佈命令IDT_CMD與開始寫入資料傳送之間的延時可比讀取資料傳送中第一輸出資料字(圖6a)之前的延時短許多。較佳方式為，介於相對應於起始命令IDT_CMD的寫入啟用訊號WE_之脈衝之上升邊沿與相對應於第一輸入資料字Din (0)的寫入啟用訊號WE＿之第一脈衝之下降邊沿之間歷時一指定時間，如圖所示。In the processing program 68, the controller 30 and the flash memory device 10 perform advanced write data transfer. 6d illustrates the signal timing in the example of the operation (including the processing program 66), wherein the controller 30 issues the command value IDT_CMD, the command latch enable signal CLE, and the write enable signal WE_. The combination of low pulses is coupled to the flash memory device 10, thus initiating advanced mode data transfer. As in the previous example, the address latch enable signal ALE is maintained at the inactive low level and the wafer enable signal CE is maintained at the active low level. And since this operation will be a data write operation, the controller 30 causes the read enable signal RE_ (not shown in Fig. 6d) to remain in the inactive high state at all times. In this embodiment of the present invention, since the write data transfer processing program 68 is still under the full control of the controller 30, the delay between the issue command IDT_CMD and the start of the write data transfer can be compared to the read data. The delay before the transmission of the first output data word (Fig. 6a) is much shorter. Preferably, the rising edge of the write enable signal WE_ corresponding to the start command IDT_CMD and the first pulse of the write enable signal WE_ corresponding to the first input data word D in (0) The falling edge spans a specified time as shown.

在本發明之此項較佳具體實施例中，一旦寫入資料傳送開始，寫入啟用訊號WE＿之上升邊沿與下降邊沿兩者皆用作為寫入資料選通，由控制器30確證。如圖6d所示，此准許控制器30以同步於寫入啟用訊號WE＿之每一邊沿的方式發佈新的有效寫入資料字Din (k)至輸入/輸出線I/O1至I/On上。結果，對於相同之寫入啟用訊號WE＿頻率，此進階模式中之寫入資料傳送速率可係常態操作模式寫入操作之資料速率的約兩倍。In the preferred embodiment of the present invention, once the write data transfer begins, both the rising edge and the falling edge of the write enable signal WE_ are used as the write data strobe, which is verified by the controller 30. As shown in FIG. 6d, the grant controller 30 issues a new valid write data word D in (k) to the input/output lines I/O1 to I/On in synchronization with each edge of the write enable signal WE_. on. As a result, for the same write enable signal WE_frequency, the write data transfer rate in this advanced mode can be approximately twice the data rate of the normal operation mode write operation.

根據本發明之此項具體實施例，請重新參考圖5b，進階模式寫入資料傳送中亦實行暫停決策69。典型地，僅由控制器30決定對於寫入暫停之需求，其預期快閃記憶體裝置10可依此資料速率接收輸入資料而無緩衝器溢位等等。如果不需要暫停(決策69決定"否")，則於處理程序72中繼續進行資料傳送。如果控制器30要求暫停(決策69決定"是")，則於處理程序70中實現寫入資料傳送之暫停。在此實例中，控制器30視需要延長寫入啟用訊號WE＿而簡單地實現暫停處理程序70。可在任一狀態(寫入啟用訊號WE＿保持高狀態或保持低狀態)中實行此暫停；圖6d繪示於寫入資料字Din (2)之持續期間的暫停處理程序70，其中使寫入啟用訊號WE＿保持低狀態。當然，在暫停處理程序70期間，控制器30不發佈額外寫入資料字Din (k)。控制器30僅僅驅動寫入啟用訊號WE＿之轉變連同下一有效寫入資料字Din (3)(在圖6d所示之實例中)而實現暫停時期結束，以繼續進行寫入資料傳送(處理程序72)。In accordance with this embodiment of the present invention, please refer back to FIG. 5b again, and the pause decision 69 is also implemented in the advanced mode write data transfer. Typically, only the controller 30 determines the need for a write suspend that expects the flash memory device 10 to receive input data at this data rate without buffer overflow or the like. If no pause is required (decision 69 decides "No"), then data transfer continues in process 72. If the controller 30 requests a timeout (decision 69 decides "Yes"), then a stall of the write data transfer is implemented in the handler 70. In this example, controller 30 simply implements suspend handler 70 as needed to extend write enable signal WE_. This pause can be implemented in either state (the write enable signal WE_ remains high or remains low); Figure 6d illustrates the pause handler 70 during the duration of the write data word D in (2), where writes are made Enable signal WE_ remains low. Of course, during the suspend processing routine 70, the controller 30 does not issue an extra write material word D in (k). The controller 30 only drives the transition of the write enable signal WE_ together with the next valid write data word D in (3) (in the example shown in Figure 6d) to effect the end of the pause period to continue the write data transfer (processing Procedure 72).

並且，如同讀取資料傳送之情況，資料訊號與控制訊號之電壓位準(輸入/輸出線I/O1至I/On，及用於寫入啟用訊號WE＿之線路)較佳係低於習知位準的電壓位準，舉例而言，具有介於高邏輯位準與低邏輯位準之間的1.8伏"擺動"。如上文詳細論述所述，在二分之一資料速率下，此較低電壓之匯流排將使此進階寫入資料傳送模式所消耗之功率維持等於或小於在常態操作模式中運作之習知快閃記憶體系統中消耗之功率。Moreover, as in the case of reading data transmission, the voltage level of the data signal and the control signal (input/output lines I/O1 to I/On, and the line for writing the enable signal WE_) are preferably lower than the conventional ones. The level of the voltage level, for example, has a 1.8 volt "wobble" between the high logic level and the low logic level. As discussed in detail above, at a data rate of one-half, this lower voltage bus will maintain the power consumed by this advanced write data transfer mode equal to or less than the normal operation in the normal mode of operation. The power consumed in a flash memory system.

請重新參考圖5b且結合圖6e，以完全相同於終止讀取資料傳送之方式實現終止寫入資料傳送。在處理程序74中，控制器30在處理程序74中確證位址鎖存啟用訊號ALE至作用中高位準以暫停傳送，並且接著在處理程序76中確證命令鎖存啟用訊號CLE至作用中高位準(同時使位址鎖存啟用訊號ALE維持高位準)，其接著終止寫入資料傳送。圖6e繪示終止寫入資料傳送過程中各種訊號之時序。寫入啟用訊號WE＿保持在高位準(如圖6e所示)，或在已鎖存最後資料字Din (5)(在此實例中)之後自低位準轉為高位準。繼終止進階模式寫入資料傳送(藉由使位址鎖存啟用訊號ALE與命令鎖存啟用訊號CLE分別保持高位準達指定脈衝寬度而實現)之後，接著再次進入快閃記憶體裝置10與控制器30之常態操作模式。Referring back to FIG. 5b and in conjunction with FIG. 6e, the termination of the write data transfer is implemented in exactly the same manner as terminating the read data transfer. In the processing 74, the controller 30 verifies in the processing 74 the address latch enable signal ALE to the active high level to suspend the transfer, and then in the processing program 76 confirms the command latch enable signal CLE to the active high level. (At the same time, the address latch enable signal ALE is maintained at a high level), which then terminates the write data transfer. Figure 6e illustrates the timing of various signals during the termination of the write data transfer. The write enable signal WE_ remains at a high level (as shown in Figure 6e) or transitions from a low level to a high level after the last data word D in (5) has been latched (in this example). Following the termination of the advanced mode write data transfer (by enabling the address latch enable signal ALE and the command latch enable signal CLE to remain high for a specified pulse width, respectively), then entering the flash memory device 10 again The normal mode of operation of controller 30.

在此實例中，考慮到需要執行命令以調用進階模式，並且考慮到在資料傳送終止時快閃記憶體裝置10之運作返回常態操作模式(即，不需要執行命令)，常態操作模式實際上係"預設"操作模式。替代做法為，可組態快閃記憶體裝置10，使得需要執行命令才能進入進階資料傳送模式與常態操作模式兩者，致使一旦快閃記憶體裝置10係處於進階資料傳送模式中，則其仍是處於該模式中，直到控制器30發佈返回常態操作模式之命令且快閃記憶體裝置10執行該命令為止。當然，此種做法涉及命令序列本質上的額外耗用。In this example, the normal mode of operation is actually considered in view of the need to execute a command to invoke the advanced mode, and considering that the operation of the flash memory device 10 returns to the normal mode of operation when the data transfer is terminated (ie, no command is required to be executed). The "preset" operating mode. Alternatively, the flash memory device 10 can be configured such that a command needs to be executed to enter both the advanced data transfer mode and the normal mode of operation, such that once the flash memory device 10 is in the advanced data transfer mode, It is still in this mode until the controller 30 issues a command to return to the normal mode of operation and the flash memory device 10 executes the command. Of course, this approach involves the extra cost of the command sequence.

進一步，在替代做法中，快閃記憶體裝置10之"預設"操作模式可係進階資料傳送模式，致使在進階模式中實行所有資料傳送，直到控制器30發佈命令以使快閃記憶體裝置10進入常態操作模式為止。根據本發明之此項替代具體實施例，一旦快閃記憶體裝置10係處於常態操作模式，則完成資料傳送將導致快閃記憶體裝置10返回進階資料傳送模式。Further, in the alternative, the "preset" mode of operation of the flash memory device 10 can be an advanced data transfer mode, such that all data transfers are performed in the advanced mode until the controller 30 issues a command to flash the memory. The body device 10 enters the normal mode of operation. In accordance with this alternative embodiment of the present invention, once the flash memory device 10 is in the normal mode of operation, completing the data transfer will cause the flash memory device 10 to return to the advanced data transfer mode.

圖7繪示根據本發明替代較佳具體實施例建構之快閃記憶體裝置10的操作，其中進階資料傳送模式實際上係"預設"模式。在處理程序80中，供電給快閃記憶體裝置10與控制器30，或以其他方式完成重設操作，並且在處理程序82中進入進階操作模式(實際上作為預設條件)，而不需要發佈或執行命令。於處理程序84中，在進階資料傳送操作模式中實行讀取操作與寫入操作，實際上如上文關於圖6b至6d之描述所述。舉例而言，在此進階模式中，預期可如上文關於圖6c之描述所述實行暫停操作及類似操作；進一步預期其他操作(諸如位址、命令與狀態通信操作)仍然可遵循常態操作模式做法(若希望)。7 illustrates the operation of a flash memory device 10 constructed in accordance with a preferred embodiment of the present invention, wherein the advanced data transfer mode is in fact a "preset" mode. In the processing program 80, power is supplied to the flash memory device 10 and the controller 30, or the reset operation is otherwise completed, and the advanced operation mode (actually as a preset condition) is entered in the processing program 82 without Need to issue or execute commands. In processing 84, the read and write operations are performed in the advanced data transfer mode of operation, as described above with respect to Figures 6b through 6d. For example, in this advanced mode, it is contemplated that the suspend operation and the like can be performed as described above with respect to FIG. 6c; further it is contemplated that other operations, such as address, command and status communication operations, can still follow the normal mode of operation. Practice (if desired).

在處理程序86中，根據本發明此項較佳具體實施例之快閃記憶體卡25準備常態(或"舊型")模式方式為：由控制器30發佈位址值至快閃記憶體裝置10，該位址值指示出常態操作模式傳送的開始記憶體位址。在處理程序88中，控制器30發佈命令序列以起始常態操作模式；預期此命令序列實質上對應於上文關於圖6a之描述所述，而該命令序列本身較佳係按照常態操作模式運作(預期命令碼值係單個位元組值)。回應於命令88，快閃記憶體裝置10依據資料傳送之方向而實行常態操作模式讀取或寫入資料傳送操作，例如，如上文關於圖4c與4d之描述所述。在本發明之此項具體實施例中，較佳方式為，控制器30發佈讀取資料選通控制訊號與寫入資料選通控制訊號兩者，如上文所述。In the processing program 86, the flash memory card 25 according to the preferred embodiment of the present invention prepares the normal (or "old" mode) mode: the controller 30 issues the address value to the flash memory device. 10. The address value indicates the start memory address of the normal operation mode transmission. In process 88, controller 30 issues a sequence of commands to initiate a normal mode of operation; it is contemplated that this sequence of commands substantially corresponds to that described above with respect to Figure 6a, and that the sequence of commands itself preferably operates in a normal mode of operation. (The expected command code value is a single byte value). In response to command 88, flash memory device 10 performs a normal mode of operation read or write data transfer operation depending on the direction of data transfer, for example, as described above with respect to Figures 4c and 4d. In this embodiment of the invention, preferably, the controller 30 issues both the read data strobe control signal and the write data strobe control signal, as described above.

並且，根據本發明之此項替代較佳具體實施例，在完成資料傳送後隨即退出常態操作模式。在圖7之實例中，類似於如上文關於圖5a與5b之描述所述。在處理程序92中，控制器30發佈暫停訊號(例如，位址鎖存啟用訊號上的作用中位準)而終止資料傳送，其後在處理程序93中，控制器30終止傳送(例如，藉由發佈命令鎖存啟用訊號之作用中位準)。根據本發明之此項較佳具體實施例，在終止常態操作模式資料傳送之後，控制返回處理程序84，其中再次進入進階資料傳送操作模式，並且在處理程序84中按需要實行讀取與寫入資料傳送操作。Moreover, in accordance with this alternative embodiment of the present invention, the normal mode of operation is exited upon completion of the data transfer. In the example of Figure 7, it is similar to that described above with respect to Figures 5a and 5b. In processing 92, controller 30 issues a pause signal (e.g., an active level on the address latch enable signal) to terminate the data transfer, and thereafter in process 93, controller 30 terminates the transfer (e.g., borrows The level of the enable signal is latched by the issue command). In accordance with this preferred embodiment of the present invention, after terminating the normal mode of operation data transfer, control returns to the process 84 where the advanced data transfer mode of operation is again entered and the read and write are performed as needed in the process 84. Enter the data transfer operation.

已參閱此份說明書的熟悉此項技術者應明白，除了本發明之此項替代較佳具體實施例以外，預期尚有進入與退出快閃記憶體裝置10之各種操作模式的替代做法，並且亦應明白，彼等及此類其他替代實施方案皆歸屬於如申請專利範圍之本發明範疇內。Those skilled in the art having access to this specification will appreciate that in addition to this alternative embodiment of the present invention, alternative approaches to entering and exiting the flash memory device 10 are contemplated, and It is to be understood that these and other alternative embodiments are within the scope of the invention as claimed.

現在請參考圖8a至圖8e，現在將詳細說明在根據本發明之第二較佳具體實施例的快閃記憶體卡25背景中介於快閃記憶體裝置10與控制器30之間的訊號之時序。在根據本發明之第二較佳具體實施例的進階模式期間，進入與退出操作的整體處理程序較佳係遵循上文關於圖5a之讀取操作所述的處理程序及關於圖5a之寫入操作所述的處理程序。就其本身而論，此處在結合圖8a至圖8e之描述將不重複彼等處理程序之詳細描述。Referring now to Figures 8a through 8e, the signal between the flash memory device 10 and the controller 30 in the context of the flash memory card 25 in accordance with the second preferred embodiment of the present invention will now be described in detail. Timing. During the advanced mode in accordance with the second preferred embodiment of the present invention, the overall processing of the entry and exit operations preferably follows the processing described above with respect to the read operation of Figure 5a and with respect to Figure 5a. Enter the processing procedure described. As such, the detailed description of the processing procedures herein will not be repeated in connection with the description of Figures 8a-8e.

如上文關於本發明之第一較佳具體實施例之描述所述，快閃記憶體裝置10與控制器30在經供電後皆處於常態操作模式(或"舊型"模式)。就其本身而論，由使用者按需要實行在此常態模式中的讀取操作與寫入操作(若有的話)。接著，在常態操作模式中由控制器30發佈記憶體位址值(其相對應於在此進階操作模式中將自該處讀取資料的起始記憶體位址)至快閃記憶體裝置10，以實行進入讀取操作的進階操作模式。如上文所述，結合位址鎖存啟用訊號ALE上的作用中位準，將此記憶體位址置於輸入/輸出線I/O1至I/On上。As described above with respect to the first preferred embodiment of the present invention, the flash memory device 10 and the controller 30 are in a normal mode of operation (or "old" mode) after being powered. For its part, the user performs the read and write operations (if any) in this normal mode as needed. Then, in the normal operation mode, the controller 30 issues a memory address value (corresponding to the starting memory address from which the data is to be read in the advanced operation mode) to the flash memory device 10, To implement an advanced mode of operation that enters the read operation. As described above, this memory address is placed on the input/output lines I/O1 to I/On in conjunction with the active bit on the address latch enable signal ALE.

在傳達記憶體位址後，控制器30藉由使晶片啟用訊號CE＿成為作用中低狀態、使位址鎖存啟用訊號ALE成為非作用中低狀態及使命令鎖存啟用訊號CLE成為作用中高狀態，而發佈一「起始資料傳送」(或「IDT」)命令序列至快閃記憶體裝置10，如上文所述。圖8a繪示此項操作。寫入啟用訊號WE＿之作用中低脈衝之上升邊沿係用作為用於由控制器30驅動至輸入/輸出線I/O1至I/On上之IDT命令值IDT_CMD(其係二進位字且值不同於其他指派之命令值)的資料選通。繼寫入啟用訊號WE＿正處於高狀態之後的一特定時間之後，控制器30使輸入/輸出線I/O1至I/On成為高阻抗狀態。After the memory address is communicated, the controller 30 causes the address enable signal ALE to be in the inactive low state and the command latch enable signal CLE to become the active high state by causing the wafer enable signal CE_ to be in the active low state. A "Start Data Transfer" (or "IDT") command sequence is issued to the flash memory device 10 as described above. Figure 8a illustrates this operation. The rising edge of the low-pulse pulse applied to the enable signal WE_ is used as the IDT command value IDT_CMD for driving to the input/output lines I/O1 to I/On by the controller 30 (the binary word is different in value) Data strobes for other assigned command values). After a certain time after the write enable signal WE_ is in the high state, the controller 30 causes the input/output lines I/O1 to I/On to be in a high impedance state.

根據本發明之此項第二較佳具體實施例，快閃記憶體裝置10將取得對讀取啟用訊號RE＿之控制且驅動讀取啟用訊號RE＿。據此，如圖8a示，在選通IDT命令的寫入啟用訊號WE＿之上升邊沿後歷時時間trel 之後，控制器30隨即釋放其對讀取啟用訊號RE＿之控制。接著，快閃記憶體裝置10的控制邏輯18驅動相對應之線RE＿的狀態，而不需要與控制器30競爭。接著，快閃記憶體裝置10開始實行高速進階模式讀取資料傳送。根據本發明之此項第二較佳具體實施例，如圖8a示，快閃記憶體裝置10結合較高頻率之讀取啟用訊號RE＿(高於舊型模式中可取得之頻率)，以較高資料速率(高於舊型模式中之資料速率)提供來自經位址記憶體單元的資料。According to this second preferred embodiment of the present invention, the flash memory device 10 will take control of the read enable signal RE_ and drive the read enable signal RE_. Accordingly, as shown in FIG. 8a, after lapse of time t rel after the rising edge of the write enable signal WE_ of the strobe IDT command, the controller 30 then releases its control of the read enable signal RE_. Next, the control logic 18 of the flash memory device 10 drives the state of the corresponding line RE_ without competing with the controller 30. Next, the flash memory device 10 starts the high speed advanced mode read data transfer. According to this second preferred embodiment of the present invention, as shown in FIG. 8a, the flash memory device 10 incorporates a higher frequency read enable signal RE_ (higher than the frequency available in the old mode). The high data rate (higher than the data rate in the old mode) provides data from the address memory unit.

舉例而言，在此進階模式中，快閃記憶體裝置10結合以舊型模式中讀取啟用訊號之頻率的兩倍之頻率驅動讀取啟用訊號RE＿，以舊型模式中提供資料之頻率的兩倍之頻率在輸入/輸出線I/O1至I/On處提供輸出資料。對於在舊型模式中最大可用資料速率與讀取選通頻率係25 MHz的實例中，進階模式資料速率及讀取啟用訊號RE＿之頻率可係高達50 MHz。因為快閃記憶體裝置10本身正在發佈讀取啟用訊號RE＿且亦發佈資料字，所以快閃記憶體裝置10產生彼等訊號的頻率係不在控制器30之直接控制下。For example, in this advanced mode, the flash memory device 10 drives the read enable signal RE_ in combination with the frequency of reading the enable signal in the old mode to the frequency of the data provided in the old mode. The frequency twice is provided at the input/output lines I/O1 to I/On. For the example of the maximum available data rate and the read strobe frequency of 25 MHz in the legacy mode, the advanced mode data rate and the read enable signal RE_ can be as high as 50 MHz. Since the flash memory device 10 itself is issuing the read enable signal RE_ and also issues the data word, the frequency at which the flash memory device 10 generates the signals is not under the direct control of the controller 30.

圖8a繪示此項進階模式讀取操作。繼寫入啟用訊號WE＿之上升邊沿之後歷時非零存取時間之後，讀取資料傳送處理程序開始於快閃記憶體裝置10發佈第一有效輸出資料字Dout (0)。在快閃記憶體裝置10提供第一輸出資料字Dout (0)之後，接著其以同步於額外輸出資料字Dout (1)以及下列等等之方式開始發佈讀取啟用訊號RE＿之作用中脈衝。根據本發明之此項較佳具體實施例，以同步於讀取啟用訊號RE＿之每一完整循環方式發佈一個資料字Dout (k)。在圖8a之實例中，讀取啟用訊號RE＿之下降邊沿係與其同步之資料字的訊號邊沿；當然，讀取啟用訊號RE＿(即，讀取啟用訊號"RE")之上升邊沿可作為替代地作為操作邊沿。如圖8a示，每一輸出資料字Dout (k)係接在其相對應之讀取啟用訊號RE＿之下降邊沿之後相差非零存取時間。替代做法為，可於相對應的有效資料字Dout (k)內發佈(或延遲發佈)讀取啟用訊號RE＿之每一下降邊沿至控制器30。Figure 8a illustrates this advanced mode read operation. After the non-zero access time has elapsed after the rising edge of the write enable signal WE_, the read data transfer process begins with the flash memory device 10 issuing the first valid output data word Dout (0). After the flash memory device 10 provides the first output material word D out (0), it then begins to issue the read enable signal RE_ in synchronization with the additional output data word D out (1) and the like. pulse. In accordance with this preferred embodiment of the present invention, a data word D out (k) is issued in synchronization with each complete cycle of the read enable signal RE_. In the example of FIG. 8a, the falling edge of the read enable signal RE_ is the signal edge of the data word synchronized with it; of course, the rising edge of the read enable signal RE_ (ie, the read enable signal "RE") can alternatively be used instead. As an operating edge. As shown in Figure 8a, each output data word Dout (k) is coupled to a falling non-zero access time after the falling edge of its corresponding read enable signal RE_. Alternatively, each falling edge of the read enable signal RE_ can be issued (or delayed) to the controller 30 within the corresponding valid data word D out (k).

根據本發明之此項第二較佳具體實施例，因此，對於快閃記憶體裝置10經由輸入/輸出線I/O1至I/On提供資料至控制器30的速率：在此進階模式中的速率實質上快於常態操作模式(圖4d)中的速率，大約係典型實現中之資料速率的兩倍。在某種程度上，實現此較高資料速率之方式為：准許快閃記憶體裝置10發佈讀取啟用訊號RE＿之讀取資料選通邊沿，其排除若控制器30發佈彼等讀取資料選通邊沿情況下所涉及的傳播延遲與必然的時序窗。此外，如上文關於本發明之第一較佳具體實施例之描述所述，藉由使用資料訊號之經減小電壓擺動(以及讀取啟用訊號RE＿之經減小電壓擺動，若需要)，達成在輸入/輸出線I/O1至I/On處的增加之資料速率，而不會急遽增加快閃記憶體裝置10及控制器30的功率消耗。如上文所述，彼等線路之標稱匯流排電壓從此習知3.3伏匯流排位準實質上減小(例如)至約1.80伏之匯流排電壓。According to this second preferred embodiment of the present invention, therefore, the rate at which the flash memory device 10 provides data to the controller 30 via the input/output lines I/O1 to I/On: in this advanced mode The rate is substantially faster than the rate in the normal mode of operation (Fig. 4d), which is approximately twice the data rate in a typical implementation. To some extent, the higher data rate is achieved by allowing the flash memory device 10 to issue a read data strobe edge of the read enable signal RE_, which excludes if the controller 30 issues their read data. The propagation delay involved in the case of the edge and the inevitable timing window. Moreover, as described above with respect to the first preferred embodiment of the present invention, the voltage swing is reduced by using the data signal (and the voltage swing is reduced by reading the enable signal RE_, if needed) The increased data rate at input/output lines I/O1 through I/On does not rush to increase the power consumption of flash memory device 10 and controller 30. As noted above, the nominal busbar voltages of their lines are substantially reduced, for example, to a busbar voltage of about 1.80 volts from the conventional 3.3 volt busbar level.

對於介於快閃記憶體裝置10與控制器30之間的一16位元輸入/輸出匯流排介面(即，有16條輸入/輸出線I/O1至I/On)之實例，本發明之此項第二較佳具體實施例所涉及的功率消耗僅稍微多於本發明之第一較佳具體實施例所涉及的功率消耗。如上文所述，根據本發明之此項較佳具體實施例，以50 MHz之資料速率，用於輸入/輸出線I/O1至I/On的充電頻率將係25 MHz。因此，可利用下式計算用於單個輸入/輸出線I/Ok所消耗的電流Ik ：Ik＝25*0.065(1.8)＝2.925 mA上式使用介於高資料位準與低資料位準之間典型的1.8伏擺動。但是，因為讀取啟用訊號RE_係在常態操作模式中及本發明第一較佳具體實施例中在該頻率的兩倍之頻率運作，並且其電流消耗本身將係單個輸入/輸出線I/Ok之電流消耗的兩倍：IRE ＝50*0.065(1.8)＝2*2.925毫安培＝5.850毫安培據此，對於有16條輸入/輸出線I/O1至I/O16之情況，因此在用於此項實例的進階操作模式中所消耗之總電流將係：Itotal ＝16(2.925)＋5.850＝52.65毫安培其稍微多於根據本發明之第一較佳具體實施例所消耗的電流(即，49.73毫安培)。遵循上文所述，對於一16位元I/O匯流排之情況，習知資料傳送所消耗之總電流將係：Itotal ＝16(2.681)＋2(2.681)＝48.62毫安培其稍微低於根據本發明之根據本發明之此項第二較佳具體實施例所消耗的電流52.65毫安培。但是，即使根據本發明之此項較佳具體實施例所消耗的電流稍微高於習知實施方案，但是此電流位準係以對於輸入/輸出訊號的較低電壓擺動(1.8伏相對於3.3伏)予以達成。結果，在此進階操作模式中消耗之功率實質上小於習知快閃記憶體卡中消耗之功率。根據彼等實例，在該常態操作模式中之一習知16I/O快閃記憶體中消耗之功率將係約160毫瓦特(3.3伏乘48.62毫安培)，然而上文所述之本發明較佳具體實施例之實例消耗之功率將係約95毫瓦特(1.8伏乘52.65毫安培)。此功率消耗之實質減小係結合資料傳送速率(接近用於大型叢發之資料速率的兩倍)之實質改良予以達成。For an example of a 16-bit input/output bus interface (ie, having 16 input/output lines I/O1 to I/On) between the flash memory device 10 and the controller 30, the present invention The power consumption involved in this second preferred embodiment is only slightly greater than the power consumption involved in the first preferred embodiment of the present invention. As described above, in accordance with this preferred embodiment of the present invention, the charging frequency for the input/output lines I/O1 to I/On will be 25 MHz at a data rate of 50 MHz. Therefore, the current I k used for a single input/output line I/Ok can be calculated by the following formula: Ik=25*0.065(1.8)=2.925 mA. The above formula uses a high data level and a low data level. A typical 1.8 volt swing. However, since the read enable signal RE_ operates in the normal mode of operation and at twice the frequency of the first preferred embodiment of the invention, and its current consumption itself is a single input/output line I/ The current consumption of Ok is twice: I RE = 50 * 0.065 (1.8) = 2 * 2.925 mA = 5.850 mA. Therefore, for the case of 16 input/output lines I/O1 to I/O16, therefore The total current consumed in the advanced mode of operation for this example would be: I total = 16 (2.925) + 5.850 = 52.65 milliamps, which is slightly more than the first preferred embodiment of the present invention. The current (ie, 49.73 mA). Following the above, for a 16-bit I/O bus, the total current consumed by conventional data transfer would be: I total = 16 (2.681) + 2 (2.681) = 48.62 mA, which is slightly lower. The current consumed in accordance with this second preferred embodiment of the present invention in accordance with the present invention is 52.65 milliamperes. However, even though the current consumed in accordance with this preferred embodiment of the present invention is slightly higher than conventional embodiments, this current level is oscillated at a lower voltage for the input/output signal (1.8 volts versus 3.3 volts). ) to be reached. As a result, the power consumed in this advanced mode of operation is substantially less than the power consumed in conventional flash memory cards. According to their examples, the power consumed in one of the normal mode of operation of conventional 16I/O flash memory will be about 160 milliwatts (3.3 volts by 48.62 milliamperes), although the invention described above is more The power consumed by the example of a preferred embodiment will be about 95 milliwatts (1.8 volts by 52.65 milliamperes). This substantial reduction in power consumption is achieved in combination with a substantial improvement in the data transfer rate (nearly twice the data rate for large bursts).

如上文所述，舉例而言，如果控制器30之輸入緩衝器(來自快閃記憶體裝置10)填滿，則可發佈暫停請求至快閃記憶體裝置10。圖8b中繪示快閃記憶體裝置10回應此暫停請求之操作。控制器30於讀取傳送操作期間藉由確證(assert)位址鎖存啟用訊號ALE上之作用中高位準而提出暫停請求。回應此項請求，快閃記憶體裝置10暫停讀取啟用訊號RE＿(當在高位準(如圖所示)或在低位準時)，並且延遲讀取啟用訊號RE＿之下一循環。因為高資料速率傳送，所以一個或兩個額外資料字(及讀取啟用訊號RE＿之相對應循環)可能已在快閃記憶體裝置10的輸出"管線"中，使得可在快閃記憶體裝置10對暫停報告作出反應之前輸出彼等相對應之資料字。在此實例中，於輸出資料字Dout (4)期間，控制器30已確證位址鎖存啟用訊號ALE，並且於輸出資料字Dout (6)期間，快閃記憶體裝置10藉由保持讀取啟用訊號RE＿之進一步循環及輸入/輸出線I/O1至I/On之轉變而作出回應。As described above, for example, if the input buffer of the controller 30 (from the flash memory device 10) is full, a pause request can be issued to the flash memory device 10. The operation of the flash memory device 10 in response to this pause request is illustrated in Figure 8b. The controller 30 asserts a suspend request during the read transfer operation by asserting the address latch to enable the mid-high level on the enable signal ALE. In response to this request, the flash memory device 10 suspends the read enable signal RE_ (when at the high level (as shown) or at the low level) and delays reading the enable signal RE_ for the next cycle. Because of the high data rate transfer, one or two additional data words (and corresponding cycles of the read enable signal RE_) may already be in the output "line" of the flash memory device 10, making it possible to flash memory devices 10 Output their corresponding information words before responding to the suspension report. In this example, during output of the data word D out (4), the controller 30 has confirmed the address latch enable signal ALE, and during the output of the material word D out (6), the flash memory device 10 is maintained. The response is read by reading the further loop of the enable signal RE_ and the transition of the input/output lines I/O1 to I/On.

圖8c繪示根據本發明之此項較佳具體實施例終止進階模式高速讀取資料傳送。如上文所述，控制器30首先藉由確證位址鎖存啟用訊號ALE之作用中高位準來發佈暫停報告，藉此終高速資料傳送。在暫停請求期間，控制器30在位址鎖存啟用訊號ALE係處於作用中高位準時藉由確證命令鎖存啟用訊號CLE上之作用中高位準，而終止資料傳送操作。作為回應，快閃記憶體裝置10促使其輸出驅動器將輸入/輸出線I/O1至I/On置於高阻抗狀態，並且亦釋放其對相對應於讀取啟用訊號RE＿的導體之控制。現在，若適合下一操作，則控制器30可取得對彼等線路之控制。Figure 8c illustrates the termination of advanced mode high speed read data transfer in accordance with this preferred embodiment of the present invention. As described above, the controller 30 first issues a suspend report by confirming the mid-high level of the address latch enable signal ALE, thereby finalizing the high speed data transfer. During the suspend request, the controller 30 terminates the data transfer operation by asserting the command to latch the mid-high level on the enable signal CLE when the address latch enable signal ALE is at the active high level. In response, the flash memory device 10 causes its output driver to place the input/output lines I/O1 to I/On in a high impedance state and also release its control of the conductor corresponding to the read enable signal RE_. Now, if suitable for the next operation, controller 30 can take control of their lines.

現在將參考圖8d與圖8e來說明根據本發明之此項第二較佳具體實施例的進階模式中寫入操作。如同讀取資料傳送之情況，在快閃記憶體裝置10與控制器30已運作於常態(或舊型)模式中之後進入進階模式。進入寫入操作之進階資料傳送模式之實行方式類似於上文關於圖8a描述之進階讀取資料傳送所述的實行方式。如圖8d所示，控制器30結合命令鎖存啟用訊號CLE上之作用中高位準及寫入啟用訊號WE＿之作用中低脈衝而發佈進階模式命令值IDT_CMD。如上文所述，使位址鎖存啟用訊號ALE維持在非作用中低位準，以及使晶片啟用訊號CE維持在作用中低位準。控制器30在整個資料寫入操作期間使讀取啟用訊號RE＿(圖8d中未繪示)維持在非作用中高狀態，來指示出對於資料寫入操作進入進階模式。接著，准許介於對應起始命令IDT_CMD的寫入啟用訊號WE＿之脈衝之上升邊沿與相對應於第一輸入資料字Din (0)的寫入啟用訊號WE_之第一脈衝之下降邊沿之間歷時一指定時間。The write operation in the advanced mode according to this second preferred embodiment of the present invention will now be described with reference to Figs. 8d and 8e. As in the case of reading data transfer, the advanced mode is entered after the flash memory device 10 and the controller 30 have been operating in the normal (or old) mode. The advanced data transfer mode of entering the write operation is performed in a manner similar to that described above with respect to the advanced read data transfer described with respect to Figure 8a. As shown in FIG. 8d, the controller 30 issues the advanced mode command value IDT_CMD in conjunction with the middle and low levels of the active high level and the write enable signal WE_ on the command enable signal CLE. As described above, the address latch enable signal ALE is maintained at the inactive low level and the wafer enable signal CE is maintained at the active low level. The controller 30 maintains the read enable signal RE_ (not shown in FIG. 8d) in an inactive high state during the entire data write operation to indicate that the data write operation enters the advanced mode. Then, the rising edge of the pulse of the write enable signal WE_ corresponding to the start command IDT_CMD and the falling edge of the first pulse of the write enable signal WE_ corresponding to the first input data word D in (0) are permitted. The time is specified by the time.

根據本發明之此項第二較佳具體實施例，在此進階模式寫入資料傳送期間，使寫入啟用訊號WE＿之循環的頻率增加(例如)至在常態模式中寫入時使用的寫入啟用訊號WE＿之循環的頻率之兩倍。在此實例中，寫入啟用訊號WE＿的下降邊沿係用作為寫入資料選通。而且，在此進階模式中及在常態模式中，控制器30結合控制器30在輸入/輸出線I/O1至I/On上驅動的資料值來確證寫入啟用訊號WE＿。如圖8d所示，控制器30以同步於寫入啟用訊號WE＿之每一下降邊沿的方式發佈新的有效寫入資料字Din (k)至輸入/輸出線I/O1至I/On上。在此實例中，因為寫入啟用訊號WE＿之頻率加倍，所以此進階模式中之寫入資料傳送速率可係常態操作模式寫入操作之資料速率的約兩倍。舉例而言，如果最大寫入資料傳送速率及寫入啟用訊號頻率係25 MHz，則在根據本發明之此項第二較佳具體實施例的進階模式中，可使資料傳送速率及寫入啟用訊號頻率增加高達50 MHz。根據本發明之此項具體實施例建構快閃記憶體裝置10，使得其能夠以該較高速率接收及處理資料。當然，控制器30可依據系統應用及控制器30本身處理資料的速率，使用低於最大頻率(例如，50 MHz)的實際寫入啟用訊號頻率及資料速率頻率。According to this second preferred embodiment of the present invention, during the advanced mode write data transfer, the frequency of the cycle of writing the enable signal WE_ is increased, for example, to the write used in the normal mode write. Double the frequency of the loop that enables the signal WE_. In this example, the falling edge of the write enable signal WE_ is used as the write data strobe. Moreover, in this advanced mode and in the normal mode, the controller 30 confirms the write enable signal WE_ in conjunction with the data values driven by the controller 30 on the input/output lines I/O1 to I/On. As shown in FIG. 8d, the controller 30 issues a new valid write data word D in (k) to the input/output lines I/O1 to I/On in synchronization with each falling edge of the write enable signal WE_. . In this example, because the frequency of the write enable signal WE_ is doubled, the write data transfer rate in this advanced mode can be approximately twice the data rate of the normal operation mode write operation. For example, if the maximum write data transfer rate and the write enable signal frequency are 25 MHz, the data transfer rate and write can be made in the advanced mode according to the second preferred embodiment of the present invention. The enable signal frequency is increased by up to 50 MHz. Flash memory device 10 is constructed in accordance with this embodiment of the invention such that it can receive and process data at the higher rate. Of course, controller 30 can use the actual write enable signal frequency and data rate frequency below the maximum frequency (eg, 50 MHz) depending on the system application and the rate at which controller 30 itself processes the data.

再者，根據本發明之此項具體實施例，可將暫停***於進階模式寫入資料傳送中。如上文所述，在此實例中，控制器30藉由視需要延長寫入啟用訊號WE＿而簡單地暫停寫入資料傳送。如圖8d所示。可在任一狀態(寫入啟用訊號WE＿保持高狀態或保持低狀態)中實行此暫停。當然，在此暫停時期期間，不發佈新的資料字Din (k)。控制器30驅動寫入啟用訊號WE＿之下一循環連同下一有效寫入資料字Din (3)(在圖8d所示之實例中)而結束暫停時期，以繼續進行寫入資料傳送。Furthermore, in accordance with this embodiment of the invention, the pause can be inserted into the advanced mode write data transfer. As described above, in this example, the controller 30 simply suspends the write data transfer by extending the write enable signal WE_ as needed. As shown in Figure 8d. This pause can be implemented in either state (write enable signal WE_ remains high or remains low). Of course, during this pause period, the new material word D in (k) is not released. The controller 30 drives the write enable signal WE_ next cycle along with the next valid write data word D in (3) (in the example shown in Figure 8d) to end the pause period to continue the write data transfer.

並且，如同讀取資料傳送之情況，資料訊號與控制訊號之電壓位準(輸入/輸出線I/O1至I/On，及用於寫入啟用訊號WE＿之線路)較佳係低於習知位準的電壓位準，舉例而言，具有介於高邏輯位準與低邏輯位準之間的1.8伏"擺動"。如上文詳細論述所述，在二分之一資料速率下，此較低電壓之匯流排將使此進階寫入資料傳送模式所消耗之功率維持等於或小於在常態操作模式中運作之習知快閃記憶體系統中消耗之功率。Moreover, as in the case of reading data transmission, the voltage level of the data signal and the control signal (input/output lines I/O1 to I/On, and the line for writing the enable signal WE_) are preferably lower than the conventional ones. The level of the voltage level, for example, has a 1.8 volt "wobble" between the high logic level and the low logic level. As discussed in detail above, at a data rate of one-half, this lower voltage bus will maintain the power consumed by this advanced write data transfer mode equal to or less than the normal operation in the normal mode of operation. The power consumed in a flash memory system.

現在請參考圖8e，進階模式寫入資料傳送之實行方式相同於根據本發明之此項第二較佳具體實施例的進階讀取資料傳送。控制器30驅動位址鎖存啟用訊號ALE至作用中高位準以暫停寫入傳送而終止進階模式，在此期間，控制器30確證命令鎖存啟用訊號CLE至作用中高位準(同時使位址鎖存啟用訊號ALE維持高位準)以終止寫入資料傳送。寫入啟用訊號WE＿保持在高位準，或在已鎖存最後資料字Din (5)(在此實例中)之後轉為高位準。繼終止進階模式寫入資料傳送(藉由使位址鎖存啟用訊號ALE與命令鎖存啟用訊號CLE分別保持高位準達指定脈衝寬度而實現)之後，接著再次進入快閃記憶體裝置10與控制器30之常態操作模式。Referring now to Figure 8e, the advanced mode write data transfer is performed in the same manner as the advanced read data transfer in accordance with this second preferred embodiment of the present invention. The controller 30 drives the address latch enable signal ALE to the active high level to suspend the write transfer to terminate the advanced mode, during which the controller 30 confirms the command latch enable signal CLE to the active high level (while making the bit The address latch enable signal ALE maintains a high level to terminate the write data transfer. The write enable signal WE_ remains at the high level or goes high after the last data word D in (5) has been latched (in this example). Following the termination of the advanced mode write data transfer (by enabling the address latch enable signal ALE and the command latch enable signal CLE to remain high for a specified pulse width, respectively), then entering the flash memory device 10 again The normal mode of operation of controller 30.

因此，根據本發明之此項第二較佳具體實施例，可藉由准許使用較高頻率之選通訊號來增加資料速率，以替代方式實行高速資料傳送操作模式。預期根據本發明之第二較佳具體實施例的此項操作可更相容於一些快閃記憶體應用中的所要操作。Thus, in accordance with this second preferred embodiment of the present invention, the high speed data transfer mode of operation can be implemented in an alternative manner by permitting the use of higher frequency select communication numbers to increase the data rate. It is contemplated that this operation in accordance with the second preferred embodiment of the present invention may be more compatible with the desired operation in some flash memory applications.

請重新參考圖2，並且根據本發明之第三較佳具體實施例，讀取啟用訊號RE＿與寫入啟用訊號WE＿兩者皆是雙向。對於常態操作模式中之讀取操作，外部裝置(即係正在自快閃記憶體陣列12讀取資料之目的地)係讀取資料選通的來源，接著作為一至快閃記憶體裝置10的輸入來載運該讀取資料選通以作為讀取啟用RE＿訊號。在此常態操作模式中的寫入操作，正在提供輸入資料的外部裝置以同步於將輸入資料置於輸入/輸出線I/O1至I/On處之方式發佈寫入資料選通以作為寫入啟用WE＿訊號。在根據本發明之較佳具體實施例的進階操作模式中之讀取操作中，如下文中的進一步詳細說明所述，控制邏輯18發佈兩個讀取資料選通(彼此相移)，該等讀取資料選通中之一者係讀取啟用RE＿訊號，另一者係寫入啟用WE＿訊號。彼等訊號之每一者的邊沿或轉變將同步於自快閃記憶體陣列12讀取資料且經由資料暫存器14、I/O控制電路20與輸入/輸出終端I/O1至I/On傳達資料。同樣地，藉由使用讀取啟用RE＿訊號與寫入啟用WE＿訊號兩者作為寫入資料選通(由資料來源發佈至快閃記憶體裝置10)，在進階操作模式中實行寫入操作。Referring back to FIG. 2, and according to the third preferred embodiment of the present invention, both the read enable signal RE_ and the write enable signal WE_ are bidirectional. For a read operation in the normal mode of operation, the external device (ie, the destination from which data is being read from the flash memory array 12) is the source of the read data strobe, and is input to the input of the flash memory device 10. The read data strobe is carried to be used as a read enable RE_signal. In the write operation in this normal operation mode, an external device that is providing input data issues a write data strobe as a write in synchronization with placing the input data at the input/output lines I/O1 to I/On. Enable WE_ signal. In a read operation in an advanced mode of operation in accordance with a preferred embodiment of the present invention, control logic 18 issues two read data strobes (phase shifts from each other), as described in further detail below, One of the read data strobes reads the enable RE_signal and the other writes the enable WE_signal. The edges or transitions of each of the signals will be synchronized to the data read from the flash memory array 12 and via the data register 14, the I/O control circuit 20, and the input/output terminals I/O1 to I/On. Communicate the information. Similarly, the write operation is performed in the advanced mode of operation by using both the read enable RE_signal and the write enable WE_signal as write data strobes (published by the data source to the flash memory device 10).

在本發明之此項第三較佳具體實施例中，請參考圖3，線RE＿載送用於舊型模式讀取操作(自快閃記憶體裝置10讀取資料且將資料傳達至控制器30)之資料選通，並且其本身係連接至快閃記憶體裝置1之終端RE＿(圖2)。如上文所述，根據本發明之此項第三較佳具體實施例，控制線RE＿為雙向，而讀取資料選通之來源取決於快閃記憶體裝置10之現行操作模式。在常態操作模式中，控制器30發佈讀取資料選通，快閃記憶體裝置10回應其而維持作為存在於訊號線I/O1至I/On上的有效資料。在根據本發明之較佳具體實施例的進階操作模式中，快閃記憶體裝置10係在線RE＿上發佈讀取資料選通，以用於將資料自快閃記憶體裝置10傳送至控制器30。並且亦如下文中的進一步詳細說明所述，於進階模式寫入操作期間，控制器30亦將選通線RE＿。因此，類似於線WE＿，在根據本發明較佳具體實施例之進階資料傳送模式中之讀取操作與寫入操作兩者中需要控制線RE＿，以提供第二相移選通訊號，該第二相移選通訊號係用於在讀取操作與寫入操作兩者中選通交替之資料字。In the third preferred embodiment of the present invention, referring to FIG. 3, the line RE_ is carried for the old mode read operation (reading data from the flash memory device 10 and transmitting the data to the controller) 30) The data strobe is itself connected to the terminal RE_ of the flash memory device 1 (Fig. 2). As described above, in accordance with this third preferred embodiment of the present invention, the control line RE_ is bidirectional, and the source of the read data strobe depends on the current mode of operation of the flash memory device 10. In the normal mode of operation, the controller 30 issues a read data strobe that the flash memory device 10 maintains as valid data present on the signal lines I/O1 to I/On. In an advanced mode of operation in accordance with a preferred embodiment of the present invention, the flash memory device 10 issues a read data strobe on the line RE_ for transmitting data from the flash memory device 10 to the controller. 30. Also, as described in further detail below, controller 30 will also gate line RE_ during an advanced mode write operation. Therefore, similar to the line WE_, the control line RE_ is required in both the read operation and the write operation in the advanced data transfer mode according to the preferred embodiment of the present invention to provide the second phase shift selection communication number. The second phase shift selection communication number is used to gate alternate data words in both the read operation and the write operation.

如同下文進一步詳細描述所述，控制器30透過訊號線I/O1至I/On所傳達之命令同步於訊號線RE＿上的讀取資料選通來源，而不顧慮快閃記憶體裝置10正在傳送資料至控制器30的操作模式。As described in further detail below, the command communicated by controller 30 via signal lines I/O1 through I/On is synchronized to the read data strobe source on signal line RE_, regardless of the flash memory device 10 being transmitted. The data is sent to the operating mode of the controller 30.

因此，根據本發明之較佳具體實施例，快閃記憶體裝置10提供進階較高效能之讀取與寫入操作模式，並且控制器30經建構以利用該進階模式。現在將參考圖5a與5b之流程圖以及圖9a至9e之時序圖來詳細描述根據本發明之此項第三較佳具體實施例快閃記憶體裝置10與控制器30利用此進階模式之操作。Thus, in accordance with a preferred embodiment of the present invention, flash memory device 10 provides an advanced higher performance read and write mode of operation, and controller 30 is configured to utilize the advanced mode. The flash memory device 10 and the controller 30 according to the third preferred embodiment of the present invention will now be described in detail with reference to the flowcharts of FIGS. 5a and 5b and the timing diagrams of FIGS. 9a through 9e. operating.

圖5a以及圖9a至9c繪示快閃記憶體裝置10在實行資料讀取操作(即，在快閃記憶體卡25中，自快閃記憶體裝置10至控制器30)過程中之操作。在圖5a之處理程序40中，供電給快閃記憶體裝置10與控制器30，使該兩個裝置進入常態操作模式中(處理程序42)，如上文關於圖4a至4d之描述所述。在處理程序44中，在此常態操作模式(即，"舊型"模式)中，實行在此常態模式中的讀取操作與寫入操作(若有的話)。5a and 9a through 9c illustrate the operation of the flash memory device 10 during the data reading operation (i.e., in the flash memory card 25 from the flash memory device 10 to the controller 30). In the process 40 of Figure 5a, power is supplied to the flash memory device 10 and controller 30 to bring the two devices into a normal mode of operation (process 42) as described above with respect to Figures 4a through 4d. In the processing program 44, in this normal mode of operation (i.e., "old" mode), read operations and write operations (if any) in this normal mode are performed.

進入進階讀取操作模式開始於處理程序46，其中控制器30按照常態操作模式發佈記憶體位址值至快閃記憶體裝置10，如上文關於圖4b之描述所述。在處理程序46中由控制器30所發佈之記憶體位址係在此進階操作模式中將自該處讀取資料的起始記憶體位址，並且較佳係繼傳輸相對應之讀取位址輸入命令之後，如上文所述。在處理程序48中，控制器30發佈"起始資料傳送"或"IDT"命令序列至快閃記憶體裝置10。圖9a進一步詳細繪示此項操作。Entering the advanced read mode of operation begins with a process 46 in which the controller 30 issues a memory address value to the flash memory device 10 in accordance with the normal mode of operation, as described above with respect to FIG. 4b. The memory address issued by the controller 30 in the processing program 46 is the starting memory address from which the data will be read in this advanced mode of operation, and preferably the corresponding read address is transmitted. After entering the command, as described above. In the processing program 48, the controller 30 issues a "start data transfer" or "IDT" command sequence to the flash memory device 10. This operation is illustrated in further detail in Figure 9a.

根據本發明之較佳具體實施例，在處理程序48中，控制器30發佈"IDT讀取"命令至快閃記憶體裝置10，以起始進階資料傳送模式。以類似於上文關於圖4a之描述所述之方式發佈此命令，其中控制器30驅動晶片啟用訊號CE＿至作用中低狀態、驅動位址鎖存啟用訊號ALE至非作用中低狀態及驅動命令鎖存啟用訊號CLE至作用中高狀態。寫入啟用訊號WE＿之作用中低脈衝之上升邊沿係用作為用於由控制器30驅動至輸入/輸出線I/O1至I/On上之IDT命令值IDT_RD_CMD(其係二進位字且值不同於其他指派之命令值)的資料選通。繼寫入啟用訊號WE_正處於高狀態之後的一特定時間之後，控制器30使輸入/輸出線I/O1至I/On成為高阻抗狀態。並且，繼寫入啟用訊號WE＿之上升邊沿之後的另一歷時時間trel 之後，當選通IDT讀取命令時，接著控制器30亦釋放其對讀取啟用訊號RE＿之控制，准許快閃記憶體裝置10之控制邏輯18驅動相對應於線RE＿之狀態(無與控制器30發生資料競爭之風險)。根據本發明之此項較佳具體實施例，在進入進階資料傳送模式後隨即藉由IDT命令之值來建置進階模式資料傳送之方向(即，寫入或讀取)，其准許在資料傳送本身中使用讀取啟用訊號RE＿與寫入啟用訊號WE＿兩個，如下文所述。In accordance with a preferred embodiment of the present invention, in processing 48, controller 30 issues an "IDT Read" command to flash memory device 10 to initiate an advanced data transfer mode. This command is issued in a manner similar to that described above with respect to FIG. 4a, in which controller 30 drives wafer enable signal CE_ to active low state, drive address latch enable signal ALE to inactive low state, and drive command. The enable signal CLE is latched to the active high state. The rising edge of the low-pulse pulse applied to the enable signal WE_ is used as the IDT command value IDT_RD_CMD for driving to the input/output lines I/O1 to I/On by the controller 30 (the binary word is different in value) Data strobes for other assigned command values). After a certain time after the write enable signal WE_ is in the high state, the controller 30 causes the input/output lines I/O1 to I/On to be in a high impedance state. Moreover, after another duration t rel after the rising edge of the write enable signal WE_, when the strobe IDT read command is followed, the controller 30 also releases its control of the read enable signal RE_, permitting the flash memory. Control logic 18 of device 10 drives the state corresponding to line RE_ (without the risk of data competition with controller 30). According to the preferred embodiment of the present invention, after entering the advanced data transfer mode, the direction of the advanced mode data transfer (ie, writing or reading) is established by the value of the IDT command, which permits The data transfer itself uses the read enable signal RE_ and the write enable signal WE_, as described below.

替代做法為，進入進階資料傳送模式，以及在此模式中待實行讀取或寫入操作的指示，可用其他方式自控制器30傳達至快閃記憶體裝置10；舉例而言，特定之控制訊號轉變序列(例如，控制匯流排CTRL之一或多個線路上的控制訊號，包括連接至ALE、CLE、WP＿與CE＿線路的訊號線中之一或多者，連同讀取啟用訊號RE＿與寫入啟用訊號WE＿)。預期已參閱本份說明書之熟悉此項技術者將明瞭用於實施進入讀取操作與寫入操作中任一者或兩者之進階資料傳送模式的彼等與其他替代做法。Alternatively, entering the advanced data transfer mode, and the indication of the read or write operation to be performed in this mode, may be communicated from the controller 30 to the flash memory device 10 in other manners; for example, specific control Signal transition sequence (eg, control signal on one or more lines of the control bus CTRL, including one or more of the signal lines connected to the ALE, CLE, WP_, and CE_ lines, along with the read enable signal RE_ and write Enable the enable signal WE_). It is contemplated that those skilled in the art having access to this specification will be aware of other alternatives for implementing advanced data transfer modes for either or both of the read and write operations.

一旦IDT讀取命令已被鎖存於快閃記憶體裝置10中且由快閃記憶體裝置10予以執行，接著快閃記憶體裝置10開始執行高速模式讀取資料傳送處理程序50。如圖9a示，繼寫入啟用訊號WE＿之上升邊沿之後歷時非零存取時間之後，此讀取資料傳送處理程序開始於快閃記憶體裝置10發佈第一有效輸出資料字Dout (0)。一旦快閃記憶體裝置10提供此第一輸出資料字Dout (0)，接著其以同步於額外輸出資料字Dout (1)以及下列等等之交替者之方式開始發佈讀取啟用訊號RE＿與寫入啟用訊號WE＿兩者之作用中脈衝。根據本發明之此項較佳具體實施例，讀取啟用訊號RE＿與寫入啟用訊號WE＿彼此不同相，以每一者的相同邊沿(例如，在此實例中，係下降邊沿，然而當然可替代地使用上升邊沿)計時一相對應之資料字。如圖9a示，在此進階模式讀取操作中，寫入啟用訊號WE＿與讀取啟用訊號RE＿相對於彼此180°異相位。此互補式相位關係非屬根據本發明此項較佳具體實施例之操作的必要項，此乃因在下一交替下降邊沿(每當其發生時)後將隨即發生輸出資料字之選通；但是，為了以最快的指定程度最大化資料傳送速率，互補式相位關係為吾人所要的。如圖9a示，以同步於快閃記憶體裝置10本身所驅動的讀取啟用訊號RE_與寫入啟用訊號WE＿之每一下降邊沿方式發佈一個資料字Dout (k)。在圖9a之實例中，每一輸出資料字Dout (k)係接在其相對應的選通邊沿之後相差非零存取時間；替代做法為，可於相對應的有效資料字Dout (k)內發佈(或延遲發佈)每一讀取啟用訊號RE＿與寫入啟用訊號WE＿下降邊沿至控制器30。Once the IDT read command has been latched into the flash memory device 10 and executed by the flash memory device 10, then the flash memory device 10 begins executing the high speed mode read data transfer processing routine 50. As shown in FIG. 9a, after reading the rising edge of the enable signal WE_ for a non-zero access time, the read data transfer processing program begins with the flash memory device 10 issuing the first valid output data word D out (0). . Once the flash memory device 10 provides this first output material word D out (0), it then begins issuing the read enable signal RE_ in a manner synchronized with the alternate output data word D out (1) and the following. The pulse is applied to both the write enable signal WE_. According to this preferred embodiment of the invention, the read enable signal RE_ and the write enable signal WE_ are out of phase with each other, with the same edge of each (for example, in this example, the falling edge, but of course it can be replaced Use the rising edge to count a corresponding data word. As shown in FIG. 9a, in this advanced mode read operation, the write enable signal WE_ and the read enable signal RE_ are 180° out of phase with respect to each other. This complementary phase relationship is not a requirement for operation of this preferred embodiment of the present invention, as the output data word strobe will occur immediately after the next alternate falling edge (whenever it occurs); In order to maximize the data transfer rate with the fastest degree of designation, the complementary phase relationship is what we want. As shown in FIG. 9a, a data word D out (k) is issued in synchronization with each falling edge of the read enable signal RE_ and the write enable signal WE_ driven by the flash memory device 10 itself. In the example of Figure 9a, each output data word D out (k) is connected to its corresponding strobe edge by a non-zero access time; alternatively, the corresponding valid data word D out ( k) Release (or delay release) each read enable signal RE_ and write enable signal WE_ falling edge to controller 30.

根據本發明之較佳具體實施例，因此，對於快閃記憶體裝置10經由輸入/輸出線I/O1至I/On提供資料至控制器30的速率：在此進階模式中的速率實質上快於常態操作模式(圖4d)中的速率，大約係典型實現中之資料速率的兩倍。在某種程度上，實現此較高資料速率之方式為：准許快閃記憶體裝置10發佈讀取啟用訊號RE＿與寫入啟用訊號WE＿之讀取資料選通邊沿，其排除若控制器30發佈彼等讀取資料選通邊沿情況下所涉及的傳播延遲與必然的時序窗。此外，該兩個訊號之下降選通邊沿的頻率可接近單個訊號之下降選通邊沿的頻率之兩倍。在此讀取操作中可使用寫入啟用訊號WE＿，此乃因資料傳送之方向係藉由IDT讀取命令值予以設定。In accordance with a preferred embodiment of the present invention, therefore, the rate at which the flash memory device 10 provides data to the controller 30 via input/output lines I/O1 through I/On: the rate in this advanced mode is substantially The rate in the normal mode of operation (Fig. 4d) is approximately twice the data rate in a typical implementation. To some extent, the higher data rate is achieved by allowing the flash memory device 10 to issue the read enable signal RE_ and the write enable signal WE_ to read the data strobe edge, which is excluded if the controller 30 issues They read the propagation delay and the inevitable timing window involved in the data strobe edge. In addition, the frequency of the falling gate edges of the two signals can be close to twice the frequency of the falling gate edges of the individual signals. The write enable signal WE_ can be used in this read operation because the direction of data transfer is set by the IDT read command value.

然而，熟悉此項技術者應明白，在所有其他因數相等之情況下，在輸入/輸出線I/O1至I/On上提供輸出資料的增大速率實質上增大快閃記憶體卡25內的功率消耗，在此讀取操作中，功率消耗主要源自於快閃記憶體裝置10之I/O控制電路20內的輸出驅動電路。隨著資料字寬度(即，輸入/輸出線I/O1至I/On之數量n)增大(此為現代趨勢)，使此功率消耗惡化。根據本發明之較佳具體實施例，現在將描述藉由減小輸入/輸出線I/O1至I/On上之輸出訊號的電壓擺動而使此功率消耗大幅減小。However, those skilled in the art will appreciate that the rate of increase in the output data provided on input/output lines I/O1 through I/On substantially increases the amount of memory within flash memory card 25, with all other factors being equal. The power consumption, in this read operation, is primarily derived from the output drive circuitry within the I/O control circuitry 20 of the flash memory device 10. As the data word width (i.e., the number n of input/output lines I/O1 to I/On) increases (this is a modern trend), this power consumption is deteriorated. In accordance with a preferred embodiment of the present invention, it will now be described that this power consumption is substantially reduced by reducing the voltage swing of the output signals on input/output lines I/O1 through I/On.

習知快閃記憶體裝置利用熟知的3.3伏匯流排標準，其中使得最小高位準輸出電壓(VOH )係2.4伏並且最大低位準輸出電壓(VOL )係0.4伏，並且其標稱電壓擺動係約3.3伏。如此項技術所已知，根據此標準，彼等電壓係以標稱上為3.30伏的電源供應電壓為基礎，並且其規格範圍係在2.70伏與3.60伏之間。Conventional flash memory devices utilize the well-known 3.3 volt busbar standard in which the minimum high level output voltage (V OH ) is 2.4 volts and the maximum low level output voltage (V OL ) is 0.4 volts, and its nominal voltage swing It is about 3.3 volts. As is known in the art, according to this standard, their voltages are based on a nominal supply voltage of 3.30 volts and are specified between 2.70 volts and 3.60 volts.

根據本發明之較佳具體實施例，匯流排電壓從此習知3.3伏匯流排位準實質上減小(例如)至約1.8伏之匯流排電壓，其定義標稱電壓擺動為1.8伏。在此情況中，最小輸出高位準電壓VOH－R 限制之實例可係約1.44伏(標稱電源供應電壓之80%)，並且最大低輸出位準電壓VOL－R 之實例可係約0.36伏(標稱電源供應電壓之20%)。在此減小電壓操作中，彼等電壓係以標稱上為1.80伏的電源供應電壓為基礎，並且所准許之範圍係從約1.60伏至約2.0伏。可輕易地計算出：即使資料速率較高，在此進階操作模式中消耗之電流實質上不會較高於(且可能稍微低於)電壓擺動較高的常態操作模式中消耗之電流。原因在於在每一輸出處資料轉變而必須對寄生電容充電所到達的電壓低於電壓擺動較高的常態操作模式中之電壓。但是，輸入/輸出訊號之較低電壓擺動導致此進階操作模式中的功率消耗實質上低於習知快閃記憶體卡中消耗之功率。此實質減小之功率消耗係結合實質改良之資料傳送速率(約大型叢發之資料速率的兩倍)予以達成。In accordance with a preferred embodiment of the present invention, the busbar voltage is substantially reduced from the conventional 3.3 volt busbar level, for example, to a busbar voltage of about 1.8 volts, which defines a nominal voltage swing of 1.8 volts. In this case, the example of the minimum output high level voltage V OH-R limit may be about 1.44 volts (80% of the nominal power supply voltage), and the example of the maximum low output level voltage V OL-R may be about 0.36. Volts (20% of the nominal power supply voltage). In this reduced voltage operation, these voltages are based on a nominal supply voltage of 1.80 volts and are permitted to range from about 1.60 volts to about 2.0 volts. It can be easily calculated that even if the data rate is high, the current consumed in this advanced mode of operation will not be substantially higher (and possibly slightly lower) than the current consumed in the normal mode of operation with a higher voltage swing. The reason is that the voltage at which the parasitic capacitance must be charged at each output is lower than the voltage in the normal operating mode where the voltage swing is higher. However, the lower voltage swing of the input/output signals causes the power consumption in this advanced mode of operation to be substantially lower than the power consumed in conventional flash memory cards. This substantially reduced power consumption is achieved in conjunction with a substantially improved data transfer rate (about twice the data rate of a large burst).

因此，根據本發明之較佳具體實施例，其中以較低匯流排電壓(相對於習知快閃記憶體裝置)執行進階讀取資料傳送，在進階模式中消耗之電流不會比習知快閃記憶體裝置在常態操作模式中消耗之電流更槽。並且，在根據本發明之此項較佳具體實施例中，其中快閃記憶體裝置10亦具有以常態操作模式運作之能力，進階模式與常態操作模式運作兩者中使用較低之匯流排電壓，並且亦對於包括命令與位址值之傳達的其他操作使用較低之匯流排電壓。就其本身而論，快閃記憶體裝置10在傳送資料中消耗之功率低於習知快閃記憶體裝置。Therefore, in accordance with a preferred embodiment of the present invention in which advanced read data transfer is performed with a lower bus voltage (relative to conventional flash memory devices), the current consumed in the advanced mode is not It is known that the flash memory device consumes more current in the normal mode of operation. Moreover, in the preferred embodiment of the present invention, the flash memory device 10 also has the ability to operate in a normal mode of operation, and the lower bus is used in both the advanced mode and the normal mode of operation. The voltage, and also the lower bus voltage, is used for other operations including the transmission of commands and address values. For its part, the flash memory device 10 consumes less power in transmitting data than conventional flash memory devices.

如前文所述，在常態操作模式中傳達命令訊號與位址訊號。為了易於實施，較佳方式為，用於傳達彼等訊號之匯流排電壓亦維持在較低匯流排電壓(例如，1.8伏)，其提供額外減小快閃記憶體卡25之功率消耗。As described above, the command signal and the address signal are conveyed in the normal mode of operation. For ease of implementation, it is preferred that the busbar voltages used to communicate their signals are also maintained at a lower busbar voltage (e.g., 1.8 volts), which provides additional reduction in power consumption of the flash memory card 25.

請重新參考圖5a，根據本發明之此項具體實施例之快閃記憶體裝置10能夠回應來自控制器30的暫停請求。根據本發明，預期控制器30為了若干原因中任一者(例如，其內部接收資料緩衝器已滿)而認為必須暫停讀取資料傳送。就其本身而論，圖5a之決策51決定是否需要此一暫停。若否，則以上文關於圖9a之描述所述的方式，於處理程序56中繼續進行高速讀取資料傳送。Referring again to FIG. 5a, the flash memory device 10 in accordance with this embodiment of the present invention is capable of responding to a suspend request from the controller 30. In accordance with the present invention, controller 30 is expected to consider having to suspend reading data transfer for any of a number of reasons (e.g., its internal receive data buffer is full). For its part, decision 51 of Figure 5a determines whether this suspension is required. If not, the high speed read data transfer continues in processing 56 in the manner described above with respect to the description of FIG. 9a.

如果控制器30需要暫停讀取資料傳送(決策51決定"是")，則其於處理程序52中發佈暫停請求。在此項示範性實施中，控制器30於讀取傳送操作期間藉由確證位址鎖存啟用訊號ALE上之作用中高位準而提出此項請求。圖9b繪示此暫停操作，其發生於進階模式中之讀取資料傳送期間(即，已調用進階模式並且已開始資料傳送)。在圖9b之實例中，於自快閃記憶體裝置10至控制器30之資料傳送期間，控制器30藉由確證位址鎖存啟用訊號ALE而請求資料傳送暫停。作為回應，快閃記憶體裝置10暫停讀取啟用訊號RE＿與寫入啟用訊號WE＿(當在低位準或在高位準時，如圖所示)，並且因此在暫停讀取啟用訊號RE＿與寫入啟用訊號WE＿之後延遲發佈下一資料字。假定在此進階模式中讀取啟用訊號RE＿、寫入啟用訊號WE＿與輸入/輸出線I/O1至I/On之迅速切換速率，預期在位址鎖存啟用訊號ALE被驅動至作用中高狀態以請求暫停之後，快閃記憶體裝置10可驅動一個或兩個額外資料字以及讀取啟用訊號RE＿與寫入啟用訊號WE＿之相對應邊沿。在此實例中，於輸出資料字Dout (4)期間，控制器30已確證位址鎖存啟用訊號ALE，並且於輸出資料字Dout (6)期間，快閃記憶體裝置10藉由保持讀取啟用訊號RE＿、寫入啟用訊號WE＿及輸入/輸出線I/O1至I/On之進一步轉變而作出回應。If the controller 30 needs to suspend the read data transfer (decision 51 decides "Yes"), it issues a pause request in the processing program 52. In this exemplary implementation, the controller 30 makes this request during the read transfer operation by verifying that the address latches the high level on the enable signal ALE. Figure 9b illustrates this pause operation, which occurs during the read data transfer in the advanced mode (i.e., the advanced mode has been invoked and data transfer has begun). In the example of FIG. 9b, during data transfer from the flash memory device 10 to the controller 30, the controller 30 requests a data transfer pause by confirming the address latch enable signal ALE. In response, the flash memory device 10 suspends the read enable signal RE_ and the write enable signal WE_ (when at a low level or at a high level, as shown), and thus disables the read enable signal RE_ and write enable. After the signal WE_, the next data word is delayed. Assuming that the fast switching rate of the enable signal RE_, the write enable signal WE_, and the input/output lines I/O1 to I/On is read in this advanced mode, it is expected that the address latch enable signal ALE is driven to the active high state. After the request is paused, the flash memory device 10 can drive one or two additional data words and the corresponding edge of the read enable signal RE_ and the write enable signal WE_. In this example, during output of the data word D out (4), the controller 30 has confirmed the address latch enable signal ALE, and during the output of the material word D out (6), the flash memory device 10 is maintained. A response is made to read the enable signal RE_, the write enable signal WE_, and the input/output lines I/O1 to I/On.

此暫停進一步資料傳送持續，直到控制器30執行處理程序54以撤銷啟動位址鎖存啟用訊號ALE，因此結束暫停。如圖9b所示，在控制器30使位址鎖存啟用訊號ALE成為非作用中低狀態後隨即結束此暫停狀態。根據本發明之此項具體實施例，位址鎖存啟用訊號ALE之此轉變係用作為來自快閃記憶體裝置10之下一輸出資料字(在此實例中係資料字Dout (7))的讀取資料選通。在此起始暫停後之資料字之後，快閃記憶體裝置10藉由確證讀取啟用訊號RE＿與寫入啟用訊號WE＿之轉變而再次產生讀取選通訊號，如圖所示。寫入啟用訊號WE＿之下一運作轉變係用於繼暫停時期結束之後的第二輸出資料字Dout (8)的選通，並且讀取啟用訊號RE＿之下一運作轉變係用於在暫停時期之後的第三輸出資料字Dout (9)的選通。於處理程序56中繼續進行進階模式讀取資料傳送，如圖9b所示。This pause further data transfer continues until controller 30 executes processing 54 to deactivate the enable address latch enable signal ALE, thus ending the pause. As shown in FIG. 9b, the pause state is terminated immediately after the controller 30 causes the address latch enable signal ALE to become the inactive low state. According to this embodiment of the invention, the transition of the address latch enable signal ALE is used as an output data word from the underlying flash memory device 10 (in this example, the data word D out (7)) Read data strobe. After the start of the suspended data word, the flash memory device 10 reproduces the read selection communication number by confirming the transition between the read enable signal RE_ and the write enable signal WE_, as shown. Write enable signal WE_ The next operational transition is for the strobe of the second output data word D out (8) after the end of the pause period, and the read enable signal RE_ is below the operational transition for the pause period The subsequent strobe of the third output material word D out (9). The advanced mode read data transfer continues in the processing program 56, as shown in Figure 9b.

請重新參考圖5a，繼續進行進階模式讀取資料傳送直到控制器30想要終止傳送之時，其在處理程序58、59中向快閃記憶體裝置10指示出其想要終止傳送。典型地，在控制器30決定正在抵達快閃記憶體裝置10內之頁尾後隨即終止此傳送，然而控制器30亦可為了其他原因(例如，在接收到用於操作的全部所要資料之後)終止傳送。Referring again to Figure 5a, proceeding with the advanced mode read data transfer until the controller 30 wants to terminate the transfer, it indicates to the flash memory device 10 in the processing program 58, 59 that it wants to terminate the transfer. Typically, the transfer is terminated immediately after the controller 30 determines that it is reaching the end of the flash memory device 10, however the controller 30 may also be for other reasons (eg, after receiving all of the desired material for operation) Termination of the transfer.

根據此項實例，為了終止此資料傳送，控制器30首先於處理程序58中發佈暫停，例如，藉由確證位址鎖存啟用訊號ALE之作用中高位準，如上文所述。圖9c繪示終止處理程序58、59之實例，圖中繪示在進階讀取資料傳送操作期間位址鎖存啟用訊號ALE之轉變。控制器30於暫停操作期間實行處理程序59，使處理程序58之暫停操作變換至終止進階讀取資料傳送。替代做法為，可於快閃記憶體裝置10本身決定其輸出資料已抵達頁尾之後實行處理程序59，在此情況中，快閃記憶體裝置10本身使讀取啟用訊號RE＿與寫入啟用訊號WE＿維持在其最後位準，並且在輸入/輸出線I/O1至I/On上維持現行(即，最後的)輸出資料字；在此情況中，位址鎖存啟用訊號ALE仍是維持非作用中低狀態。在圖9c所示之此實例中，控制器30在位址鎖存啟用訊號ALE係處於作用中高位準時確證命令鎖存啟用訊號CLE上之作用中高位準，而終止此資料傳送。回應於此命令鎖存啟用訊號CLE之轉變，快閃記憶體裝置10控制其輸出驅動器以將輸入/輸出線I/O1至I/On置於高阻抗狀態，並且亦釋放其對相對應於讀取啟用訊號RE＿與寫入啟用訊號WE＿的導體之控制，在彼兩種情況中，准許控制器30在適當時取得對彼等線路之控制，同時避免資料競爭問題。如圖9c之實例中所示，因為暫停操作與終止操作發生於讀取啟用訊號RE＿與寫入啟用訊號WE＿處於低位準，所以一旦控制器30取得對讀取啟用訊號RE＿與寫入啟用訊號WE＿之控制，隨即驅動相對應之線路上之非作用中高位準，導致如圖所示之轉變；如果暫停操作與終止操作發生於彼等訊號中任一者或兩者已處於高位準，則當然在該線路上無任何轉變。In accordance with this example, to terminate this data transfer, the controller 30 first issues a pause in the handler 58, for example, by verifying that the address latch enables the high level of the enable signal ALE, as described above. Figure 9c illustrates an example of termination processing routines 58, 59, which illustrate the transition of the address latch enable signal ALE during an advanced read data transfer operation. Controller 30 executes processing routine 59 during the suspend operation to cause the suspend operation of handler 58 to transition to terminate the advanced read data transfer. Alternatively, the processing program 59 may be executed after the flash memory device 10 itself determines that its output data has reached the end of the page. In this case, the flash memory device 10 itself causes the read enable signal RE_ and the write enable signal. WE_ is maintained at its last level and maintains the current (ie, last) output data word on input/output lines I/O1 to I/On; in this case, the address latch enable signal ALE remains asserted. Moderate low state. In the example shown in FIG. 9c, the controller 30 terminates the data transfer when the address latch enable signal ALE is at the active high level to confirm the high level on the command latch enable signal CLE. In response to the transition of the command latch enable signal CLE, the flash memory device 10 controls its output driver to place the input/output lines I/O1 to I/On in a high impedance state, and also releases its pair corresponding to the read. The control of the enable signal RE_ and the conductor of the write enable signal WE_ is taken, and in both cases, the controller 30 is permitted to obtain control of its lines when appropriate, while avoiding data contention problems. As shown in the example of FIG. 9c, since the suspend operation and the termination operation occur when the read enable signal RE_ and the write enable signal WE_ are at a low level, once the controller 30 obtains the read enable signal RE_ and the write enable signal WE_ Control, which in turn drives the non-active high level on the corresponding line, resulting in a transition as shown; if the suspend and terminate operations occur in either or both of their signals, then of course There is no transition on this line.

接著，快閃記憶體裝置10返回常態操作模式("舊型"模式)，將控制傳回至圖5a之流程圖中的處理程序44。根據本發明之此項較佳具體實施例，新的進階模式讀取資料傳送將需要起始處理程序48之另一執行個體。Next, the flash memory device 10 returns to the normal mode of operation ("old mode" mode), and control is passed back to the process 44 in the flow chart of Figure 5a. In accordance with this preferred embodiment of the present invention, a new advanced mode read data transfer would require another execution individual of the start process 48.

進一步，在替代做法中，如果控制器30撤銷確證晶片啟用訊號CE＿，則將發生無條件終止。但是，預期此項無條件終止可導致在快閃記憶體裝置10及控制器30之內部與外部發生"差錯"及其他假性且未指定的事件。Further, in the alternative, if the controller 30 revokes the verification wafer enable signal CE_, an unconditional termination will occur. However, it is contemplated that this unconditional termination can result in "errors" and other false and unspecified events occurring inside and outside of flash memory device 10 and controller 30.

根據本發明之此項較佳具體實施例，對於自控制器30至快閃記憶體裝置10之資料傳送(換言之，對於寫入資料傳送操作)亦提供進階高效能模式。圖5b之流程圖連同圖9a與9d至9e之時序圖繪示此項操作，現在將予以描述。In accordance with this preferred embodiment of the present invention, an advanced high performance mode is also provided for data transfer from controller 30 to flash memory device 10 (in other words, for write data transfer operations). The flow chart of Figure 5b, together with the timing diagrams of Figures 9a and 9d through 9e, illustrates this operation and will now be described.

為了實現進階模式寫入資料傳送，快閃記憶體裝置10自常態操作模式開始，進入處理程序60。如同讀取資料傳送之情況，在處理程序62中首先實行此常態模式操作(若有的話)。在處理程序64中，在此常態操作模式中，控制器30發佈位址值至快閃記憶體裝置10，如上文關於圖4b之描述所述。並且於處理程序66中，控制器66以類似於上文關於圖9a描述之進階讀取資料傳送所述的實行方式起始進階資料傳送模式。預期於處理程序66中將於此進階模式中執行的寫入資料傳送實質上完全相同於讀取資料傳送，惟使用不同的命令值IDT_WR_CMD除外，該命令值指示出進階模式資料傳送係寫入操作(控制器30至快閃記憶體裝置10)，而非讀取。此不同值准許在寫入傳送內使用寫入啟用訊號WE＿與讀取啟用訊號RE＿兩者，如下文所述。In order to implement the advanced mode write data transfer, the flash memory device 10 enters the processing program 60 from the normal mode of operation. This normal mode operation (if any) is first implemented in the processing program 62 as is the case with the read data transfer. In the process 64, in this normal mode of operation, the controller 30 issues an address value to the flash memory device 10 as described above with respect to Figure 4b. And in process 66, controller 66 initiates the advanced data transfer mode in an implementation similar to that described above with respect to FIG. 9a. It is contemplated that the write data transfer performed in this advanced mode in processing 66 is substantially identical to the read data transfer except that a different command value IDT_WR_CMD is used, which indicates that the advanced mode data transfer is written. The operation (controller 30 to flash memory device 10) is performed instead of reading. This different value permits the use of both the write enable signal WE_ and the read enable signal RE_ within the write transfer, as described below.

在處理程序68中，控制器30與快閃記憶體裝置10實行進階寫入資料傳送。圖9d繪示此項操作(包括處理程序66)之實例中的訊號時序，其中由控制器30發佈命令值IDT_WR_CMD、命令鎖存啟用訊號CLE之作用中高位準與寫入啟用訊號WE＿之作用中低脈衝的組合至快閃記憶體裝置10，因此起始進階模式資料傳送。如同先前之實例，使位址鎖存啟用訊號ALE維持在非作用中低位準，以及使晶片啟用訊號CE維持在作用中低位準。並且因為此項操作將係一項資料寫入操作，所以控制器30使讀取啟用訊號RE＿(圖中9d未繪示)始終保持在非作用中高狀態。在本發明之此項具體實施例中，因為寫入資料傳送處理程序68仍是在控制器30之完全控制下，所以介於發佈命令IDT_WR_CMD與開始寫入資料傳送之間的延時可比讀取資料傳送中第一輸出資料字(圖9a)之前的延時短許多。較佳方式為，介於相對應於起始命令IDT_WR_CMD的寫入啟用訊號WE＿之脈衝之上升邊沿與相對應於第一輸入資料字Din (0)的寫入啟用訊號WE＿(或讀取啟用訊號RE)之第一脈衝之下降邊沿之間歷時一指定時間，如圖所示。In the processing program 68, the controller 30 and the flash memory device 10 perform advanced write data transfer. FIG. 9d illustrates the signal timing in the example of the operation (including the processing program 66), wherein the controller 30 issues the command value IDT_WR_CMD, the command latch enable signal CLE, and the write enable signal WE_. The combination of low pulses is coupled to the flash memory device 10, thus initiating advanced mode data transfer. As in the previous example, the address latch enable signal ALE is maintained at the inactive low level and the wafer enable signal CE is maintained at the active low level. And because this operation will be a data write operation, the controller 30 causes the read enable signal RE_ (not shown in Figure 9d) to remain in the inactive high state at all times. In this embodiment of the invention, since the write data transfer processing program 68 is still under the full control of the controller 30, the delay between the issue command IDT_WR_CMD and the start of the write data transfer can be compared to the read data. The delay before the first output data word (Fig. 9a) in the transfer is much shorter. Preferably, the rising edge of the pulse corresponding to the write enable signal WE_ corresponding to the start command IDT_WR_CMD and the write enable signal WE_ corresponding to the first input data word D in (0) (or read enable) The falling edge of the first pulse of the signal RE) lasts for a specified time as shown.

在本發明之此項較佳具體實施例中，一旦寫入資料傳送開始，寫入啟用訊號WE＿與讀取啟用訊號RE＿之下降邊沿係用作為寫入資料選通，由控制器30確證。當然，可替代地使用彼等訊號的上升邊沿。此外，如同讀取資料傳送之情況，藉由具有彼此異相位關係(為了最大化資料傳送速率，較佳係180°相位關係)的寫入啟用訊號WE＿與讀取啟用訊號RE＿來增加此寫入操作中的資料傳送速率。如圖9d示，此准許控制器30以同步於寫入啟用訊號WE＿與讀取啟用訊號RE＿兩者之每一下降邊沿的方式發佈新的有效寫入資料字Din (k)至輸入/輸出線I/O1至I/On上。結果，對於寫入啟用訊號WE＿與讀取啟用訊號RE＿之頻率相同於常態(舊型)操作模式中之頻率，此進階模式中之寫入資料傳送速率可係常態操作模式寫入操作之資料速率的約兩倍。In the preferred embodiment of the present invention, once the write data transfer begins, the falling edge of the write enable signal WE_ and the read enable signal RE_ is used as the write data strobe, which is verified by the controller 30. Of course, the rising edges of their signals can alternatively be used. In addition, as in the case of reading data transmission, the write is enabled by the write enable signal WE_ and the read enable signal RE_ having mutually different phase relationships (to maximize the data transfer rate, preferably 180° phase relationship). The data transfer rate in operation. As shown in FIG. 9d, the grant controller 30 issues a new valid write data word D in (k) to the input/output in a manner synchronized with each falling edge of both the write enable signal WE_ and the read enable signal RE_. Line I/O1 to I/On. As a result, the frequency of the write enable signal WE_ and the read enable signal RE_ is the same as the frequency in the normal (old type) operation mode, and the write data transfer rate in the advanced mode can be the data of the normal operation mode write operation. The rate is about twice.

根據本發明之此項具體實施例，請重新參考圖5b，進階模式寫入資料傳送中亦可實行暫停決策69。典型地，僅由控制器30決定對於寫入暫停之需求，其預期快閃記憶體裝置10可依此資料速率接收輸入資料而無緩衝器溢位等等。如果不需要暫停(決策69決定"否")，則於處理程序72中繼續進行資料傳送。如果控制器30要求暫停(決策69決定"是")，則於處理程序70中實現寫入資料傳送之暫停。在此實例中，控制器30視需要延長寫入啟用訊號WE＿與讀取啟用訊號RE＿而簡單地實現暫停處理程序70。可在任一狀態(寫入啟用訊號WE＿與讀取啟用訊號RE＿保持高狀態或保持低狀態)中實行此暫停；圖9d繪示於寫入資料字Din (2)之持續期間的暫停處理程序70，其中使寫入啟用訊號WE＿保持低狀態及使讀取啟用訊號RE＿保持高狀態。當然，在暫停處理程序70期間，控制器30不發佈額外寫入資料字Din (k)。控制器30僅僅驅動寫入啟用訊號WE＿或讀取啟用訊號RE＿之下降邊沿轉變連同下一有效寫入資料字Din (3)(在圖9d所示之實例中)而實現暫停時期結束，以繼續進行寫入資料傳送(處理程序72)。According to this embodiment of the invention, please refer back to FIG. 5b again, and the pause decision 69 can also be implemented in the advanced mode write data transfer. Typically, only the controller 30 determines the need for a write suspend that expects the flash memory device 10 to receive input data at this data rate without buffer overflow or the like. If no pause is required (decision 69 decides "No"), then data transfer continues in process 72. If the controller 30 requests a timeout (decision 69 decides "Yes"), then a stall of the write data transfer is implemented in the handler 70. In this example, controller 30 simply implements suspend handler 70 as needed to extend write enable signal WE_ and read enable signal RE_. This pause can be implemented in either state (the write enable signal WE_ and the read enable signal RE_ remain high or remain low); Figure 9d illustrates the pause handler during the duration of the write data word D in (2) 70, wherein the write enable signal WE_ is kept low and the read enable signal RE_ is kept high. Of course, during the suspend processing routine 70, the controller 30 does not issue an extra write material word D in (k). The controller 30 only drives the falling edge transition of the write enable signal WE_ or the read enable signal RE_ along with the next valid write data word D in (3) (in the example shown in Figure 9d) to achieve the end of the pause period, The write data transfer continues (process 72).

並且，如同讀取資料傳送之情況，資料訊號與控制訊號之電壓位準(輸入/輸出線I/O1至I/On，及用於寫入啟用訊號WE＿與讀取啟用訊號RE＿之線路)較佳係低於習知位準的電壓位準，舉例而言，具有介於高邏輯位準與低邏輯位準之間的1.8伏"擺動"。如上文詳細論述所述，在二分之一資料速率下，此較低電壓之匯流排將使此進階寫入資料傳送模式所消耗之功率維持等於或小於在常態操作模式中運作之習知快閃記憶體系統中消耗之功率。Moreover, as in the case of reading data transmission, the voltage level of the data signal and the control signal (input/output lines I/O1 to I/On, and the line for writing the enable signal WE_ and the read enable signal RE_) A better than a known voltage level, for example, has a 1.8 volt "wobble" between a high logic level and a low logic level. As discussed in detail above, at a data rate of one-half, this lower voltage bus will maintain the power consumed by this advanced write data transfer mode equal to or less than the normal operation in the normal mode of operation. The power consumed in a flash memory system.

請重新參考圖5b且結合圖9e，以完全相同於終止讀取資料傳送之方式實現終止寫入資料傳送。在處理程序74中，控制器30在處理程序74中確證位址鎖存啟用訊號ALE至作用中高位準以暫停傳送，並且接著在處理程序76中確證命令鎖存啟用訊號CLE至作用中高位準(同時使位址鎖存啟用訊號ALE維持高位準)，其接著終止寫入資料傳送。圖9e繪示終止寫入資料傳送過程中各種訊號之時序。寫入啟用訊號WE＿與讀取啟用訊號RE＿保持在高位準(如圖9e所示)，或在已鎖存最後資料字Din (5)(在此實例中)之後驅動至高位準。繼終止進階模式寫入資料傳送(藉由使位址鎖存啟用訊號ALE與命令鎖存啟用訊號CLE分別保持高位準達指定脈衝寬度而實現)之後，接著再次進入快閃記憶體裝置10與控制器30之常態操作模式。Referring back to FIG. 5b and in conjunction with FIG. 9e, the termination of the write data transfer is implemented in exactly the same manner as terminating the read data transfer. In the processing 74, the controller 30 verifies in the processing 74 the address latch enable signal ALE to the active high level to suspend the transfer, and then in the processing program 76 confirms the command latch enable signal CLE to the active high level. (At the same time, the address latch enable signal ALE is maintained at a high level), which then terminates the write data transfer. Figure 9e illustrates the timing of various signals during the termination of the write data transfer. The write enable signal WE_ and the read enable signal RE_ remain at a high level (as shown in Figure 9e) or drive to a high level after the last data word D in (5) has been latched (in this example). Following the termination of the advanced mode write data transfer (by enabling the address latch enable signal ALE and the command latch enable signal CLE to remain high for a specified pulse width, respectively), then entering the flash memory device 10 again The normal mode of operation of controller 30.

在此實例中，考慮到需要執行命令以調用進階模式，並且考慮到在資料傳送終止時快閃記憶體裝置10之運作返回常態操作模式(即，不需要執行命令)，常態操作模式實際上係"預設"操作模式。替代做法為，可組態快閃記憶體裝置10，使得需要執行命令才能進入進階資料傳送模式與常態操作模式兩者，致使一旦快閃記憶體裝置10係處於進階資料傳送模式中，則其仍是處於該模式中，直到控制器30發佈返回常態操作模式之命令且快閃記憶體裝置10執行該命令為止。當然，此種做法涉及命令序列本質上的額外耗用。In this example, the normal mode of operation is actually considered in view of the need to execute a command to invoke the advanced mode, and considering that the operation of the flash memory device 10 returns to the normal mode of operation when the data transfer is terminated (ie, no command is required to be executed). The "preset" operating mode. Alternatively, the flash memory device 10 can be configured such that a command needs to be executed to enter both the advanced data transfer mode and the normal mode of operation, such that once the flash memory device 10 is in the advanced data transfer mode, It is still in this mode until the controller 30 issues a command to return to the normal mode of operation and the flash memory device 10 executes the command. Of course, this approach involves the extra cost of the command sequence.

進一步，在替代做法中，快閃記憶體裝置10之"預設"操作模式可係進階資料傳送模式，致使在進階模式中實現所有資料傳送，直到控制器30發佈命令以使快閃記憶體裝置10進入常態操作模式為止。在此情況中，預期控制器30可指示出是否係讀取或寫入進階模式操作，以准許讀取啟用訊號與寫入啟用訊號兩者選通資料，如上文所述。根據本發明之此項替代具體實施例，一旦快閃記憶體裝置10係處於常態操作模式，則完成資料傳送將導致快閃記憶體裝置10返回進階資料傳送模式。Further, in an alternative, the "preset" mode of operation of the flash memory device 10 can be an advanced data transfer mode, such that all data transfers are implemented in the advanced mode until the controller 30 issues a command to flash the memory. The body device 10 enters the normal mode of operation. In this case, controller 30 is expected to indicate whether to read or write an advanced mode operation to permit both the read enable signal and the write enable signal to be gated, as described above. In accordance with this alternative embodiment of the present invention, once the flash memory device 10 is in the normal mode of operation, completing the data transfer will cause the flash memory device 10 to return to the advanced data transfer mode.

已參閱此份說明書的熟悉此項技術者應明白，預期尚有進入與退出快閃記憶體裝置10之各種操作模式的替代做法，並且亦應明白，彼等及此類其他替代實施方案皆歸屬於如申請專利範圍之本發明範疇內。Those skilled in the art having access to this specification will appreciate that alternative approaches to entering and exiting the flash memory device 10 are contemplated, and it should be understood that they and such other alternative embodiments are It is within the scope of the invention as set forth in the patent application.

因此，根據本發明之較佳具體實施例之快閃記憶體裝置10、控制器30及快閃記憶體卡25提供優於習知裝置及系統的重要優點。本發明實現高資料傳送速率(接近習知裝置及系統的兩倍)，同時仍然提供與不具有進階能力之"舊型"裝置的命令與訊號相容性。此外，進階資料傳送模式中所涉及的較低匯流排電壓訊號使整體裝置與系統電流與功率消耗維持在接近(或甚至低於)習知快閃記憶體裝置與系統的電流與功率消耗。Thus, flash memory device 10, controller 30 and flash memory card 25 in accordance with a preferred embodiment of the present invention provide significant advantages over conventional devices and systems. The present invention achieves a high data transfer rate (close to twice that of conventional devices and systems) while still providing command and signal compatibility with "old" devices that do not have advanced capabilities. In addition, the lower bus voltage signals involved in the advanced data transfer mode maintain overall device and system current and power consumption close to (or even below) the current and power consumption of conventional flash memory devices and systems.

結果，預期本發明可特別有利於資料傳送速率尤其關鍵的數位系統應用中。如上文所述，一項此種應用係在高效能數位靜物攝影機。在此種攝影機中，影像解析度(且因此每影像攝取之資料)現在超過10百萬像素，現在市售有高於12.4百萬像素攝影機。但是，由於自影像感測器至快閃記憶體的資料傳送速率係可攝取影像之速率(攝影機使用者通常感受到的"快門遲滯")的直接因素，所以此資料傳送速率係屬關鍵。並且，攝影機使用者首要關切感受到的絕對延遲(即，與每一影像中獲取的資料量無關)，所以隨著影像解析度增加，使對資料傳送速率的負荷更加惡化。此高資料傳送速率的另一潛在應用在於使用固態快閃記憶體作為電腦系統中的大量儲存媒體，其實質上取代習用的一些或所有磁碟機大量儲存器。預期使用固態記憶體(而不使用磁碟機)的能力實現電腦系統之進一步微型化及攜帶性，並且亦大幅增加現代攜帶型與手持型系統的功能。As a result, it is contemplated that the present invention may be particularly advantageous in digital system applications where data transfer rates are particularly critical. As mentioned above, one such application is in a high performance digital still camera. In this type of camera, the image resolution (and therefore the data per image capture) is now over 10 megapixels, and now there are commercially available cameras with higher than 12.4 megapixels. However, since the data transfer rate from the image sensor to the flash memory is a direct factor in the rate at which images can be captured (the "shutter lag" that camera users typically experience), this data transfer rate is critical. Moreover, the camera user is primarily concerned with the perceived absolute delay (ie, independent of the amount of data acquired in each image), so as the resolution of the image increases, the load on the data transfer rate is further aggravated. Another potential application for this high data transfer rate is the use of solid state flash memory as a mass storage medium in a computer system that substantially replaces some or all of the disk drive's mass storage. The ability to use solid-state memory (without a disk drive) is expected to further miniaturize and portability of computer systems, and also greatly increase the functionality of modern portable and handheld systems.

雖然已根據本發明之較佳具體實施例來說明本發明，但是當然預期已參閱此份說明書的熟悉此項技術者應明白彼等具體實施例之修改與替代方案，此等修改與替代方案獲得本發明之優點與利益。預期此等修改與替代方案均屬於如本文隨後申請專利範圍中的本發明範疇。Although the present invention has been described in terms of the preferred embodiments of the present invention, it will be understood that modifications and alternatives to the specific embodiments thereof Advantages and benefits of the present invention. It is intended that such modifications and alternatives fall within the scope of the invention as set forth in the appended claims.

2．．．快閃記憶體卡2. . . Flash memory card

4．．．快閃記憶體裝置(模組)4. . . Flash memory device (module)

6．．．記憶體控制器6. . . Memory controller

10．．．快閃記憶體裝置(模組)10. . . Flash memory device (module)

11．．．列解碼器11. . . Column decoder

12．．．快閃記憶體陣列12. . . Flash memory array

13．．．感測放大器13. . . Sense amplifier

14．．．資料暫存器14. . . Data register

15．．．行解碼器15. . . Row decoder

18．．．控制邏輯18. . . Control logic

20．．．輸入/輸出控制電路20. . . Input/output control circuit

22．．．位址暫存器twenty two. . . Address register

23．．．狀態暫存器twenty three. . . Status register

24．．．命令暫存器(狀態暫存器)twenty four. . . Command register (status register)

25．．．快閃記憶體卡25. . . Flash memory card

30．．．控制器30. . . Controller

ADD0至ADD3．．．位址字ADD0 to ADD3. . . Address word

ALE．．．位址鎖存啟用(訊號)ALE. . . Address latch enable (signal)

CE_．．．晶片啟用(訊號)CE_. . . Wafer enable (signal)

CLE．．．命令鎖存啟用(訊號)CLE. . . Command latch enable (signal)

CMD．．．命令CMD. . . command

CTRL．．．控制匯流排CTRL. . . Control bus

DATA_BUS．．．匯流排DATA_BUS. . . Busbar

Din ．．．資料字D in . . . Data word

Dout ．．．資料字D out . . . Data word

HOST_IF．．．主機介面(外部介面)HOST_IF. . . Host interface (external interface)

Ik ．．．單個輸入/輸出線所消耗的電流I k . . . Current consumed by a single input/output line

IRE ．．．讀取啟用訊號RE_所消耗的電流I RE . . . Read the current consumed by the enable signal RE_

Itotal ．．．消耗的總電流I total . . . Total current consumed

I/O1至I/On．．．共同輸入/輸出(訊號線)I/O1 to I/On. . . Common input/output (signal line)

IDT．．．起始資料傳送IDT. . . Initial data transfer

IDT_CMD,IDT_RD_CMD,IDT_WR_CMD．．．IDT命令值IDT_CMD, IDT_RD_CMD, IDT_WR_CMD. . . IDT command value

RE_．．．讀取啟用(終端，控制線，訊號)RE_. . . Read enable (terminal, control line, signal)

Vcc－R ．．．電源供應電壓V cc-R . . . Power supply voltage

VOH ．．．最小高(邏輯)位準輸出電壓V OH . . . Minimum high (logic) level output voltage

VOH－R ．．．最小輸出高位準電壓V OH-R . . . Minimum output high level voltage

VOL ．．．最大低(邏輯)位準輸出電壓V OL . . . Maximum low (logic) level output voltage

VOL－R ．．．最大低輸出位準電壓V OL-R . . . Maximum low output level voltage

WE_．．．寫入啟用(終端，控制線，訊號)WE_. . . Write enable (terminal, control line, signal)

WP_．．．寫入保護線WP_. . . Write protection line

data_I/O．匯流排data_I/O. Busbar

ctrl．．．匯流排Ctrl. . . Busbar

trel ．．．歷時時間t rel . . . Diachronic time

圖1繪示習知記憶體上的電方塊圖。Figure 1 shows an electrical block diagram on a conventional memory.

圖2繪示一種根據本發明較佳具體實施例建構之記憶體模組的電方塊圖。2 is an electrical block diagram of a memory module constructed in accordance with a preferred embodiment of the present invention.

圖3繪示根據本發明較佳具體實施例將圖2之記憶體模組結合單晶片記憶體控制器實作成為一系統或子系統的電方塊圖。3 is an electrical block diagram of a memory module of FIG. 2 in combination with a single-chip memory controller as a system or subsystem in accordance with a preferred embodiment of the present invention.

圖4a至圖4d繪示根據本發明較佳具體實施例圖2與圖3之快閃記憶體模組在常態操作模式中且在傳達命令中之操作的時序圖。4a-4d are timing diagrams showing the operation of the flash memory module of FIGS. 2 and 3 in a normal mode of operation and in communicating commands in accordance with a preferred embodiment of the present invention.

圖5a與圖5b分別繪示根據本發明較佳具體實施例之進階模式讀取資料傳送速率與寫入資料傳送之操作的流程圖。5a and 5b are respectively a flow chart showing an operation of reading data transfer rate and writing data transfer in an advanced mode according to a preferred embodiment of the present invention.

圖6a至圖6e繪示根據本發明第一較佳具體實施例之圖5a與圖5b之操作所涉及之訊號的時序圖。6a-6e are timing diagrams of signals involved in the operation of Figs. 5a and 5b in accordance with a first preferred embodiment of the present invention.

圖7繪示根據本發明第二較佳具體實施例之進階模式資料傳送之操作的流程圖。7 is a flow chart showing the operation of advanced mode data transfer in accordance with a second preferred embodiment of the present invention.

圖8a至圖8e繪示根據本發明第二較佳具體實施例之圖5a與圖5b之操作所涉及之訊號的時序圖。8a-8e are timing diagrams of signals involved in the operation of Figs. 5a and 5b in accordance with a second preferred embodiment of the present invention.

圖9a至圖9e繪示根據本發明第三較佳具體實施例之圖5a與圖5b之操作所涉及之訊號的時序圖。9a-9e are timing diagrams of signals involved in the operation of Figs. 5a and 5b in accordance with a third preferred embodiment of the present invention.

10．．．快閃記憶體裝置(模組)10. . . Flash memory device (module)

11．．．列解碼器11. . . Column decoder

12．．．快閃記憶體陣列12. . . Flash memory array

13．．．感測放大器13. . . Sense amplifier

14．．．資料暫存器14. . . Data register

15．．．行解碼器15. . . Row decoder

18．．．控制邏輯18. . . Control logic

20．．．輸入/輸出控制電路20. . . Input/output control circuit

22．．．位址暫存器twenty two. . . Address register

23．．．狀態暫存器twenty three. . . Status register

24．．．命令暫存器(狀態暫存器)twenty four. . . Command register (status register)

ALE．．．位址鎖存啟用(訊號)ALE. . . Address latch enable (signal)

CE．．．晶片啟用(訊號)CE. . . Wafer enable (signal)

CLE．．．命令鎖存啟用(訊號)CLE. . . Command latch enable (signal)

DATA_BUS．．．匯流排DATA_BUS. . . Busbar

I/O1至I/On．．．共同輸入/輸出(訊號線)I/O1 to I/On. . . Common input/output (signal line)

RE_．．．讀取啟用(終端，控制線，訊號)RE_. . . Read enable (terminal, control line, signal)

Vcc－R ．．．電源供應電壓V cc-R . . . Power supply voltage

WE_．．．寫入啟用(終端，控制線，訊號)WE_. . . Write enable (terminal, control line, signal)

WP_．．．寫入保護線WP_. . . Write protection line

Claims (23)

一種快閃記憶體裝置，其包括：至少一記憶體陣列，其係由以列與行排列的非揮發性記憶體單元所組成；一資料暫存器，用於儲存相對應於該至少一記憶體陣列中之該等記憶體單元之經儲存狀態的資料；控制電路，其耦接至該資料暫存器、耦接至多個輸入/輸出終端且耦接至複數個控制終端，用於回應於在該等控制終端處接收到之控制訊號，在一常態操作模式中與一進階資料傳送模式中，接收來自該等輸入/輸出終端之資料及提供資料至該等輸入/輸出終端，並控制該快閃記憶體裝置之操作；其中，在該常態操作模式中，該控制電路回應於在該複數個控制終端中之一第一者處接收的一讀取資料選通訊號之一第一極性之轉變，在該等輸入/輸出終端處提供資料字，該常態操作模式對應於用於介於快閃記憶體裝置與控制器之間的通信之一標準化規格，該標準化規格包括一第一指定電壓規格，該第一指定電壓規格定義用於該讀取資料選通訊號及在該等輸入/輸出終端處之該等資料字的高與低邏輯位準；其中，該進階資料傳送模式對應於一第二指定電壓規格，該第二指定電壓規格定義用於該讀取資料選通訊號及在該等輸入/輸出終端處之該等資料字的高與低邏輯位準，該第二指定電壓規格中之該等高與低邏輯位準定義 一電壓擺動小於藉由該第一指定電壓規格中之該等高與低邏輯位準所定義的電壓擺動；及其中，在該進階資料傳送模式中，該控制電路回應於該讀取資料選通訊號之該第一極性與一第二極性兩者之轉變，在該複數個控制終端中之該第一者處提供讀取資料選通訊號，並且在該等輸入/輸出終端處提供資料字。 A flash memory device comprising: at least one memory array composed of non-volatile memory cells arranged in columns and rows; a data register for storing corresponding to the at least one memory The storage state of the memory cells in the body array; the control circuit is coupled to the data register, coupled to the plurality of input/output terminals, and coupled to the plurality of control terminals for responding to Control signals received at the control terminals, in a normal operation mode and an advanced data transmission mode, receiving data from the input/output terminals and providing data to the input/output terminals, and controlling The operation of the flash memory device; wherein, in the normal mode of operation, the control circuit is responsive to a first polarity of a read data selection communication number received at a first one of the plurality of control terminals a conversion, providing a data word at the input/output terminals, the normal mode of operation corresponding to a standardized specification for communication between the flash memory device and the controller, the standard The specification includes a first specified voltage specification, the first specified voltage specification defining a high and low logic level for the read data selection communication number and the data words at the input/output terminals; The advanced data transfer mode corresponds to a second specified voltage specification defining high and low logic for the read data selection communication number and the data words at the input/output terminals Level, the definition of the high and low logic levels in the second specified voltage specification a voltage swing less than a voltage swing defined by the high and low logic levels in the first specified voltage specification; and wherein, in the advanced data transfer mode, the control circuit is responsive to the read data selection a transition of the first polarity and a second polarity of the communication number, providing a read data selection communication number at the first one of the plurality of control terminals, and providing a data word at the input/output terminals . 如請求項1之裝置，其進一步包括：一命令暫存器，其耦接至該控制電路；其中該控制電路回應於在該複數個控制終端中之一第二者處接收的一寫入資料選通訊號之一轉變，將在該等輸入/輸出終端處接收的一命令值儲存至該命令暫存器中；並且其中該控制電路回應於相對應於起始該進階資料傳送模式之該命令值，自該常態操作模式進入該進階資料傳送模式。 The device of claim 1, further comprising: a command register coupled to the control circuit; wherein the control circuit is responsive to a write data received at a second one of the plurality of control terminals Selecting one of the communication numbers to store a command value received at the input/output terminals into the command register; and wherein the control circuit is responsive to the corresponding start of the advanced data transfer mode The command value enters the advanced data transfer mode from the normal operation mode. 如請求項1之裝置，其進一步包括：一命令暫存器，其耦接至該控制電路；其中該控制電路回應於在該複數個控制終端中之一第二者處接收一寫入資料選通訊號之一轉變，將在該等輸入/輸出終端處接收的一命令值儲存至該命令暫存器中；並且其中該控制電路回應於相對應於起始該常態操作模式之該命令值，自該進階資料傳送模式進入該常態操作模式。 The device of claim 1, further comprising: a command register coupled to the control circuit; wherein the control circuit receives a write data selection in response to a second one of the plurality of control terminals Transmitting one of the communication numbers to store a command value received at the input/output terminals into the command register; and wherein the control circuit is responsive to the command value corresponding to initiating the normal mode of operation, The normal mode of operation is entered from the advanced data transfer mode. 如請求項3之裝置，其中藉由該第一指定電壓規格中之 該等高與低邏輯位準定義的該電壓擺動標稱上係約3.3伏；並且其中藉由該第二指定電壓規格中之該等高與低邏輯位準定義的該電壓擺動標稱上係約1.8伏。 The device of claim 3, wherein the first specified voltage specification is The voltage swing defined by the contour and low logic levels is nominally about 3.3 volts; and wherein the voltage swing is nominally defined by the high and low logic levels in the second specified voltage specification About 1.8 volts. 如請求項1之裝置，其中，在該進階資料傳送模式中，該控制電路回應於在該複數個控制終端中之一第二者處接收的一寫入資料選通訊號之一第一極性與一第二極性兩者之轉變，將在該等輸入/輸出終端處接收之資料字鎖存於該資料暫存器中；並且其中，在該常態操作模式中，該控制電路回應於在該複數個控制終端中之該第二者處接收的該寫入資料選通訊號之該第一極性之轉變，將在該等輸入/輸出終端處接收之資料字鎖存於該資料暫存器中。 The device of claim 1, wherein in the advanced data transfer mode, the control circuit is responsive to one of the write data selection communication numbers received at a second one of the plurality of control terminals And a transition of a second polarity, the data words received at the input/output terminals are latched in the data register; and wherein, in the normal mode of operation, the control circuit is responsive to the a transition of the first polarity of the write data selection communication number received by the second one of the plurality of control terminals, wherein the data words received at the input/output terminals are latched in the data register . 如請求項1之裝置，其進一步包括：一命令暫存器，其耦接至該控制電路；其中該控制電路回應於在該複數個控制終端中之一第二者處接收一寫入資料選通訊號之一轉變，結合在該複數個控制終端中之一第三者處接收的一命令鎖存啟用訊號，將在該等輸入/輸出終端處接收的一命令值儲存至該命令暫存器中；其中該控制電路回應於相對應於起始該進階資料傳送模式之該命令值，自該常態操作模式進入該進階資料傳送模式；其中在該進階資料傳送模式中，該控制電路回應於在 該複數個控制終端中之一者處接收一暫停請求訊號，在該等輸入/輸出終端處保持一資料字之一現行值及在該複數個控制終端中之該第一者處保持一讀取啟用訊號之一現行狀態；其中該控制電路回應於接收到來自該控制器之暫停請求之一結束，重新繼續在該進階資料傳送模式中提供資料字至該控制器以及驅動該讀取資料選通訊號；其中該控制電路結合來自該控制器之該寫入資料選通訊號之一第一極性之一轉變，並且結合接收來自該控制器之一位址鎖存啟用訊號，在該等輸入/輸出終端上接收來自該控制器之記憶體位址；並且其中在該進階資料傳送模式中提供資料字至該控制器期間，該暫停請求對應於該位址鎖存啟用訊號之一轉變。 The device of claim 1, further comprising: a command register coupled to the control circuit; wherein the control circuit receives a write data selection in response to a second one of the plurality of control terminals Transmitting one of the communication numbers, in combination with a command latch enable signal received at one of the plurality of control terminals, storing a command value received at the input/output terminals to the command register The control circuit enters the advanced data transfer mode from the normal operation mode in response to the command value corresponding to the start of the advanced data transfer mode; wherein the control circuit is in the advanced data transfer mode Responding to Receiving a pause request signal at one of the plurality of control terminals, maintaining an active value of a data word at the input/output terminals, and maintaining a read at the first one of the plurality of control terminals Enabling an active state of one of the signals; wherein the control circuit is responsive to receiving the end of one of the suspend requests from the controller, re-continuing to provide the data word to the controller in the advanced data transfer mode, and driving the read data selection a communication number; wherein the control circuit converts one of the first polarities of the one of the write data selection communication numbers from the controller, and in combination with receiving an address from the controller, the latch enable signal is at the input/ Receiving, by the output terminal, a memory address from the controller; and wherein during the providing of the data word to the controller in the advanced data transfer mode, the pause request corresponds to one of the address latch enable signals. 如請求項1之裝置，其中該快閃記憶體裝置係實施於一快閃記憶體子系統中，該快閃記憶體子系統進一步包括：一快閃記憶體控制器，其具有用於介接一主機系統之一主機介面；一資料匯流排，其耦接至該快閃記憶體控制器；及複數個控制線，其耦接至該快閃記憶體控制器；其中該快閃記憶體裝置之該控制電路被耦接至該資料匯流排及該複數個控制線，並且該控制電路係用於回應於接收自該等控制線的控制訊號，在該常態操作模式中與 該進階資料傳送模式中，接收來自該資料匯流排之資料及提供資料至該資料匯流排、以及控制該快閃記憶體裝置之操作。 The device of claim 1, wherein the flash memory device is implemented in a flash memory subsystem, the flash memory subsystem further comprising: a flash memory controller having a interface for interfacing a host interface of a host system; a data bus, coupled to the flash memory controller; and a plurality of control lines coupled to the flash memory controller; wherein the flash memory device The control circuit is coupled to the data bus and the plurality of control lines, and the control circuit is configured to respond to the control signals received from the control lines, in the normal operation mode In the advanced data transfer mode, receiving data from the data bus and providing data to the data bus, and controlling the operation of the flash memory device. 如請求項1至7中任一項之裝置，其中在該常態操作模式中，該讀取資料選通訊號具有一最大可用頻率；且其中在該進階資料傳送模式中該讀取資料選通訊號之頻率高於在該常態操作模式中該讀取資料選通訊號之該最大可用頻率。 The apparatus of any one of claims 1 to 7, wherein in the normal mode of operation, the read data selection communication number has a maximum available frequency; and wherein the read data selection communication is in the advanced data transmission mode The frequency of the number is higher than the maximum available frequency of the read data selection communication number in the normal operation mode. 如請求項1至7中任一項之裝置，其中在該進階資料傳送模式中，該控制電路回應於在該複數個控制終端中之一第二者處接收的一寫入資料選通訊號之一所選極性之轉變，將在該等輸入/輸出終端處接收之資料字鎖存於該資料暫存器中；其中在該常態操作模式中，該寫入資料選通訊號具有一最大可用頻率；其中在該進階資料傳送模式中該寫入資料選通訊號之頻率高於在該常態操作模式中該寫入資料選通訊號之該最大可用頻率；且其中，在該常態操作模式中，該控制電路回應於在該複數個控制終端中之該第二者處接收的該寫入資料選通訊號之一第一極性之轉變，將在該等輸入/輸出終端處接收之資料字鎖存於該資料暫存器中。 The apparatus of any one of claims 1 to 7, wherein in the advanced data transfer mode, the control circuit is responsive to a write data selection communication number received at a second one of the plurality of control terminals a change in the selected polarity, the data word received at the input/output terminals is latched in the data register; wherein in the normal mode of operation, the write data selection communication number has a maximum available Frequency; wherein the frequency of writing the data selection communication number in the advanced data transmission mode is higher than the maximum available frequency of the write data selection communication number in the normal operation mode; and wherein, in the normal operation mode And the control circuit responds to the change of the first polarity of one of the write data selection communication numbers received at the second one of the plurality of control terminals, and the data word lock received at the input/output terminals Stored in the data register. 如請求項9之裝置，其中該等寫入資料選通訊號相對於該等讀取資料選通訊號係異相位，且其中在該等輸入/輸 出終端處提供資料字，其回應於該讀取資料選通訊號及該寫入資料選通訊號之每一者之一所選轉變。 The device of claim 9, wherein the write data selection communication numbers are out of phase with respect to the read data selection communication numbers, and wherein the input/output is in the input/output A data word is provided at the terminal, and the selected change is selected in response to one of the read data selection communication number and the written data selection communication number. 一種操作一快閃記憶體裝置以與一快閃記憶體控制器通信之方法，其包括下列步驟：在一常態操作模式中，回應於接收來自該控制器的一讀取資料選通訊號之一第一極性之轉變，在多個輸入/輸出終端上提供資料字至該控制器；執行一接收來自該控制器的命令，以起始一進階資料傳送模式；接著驅動該讀取資料選通訊號至該控制器；及同步於該讀取資料選通訊號之一第一與一第二極性兩者之轉變，及在該進階資料傳送模式中，對應於該快閃記憶體裝置中所儲存之資料，以在多個輸入/輸出終端上提供資料字至該控制器；其中該常態操作模式對應於用於介於快閃記憶體裝置與控制器之間的通信之一標準化規格，該等標準化規格包括一第一指定電壓規格，該第一指定電壓規格定義用於該讀取資料選通訊號及在該等輸入/輸出終端上之該等資料字的高與低邏輯位準；並且其中該常態操作模式之該提供步驟及該進階資料傳送模式之該驅動步驟與該提供步驟係使用一第二指定電壓規格予以實行，該第二指定電壓規格定義用於該讀取資料選通訊號及在該等輸入/輸出終端上之該等資料字的高與低邏輯位準，該第二指定電壓規格中之該等高與低邏輯位準定義一電壓擺動小於藉由該第一指定電壓規 格中之該等高與低邏輯位準所定義的電壓擺動。 A method of operating a flash memory device to communicate with a flash memory controller, the method comprising the steps of: in a normal mode of operation, responding to receiving a read data selection message from the controller a first polarity transition, providing a data word to the controller on a plurality of input/output terminals; performing a command from the controller to initiate an advanced data transfer mode; and subsequently driving the read data selection communication a signal to the controller; and a transition between the first and a second polarity of one of the read data selection communication numbers, and corresponding to the flash memory device in the advanced data transfer mode Storing data to provide a data word to the controller on a plurality of input/output terminals; wherein the normal mode of operation corresponds to a standardized specification for communication between the flash memory device and the controller, The standardized specification includes a first specified voltage specification defining a high and low logic for the read data selection communication number and the data words on the input/output terminals. And wherein the providing step of the normal mode of operation and the step of providing the advanced data transfer mode are performed using a second specified voltage specification for the read Taking the data selection communication number and the high and low logic levels of the data words on the input/output terminals, wherein the high and low logic levels in the second specified voltage specification define a voltage swing less than The first specified voltage gauge The voltage swing defined by the contour and the low logic level in the cell. 如請求項11之方法，其中藉由該第一指定電壓規格中之該等高與低邏輯位準定義的該電壓擺動標稱上係約3.3伏；並且其中藉由該第二指定電壓規格中之該等高與低邏輯位準定義的該電壓擺動標稱上係約1.8伏。 The method of claim 11, wherein the voltage swing defined by the high and low logic levels in the first specified voltage specification is nominally about 3.3 volts; and wherein the second specified voltage specification is The voltage swing defined by the contour and the low logic level is nominally about 1.8 volts. 如請求項11之方法，其進一步包括：在該執行步驟之後，接收來自該控制器的寫入資料選通訊號；及回應於接收該寫入資料選通訊號之一第一與一第二極性兩者之轉變，鎖存在該等輸入/輸出終端上之資料字以用於儲存於該快閃記憶體裝置中。 The method of claim 11, further comprising: after the performing step, receiving a write data selection communication number from the controller; and responding to receiving the write data selection communication number one of the first and a second polarity The transition between the two, the data words latched on the input/output terminals for storage in the flash memory device. 如請求項13之方法，其進一步包含：在該常態操作模式中，回應於接收來自該控制器的該寫入資料選通訊號之一第一極性之轉變，鎖存在該等輸入/輸出終端上之資料字以用於儲存於該快閃記憶體裝置中。 The method of claim 13, further comprising: in the normal mode of operation, latching on the input/output terminals in response to receiving a change in a first polarity of the write data selection communication number from the controller The data word is for storage in the flash memory device. 如請求項11之方法，其中實行該執行步驟係回應於在該等輸入/輸出終端上接收到一起始命令值，其係結合來自該控制器之一寫入資料選通訊號之一第一極性之一轉變，並且結合接收來自該控制器之一命令鎖存啟用訊號。 The method of claim 11, wherein the executing the step is in response to receiving a start command value on the input/output terminals in combination with a first polarity from one of the controllers for writing a data selection number One of the transitions, combined with receiving a command from one of the controllers, latches the enable signal. 如請求項15之方法，其進一步包含：在該進階資料傳送模式中提供資料字至該控制器之該 步驟期間，並且回應於接收到來自該控制器之一暫停請求，保持該等輸入/輸出終端上之一資料字之一值，並且保持一讀取啟用訊號之一現行狀態。 The method of claim 15, further comprising: providing the information word to the controller in the advanced data transfer mode During the step, and in response to receiving a pause request from the controller, one of the data words on one of the input/output terminals is maintained, and one of the read enable signals is maintained in an active state. 如請求項16之方法，其進一步包含：回應於接收到來自該控制器之該暫停請求之一結束，重新繼續在該進階資料傳送模式中提供資料字至該控制器之該步驟及驅動該讀取資料選通訊號之該步驟。 The method of claim 16, further comprising: in response to receiving the end of the pause request from the controller, resuming the step of providing the data word to the controller in the advanced data transfer mode and driving the step This step of reading the data selection communication number. 如請求項16之方法，其中該暫停請求對應於接收到來自該控制器之一控制訊號之一轉變。 The method of claim 16, wherein the suspend request corresponds to receiving a transition from one of the control signals of the controller. 如請求項18之方法，其進一步包含：在該進階資料傳送模式中提供資料字至該控制器之該步驟及驅動該讀取資料選通訊號之該步驟之前，結合來自該控制器之該寫入資料選通訊號之該第一極性之一轉變，並且結合接收來自該控制器之一位址鎖存啟用訊號，在該等輸入/輸出終端上接收來自該控制器之一記憶體位址；且其中該暫停請求對應於在該進階資料傳送模式中提供資料字至該控制器之該步驟期間該位址鎖存啟用訊號之一轉變。 The method of claim 18, further comprising: combining the step from the step of providing the data word to the controller in the advanced data transfer mode and the step of driving the read data selection communication number Writing one of the first polarity of the data selection communication number, and receiving an address enable signal from an address of the controller, receiving a memory address from the controller on the input/output terminal; And wherein the pause request corresponds to one of the address latch enable signals transitions during the step of providing the data word to the controller in the advanced data transfer mode. 如請求項19之方法，其中該暫停請求之該結束對應於該位址鎖存啟用訊號之一第二轉變。 The method of claim 19, wherein the ending of the pause request corresponds to a second transition of one of the address latch enable signals. 一種操作一快閃記憶體裝置以與一快閃記憶體控制器通信之方法，其包括下列步驟：在一進階資料傳送操作模式中： 驅動一讀取資料選通訊號至該控制器，並且同步於該讀取資料選通訊號之一第一與一第二極性兩者之轉變；及相對應於該快閃記憶體裝置中儲存之資料，在多個輸入/輸出終端上提供資料字至該控制器；執行一接收來自該控制器的命令，以起始一常態操作模式；及接著回應於接收來自該控制器的該讀取資料選通訊號之一第一極性之轉變，在多個輸入/輸出終端上提供資料字至該控制器；其中該常態操作模式對應於用於介於多個快閃記憶體裝置與多個控制器之間的通信之一標準化規格，該等標準化規格包括一第一指定電壓規格，該第一指定電壓規格定義用於該讀取資料選通訊號及在該等輸入/輸出終端上之該等資料字的高與低邏輯位準；並且其中該進階資料傳送模式之該驅動步驟與該提供步驟係使用一第二指定電壓規格予以實行，該第二指定電壓規格定義該讀取資料選通訊號及在該等輸入/輸出終端上之該等資料字的高與低邏輯位準，該第二指定電壓規格中之該等高與低邏輯位準定義一電壓擺動小於藉由該第一指定電壓規格中之該等高與低邏輯位準所定義的電壓擺動。 A method of operating a flash memory device to communicate with a flash memory controller, the method comprising the steps of: in an advanced data transfer mode of operation: Driving a read data selection communication number to the controller, and synchronizing with the transition of the first and second polarity of one of the read data selection communication numbers; and corresponding to the storage in the flash memory device Data, providing a data word to the controller on a plurality of input/output terminals; performing a command from the controller to initiate a normal mode of operation; and then responding to receiving the read data from the controller Selecting a first polarity transition of one of the communication numbers to provide a data word to the controller on the plurality of input/output terminals; wherein the normal mode of operation corresponds to being used between the plurality of flash memory devices and the plurality of controllers One of the communication between the standardized specifications, the standardized specifications including a first specified voltage specification defining the read data selection communication number and the data on the input/output terminals The high and low logic levels of the word; and wherein the driving step and the providing step of the advanced data transfer mode are performed using a second specified voltage specification, the second specified voltage specification The read data selects a communication number and high and low logic levels of the data words on the input/output terminals, and the high and low logic levels in the second specified voltage specification define a voltage swing less than A voltage swing defined by the high and low logic levels in the first specified voltage specification. 如請求項21之方法，其進一步包含：在該進階資料傳送模式中，接收來自該控制器的多個寫入資料選通訊號；及 回應於接收該寫入資料選通訊號之一第一與一第二極性兩者之轉變，鎖存在該等輸入/輸出終端上之資料字以用於儲存於該快閃記憶體裝置中。 The method of claim 21, further comprising: receiving, in the advanced data transfer mode, a plurality of write data selection communication numbers from the controller; In response to receiving a transition of both the first and a second polarity of the write data selection communication number, the data words latched on the input/output terminals are stored for storage in the flash memory device. 如請求項22之方法，其進一步包含：在該常態操作模式中，回應於接收來自該控制器的該寫入資料選通訊號之一第一極性之轉變，鎖存在該等輸入/輸出終端上之資料字以用於儲存於該快閃記憶體裝置中。The method of claim 22, further comprising: in the normal mode of operation, latching on the input/output terminal in response to receiving a change in a first polarity of the write data selection communication number from the controller The data word is for storage in the flash memory device.
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