TWI485788B - Near-field communication components of the substrate tilt flip-chip process - Google Patents

Near-field communication components of the substrate tilt flip-chip process Download PDF

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Publication number
TWI485788B
TWI485788B TW101101430A TW101101430A TWI485788B TW I485788 B TWI485788 B TW I485788B TW 101101430 A TW101101430 A TW 101101430A TW 101101430 A TW101101430 A TW 101101430A TW I485788 B TWI485788 B TW I485788B
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substrate
field communication
chip process
flip chip
near field
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TW101101430A
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Chinese (zh)
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TW201330119A (en
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Chi Ming Chan
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Chi Ming Chan
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近場通訊元件之基板傾斜覆晶製程Sub-field communication component substrate tilting flip chip process

本發明為提供一種覆晶製程,尤指一種有效保護資料安全的近場通訊元件之基板傾斜覆晶製程。The invention provides a flip chip process, in particular to a substrate tilt flip chip process for a near field communication component that effectively protects data security.

按,習用覆晶技術由於積體電路之接觸部結合於平整基板之電路層上,隨後加以進行封膠,此一結構容易被有心人士藉由研磨平整基板而使接觸部完整露出,進而加以破解並讀取內部資訊,導致資料遭有心人士竊取並利用,造成資訊安全之隱憂。According to the conventional flip chip technology, since the contact portion of the integrated circuit is bonded to the circuit layer of the flat substrate, and then the sealing is performed, the structure is easily exposed by the interested person to completely expose the contact portion by grinding the flat substrate, thereby cracking And the internal information is read, which causes the data to be stolen and used by the people who are interested, which causes the security of information security.

是以,要如何解決上述習用之問題與缺失,即為本發明之創作人與從事此行業之相關廠商所亟欲研究改善之方向所在者。Therefore, how to solve the above problems and lack of use, that is, the creators of the invention and the relevant manufacturers engaged in the industry are eager to study the direction of improvement.

故,本發明之創作人有鑑於上述缺失,乃搜集相關資料,經由多方評估及考量,並以從事於此行業累積之多年經驗,經由不斷試作及修改,始設計出此種有效保護資料安全的近場通訊元件之基板傾斜覆晶製程發明專利者。Therefore, in view of the above-mentioned deficiencies, the creators of the present invention have collected relevant information, and through multi-party evaluation and consideration, and through years of experience in the industry, through continuous trial and modification, have designed such effective protection of data security. The patent for the substrate tilting and flip chip process of the near field communication component.

本發明之主要目的在於:為針對習用封裝技術所存在之有心人士藉由研磨平整基板而使接觸部完整露出,進而加以破解並讀取內部資訊的問題點加以突破,達到有效保護資料安全之實用進步性。The main object of the present invention is to solve the problem that the contact person who is interested in the conventional packaging technology completely exposes the contact portion by grinding the flat substrate, thereby cracking and reading the internal information, thereby achieving practical protection of data security. Progressive.

為達到上述之目的,本發明一種近場通訊元件之基板傾斜覆晶製程,係包含下列步驟:a、於具傾斜角度之斜面基板上披覆導電層,其中斜面基板係為陶瓷基板,其中斜面基板與導電層間係形成電路層,而導電層內係包含針狀金屬粒子或球狀金屬粒子,並取積體電路置於導電層上,積體電路係延伸至少一對應電路層之接觸部;b、利用斜面壓頭裝置將斜面基板、導電層及積體電路進行壓合形成壓合體;c、將壓合體置於模具內並填充封裝層,封裝層係為陶土,使封裝層完整覆蓋壓合體上;d、利用整平元件將封裝層頂面切齊模具之頂部,整平元件係為將封裝層刮平之刮刀,使封裝層與壓合體形成結合體;以及e、將結合體進行烘烤形成晶片模組。In order to achieve the above object, the substrate tilting and flip chip process of the near field communication component comprises the following steps: a. coating a conductive layer on the inclined substrate with an inclined angle, wherein the inclined substrate is a ceramic substrate, wherein the inclined surface Forming a circuit layer between the substrate and the conductive layer, and the conductive layer comprises acicular metal particles or spherical metal particles, and the integrated circuit is disposed on the conductive layer, and the integrated circuit extends at least one contact portion of the corresponding circuit layer; b. using a beveling head device to press the bevel substrate, the conductive layer and the integrated circuit to form a pressed body; c, placing the pressed body in the mold and filling the encapsulating layer, the encapsulating layer is made of clay, and the encapsulating layer is completely covered and pressed D, using the leveling component to cut the top surface of the encapsulation layer to the top of the mold, the leveling component is a scraper that flattens the encapsulation layer, and the encapsulation layer and the compression body form a combination; and e, the combination is performed Baking forms a wafer module.

為達成上述目的及功效,本發明所採用之技術手段及構造,茲繪圖就本發明較佳實施例詳加說明其特徵與功能如下,俾利完全了解。In order to achieve the above objects and effects, the technical means and the structure of the present invention will be described in detail with reference to the preferred embodiments of the present invention.

請參閱第一圖、第二圖、第三圖、第四圖及第五圖所示,係為本發明較佳實施例之剖面示意圖、方塊流程圖、披覆動作示意圖、壓合動作示意圖及封裝動作示意圖,由圖中可清楚看出本發明一種近場通訊元件之基板傾斜覆晶製程,係包含下列步驟:a、於一具傾斜角度之斜面基板11上披覆一導電層12,所述的導電層12係為導電膠體或錫體其中之一者,又該斜面基板11係為陶瓷基板,該斜面基板11與該導電層12間係形成一電路層111,而該導電層12內係包含複數針狀金屬粒子121,並取一積體電路13置於該導電層12上,該積體電路13係延伸至少一對應該電路層111之接觸部131;b、利用一斜面壓頭裝置2將該斜面基板11、該導電層12及該積體電路13進行壓合形成一壓合體14;c、將該壓合體14置於一模具3內並填充一封裝層15,該封裝層15係為陶土,使該封裝層15完整覆蓋該壓合體14上;d、利用一整平元件4將該封裝層15頂面切齊該模具3之頂部,該整平元件4係為將封裝層15刮平之刮刀,使該封裝層15與該壓合體14形成一結合體16;以及e、將該結合體16進行烘烤形成一晶片模組1。Please refer to the first, second, third, fourth and fifth figures, which are schematic cross-sectional views, block flow diagrams, schematic diagrams of the overlaying actions, and schematic views of the pressing action according to a preferred embodiment of the present invention. Schematic diagram of the package operation. It can be clearly seen from the figure that the substrate tilting flip chip process of the near field communication component of the present invention comprises the following steps: a. coating a conductive layer 12 on a sloped substrate 11 having an oblique angle. The conductive layer 12 is one of a conductive paste or a tin body, and the bevel substrate 11 is a ceramic substrate. A circuit layer 111 is formed between the bevel substrate 11 and the conductive layer 12, and the conductive layer 12 is formed. And comprising a plurality of acicular metal particles 121, and an integrated circuit 13 is disposed on the conductive layer 12, the integrated circuit 13 extends at least a pair of contact portions 131 of the circuit layer 111; b, using a beveled indenter The device 2 presses the bevel substrate 11, the conductive layer 12 and the integrated circuit 13 to form a pressing body 14; c, the pressing body 14 is placed in a mold 3 and filled with an encapsulation layer 15, the encapsulation layer The 15 series is clay, so that the encapsulation layer 15 completely covers the And the top surface of the encapsulation layer 15 is cut into the top of the mold 3 by a flattening element 4, which is a scraper that scrapes the encapsulation layer 15 so that the encapsulation layer 15 and the encapsulation layer 15 The embossed body 14 forms a combined body 16; and e, the bonded body 16 is baked to form a wafer module 1.

藉由上述之結構、組成設計,茲就本發明之使用作動情形說明如下,請同時配合參閱第一圖、第二圖、第四圖、第六圖及第七圖所示,係為本發明較佳實施例之剖面示意圖、方塊流程圖、壓合動作示意圖、研磨第一動作示意圖及研磨第二動作示意圖,由圖中可清楚看出,藉由斜面基板11上方形成具角度之斜面,並利用斜面壓頭裝置2將斜面基板11、導電層12及積體電路13加以壓合,此時,由於電路層111以及接觸部131係位於不同之平面,因此當有心人士將斜面基板11進行研磨時,雖然一側之接觸部131已經顯露,卻因另一側尚未出現而繼續研磨,當另一側之接觸部131研磨出現時,積體電路13係也遭受研磨破壞,而有效保護內部資訊不易遭到竊取,達到有效保護資料安全之優點。With the above structure and composition design, the operation of the present invention will be described as follows. Please refer to the first, second, fourth, sixth and seventh figures as shown in the present invention. A schematic cross-sectional view, a block flow diagram, a press-fit action schematic, a first operation diagram of the grinding, and a second operation diagram of the grinding according to a preferred embodiment, as is clear from the figure, an angled slope is formed by the upper surface of the inclined substrate 11, and The bevel substrate 11, the conductive layer 12, and the integrated circuit 13 are pressed by the bevel indenter device 2. At this time, since the circuit layer 111 and the contact portion 131 are located on different planes, the person who is interested in polishing the bevel substrate 11 At the same time, although the contact portion 131 on one side has been revealed, the grinding is continued because the other side has not yet appeared, and when the contact portion 131 on the other side is polished, the integrated circuit 13 is also subjected to the grinding damage, thereby effectively protecting the internal information. It is not easy to be stolen and achieves the advantage of effectively protecting data security.

請同時配合參閱第八圖所示,係為本發明再一較佳實施例之導電層示意圖,由圖中可清楚看出,該導電層12a內係包含球狀金屬粒子122a,以提供另一不同之導電方式。Please also refer to the eighth embodiment, which is a schematic diagram of a conductive layer according to still another preferred embodiment of the present invention. As is clear from the figure, the conductive layer 12a contains spherical metal particles 122a to provide another Different ways of conducting electricity.

惟,以上所述僅為本發明之較佳實施例而已,非因此即侷限本發明之專利範圍,故舉凡運用本發明說明書及圖式內容所為之簡易修飾及等效結構變化,均應同理包含於本發明之專利範圍內,合予陳明。However, the above description is only the preferred embodiment of the present invention, and thus it is not intended to limit the scope of the present invention. Therefore, the simple modification and equivalent structural changes of the present specification and the drawings should be treated similarly. It is included in the scope of the patent of the present invention and is combined with Chen Ming.

綜上所述,本發明之近場通訊元件之基板傾斜覆晶製程於使用時,為確實能達到其功效及目的,故本發明誠為一實用性優異之創作,為符合發明專利之申請要件,爰依法提出申請,盼 審委早日賜准本發明,以保障創作人之辛苦創作,倘若 鈞局審委有任何稽疑,請不吝來函指示,創作人定當竭力配合,實感德便。In summary, the substrate tilting and flip chip process of the near field communication component of the present invention can achieve its efficacy and purpose when used, so the invention is a practical and excellent creation, and is an application for conforming to the invention patent.爰Protect the application according to law, and hope that the trial committee will grant the invention as soon as possible to protect the creators' hard work. If there is any doubt in the arbitral tribunal, please do not hesitate to give instructions, the creator will try his best to cooperate with him.

1...晶片模組1. . . Chip module

11...斜面基板11. . . Beveled substrate

111...電路層111. . . Circuit layer

12. 12a...導電層12. 12a. . . Conductive layer

121...針狀金屬粒子121. . . Acicular metal particles

122a...球狀金屬粒子122a. . . Spherical metal particles

13...積體電路13. . . Integrated circuit

131...接觸部131. . . Contact

14...壓合體14. . . Compressed body

15...封裝層15. . . Encapsulation layer

16...結合體16. . . hybrid

2...斜面壓頭裝置2. . . Bevel head device

3...模具3. . . Mold

4...整平元件4. . . Leveling component

第一圖 係為本發明較佳實施例之剖面示意圖。The first figure is a schematic cross-sectional view of a preferred embodiment of the invention.

第二圖 係為本發明較佳實施例之方塊流程圖。The second drawing is a block flow diagram of a preferred embodiment of the invention.

第三圖 係為本發明較佳實施例之披覆動作示意圖。The third figure is a schematic diagram of the overlaying action of the preferred embodiment of the present invention.

第四圖 係為本發明較佳實施例之壓合動作示意圖。The fourth figure is a schematic view of the pressing action of the preferred embodiment of the present invention.

第五圖 係為本發明較佳實施例之封裝動作示意圖。Figure 5 is a schematic diagram of the packaging operation of the preferred embodiment of the present invention.

第六圖 係為本發明較佳實施例之研磨第一動作示意圖。Figure 6 is a schematic view of the first operation of the polishing according to a preferred embodiment of the present invention.

第七圖 係為本發明較佳實施例之研磨第二動作示意圖。Figure 7 is a schematic view of the second operation of the polishing according to a preferred embodiment of the present invention.

第八圖 係為本發明再一較佳實施例之導電層示意圖。Figure 8 is a schematic view of a conductive layer in accordance with still another preferred embodiment of the present invention.

Claims (9)

一種近場通訊元件之基板傾斜覆晶製程,係包含下列步驟:a、於一具傾斜角度之斜面基板上披覆一導電層,且取一積體電路置於該導電層上;b、利用一斜面壓頭裝置將該斜面基板、該導電層及該積體電路進行壓合形成一壓合體;c、將該壓合體置於一模具內並填充一披覆層,使該披覆層完整覆蓋該壓合體上;d、利用一整平元件將該披覆層頂面切齊該模具之頂部,使該披覆層與該壓合體形成一結合體;以及e、將該結合體進行烘烤形成一晶片模組。A substrate tilting flip chip process for a near field communication component comprises the steps of: a. coating a conductive layer on a sloped substrate with an oblique angle, and placing an integrated circuit on the conductive layer; b, utilizing a beveling head device presses the bevel substrate, the conductive layer and the integrated circuit to form a pressing body; c, placing the pressing body in a mold and filling a coating layer to complete the coating layer Covering the pressing body; d, using a flattening element to cut the top surface of the coating layer to the top of the mold, so that the coating layer forms a combination with the pressing body; and e, baking the combined body Bake to form a wafer module. 如申請專利範圍第1項所述之近場通訊元件之基板傾斜覆晶製程,其中該斜面基板係為陶瓷基板。The substrate tilting flip chip process of the near field communication device according to claim 1, wherein the slope substrate is a ceramic substrate. 如申請專利範圍第1項所述之近場通訊元件之基板傾斜覆晶製程,其中該導電層內係包含複數針狀金屬粒子。The substrate tilting flip chip process of the near field communication device according to claim 1, wherein the conductive layer comprises a plurality of acicular metal particles. 如申請專利範圍第1項所述之近場通訊元件之基板傾斜覆晶製程,其中該導電層內係包含複數球狀金屬粒子。The substrate tilting flip chip process of the near field communication device according to claim 1, wherein the conductive layer comprises a plurality of spherical metal particles. 如申請專利範圍第1項所述之近場通訊元件之基板傾斜覆晶製程,其中該披覆層係為陶土。The substrate tilting flip chip process of the near field communication device according to claim 1, wherein the coating layer is clay. 如申請專利範圍第1項所述之近場通訊元件之基板傾斜覆晶製程,其中該整平元件係為將披覆層刮平之刮刀。The substrate tilting flip chip process of the near field communication component according to claim 1, wherein the leveling component is a doctor blade for flattening the coating layer. 如申請專利範圍第1項所述之近場通訊元件之基板傾斜覆晶製程,其中該斜面基板與該導電層間係形成一電路層。The substrate tilting flip chip process of the near field communication device according to claim 1, wherein the bevel substrate and the conductive layer form a circuit layer. 如申請專利範圍第1項所述之近場通訊元件之基板傾斜覆晶製程,其中該積體電路係延伸至少一對應該電路層之接觸部。The substrate tilt flip chip process of the near field communication device according to claim 1, wherein the integrated circuit extends at least one pair of contact portions of the circuit layer. 如申請專利範圍第1項所述之近場通訊元件之基板傾斜覆晶製程,其中該導電層係為導電膠體或錫體其中之一者。The substrate tilting flip chip process of the near field communication component according to claim 1, wherein the conductive layer is one of a conductive colloid or a tin body.
TW101101430A 2012-01-13 2012-01-13 Near-field communication components of the substrate tilt flip-chip process TWI485788B (en)

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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001143039A (en) * 1999-11-17 2001-05-25 Hitachi Maxell Ltd Semiconductor device and manufacturing method therefor
TW523920B (en) * 2000-11-18 2003-03-11 Lenghways Technology Co Ltd Integrated multi-channel communication passive device manufactured by using micro-electromechanical technique
US6586274B2 (en) * 1998-02-17 2003-07-01 Seiko Epson Corporation Semiconductor device, substrate for a semiconductor device, method of manufacture thereof, and electronic instrument
JP2005108955A (en) * 2003-09-29 2005-04-21 Matsushita Electric Ind Co Ltd Semiconductor device, manufacturing method thereof, and optical communication module
TW200531294A (en) * 2004-03-12 2005-09-16 Opto Tech Corp Light-emitting device with high heat dissipation efficiency
US7170149B2 (en) * 2001-04-13 2007-01-30 Yamaha Corporation Semiconductor device and package, and method of manufacture therefor
JP2007080153A (en) * 2005-09-16 2007-03-29 Dainippon Printing Co Ltd Non-contact data carrier inlet, non-contact data carrier inlet roll, non-contact data carrier, and method of manufacturing the same
US7309916B2 (en) * 2004-07-14 2007-12-18 Samsung Electronics Co., Ltd. Semiconductor package and method for its manufacture
JP2008053254A (en) * 2006-08-22 2008-03-06 Matsushita Electric Ind Co Ltd Method for manufacturing semiconductor device
TW201003890A (en) * 2008-05-27 2010-01-16 Intematix Corp Light emitting device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586274B2 (en) * 1998-02-17 2003-07-01 Seiko Epson Corporation Semiconductor device, substrate for a semiconductor device, method of manufacture thereof, and electronic instrument
JP2001143039A (en) * 1999-11-17 2001-05-25 Hitachi Maxell Ltd Semiconductor device and manufacturing method therefor
TW523920B (en) * 2000-11-18 2003-03-11 Lenghways Technology Co Ltd Integrated multi-channel communication passive device manufactured by using micro-electromechanical technique
US7170149B2 (en) * 2001-04-13 2007-01-30 Yamaha Corporation Semiconductor device and package, and method of manufacture therefor
JP2005108955A (en) * 2003-09-29 2005-04-21 Matsushita Electric Ind Co Ltd Semiconductor device, manufacturing method thereof, and optical communication module
TW200531294A (en) * 2004-03-12 2005-09-16 Opto Tech Corp Light-emitting device with high heat dissipation efficiency
US7309916B2 (en) * 2004-07-14 2007-12-18 Samsung Electronics Co., Ltd. Semiconductor package and method for its manufacture
JP2007080153A (en) * 2005-09-16 2007-03-29 Dainippon Printing Co Ltd Non-contact data carrier inlet, non-contact data carrier inlet roll, non-contact data carrier, and method of manufacturing the same
JP2008053254A (en) * 2006-08-22 2008-03-06 Matsushita Electric Ind Co Ltd Method for manufacturing semiconductor device
TW201003890A (en) * 2008-05-27 2010-01-16 Intematix Corp Light emitting device

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