TWI485711B

TWI485711B - Flash memory apparatus

Info

Publication number: TWI485711B
Application number: TW101109528A
Authority: TW
Inventors: Ching Sung Yang; Wen Hao Ching; Wei Ming Ku; Yung Hsiang Chen; Shih Chen Wang; Hsin Ming Chen
Original assignee: Ememory Technology Inc
Priority date: 2012-03-20
Filing date: 2012-03-20
Publication date: 2015-05-21
Also published as: TW201340108A

Description

快閃記憶體裝置Flash memory device

本發明是有關於一種快閃記憶體裝置，且特別是有關於一種具有電壓提升電路的快閃記憶體裝置。The present invention relates to a flash memory device, and more particularly to a flash memory device having a voltage boosting circuit.

現今的記憶體可分為揮發性記憶體與非揮發性記憶體，其中揮發性記憶體，例如動態隨機存取記憶體(DRAM,Dynamic Random Access Memory)，其優點為操作存取速度快，然而只有在電源啟動的情況下，揮發性記憶體才能存取資料。另一方面，非揮發性記憶體，例如快閃記憶體(flash memory)，其操作存取速度雖然較揮發性記憶體慢，但是即使在斷電的情形下，其內部儲存之資料可以保留很長的時間。Today's memory can be divided into volatile memory and non-volatile memory. Volatile memory, such as Dynamic Random Access Memory (DRAM), has the advantage of fast access speed. Volatile memory can access data only when the power is turned on. On the other hand, non-volatile memory, such as flash memory, has a slower operating access speed than volatile memory, but even in the case of power failure, the data stored internally can be retained very much. Long time.

一般快閃記憶體在操作方面，在寫入或抹除之操作時，需要特定電壓值將電荷注入或引出浮間(floating gate)。所以，通常會有一個升壓電路(charge-pump circuit)，或是電壓產生電路，來提供電壓以進行操作。因此，快閃記憶體的電壓產生電路在快閃記憶體操作上扮演了一個重要的角色。In general, flash memory requires a specific voltage value to inject or pull a charge into a floating gate during an operation of writing or erasing. Therefore, there is usually a charge-pump circuit or a voltage-generating circuit to supply voltage for operation. Therefore, the voltage generating circuit of the flash memory plays an important role in the operation of the flash memory.

據此，本發明提供一種快閃記憶體裝置，並且更進一步提供一種具有低輸入電壓及低耗能的特性之快閃記憶體裝置。Accordingly, the present invention provides a flash memory device, and further provides a flash memory device having low input voltage and low power consumption characteristics.

本發明提出一種快閃記憶體裝置，包括多數個記憶單元及多數個寫入控制電壓產生器。其中各記憶單元透過控制端點接收寫入控制電壓，並依據寫入控制電壓以執行資料寫入的操作。並且多數個寫入控制電壓產生器，分別耦接該些記憶單元。其中各寫入控制電壓產生器包括預充電壓傳送器及升壓電容。預充電壓傳送器耦接至各記憶單元的控制端點，這些預充電壓傳送器並依據預充驅動信號在第一時間週期提供預充電壓至對應的記憶單元的控制端點。此外，升壓電容耦接在各記憶單元的控制端點及推升電壓間，推升電壓在第二時間週期被提供至升壓電容，並在這些記憶單元的控制端點上產生寫入控制電壓。The invention provides a flash memory device comprising a plurality of memory cells and a plurality of write control voltage generators. Each of the memory units receives the write control voltage through the control terminal, and performs a data write operation according to the write control voltage. And a plurality of write control voltage generators are respectively coupled to the memory units. Each of the write control voltage generators includes a precharge voltage transmitter and a boost capacitor. The pre-charge pressure transmitter is coupled to the control terminals of the memory units, and the pre-charge voltage transmitters provide a pre-charge voltage to the control terminal of the corresponding memory unit in a first time period according to the pre-charge driving signal. In addition, the boosting capacitor is coupled between the control terminal of each memory unit and the push-up voltage, and the push-up voltage is supplied to the boost capacitor during the second time period, and write control is generated on the control terminals of the memory cells. Voltage.

在本發明之一實施例中，上述之快閃記憶體裝置更包括多數個抹除控制電壓產生器。多數個抹除控制電壓產生器分別耦接多數個記憶單元。其中各抹除控制電壓產生器包括抹除預充電壓傳送器及抹除升壓電容。抹除預充電壓傳送器耦接至各記憶單元的抹除端點，這些抹除預充電壓傳送器並依據抹除預充驅動信號在第三時間週期傳送抹除預充電壓至對應的記憶單元的抹除端點。抹除升壓電容耦接在各記憶單元的抹除端點及抹除推升電壓間，抹除推升電壓在第四時間週期被提供至抹除升壓電容，產生應用於抹除的抹除控制電壓。In an embodiment of the invention, the flash memory device further includes a plurality of erase control voltage generators. A plurality of erase control voltage generators are coupled to a plurality of memory cells, respectively. Each of the erase control voltage generators includes an erase precharge voltage transmitter and an erase boost capacitor. The erase pre-charge transmitter is coupled to the erase end of each memory unit, and the erase pre-charge transmitter transmits and erases the pre-charge voltage to the corresponding memory in a third time period according to the erase pre-charge drive signal. The erase point of the unit. The erase boost capacitor is coupled between the erase terminal of each memory cell and the erase push voltage, and the erase push voltage is supplied to the erase boost capacitor during the fourth time period to generate a wipe applied to the erase. In addition to the control voltage.

基於上述，本發明提出一種快閃記憶體裝置，快閃記憶體裝置透過預充電壓傳送器傳送外部電壓至記憶單元之控制或抹除端點，並將記憶單元之控制或抹除端點所接收之預充電壓提升至可供快閃記憶體裝置操作之寫入或抹除控制電壓。裝置外部所需要提供之電壓將被降低，也因此減低裝置外部提供之預充電壓之耗能。Based on the above, the present invention provides a flash memory device that transmits an external voltage to a control or erase end of a memory cell through a precharged voltage transmitter, and controls or erases the memory terminal. receive The precharge voltage is boosted to a write or erase control voltage that can be operated by the flash memory device. The voltage required to be supplied externally to the device will be reduced, thereby reducing the energy consumption of the pre-charge voltage provided externally to the device.

為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.

圖1A繪示本發明一實施例之快閃記憶體裝置100之示意圖。請參照圖1A，快閃記憶體裝置100包括多數個記憶單元120及多數個寫入控制電壓產生器110。記憶單元120以陣列的方式排列，並且，各寫入控制電壓產生器110耦接至所對應的各記憶單元120的控制端點CL。一般而言，快閃記憶體100之記憶單元120包括電晶體MF，像是堆疊式浮閘電晶體、單一多晶矽浮閘電晶體或是介電質儲存電晶體。各記憶單元120的兩端分別耦接至源極線SL和位元線BL。記憶單元120透過其控制端點CL接收由寫入控制電壓產生器110產生的寫入控制電壓Vc，以個別執行資料寫入操作。FIG. 1A is a schematic diagram of a flash memory device 100 according to an embodiment of the invention. Referring to FIG. 1A, the flash memory device 100 includes a plurality of memory cells 120 and a plurality of write control voltage generators 110. The memory cells 120 are arranged in an array, and each of the write control voltage generators 110 is coupled to the control endpoints CL of the corresponding memory cells 120. In general, the memory unit 120 of the flash memory 100 includes a transistor MF, such as a stacked floating gate transistor, a single polysilicon floating gate transistor, or a dielectric storage transistor. Both ends of each memory unit 120 are respectively coupled to the source line SL and the bit line BL. The memory unit 120 receives the write control voltage Vc generated by the write control voltage generator 110 through its control terminal CL to individually perform a data write operation.

圖1B繪示本發明一實施例之寫入控制電壓產生器110之示意圖。請參照圖1B，寫入控制電壓產生器110包括預充電壓傳送器111及升壓電容Cp。其中的預充電壓傳送器111耦接至記憶單元120的控制端點CL。關於預充電壓傳送器111的動作，首先，在第一時間週期中，提供預充驅動信號PREN至預充電壓傳送器111，以使得預充電壓傳送器111對應導通。在此同時，預充電壓Vpr會透過導通的預充電壓傳送器111，而被提供至對應的記憶單元120的控制端點CL。此時，寫入控制電壓Vc的電壓值等於預充電壓Vpr的電壓值。另外一方面，升壓電容Cp耦接在記憶單元120的控制端點CL及推升電壓Vpu間，並且在第一時間週期後，於第二時間週期推升電壓Vpu被提供至升壓電容Cp未耦接預充電壓傳送器111的端點上。如此一來，記憶單元120的控制端點CL上的寫入控制電壓Vc將被推升。具體來說，此時的寫入控制電壓Vc的電壓值，接近等於推升電壓Vpu的電壓值加上預充電壓Vpr的電壓值。FIG. 1B is a schematic diagram of a write control voltage generator 110 according to an embodiment of the invention. Referring to FIG. 1B, the write control voltage generator 110 includes a precharge voltage transmitter 111 and a boost capacitor Cp. The pre-charge pressure transmitter 111 is coupled to the control terminal CL of the memory unit 120. Regarding the action of the precharge pressure transmitter 111, first, in the first time period, the precharge drive signal PREN is supplied to the precharge pressure transmitter 111 to make the precharge The pressure transmitter 111 is correspondingly turned on. At the same time, the precharge voltage Vpr is supplied to the control terminal CL of the corresponding memory unit 120 through the turned-on precharge voltage transmitter 111. At this time, the voltage value of the write control voltage Vc is equal to the voltage value of the precharge voltage Vpr. On the other hand, the boosting capacitor Cp is coupled between the control terminal CL of the memory unit 120 and the push-up voltage Vpu, and after the first time period, the boost voltage Vpu is supplied to the boost capacitor Cp in the second time period. Not connected to the end of the pre-charged pressure transmitter 111. As a result, the write control voltage Vc on the control terminal CL of the memory unit 120 will be boosted. Specifically, the voltage value of the write control voltage Vc at this time is approximately equal to the voltage value of the push-up voltage Vpu plus the voltage value of the precharge voltage Vpr.

接著請參照圖2A，圖2A繪示本發明一實施例之預充電壓傳送器111的一實施方式的示意圖。在本實施方式中，預充電壓傳送器111包括預充寫入開關113，其由電晶體M1所建構。預充寫入開關113具有第一端、第二端及控制端，預充寫入開關113的第一端耦接對應的記憶單元120的控制端點CL，預充寫入開關113的第二端接收預充電壓Vpr，並且預充寫入開關113的控制端接收預充驅動信號PREN。2A, FIG. 2A is a schematic diagram of an embodiment of a pre-charged pressure transmitter 111 according to an embodiment of the present invention. In the present embodiment, the precharge pressure transmitter 111 includes a precharge write switch 113 which is constructed by a transistor M1. The pre-charge write switch 113 has a first end, a second end, and a control end. The first end of the pre-charge write switch 113 is coupled to the control end point CL of the corresponding memory unit 120, and the second pre-charge write switch 113 is The terminal receives the precharge voltage Vpr, and the control terminal of the precharge write switch 113 receives the precharge drive signal PREN.

為了更進一步說明，請配合參照圖2A以及2B。其中，圖2B繪示本發一明實施例之預充電壓傳送器111之應用波形圖。於本實施例中，應用波形圖繪示多個寫入控制電壓產生器110如何來同時執行選擇性的資料寫入及資料抹除操作。當對控制端點CL充電時，請參照圖2B之曲線 201、203、205及207。於時間週期T1時，電晶體M1的第二端接收預充電壓Vpr，例如5伏特(曲線201)。此外，由電晶體M1的控制端所接收的預充驅動信號PREN偏壓至，例如7.5伏特(曲線203)，並且電晶體M1對應導通。於此同時，推升電壓Vpu的初始值例如為0伏特(曲線205)，預充電壓Vpr傳送至對應的記憶單元120的控制端CL，並且寫入控制電壓Vc之值相等於預充電壓Vpr的值(曲線207)。接著，於第二時間週期T2時，推升電壓Vpu偏壓至例如5伏特(曲線205)，寫入控制電壓Vc被推升至例如9.5伏特(曲線207)，其值約等於預充電壓Vpr與推升電壓Vpu之和。接下來，記憶單元120則可執行資料寫入操作。For further explanation, please refer to FIGS. 2A and 2B. 2B is a waveform diagram of application of the pre-charge pressure transmitter 111 of the embodiment of the present invention. In the present embodiment, the application waveform diagram illustrates how the plurality of write control voltage generators 110 simultaneously perform selective data writing and data erasing operations. When charging the control terminal CL, please refer to the curve of Figure 2B. 201, 203, 205, and 207. At time period T1, the second end of transistor M1 receives a precharge voltage Vpr, such as 5 volts (curve 201). Further, the precharge drive signal PREN received by the control terminal of the transistor M1 is biased to, for example, 7.5 volts (curve 203), and the transistor M1 is turned on. At the same time, the initial value of the push-up voltage Vpu is, for example, 0 volt (curve 205), the pre-charge voltage Vpr is transmitted to the control terminal CL of the corresponding memory unit 120, and the value of the write control voltage Vc is equal to the precharge voltage Vpr. Value (curve 207). Next, during the second time period T2, the push-up voltage Vpu is biased to, for example, 5 volts (curve 205), and the write control voltage Vc is boosted to, for example, 9.5 volts (curve 207), which is approximately equal to the pre-charge voltage Vpr. The sum of the push voltage Vpu. Next, the memory unit 120 can perform a data write operation.

在本發明另一實施例中，當對控制端點CL放電時，請參照曲線203、205、211及217。在本實施例中，預充驅動信號PREN與推升電壓Vpu表現如上述實施例的曲線203及205。此外，於第一時間週期T1時，電晶體M1接收預充電壓Vpr例如為5伏特(曲線211)，並且寫入控制電壓Vc之值相等於預充電壓Vpr之值(曲線217)。於時間週期T2時，預充電壓Vpr被驅動降至例如0伏特(曲線211)，並且寫入控制電壓Vc放電至例如0伏特(曲線217)。接著，記憶單元120可執行資料抹除操作。In another embodiment of the invention, when discharging the control terminal CL, please refer to curves 203, 205, 211 and 217. In the present embodiment, the precharge drive signal PREN and the push-up voltage Vpu exhibit the curves 203 and 205 as in the above embodiment. Further, at the first time period T1, the transistor M1 receives the precharge voltage Vpr, for example, 5 volts (curve 211), and the value of the write control voltage Vc is equal to the value of the precharge voltage Vpr (curve 217). At time period T2, the precharge voltage Vpr is driven down to, for example, 0 volts (curve 211), and the write control voltage Vc is discharged to, for example, 0 volts (curve 217). Next, the memory unit 120 can perform a data erase operation.

值得注意的是，預充驅動信號PREN在進入時間週期T2之前，電壓準位可以略為下降至與預充電壓Vpr相同，例如從7.5伏特降至5伏特(曲線203)。此時電晶體M1將截止而成為二極體的形態，並逆向偏壓於預充電壓Vpr與寫入控制電壓Vc之間。如此一來，在寫入控制電壓Vc在第二時間週期T2被推升時，預充電壓Vpr不致影響到寫入控制電壓Vc的被推升動作。It is worth noting that before the pre-charge period signal TREN enters the time period T2, the voltage level may drop slightly to be the same as the pre-charge voltage Vpr, for example from 7.5 volts to 5 volts (curve 203). At this time, the transistor M1 will The diode is turned off to form a diode and is reversely biased between the precharge voltage Vpr and the write control voltage Vc. As a result, when the write control voltage Vc is boosted in the second time period T2, the precharge voltage Vpr does not affect the push-up operation of the write control voltage Vc.

以下請參照圖2C，圖2C繪示本發明實施例之預充電壓傳送器111的另一實施方式。請參照圖2C，與上一實施方式不相同的是，在本實施方式中，預充電壓傳送器111中的預充寫入開關113更包括電晶體M2與電晶體M1。電晶體M1與電晶體M2各別包括第一端、第二端及控制端。電晶體M2與電晶體M1串接，並且電晶體M2耦接在電晶體M1耦接對應的記憶單元120的控制端點CL的路徑間。具體一點來說明，電晶體M2的第一端耦接至對應的記憶單元120的控制端點CL，電晶體M2的第二端耦接至電晶體M1的第一端，電晶體M2的控制端接收控制信號CTLS。藉此，透過電晶體M1及電晶體M2的串接，便可讓寫入控制電壓Vc以及預充電壓Vpr的最大可能的電壓差，分擔於電晶體M1及電晶體M2之上。Referring to FIG. 2C, FIG. 2C illustrates another embodiment of the pre-charged pressure transmitter 111 of the embodiment of the present invention. Referring to FIG. 2C, unlike the previous embodiment, in the present embodiment, the precharge write switch 113 in the precharge pressure transmitter 111 further includes a transistor M2 and a transistor M1. The transistor M1 and the transistor M2 each include a first end, a second end, and a control end. The transistor M2 is connected in series with the transistor M1, and the transistor M2 is coupled between the paths of the transistor M1 coupled to the control terminal CL of the corresponding memory unit 120. Specifically, the first end of the transistor M2 is coupled to the control terminal CL of the corresponding memory unit 120, and the second end of the transistor M2 is coupled to the first end of the transistor M1, and the control end of the transistor M2. Receive control signal CTLS. Thereby, the maximum possible voltage difference between the write control voltage Vc and the precharge voltage Vpr can be shared between the transistor M1 and the transistor M2 through the series connection of the transistor M1 and the transistor M2.

請參照圖3A，圖3A繪示本發明實施例之預充電壓傳送器111之另一實施方式的示意圖。在本實施方式中，預充電壓傳送器111包括預充寫入開關115及預充寫入開關117。預充寫入開關115串接在第一預充電壓Vpr1以及對應的記憶單元120的控制端點CL間，並且預充寫入開關117串接在第二預充電壓Vpr2以及對應的記憶單元120的控制端點CL間。預充寫入開關115及117分別包括電晶體M1及M2，電晶體M1耦接於第一預充電壓Vpr1及對應的記憶單元120的控制端點CL之間，並且電晶體M2耦接於第二預充電壓Vpr2及對應的記憶單元120的控制端點CL之間。分別根據第一預充驅動信號PREN1或是第二預充驅動信號PREN2，將第一或第二預充電壓Vpr1或Vpr2傳至記憶單元120。Please refer to FIG. 3A. FIG. 3A is a schematic diagram of another embodiment of a pre-charged pressure transmitter 111 according to an embodiment of the present invention. In the present embodiment, the precharge voltage transmitter 111 includes a precharge write switch 115 and a precharge write switch 117. The precharge write switch 115 is serially connected between the first precharge voltage Vpr1 and the control terminal CL of the corresponding memory unit 120, and the precharge write switch 117 is serially connected to the second precharge voltage Vpr2 and the corresponding memory unit 120. The control endpoint is between CL. The precharge write switches 115 and 117 respectively include an electric crystal The body M1 and the M2, the transistor M1 is coupled between the first pre-charge voltage Vpr1 and the control terminal CL of the corresponding memory unit 120, and the transistor M2 is coupled to the second pre-charge voltage Vpr2 and the corresponding memory unit 120. Control between endpoints CL. The first or second pre-charge voltages Vpr1 or Vpr2 are transmitted to the memory unit 120 according to the first pre-charge driving signal PREN1 or the second pre-charge driving signal PREN2, respectively.

請注意，在本實施例中，可透過預充寫入開關115或117傳送不同電壓值之預充電壓，例如為第一或第二預充電壓Vpr1或Vpr2，以符合不同操作的電壓需求。舉例來說，在執行資料寫入的動作時，可透過預充寫入開關117提供資料寫入所需要之第二預充電壓Vpr2，例如5伏特。另一方面，若要執行不同的操作(例如讀取操作)，亦可透過預充寫入開關115提供第一預充電壓Vpr1，例如0伏特。藉此，可經由不同之開關，傳送不同電壓值至對應的記憶單元120的控制端點CL。Please note that in the present embodiment, the precharge voltage of different voltage values, for example, the first or second precharge voltage Vpr1 or Vpr2, can be transmitted through the precharge write switch 115 or 117 to meet the voltage requirements of different operations. For example, when performing the data writing operation, the second pre-charging voltage Vpr2 required for data writing, for example, 5 volts, can be provided through the pre-filling write switch 117. On the other hand, if a different operation (for example, a read operation) is to be performed, the first precharge voltage Vpr1, for example, 0 volts, may also be supplied through the precharge write switch 115. Thereby, different voltage values can be transmitted to the control endpoint CL of the corresponding memory unit 120 via different switches.

請參照圖3B，圖3B繪示本發明實施例的預充電壓傳送器111包括預充寫入開關115與117之再一實施方式的示意圖。本實施方式之預充寫入開關115與117可以分別用兩個電晶體串接形成。預充寫入開關115包括電晶體M1及M3，串接於第一預充電壓Vpr1及對應的記憶單元120的控制端點CL之間。同樣地，預充寫入開關117包括電晶體M2及M4，串接於第二預充電壓Vpr2及對應的記憶單元120的控制端點CL之間。二者選一的是，在本實施方式中，第一預充電壓Vpr1可藉由提供第一預充驅動信號PREN1至電晶體M1的控制端以及提供第一控制信號CTLS1至電晶體M3的控制端，傳遞至對應的記憶單元120的控制端點CL，或者是，第二預充電壓Vpr2可藉由提供第二預充驅動信號PREN2至電晶體M2的控制端及提供第二控制信號CTLS2至電晶體M4的控制端，傳遞至對應的記憶單元120的控制端點CL。Please refer to FIG. 3B. FIG. 3B is a schematic diagram of still another embodiment of the precharge voltage transmitter 111 including the precharge write switches 115 and 117 according to an embodiment of the present invention. The precharge write switches 115 and 117 of the present embodiment can be formed by serially connecting two transistors. The precharge write switch 115 includes transistors M1 and M3 connected in series between the first precharge voltage Vpr1 and the control terminal CL of the corresponding memory unit 120. Similarly, the precharge write switch 117 includes transistors M2 and M4 connected in series between the second precharge voltage Vpr2 and the control terminal CL of the corresponding memory unit 120. Alternatively, in the embodiment, the first pre-charge voltage Vpr1 can be provided by providing the first pre-charge drive. The control terminal of the signal PREN1 to the transistor M1 and the control terminal for providing the first control signal CTLS1 to the transistor M3 are transferred to the control terminal CL of the corresponding memory unit 120, or the second pre-charge voltage Vpr2 can be provided by The second pre-charge driving signal PREN2 to the control terminal of the transistor M2 and the control terminal providing the second control signal CTLS2 to the transistor M4 are transmitted to the control terminal CL of the corresponding memory unit 120.

值得一提的是，在本發明實施例中，預充寫入開關115之電晶體M1及電晶體M3可為N型電晶體。相對的，預充寫入開關117之電晶體M2及電晶體M4可為P型電晶體。P型電晶體適於傳遞高電壓，例如5伏特，而N型電晶體適於傳遞低電壓，例如0伏特。如此一來，本實施方式之預充電壓傳送器111可適用於大範圍的操作快閃記憶體的電壓傳遞。It should be noted that in the embodiment of the present invention, the transistor M1 and the transistor M3 of the precharge switch 115 may be N-type transistors. In contrast, the transistor M2 and the transistor M4 of the precharge switch 117 may be P-type transistors. P-type transistors are suitable for delivering high voltages, such as 5 volts, while N-type transistors are suitable for delivering low voltages, such as 0 volts. In this way, the pre-charge pressure transmitter 111 of the present embodiment can be applied to a wide range of operation of the voltage transfer of the flash memory.

圖4繪示本發明另一實施例之快閃記憶體裝置400之示意圖。請參照圖4，快閃記憶體裝置400包括複數個記憶單元420與複數個寫入控制電壓產生器410。每個耦接於源極線SL與位元線BL之間的記憶肥420包括單一多晶矽浮閘電晶體MF、選擇電晶體MS、操作電晶體MO及閘極電容Cf。單一多晶矽浮閘電晶體MF、選擇電晶體MS及操作電晶體MO各包括第一端、第二端及控制端。單一多晶矽浮閘電晶體MF的第一端耦接源極線SL，單一多晶矽浮閘電晶體MF的第二端耦接位元線BL，並且單一多晶矽浮閘電晶體MF的控制端接收寫入控制電壓Vc用以操作。選擇電晶體MS耦接於源極線SL耦接單一多晶矽浮閘電晶體MF的路徑上。詳言之，選擇電晶體MS的第一端耦接源極線SL，選擇電晶體MS的第二端耦接單一多晶矽閘極電晶體MF的第一端，並且選擇電晶體MS的控制端接收選擇信號SG。操作電晶體MO耦接於位元線BL耦接單一多晶矽浮閘電晶體MF的路徑上。更詳細而言，操作電晶體MO的第一端耦接單一多晶矽閘極電晶體MF的第二端，操作電晶體MO的第二端耦接位元線BL，並且操作電晶體MO的控制端耦接字元線驅動信號WL。除此之外，閘極電容Cf耦接在寫入控制電壓Vc與單一多晶矽浮閘電晶體MF的控制端之間。FIG. 4 is a schematic diagram of a flash memory device 400 according to another embodiment of the present invention. Referring to FIG. 4, the flash memory device 400 includes a plurality of memory cells 420 and a plurality of write control voltage generators 410. Each memory fertilizer 420 coupled between the source line SL and the bit line BL includes a single polysilicon floating gate transistor MF, a selection transistor MS, an operating transistor MO, and a gate capacitance Cf. The single polysilicon floating gate transistor MF, the selection transistor MS, and the operating transistor MO each include a first end, a second end, and a control end. The first end of the single polysilicon floating gate transistor MF is coupled to the source line SL, the second end of the single polysilicon floating gate transistor MF is coupled to the bit line BL, and the control end of the single polysilicon floating gate transistor MF receives the write The control voltage Vc is used for operation. Selecting a transistor MS coupled to the source line SL coupled to a single polysilicon float On the path of the gate transistor MF. In detail, the first end of the selected transistor MS is coupled to the source line SL, the second end of the selected transistor MS is coupled to the first end of the single polysilicon gate transistor MF, and the control end of the transistor MS is selected. The selection signal SG is received. The operating transistor MO is coupled to the path of the bit line BL coupled to the single polysilicon floating gate transistor MF. In more detail, the first end of the operating transistor MO is coupled to the second end of the single polysilicon gate transistor MF, the second end of the operating transistor MO is coupled to the bit line BL, and the control of the operating transistor MO is performed. The terminal is coupled to the word line drive signal WL. In addition, the gate capacitance Cf is coupled between the write control voltage Vc and the control terminal of the single polysilicon floating gate transistor MF.

圖5A繪示本發明再一實施例之快閃記憶體裝置500的部份電路示意圖。請參照圖5A，除了資料寫入之操作外，快閃記憶體裝置500亦需要電壓產生電路以進行抹除操作。因此，本實施例之快閃記憶體裝置500中，記憶單元520的抹除端點EL耦接抹除控制電壓產生器530，並且抹除預充電壓Vpre依據抹除預充驅動信號PRENE，傳遞至記憶單元520的抹除端點EL。緊接著，用以抹除的抹除控制電壓Vce根據提供至抹除升壓電容Cpe的抹除推升電壓Vpue而產生。其中，記憶單元520包括電晶體MF，像是堆疊式浮閘電晶體、單一多晶矽浮閘電晶體或是介電質儲存電晶體。FIG. 5A is a partial circuit diagram of a flash memory device 500 according to still another embodiment of the present invention. Referring to FIG. 5A, in addition to the data writing operation, the flash memory device 500 also requires a voltage generating circuit to perform an erase operation. Therefore, in the flash memory device 500 of the embodiment, the erase end point EL of the memory unit 520 is coupled to the erase control voltage generator 530, and the erase precharge voltage Vpre is transmitted according to the erase precharge drive signal PRENE. The erase endpoint EL to the memory unit 520. Next, the erase control voltage Vce for erasing is generated in accordance with the erase push-up voltage Vpue supplied to the erase boost capacitor Cpe. The memory unit 520 includes a transistor MF, such as a stacked floating gate transistor, a single polysilicon floating gate transistor, or a dielectric storage transistor.

圖5B繪示本發明一實施例之抹除預充電壓傳送器531之示意圖。請參照圖5B，抹除預充電壓傳送器531包括抹除預充開關533，於本實施例中，其中抹除預充開關 533可為電晶體M1，耦接於抹除預充電壓Vpre及對應的記憶單元520的抹除端點EL之間，並且根據抹除預充驅動信號PRENE，將電晶體M1導通。FIG. 5B is a schematic diagram of the erase pre-charge transmitter 531 according to an embodiment of the invention. Referring to FIG. 5B, the erase pre-charge transmitter 531 includes an erase pre-charge switch 533. In this embodiment, the pre-charge switch is erased. 533 may be a transistor M1 coupled between the erase precharge voltage Vpre and the erase terminal EL of the corresponding memory unit 520, and turn on the transistor M1 according to the erase precharge drive signal PRENE.

圖5C繪示本發明一實施例之抹除預充電壓傳送器531包括抹除預充開關533之另一實施方式。請參照圖5C，抹除預充開關533亦可包括兩電晶體M1與M2，串接於抹除預充電壓Vpre與對應的記憶單元520的抹除端點EL之間，並且分別依據預充驅動信號PRENE及控制信號CTLS驅動電晶體M1與電晶體M2。FIG. 5C illustrates another embodiment of the erase pre-charge transmitter 531 including the erase pre-charge switch 533 in accordance with an embodiment of the present invention. Referring to FIG. 5C, the erase precharge switch 533 may further include two transistors M1 and M2 connected in series between the erase precharge voltage Vpre and the erase terminal EL of the corresponding memory unit 520, and respectively according to the precharge. The drive signal PRENE and the control signal CTLS drive the transistor M1 and the transistor M2.

圖5D繪示本發明一實施例之抹除預充電壓傳送器531之另一實施方式。請參照圖5D，抹除預充電壓傳送器531包括抹除預充開關535及537。抹除預充開關535及537可為電晶體M1及M2，分別耦接於第一抹除預充電壓Vpre1與對應的記憶單元520的抹除端點EL之間，以及介於第二抹除預充電壓Vpre2與對應的記憶單元520的抹除端點EL之間。藉由分別提供第一抹除預充驅動信號PRENE1至電晶體M1，或提供第二抹除預充驅動信號PRENE2至電晶體M2，來操作抹除預充開關535與537。FIG. 5D illustrates another embodiment of the erase pre-charge transmitter 531 in accordance with an embodiment of the present invention. Referring to FIG. 5D, erasing the pre-charge pressure transmitter 531 includes erasing the pre-charge switches 535 and 537. The erase pre-charge switches 535 and 537 may be the transistors M1 and M2 respectively coupled between the first erase pre-charge voltage Vpre1 and the erase end EL of the corresponding memory unit 520, and between the second erase The precharge voltage Vpre2 is between the eraser terminal EL of the corresponding memory unit 520. The erase precharge switches 535 and 537 are operated by providing the first erase precharge drive signal PRENE1 to the transistor M1, respectively, or providing the second erase precharge drive signal PRENE2 to the transistor M2.

圖5E繪示本發明一實施例之抹除預充電壓傳送器531包括抹除預充開關535與537之另一實施方式。請參照圖5E，抹除預充開關535及537可各別以兩個電晶體串接實現。抹除預充開關535包括電晶體M1及M3串接於第一抹除預充電壓Vpre1與對應的記憶單元520的抹除端點EL之間，並且抹除預充開關537包括電晶體M2及M4 串接於第二抹除預充電壓Vpre2與對應的記憶單元520的抹除端點之間。二者選一的是，可根據第一抹除預充驅動信號PRENE1及第一抹除控制信號CTLS1導通電晶體M1及M3，或是，根據第二抹除預充驅動信號PRENE2及第二抹除控制信號CTLS2導通電晶體M2及M4。透過上述的過程，分別對抹除預充開關535或537進行操作。FIG. 5E illustrates another embodiment of the erase pre-charge transmitter 531 including the erase pre-charge switches 535 and 537, in accordance with an embodiment of the present invention. Referring to FIG. 5E, the erase precharge switches 535 and 537 can be implemented by serially connecting two transistors. The erase precharge switch 535 includes transistors M1 and M3 connected in series between the first erase precharge voltage Vpre1 and the erase terminal EL of the corresponding memory unit 520, and the erase precharge switch 537 includes the transistor M2 and M4 It is connected in series between the second erase precharge voltage Vpre2 and the erase end of the corresponding memory unit 520. Alternatively, the pre-charge driving signal PRENE1 and the first erasing control signal CTLS1 may be used to conduct the transistors M1 and M3, or according to the second erasing pre-charging driving signal PRENE2 and the second erasing. In addition to the control signal CTLS2, the transistors M2 and M4 are energized. Through the above process, the erase precharge switch 535 or 537 is operated separately.

圖6繪示本發明一實施例的快閃記憶體裝置600的示意圖。請參照圖6，本實施例大致與圖4實施例相同，於圖6的相同的參考標號代表相同或相似的元件。相較於圖4實施例的記憶體裝置400，快閃記憶體裝置600更包括複數個記憶單元620及複數個抹除控制電壓產生器630。更詳細而言，各個耦接於源極線SL與位元線BL間的記憶單元620包括單一多晶矽浮閘電晶體MF、選擇電晶體MS、操作電晶體MO、閘極電容Cf以及抹除閘極電容Cfe。FIG. 6 is a schematic diagram of a flash memory device 600 according to an embodiment of the invention. Referring to FIG. 6, the embodiment is substantially the same as the embodiment of FIG. 4, and the same reference numerals in FIG. 6 denote the same or similar elements. Compared with the memory device 400 of the embodiment of FIG. 4, the flash memory device 600 further includes a plurality of memory cells 620 and a plurality of erase control voltage generators 630. In more detail, each of the memory cells 620 coupled between the source line SL and the bit line BL includes a single polysilicon floating gate transistor MF, a selection transistor MS, an operating transistor MO, a gate capacitance Cf, and an erase gate. Pole capacitor Cfe.

此外，一般而言，於資料抹除時，可針對一整個區塊的記憶單元同時進行抹除的操作。因此，透過一個抹除預充電壓傳送器搭配多個記憶單元之設計，可減少抹除預充電壓傳送器之數量。In addition, in general, at the time of data erasing, the erasing operation can be simultaneously performed for the memory cells of an entire block. Therefore, the number of pre-charged pressure transmitters can be reduced by a design that erases the pre-charger transmitter with multiple memory cells.

綜上所述，本發明提出一種快閃記憶體裝置，依據此快閃記憶體裝置提升電壓的操作，可降低裝置外部所需要提供之電壓，因此減低裝置外部提供電壓時產生之耗能。此外，提供多重電壓輸入的設計，以擴大電壓輸入的範圍，以利於快閃記憶體裝置在不同電壓下進行各種操作。In summary, the present invention provides a flash memory device according to which the operation of boosting the voltage of the flash memory device can reduce the voltage required to be externally supplied to the device, thereby reducing the energy consumption generated when the voltage is externally supplied from the device. In addition, multiple voltage input designs are provided to extend the range of voltage inputs to facilitate various operations of flash memory devices at different voltages.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the invention has been disclosed above by way of example, it is not intended to be limiting The scope of the present invention is defined by the scope of the appended claims, and the scope of the invention is defined by the scope of the appended claims. Prevail.

100、400、500、600‧‧‧快閃記憶體裝置100, 400, 500, 600‧‧‧ flash memory devices

110、410、510‧‧‧寫入控制電壓產生器110, 410, 510‧‧‧ write control voltage generator

111‧‧‧預充電壓傳送器111‧‧‧Precharged pressure transmitter

120、420、520、620‧‧‧記憶單元120, 420, 520, 620‧‧‧ memory unit

113、115、117‧‧‧預充寫入開關113, 115, 117‧‧‧ pre-filled write switch

201、203、205、207、211、217‧‧‧曲線201, 203, 205, 207, 211, 217‧‧‧ curves

530、630‧‧‧抹除控制電壓產生器530, 630‧‧‧ erase control voltage generator

531‧‧‧抹除預充電壓傳送器531‧‧‧Erasing precharged pressure transmitter

533、535、537‧‧‧抹除預充開關533, 535, 537‧‧‧ erase pre-charge switch

CL‧‧‧控制端點CL‧‧‧ control endpoint

EL‧‧‧抹除端點EL‧‧‧ erased endpoint

Cp、Cf、Cpe、Cfe‧‧‧電容Cp, Cf, Cpe, Cfe‧‧‧ capacitors

Vpu‧‧‧推升電壓Vpu‧‧‧ push up voltage

PREN、PREN1、PREN2、PRENE、PRENE1、PRENE2‧‧‧驅動信號PREN, PREN1, PREN2, PRENE, PRENE1, PRENE2‧‧‧ drive signals

Vc、Vce、Vpr、Vpr1、Vpr2、Vpre、Vpue、Vpre1、Vpre2‧‧‧電壓Vc, Vce, Vpr, Vpr1, Vpr2, Vpre, Vpue, Vpre1, Vpre2‧‧‧ voltage

M1、M2、M3、M4、MF、MS、MO‧‧‧電晶體M1, M2, M3, M4, MF, MS, MO‧‧‧ transistors

T1、T2‧‧‧時間週期T1, T2‧‧ ‧ time period

CTLS、CTLS1、CTLS2‧‧‧控制信號CTLS, CTLS1, CTLS2‧‧‧ control signals

WL‧‧‧字元線WL‧‧‧ character line

BL‧‧‧位元線BL‧‧‧ bit line

SL‧‧‧源極線SL‧‧‧ source line

SG‧‧‧選擇信號SG‧‧‧Selection signal

圖1A繪示本發明一實施例之快閃記憶體裝置100之示意圖。FIG. 1A is a schematic diagram of a flash memory device 100 according to an embodiment of the invention.

圖1B繪示本發明一實施例之寫入控制電壓產生器110之示意圖。FIG. 1B is a schematic diagram of a write control voltage generator 110 according to an embodiment of the invention.

圖2A繪示本發明一實施例之預充電壓傳送器111之示意圖。2A is a schematic diagram of a pre-charged pressure transmitter 111 in accordance with an embodiment of the present invention.

圖2B繪示本發一明實施例之預充電壓傳送器111之動作波形圖。FIG. 2B is a waveform diagram showing the operation of the pre-charge pressure transmitter 111 of the embodiment of the present invention.

圖2C、圖3A與圖3B分別繪示本發明一實施例之預充電壓傳送器111之不同實施方式的示意圖。2C, 3A and 3B are schematic views respectively showing different embodiments of the pre-charge pressure transmitter 111 according to an embodiment of the present invention.

圖4繪示本發明另一實施例之快閃記憶體裝置400之示意圖。FIG. 4 is a schematic diagram of a flash memory device 400 according to another embodiment of the present invention.

圖5A繪示本發明再一實施例之快閃記憶體裝置500之部份電路示意圖。FIG. 5A is a partial circuit diagram of a flash memory device 500 according to still another embodiment of the present invention.

圖5B~圖5E分別繪示本發明實施例之抹除預充電壓傳送器531之不同實施方式的示意圖。5B-5E are schematic views respectively showing different embodiments of the erase pre-charge transmitter 531 according to the embodiment of the present invention.

圖6繪示本發明一實施例的快閃記憶體裝置600的示意圖。FIG. 6 is a schematic diagram of a flash memory device 600 according to an embodiment of the invention.

100‧‧‧快閃記憶體裝置100‧‧‧Flash memory device

110‧‧‧寫入控制電壓產生器110‧‧‧Write control voltage generator

120‧‧‧記憶單元120‧‧‧ memory unit

CL‧‧‧控制端點CL‧‧‧ control endpoint

Vc‧‧‧寫入控制電壓Vc‧‧‧ write control voltage

SL‧‧‧源極線SL‧‧‧ source line

BL‧‧‧位元線BL‧‧‧ bit line

MF‧‧‧電晶體MF‧‧•O crystal

Claims

一種快閃記憶體裝置，包括：多數個記憶單元，其中各該記憶單元透過一控制端點接收一寫入控制電壓，並依據該寫入控制電壓執行資料寫入的操作；多數個寫入控制電壓產生器，分別耦接該些記憶單元，其中各該寫入控制電壓產生器包括：一預充電壓傳送器，耦接至各該記憶單元的控制端點，該些預充電壓傳送器依據一預充驅動信號在一第一時間週期時，提供一預充電壓至對應的記憶單元的控制端點；以及一升壓電容，耦接在各該記憶單元的控制端點及一推升電壓間，該推升電壓在一第二時間週期被提供至該升壓電容，並在該些記憶單元的控制端點上產生該寫入控制電壓；以及多數個抹除控制電壓產生器，分別耦接該些記憶單元，其中各該抹除控制電壓產生器包括：一抹除預充電壓傳送器，耦接至各該記憶單元的抹除端點，該些抹除預充電壓傳送器並依據一抹除預充驅動信號在一第三時間週期傳送一抹除預充電壓至對應的該記憶單元的抹除端點；以及一抹除升壓電容，該抹除升壓電容耦接在各該記憶單元的抹除端點及一抹除推升電壓間，該抹除推升電壓在一第四時間週期被提供至該抹除升壓電容，產生應用於抹除的該抹除控制電壓。 A flash memory device includes: a plurality of memory cells, wherein each memory cell receives a write control voltage through a control terminal, and performs a data write operation according to the write control voltage; a plurality of write controls The voltage generators are respectively coupled to the memory units, wherein each of the write control voltage generators comprises: a precharge voltage transmitter coupled to a control terminal of each of the memory units, the precharged pressure transmitters being a precharge driving signal provides a precharge voltage to a control terminal of the corresponding memory unit in a first time period; and a boost capacitor coupled to the control terminal of each memory unit and a push voltage The push-up voltage is supplied to the boost capacitor in a second time period, and the write control voltage is generated on the control terminals of the memory cells; and a plurality of erase control voltage generators are respectively coupled Connecting the memory cells, wherein each of the erase control voltage generators comprises: a wipe pre-charge transmitter coupled to the erase end of each of the memory cells, the erase pre-charge pass And transmitting a erase precharge voltage to the corresponding erase terminal of the memory cell according to a erase precharge drive signal in a third time period; and erasing the boost capacitor, the erase boost capacitor is coupled to each Between the erased end of the memory cell and a erase push-up voltage, the erase push-up voltage is supplied to the erase boost capacitor in a fourth time period, and is applied to The erased erase voltage is erased.

如申請專利範圍第1項所述之快閃記憶體裝置，其中該預充電壓傳送器包括：一預充寫入開關，耦接在該預充電壓以及對應的該記憶單元的控制端點間，該預充寫入開關並且於該第一時間週期依據該預充驅動信號以導通，以將該預充電壓傳送至該控制端點。 The flash memory device of claim 1, wherein the precharge voltage transmitter comprises: a precharge write switch coupled between the precharge voltage and a corresponding control terminal of the memory unit The precharge write switch is turned on according to the precharge drive signal during the first time period to transmit the precharge voltage to the control terminal.

如申請專利範圍第2項所述之快閃記憶體裝置，其中該預充寫入開關包括：一第一電晶體，具有第一端、第二端以及控制端，其中該第一電晶體的第一端及第二端分別耦接至對應的該記憶單元的控制端點及該預充電壓，並且該第一電晶體的控制端接收該預充驅動信號。 The flash memory device of claim 2, wherein the precharge write switch comprises: a first transistor having a first end, a second end, and a control end, wherein the first transistor The first end and the second end are respectively coupled to the control terminal of the corresponding memory unit and the pre-charge voltage, and the control end of the first transistor receives the pre-charge driving signal.

如申請專利範圍第3項所述之快閃記憶體裝置，其中該預充寫入開關更包括：一第二電晶體，耦接在該第一電晶體耦接對應的該記憶單元的控制端點的路徑間，該第二電晶體具有第一端、第二端以及控制端，其中該第二電晶體的第一端耦接至對應的該記憶單元的控制端點，該第二電晶體的第二端耦接至該第一電晶體的第一端，並且該第二電晶體的控制端接收一控制信號。 The flash memory device of claim 3, wherein the precharge write switch further comprises: a second transistor coupled to the control end of the corresponding memory cell coupled to the first transistor Between the paths of the points, the second transistor has a first end, a second end, and a control end, wherein the first end of the second transistor is coupled to a corresponding control end of the memory unit, the second transistor The second end is coupled to the first end of the first transistor, and the control end of the second transistor receives a control signal.

如申請專利範圍第1項所述之快閃記憶體裝置，其中該預充電壓傳送器包括：一第一預充寫入開關，耦接在一第一預充電壓以及對應的該記憶單元的控制端點間；以及一第二預充寫入開關，耦接在一第二預充電壓以及對應的該記憶單元的控制端點間，其中，該第一預充寫入開關以及該第二預充寫入開關分別受控於一第一預充驅動信號以及一第二預充驅動信號，該第一預充寫入開關傳送該第一預充電壓至對應的該記憶單元的控制端點，或是該第二預充寫入開關傳送該第二預充電壓至該對應的記憶單元的控制端點。 The flash memory device of claim 1, wherein the precharge voltage transmitter comprises: a first precharge write switch coupled to a first precharge voltage and Between the control terminals of the memory unit; and a second pre-charge write switch coupled between a second pre-charge voltage and a corresponding control terminal of the memory unit, wherein the first pre-charge write The input switch and the second pre-charge write switch are respectively controlled by a first pre-charge drive signal and a second pre-charge drive signal, and the first pre-charge write switch transmits the first pre-charge voltage to the corresponding one The control terminal of the memory unit, or the second pre-charge write switch transmits the second pre-charge voltage to the control terminal of the corresponding memory unit.

如申請專利範圍第5項所述之快閃記憶體裝置，其中該第一預充寫入開關包括：一第一電晶體，具有第一端、第二端以及控制端，其中該第一電晶體的第一端及第二端分別耦接至對應的該記憶單元的控制端點及該第一預充電壓，並且該第一電晶體的控制端接收該第一預充驅動信號；以及該第二預充寫入開關包括：一第二電晶體，具有第一端、第二端以及控制端，其中該第二電晶體的第一端及第二端分別耦接至對應的該記憶單元的控制端點及該第二預充電壓，並且該第二電晶體的控制端接收該第二預充驅動信號。 The flash memory device of claim 5, wherein the first pre-charge write switch comprises: a first transistor having a first end, a second end, and a control end, wherein the first electric The first end and the second end of the crystal are respectively coupled to the control terminal of the corresponding memory unit and the first pre-charge voltage, and the control end of the first transistor receives the first pre-charge driving signal; The second pre-filled write switch includes: a second transistor having a first end, a second end, and a control end, wherein the first end and the second end of the second transistor are respectively coupled to the corresponding memory unit The control terminal and the second pre-charge voltage, and the control terminal of the second transistor receives the second pre-charge drive signal.

如申請專利範圍第6項所述之快閃記憶體裝置，其中該第一預充寫入開關更包括：一第三電晶體，耦接在該第一電晶體耦接對應的該記憶單元的控制端點的路徑間，該第三電晶體具有第一端、第二端以及控制端，其中該第三電晶體的第一端耦接至對應的該記憶單元的控制端點，該第三電晶體的第二端耦接至該第一電晶體的第一端，並且該第三電晶體的控制端接收一第一控制信號；以及該第二預充寫入開關更包括一第四電晶體，耦接在該第二電晶體耦接對應的該記憶單元的控制端點的路徑間，該第四電晶體具有第一端、第二端以及控制端，其中該第四電晶體的第一端耦接至對應的該記憶單元的控制端點，該第四電晶體的第二端耦接至該第二電晶體的第一端，該第四電晶體的控制端接收一第二控制信號。 The flash memory device of claim 6, wherein the first pre-charge write switch further comprises: a third transistor coupled to the first transistor coupled to the corresponding memory unit The third transistor has a first end, a second end, and a control end, wherein the first end of the third transistor is coupled to the pair The control terminal of the memory unit, the second end of the third transistor is coupled to the first end of the first transistor, and the control end of the third transistor receives a first control signal; The second pre-charged write switch further includes a fourth transistor coupled between the path of the second transistor coupled to the control terminal of the corresponding memory unit, the fourth transistor having a first end and a second The first end of the fourth transistor is coupled to the control terminal of the corresponding memory unit, and the second end of the fourth transistor is coupled to the first end of the second transistor. The control terminal of the fourth transistor receives a second control signal.

如申請專利範圍第7項所述之快閃記憶體裝置，其中該第二電晶體及該第四電晶體為P型電晶體，該第一電晶體及該第三電晶體為N型電晶體。 The flash memory device of claim 7, wherein the second transistor and the fourth transistor are P-type transistors, and the first transistor and the third transistor are N-type transistors .

如申請專利範圍第1項所述之快閃記憶體裝置，其中各該記憶單元包括：一浮動閘極電晶體。 The flash memory device of claim 1, wherein each of the memory units comprises: a floating gate transistor.

如申請專利範圍第9項所述之快閃記憶體裝置，其中該浮動閘極電晶體的製造藉由：一單一多晶矽互補式金氧半電晶體製程。 The flash memory device of claim 9, wherein the floating gate transistor is fabricated by: a single polysilicon complementary MOS transistor process.

如申請專利範圍第1項所述之快閃記憶體裝置，其中各該記憶單元包括：一介電質儲存電晶體。 The flash memory device of claim 1, wherein each of the memory units comprises: a dielectric storage transistor.

如申請專利範圍第1項所述之快閃記憶體裝置，其中各該記憶單元耦接至一源極線及一位元線，各該記憶單元包括：一儲存電晶體，具有第一端、第二端及控制端，其中該儲存電晶體的第一端耦接該源極線，並且該儲存電晶體的第二端耦接該位元線；一選擇電晶體，耦接在該源極線耦接該儲存電晶體的路徑上，該選擇電晶體具有第一端、第二端及控制端，其中該選擇電晶體之第一端耦接該源極線，該選擇電晶體之第二端耦接該儲存電晶體之第一端，並且該選擇電晶體之控制端接收一選擇信號；一操作電晶體，耦接在該位元線耦接該儲存電晶體的路徑上，該操作電晶體具有第一端、第二端及控制端，其中該操作電晶體之第一端耦接該儲存電晶體之第二端，該操作電晶體之第二端耦接該位元線，並且該操作電晶體的控制端接收一字元線驅動信號；以及一閘極電容，耦接在該寫入控制電壓與該儲存電晶體的控制端之間。 The flash memory device of claim 1, wherein each of the memory units is coupled to a source line and a bit line, each of the memories The unit includes: a storage transistor having a first end, a second end, and a control end, wherein the first end of the storage transistor is coupled to the source line, and the second end of the storage transistor is coupled to the bit a selection transistor, coupled to the path of the source line coupled to the storage transistor, the selection transistor having a first end, a second end, and a control end, wherein the first end of the selection transistor is coupled Connected to the source line, the second end of the selection transistor is coupled to the first end of the storage transistor, and the control end of the selection transistor receives a selection signal; an operation transistor coupled to the bit line The operating transistor has a first end, a second end, and a control end, wherein the first end of the operating transistor is coupled to the second end of the storage transistor, and the operating transistor is coupled to the storage transistor. The second end is coupled to the bit line, and the control end of the operating transistor receives a word line driving signal; and a gate capacitor coupled to the write control voltage and the control end of the storage transistor between.

如申請專利範圍第12項所述之快閃記憶體裝置，其中該儲存電晶體為一浮閘電晶體。 The flash memory device of claim 12, wherein the storage transistor is a floating gate transistor.

如申請專利範圍第1項所述之快閃記憶體裝置，其中該抹除預充電壓傳送器包括：一抹除預充開關，耦接在該抹除預充電壓以及對應的該記憶單元的抹除端點間，該抹除預充開關依據該抹除預充驅動信號導通以傳送該抹除預充電壓至該抹除端點。 The flash memory device of claim 1, wherein the erase pre-charge transmitter comprises: a wipe-off pre-charge switch coupled to the erase pre-charge voltage and the corresponding wipe of the memory unit In addition to the end points, the erase precharge switch is turned on according to the erase precharge drive signal to transfer the erase precharge voltage to the erase end point.

如申請專利範圍第14項所述之快閃記憶體裝置，其中該抹除預充開關包括：一第一電晶體，具有第一端、第二端以及控制端，其中該第一電晶體的第一端及第二端分別耦接對應的該記憶單元的抹除端點及該抹除預充電壓，並且該第一電晶體的控制端接收該抹除預充驅動信號。 The flash memory device of claim 14, wherein the erase precharge switch comprises: a first transistor having a first end, a second end, and a control end, wherein the first end and the second end of the first transistor are respectively coupled to the corresponding erase end of the memory unit and the erase pre- The charging voltage is applied, and the control terminal of the first transistor receives the erase precharge driving signal.

如申請專利範圍第15項所述之快閃記憶體裝置，其中該抹除預充開關更包括：一第二電晶體，耦接在該第一電晶體耦接對應的該記憶單元的抹除端點的路徑間，該第二電晶體具有第一端、第二端以及控制端，其中該第二電晶體的第一端耦接至對應的該記憶單元的抹除端點，該第二電晶體的第二端耦接至該第一電晶體的第一端，該第二電晶體的控制端接收一控制信號。 The flash memory device of claim 15, wherein the erase precharge switch further comprises: a second transistor coupled to the corresponding eraser of the memory unit coupled to the first transistor Between the paths of the end points, the second transistor has a first end, a second end, and a control end, wherein the first end of the second transistor is coupled to the corresponding erase end of the memory unit, the second The second end of the transistor is coupled to the first end of the first transistor, and the control end of the second transistor receives a control signal.

如申請專利範圍第1項所述之快閃記憶體裝置，其中該抹除預充電壓傳送器包括：一第一抹除預充開關，耦接在一第一抹除預充電壓以及對應的該記憶單元的抹除端點間；以及一第二抹除預充開關，耦接在一第二抹除預充電壓以及對應的該記憶單元的抹除端點間，其中，該第一抹除預充開關以及該第二抹除預充開關分別受控於該預充驅動信號的一第一抹除預充驅動信號以及一第二抹除預充驅動信號，並且傳送該第一抹除預充電壓或該第二抹除預充電壓至對應的該記憶單元的抹除端點。 The flash memory device of claim 1, wherein the erase pre-charge transmitter comprises: a first erase precharge switch coupled to a first erase precharge voltage and corresponding Between the erased end points of the memory unit; and a second erase precharge switch coupled between a second erase precharge voltage and a corresponding erase end of the memory unit, wherein the first wipe The first erase erase switch and the second erase precharge switch are respectively controlled by a first erase precharge drive signal and a second erase precharge drive signal of the precharge drive signal, and transmit the first erase The precharge voltage or the second erase precharge is pressed to the corresponding erase end of the memory cell.

如申請專利範圍第17項所述之快閃記憶體裝置，其中該第一抹除預充開關包括：一第一電晶體，具有第一端、第二端以及控制端，其中該第一電晶體的第一端及第二端分別耦接至對應的該記憶單元的抹除端點及該第一抹除預充電壓，並且該第一電晶體的控制端接收該第一抹除預充驅動信號；以及該第二抹除預充開關包括：一第二電晶體，具有第一端、第二端以及控制端，其中該第二電晶體的第一端及第二端分別耦接至對應的該記憶單元的抹除端點及該第二抹除預充電壓，並且該第二電晶體的控制端接收該第二抹除預充驅動信號。 The flash memory device of claim 17, wherein the first erase precharge switch comprises: a first transistor having a first end, a second end, and a control end, wherein the first end and the second end of the first transistor are respectively coupled to the corresponding erase end of the memory unit and the first Erasing the precharge voltage, and the control end of the first transistor receives the first erase precharge drive signal; and the second erase precharge switch includes: a second transistor having a first end, a second The first end and the second end of the second transistor are respectively coupled to the corresponding erase end of the memory unit and the second erase precharge voltage, and the second transistor is The control terminal receives the second erase precharge drive signal.

如申請專利範圍第18項所述之快閃記憶體裝置，其中該第一預充寫入開關更包括：一第三電晶體，耦接在該第一電晶體耦接對應的該記憶單元的抹除端點的路徑間，該第三電晶體具有第一端、第二端以及控制端，其中該第三電晶體的第一端耦接至對應的該記憶單元的抹除端點，該第三電晶體的第二端耦接至該第一電晶體的第一端，該第三電晶體的控制端接收一第一抹除控制信號；以及該第二抹除預充開關更包括一第四電晶體，耦接在該第二電晶體耦接對應的該記憶單元的抹除端點的路徑間，該第四電晶體具有第一端、第二端以及控制端，其中該第四電晶體的第一端耦接至對應的該記憶單元的抹除端點，該第四電晶體的第二端耦接至該第二電晶體的第一端，並且該第四電晶體的控制端接收一第二抹除控制信號。 The flash memory device of claim 18, wherein the first pre-charge write switch further comprises: a third transistor coupled to the first transistor coupled to the corresponding memory unit Between the paths of the erased end, the third transistor has a first end, a second end, and a control end, wherein the first end of the third transistor is coupled to the corresponding erase end of the memory unit, The second end of the third transistor is coupled to the first end of the first transistor, the control end of the third transistor receives a first erase control signal; and the second erase precharge switch further includes a a fourth transistor coupled between the path of the second transistor coupled to the erase end of the memory unit, the fourth transistor having a first end, a second end, and a control end, wherein the fourth The first end of the transistor is coupled to the corresponding erase end of the memory unit, the second end of the fourth transistor is coupled to the first end of the second transistor, and the fourth transistor is controlled The terminal receives a second erase control signal.

如申請專利範圍第19項所述之快閃記憶體裝置，其中該第二電晶體及該第四電晶體為P型電晶體，該第一電晶體及該第三電晶體為N型電晶體。 The flash memory device of claim 19, wherein the second transistor and the fourth transistor are P-type transistors, and the first transistor and the third transistor are N-type transistors .