TWI484546B - Flip-chip bonding process for compensating die thickness - Google Patents
Flip-chip bonding process for compensating die thickness Download PDFInfo
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本發明係有關於覆晶接合，特別係有關於一種補償晶粒厚度之覆晶接合製程，除了可以運用於傳統覆晶接合封裝製程，特別可整合於扇出型晶圓級封裝製程或是TSV(矽穿孔)晶粒之3D堆疊封裝製程。The present invention relates to flip chip bonding, and in particular to a flip chip bonding process for compensating for grain thickness, which can be applied to a conventional flip chip bonding process, in particular to a fan-out wafer level packaging process or TSV. (矽perforated) 3D stacked package process for dies.
覆晶接合(flip-chip bonding)已普遍運用於半導體封裝製程，相對於打線連接方式，乃利用晶粒表面的凸出電極對基板作電性連接，故更符合小型薄化的需求。然而，當晶粒的厚度越來越薄或/與凸出電極的間距越來越小，則封裝良率會越來越低，查其潛在風險在於覆晶接合過程中的晶粒容易隨外力產生翹曲變形，難以既有封裝設備取放處理，進而導致晶粒的損害與凸出電極的焊點斷裂。以IC晶粒為例，在矽晶圓的厚度被薄化到50微米以下時，對於封裝良率會有較為明顯的劣化，故為目前覆晶接合技術亟需克服的挑戰。Flip-chip bonding has been widely used in semiconductor packaging processes. Compared with the wire bonding method, the bump electrodes on the surface of the die are electrically connected to the substrate, which is more suitable for the miniaturization. However, as the thickness of the crystal grains becomes thinner or thinner/and the pitch of the protruding electrodes becomes smaller and smaller, the package yield will become lower and lower, and the potential risk is that the crystal grains in the flip-chip bonding process are easy to follow the external force. The warp deformation is generated, and it is difficult to carry out the handling of the packaging device, thereby causing damage to the crystal grains and breakage of the solder joints of the protruding electrodes. Taking the IC die as an example, when the thickness of the germanium wafer is thinned to less than 50 micrometers, the package yield is significantly deteriorated, which is a challenge that the flip chip bonding technology needs to overcome.
我國發明專利證書號數I338028揭示一種「半導體裝置之製造方法及晶圓加工用膠帶」，提供一種晶圓加工用膠帶，具備形成於基板膜上之可移除黏著層及黏合層，該膠帶預先貼於具凸型金屬電極之晶圓電路基板之正面，再進行下列步驟之製程中：研磨晶圓電路基板之背面；在膠帶黏貼於晶圓電路基板之狀態下，切割該晶圓基板成為晶片；在黏合層自基板膜剝離但仍黏合於個別 晶片之狀態下拾取晶片，在覆晶接合後黏合層仍包覆凸型金屬電極。故此一習知晶圓加工用膠帶中黏合層將經歷晶背研磨、晶圓切割與覆晶接合等三個階段，並且不能在其間加熱過程中產生膠固化現象，否則會影響凸型金屬電極的焊接效果，導致此一特殊黏合層的固化與黏著力特性的規範要求甚高，非由一般的填充膠體或封裝材料所能使用，故無法普遍被採用。並且，覆晶接合時接合治具仍必須直接接觸到晶片的背面，無法完全避免對晶片的損傷。The invention patent number No. I338028 discloses a "method for manufacturing a semiconductor device and a tape for wafer processing", and provides a tape for wafer processing, comprising a removable adhesive layer and an adhesive layer formed on a substrate film, the tape being advanced Attached to the front side of the wafer circuit substrate having the convex metal electrode, and then performing the following steps: polishing the back surface of the wafer circuit substrate; cutting the wafer substrate into a wafer while the tape is adhered to the wafer circuit substrate ; peeling from the substrate film in the adhesive layer but still bonding to individual The wafer is picked up in the state of the wafer, and the adhesive layer still coats the convex metal electrode after the flip chip bonding. Therefore, the adhesive layer in the conventional wafer processing tape will undergo three stages of crystal back grinding, wafer cutting and flip chip bonding, and the glue curing phenomenon cannot be generated during the heating process, otherwise the welding effect of the convex metal electrode will be affected. The specification of the curing and adhesion characteristics of this special adhesive layer is very high, and it cannot be generally used because it cannot be used by a general filling colloid or packaging material. Moreover, the bonding jig must still directly contact the back surface of the wafer during flip chip bonding, and damage to the wafer cannot be completely avoided.
為了解決上述之問題，本發明之主要目的係在於一種補償晶粒厚度之覆晶接合製程，能改善習知覆晶接合時晶粒變形與焊點斷裂之問題，並且製程中所使用的多層暫時性晶背支撐結構之任一部份皆完全不會存在最終覆晶接合產品內。In order to solve the above problems, the main object of the present invention is to provide a flip chip bonding process for compensating for crystal grain thickness, which can improve the problem of grain deformation and solder joint breakage during conventional flip chip bonding, and the multilayer used in the process is temporarily Any part of the crystalline back support structure is completely free of the final flip chip bonding product.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種補償晶粒厚度之覆晶接合製程，依序包含以下之步驟：首先，提供一多層暫時性晶背支撐結構(multi-layer temporary die-back supporting lamination,TDSL)，係依序包含一切割載膜、一感壓黏著層(pressure sensitive adhesive)、一晶粒厚度補償層以及一光感黏著層；之後，貼合一晶圓與該多層暫時性晶背支撐結構，該晶圓係具有一正面以及一背面並包含有複數個一體連接之晶粒，該正面係設有複數個凸出電 極，該光感黏著層係黏接該晶圓之該背面；之後，依照該些晶粒之圖案切穿該晶圓與該多層暫時性晶背支撐結構之該光感黏著層與該晶粒厚度補償層，但不切穿該切割載膜與該感壓黏著層，以形成複數個貼附於該切割載膜上之晶粒加厚體，每一晶粒加厚體係包含一晶粒、位在對應晶粒上方之該些凸出電極以及位在對應晶粒下方且被該光感黏著層黏接之該晶粒厚度補償層；之後，拉張該多層暫時性晶背支撐結構之切割載膜並降低該感壓黏著層之黏著力，以取出該些晶粒加厚體；進行非直接接觸晶粒之覆晶接合，利用一接合治具吸附接觸其中一晶粒加厚體之該晶粒厚度補償層並藉以接合該晶粒加厚體之該些凸出電極至一基板；之後，形成一填充膠體於該些晶粒加厚體與該基板之間，以密封該些凸出電極；之後，固化該填充膠體；最後，在固化該填充膠體之後，以照光方式降低該光感黏著層之黏著力，並由該已接合晶粒上剝離該晶粒厚度補償層。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a flip chip bonding process for compensating for grain thickness, which comprises the following steps: Firstly, a multi-layer temporary die-back supporting lamination (TDSL) is provided, which is sequentially The invention comprises a cutting carrier film, a pressure sensitive adhesive layer, a grain thickness compensation layer and a photosensitive adhesive layer; and then bonding a wafer and the multilayer temporary crystal back support structure, the wafer The utility model has a front surface and a back surface and comprises a plurality of integrally connected crystal grains, wherein the front surface is provided with a plurality of protruding electricity The light-sensitive adhesive layer is adhered to the back surface of the wafer; and then the light-sensitive adhesive layer and the crystal grain of the multi-layer temporary crystal back support structure are cut through the wafer according to the pattern of the crystal grains. a thickness compensation layer, but not cutting through the cutting carrier film and the pressure sensitive adhesive layer to form a plurality of grain thickening bodies attached to the cutting carrier film, each grain thickening system comprising a crystal grain, The plurality of protruding electrodes located above the corresponding crystal grains and the grain thickness compensation layer located under the corresponding crystal grains and bonded by the photosensitive adhesive layer; thereafter, the cutting of the multilayer temporary crystal back support structure is stretched Carrying the film and reducing the adhesion of the pressure-sensitive adhesive layer to take out the grain thickening body; performing a flip chip bonding of the indirect contact grain, and adsorbing and contacting one of the grain thickening bodies by using a bonding fixture a grain thickness compensating layer for bonding the protruding electrodes of the grain thickening body to a substrate; thereafter, forming a filling colloid between the grain thickening bodies and the substrate to seal the protrusions Electrode; thereafter, curing the filling gel; finally, curing the filling gel Thereafter, in a manner to reduce the adhesion of the illumination of the light-sensitive adhesive layer, the release of the engagement by the die has a thickness compensation layer on the die.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述之覆晶接合製程中，該晶圓之厚度係可不超過50微米，以適用於超薄型晶粒之覆晶接合製程。In the above flip chip bonding process, the thickness of the wafer may not exceed 50 micrometers, which is suitable for the flip chip bonding process of ultra-thin crystal grains.
在前述之覆晶接合製程中，該晶粒厚度補償層與該光感黏著層係較佳地可取自於一切割膠帶，以該感壓黏著層黏接該切割膠帶與該切割載膜，故在製造時可利用兩種不同黏著層切割膠帶壓貼以快速形成該多層暫時性晶 背支撐結構。In the above-mentioned flip chip bonding process, the die thickness compensation layer and the photo-adhesive layer are preferably taken from a dicing tape, and the viscous adhesive layer is adhered to the dicing tape and the cutting carrier film. Therefore, two different adhesive layer cutting tapes can be pressed at the time of manufacture to rapidly form the multilayer temporary crystal. Back support structure.
在前述之覆晶接合製程中，提供該多層暫時性晶背支撐結構之步驟中，該多層暫時性晶背支撐結構係可更包含一離形膜(release liner)，其係貼附於該光感黏著層，以保護與維持該光感黏著層之黏性。In the above-described flip chip bonding process, in the step of providing the multi-layer temporary crystal back support structure, the multi-layer temporary crystal back support structure may further comprise a release liner attached to the light Adhesive layer to protect and maintain the adhesion of the photosensitive adhesive layer.
在前述之覆晶接合製程中，該晶粒厚度補償層係或者可為一空白晶圓或一玻璃片，可供照光該光感黏著層之光線通過並有效維持被取出晶粒加厚體之硬度。In the foregoing flip chip bonding process, the grain thickness compensation layer may be a blank wafer or a glass sheet, which can pass the light of the photosensitive adhesive layer and effectively maintain the removed grain thickening body. hardness.
在前述之覆晶接合製程中，該些凸出電極係可為銅柱與銲料之組合，以符合微間距端子與低成本的覆晶接合要求。In the foregoing flip chip bonding process, the bump electrodes may be a combination of copper pillars and solder to meet the requirements of micro pitch terminals and low cost flip chip bonding.
在前述之覆晶接合製程中，該基板係可為一具有扇出重配置線路層之虛晶圓，使得該覆晶接合製程可整合於扇出型晶圓級封裝製程(fan-out wafer level packaging)並具有縮小其封裝厚度以設置更微小化外部端子之功效。In the above flip chip bonding process, the substrate can be a dummy wafer having a fan-out reconfiguration wiring layer, so that the flip chip bonding process can be integrated into a fan-out wafer level process (fan-out wafer level). Packaging) and has the effect of reducing the thickness of its package to set a more miniaturized external terminal.
在前述之覆晶接合製程中，可另包含之步驟有：設置複數個外部端子於該基板之該扇出重配置線路層之複數個扇出墊。In the foregoing flip chip bonding process, the method further includes the steps of: providing a plurality of external terminals on the plurality of fan-out pads of the fan-out reconfiguration circuit layer of the substrate.
在前述之覆晶接合製程中，每一晶粒係可具有複數個連接至該些凸出電極之矽穿孔，而該基板係為另一具有矽穿孔之晶粒，使得該覆晶接合製程可整合於TSV(矽穿孔)晶粒之3D堆疊封裝製程，在同一堆疊體(3D cube)中可堆疊更多的TSV晶粒。In the above flip chip bonding process, each of the die lines may have a plurality of turns of perforations connected to the bump electrodes, and the substrate is another die having perforated holes, so that the flip chip bonding process can be A 3D stacked package process integrated into TSV (矽perforated) dies, more TSV dies can be stacked in the same stack (3D cube).
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之第一較佳實施例，一種補償晶粒厚度之覆晶接合製程舉例說明於第1圖之流程示意圖以及第2A至2H圖之各步驟中之元件截面示意圖。本覆晶接合製程主要包含：「提供多層暫時性晶背支撐結構」之步驟1、「貼合晶圓至多層暫時性晶背支撐結構」之步驟2、「切割以形成包含晶粒厚度補償層之晶粒加厚體」之步驟3、「取出晶粒加厚體」之步驟4、「非直接接觸晶粒之覆晶接合」之步驟5、「形成填充膠體」之步驟6、「固化填充膠體」之步驟7、以及「剝離已接合晶粒上之晶粒厚度補償層」之步驟8。而「設置外部端子於基板上」之步驟9係可選置性執行在步驟8之後。According to a first preferred embodiment of the present invention, a flip chip bonding process for compensating for a crystal grain thickness is illustrated in the flow diagram of FIG. 1 and the cross-sectional views of the elements in the steps of FIGS. 2A to 2H. The flip chip bonding process mainly includes the steps of “providing a multi-layer temporary crystal back support structure”, “stepping the wafer to the multilayer temporary crystal back support structure”, and “cutting to form a grain thickness compensation layer. Step 3 of the "grain thickening body", step 4 of "removing the grain thickening body", step 5 of "in-contact bonding of the indirect contact crystal grains", step 6 of "forming the filling colloid", "curing filling" Step 7 of the "colloid" and step 8 of "stripping the grain thickness compensation layer on the bonded die". The step 9 of "setting the external terminal on the substrate" is optional after step 8.
首先，步驟1所表示元件可如第2A圖所示，提供一多層暫時性晶背支撐結構110(multi-layer temporary die-back supporting lamination,TDSL)，係依序包含一切割載膜111、一感壓黏著層112(pressure sensitive adhesive)、一晶粒厚度補償層113以及一光感黏著層114，換言之，該感壓黏著層112形成於該切割載膜111與該晶粒厚度補償層113之間，該光感黏著層114係形成於該晶粒厚度補償層113上。該感壓黏著層112作為第一階段分離之暫時黏著劑，在壓合壓力下即可產生黏性，於拉張擴張薄膜或是/以及昇降溫條件下可降低其黏著力；該光感黏著層114則作為第二階段分離之暫時黏著劑，除了以照射可產生固化反應之特定波長光線方式能降低其黏著力之外，其黏著力並不會隨著溫度高低或拉張擴張薄膜而降低，故該光感黏著層114可經歷覆晶接合過程中的熱壓合、膠固化等加熱環境後仍保有適當之黏著力。其中，在提供該多層暫時性晶背支撐結構110之步驟中，該多層暫時性晶背支撐結構110係可更包含一離形膜115(release liner)，其係貼附於該光感黏著層114，以保護與維持該光感黏著層114之黏性。該多層暫時性晶背支撐結構110係應為可拉張之膠帶狀，而能沿用既有的晶圓處理治具。較佳地，該晶粒厚度補償層113與該光感黏著層114係較佳地可取自於一切割膠帶，可藉由該感壓黏著層112黏接該切割膠帶與該切割載膜111，故在製造時可利用兩種不同黏著層之切割膠帶相互壓合以快速形成該多層暫時性晶背支撐結構110。或者，在一變化實施例中，該晶粒厚度補償層113係可為一空白晶圓120或一玻璃片，可供後續製程中照射該光感黏著層114之光線通過並有效維持被取出晶粒加厚體之硬 度。First, the component shown in step 1 can provide a multi-layer temporary die-back supporting lamination (110), which includes a cutting carrier film 111, as shown in FIG. 2A. a pressure sensitive layer 112 (pressure sensitive Adhesively, a grain thickness compensation layer 113 and a photosensitive adhesive layer 114, in other words, the pressure-sensitive adhesive layer 112 is formed between the cutting carrier film 111 and the grain thickness compensation layer 113, the photosensitive adhesive layer 114 It is formed on the crystal grain thickness compensation layer 113. The pressure-sensitive adhesive layer 112 serves as a temporary adhesive for separating in the first stage, and can be viscous under the pressure of the pressing, and can reduce the adhesion under the condition of stretching and expanding the film or under the temperature of lifting and lowering; The layer 114 acts as a temporary adhesive for the second stage separation, and the adhesion is not lowered with the temperature or the stretched film, except that the specific wavelength of the light which can generate the curing reaction can reduce the adhesion. Therefore, the photo-adhesive layer 114 can undergo proper adhesion after heating, such as thermocompression bonding and gel curing in the flip-chip bonding process. In the step of providing the multi-layer temporary back support structure 110, the multi-layer temporary back support structure 110 may further comprise a release liner 115 attached to the photo-adhesive layer. 114, to protect and maintain the adhesion of the photosensitive adhesive layer 114. The multi-layer temporary crystal back support structure 110 should be in the form of a stretchable tape, and can be used with existing wafer processing fixtures. Preferably, the die thickness compensation layer 113 and the photo-adhesive layer 114 are preferably taken from a dicing tape, and the dicing tape and the dicing film 111 are adhered by the pressure-sensitive adhesive layer 112. Therefore, the dicing tape of two different adhesive layers can be pressed together with each other at the time of manufacture to rapidly form the multilayer temporary crystal back support structure 110. Alternatively, in a variant embodiment, the die thickness compensation layer 113 can be a blank wafer 120 or a glass plate, which can pass the light that illuminates the photosensitive adhesive layer 114 in a subsequent process and effectively maintain the extracted crystal. Hard grain thickening degree.
之後，步驟2所表示元件可如第2B圖所示，貼合一晶圓120與該多層暫時性晶背支撐結構110。配合參閱第3圖，該晶圓120係具有一正面121以及一背面122並包含有複數個一體連接之晶粒123，該正面121係設有複數個凸出電極124，其係連接至對應晶粒123之內部積體電路。該光感黏著層114係黏接該晶圓120之該背面122。在本具體實施例中，該晶圓120之厚度係可不超過50微米，以適用於超薄型晶粒123之覆晶接合製程。該晶圓120可預先經過晶背研磨製程而為薄化型態，或者該晶圓120本身亦可為薄膜易翹曲之型態。在本實施例中，該些凸出電極124係可為銅柱124A與銲料124B之組合，以符合微間距端子與低成本的覆晶接合要求。Thereafter, the component shown in step 2 can be bonded to a wafer 120 and the multilayer temporary crystal back support structure 110 as shown in FIG. 2B. Referring to FIG. 3, the wafer 120 has a front surface 121 and a back surface 122 and includes a plurality of integrally connected crystal grains 123. The front surface 121 is provided with a plurality of protruding electrodes 124 connected to corresponding crystals. The internal integrated circuit of the pellet 123. The light-sensitive adhesive layer 114 is adhered to the back surface 122 of the wafer 120. In this embodiment, the thickness of the wafer 120 may not exceed 50 micrometers to be suitable for the flip chip bonding process of the ultra-thin die 123. The wafer 120 may be thinned before being subjected to a crystal back grinding process, or the wafer 120 itself may be in a form in which the film is warped. In this embodiment, the protruding electrodes 124 can be a combination of the copper pillars 124A and the solders 124B to meet the requirements of the micro pitch terminals and the low cost flip chip bonding.
之後，步驟3所表示元件可如第2C圖所示，利用一晶圓切割刀具210，依照該些晶粒123之圖案(配合參閱第3圖在該晶圓120中晶粒123之配置位置)，切穿該晶圓120與該多層暫時性晶背支撐結構110之該光感黏著層114與該晶粒厚度補償層113，但不切穿該切割載膜111與該感壓黏著層112，以形成複數個貼附於該切割載膜111上之晶粒加厚體130，每一晶粒加厚體130係包含一晶粒123、位在對應晶粒123上方之該些凸出電極124以及位在對應晶粒123下方且被該光感黏著層114黏接之該晶粒厚度補償層113。在本步驟中，該晶粒厚 度補償層113之表面尺寸係不小於對應晶粒123之背面尺寸，以完全覆蓋該晶粒123之背面。另外，依照該晶粒厚度補償層113之材質特性不同，該晶粒厚度補償層113之厚度可大於該晶粒123被磨除厚度之百分三十。而該切割載膜111與該感壓黏著層112仍保持在整片膠膜狀，未切穿成該些晶粒加厚體130之一部份。Thereafter, the component shown in step 3 can be formed by a wafer cutting tool 210 according to the pattern of the die 123 according to FIG. 2C (refer to the arrangement position of the die 123 in the wafer 120 in FIG. 3). Cutting through the wafer 120 and the photo-adhesive layer 114 of the multi-layer temporary crystal back support structure 110 and the grain thickness compensation layer 113, but not cutting through the cutting carrier film 111 and the pressure-sensitive adhesive layer 112, A plurality of grain thickening bodies 130 attached to the cutting carrier film 111 are formed, and each of the crystal grain thickening bodies 130 includes a plurality of crystal grains 123 and the protruding electrodes 124 located above the corresponding crystal grains 123. And the crystal grain thickness compensation layer 113 located under the corresponding crystal grain 123 and bonded by the photo-sensitive adhesive layer 114. In this step, the grain thickness is The surface compensation layer 113 has a surface dimension not less than the back surface dimension of the corresponding die 123 to completely cover the back surface of the die 123. In addition, according to the material properties of the grain thickness compensation layer 113, the thickness of the grain thickness compensation layer 113 may be greater than 30% of the thickness of the grain 123 being removed. The cutting carrier film 111 and the pressure-sensitive adhesive layer 112 are still in the form of a whole film, and are not cut into a part of the grain thickening body 130.
之後，步驟4所表示元件可如第2D圖所示，拉張該多層暫時性晶背支撐結構110之切割載膜111並降低該感壓黏著層112之黏著力，以取出該些晶粒加厚體130。當拉張該切割載膜111時，因該感壓黏著層112為未切穿型態一體連接於該切割載膜111，該感壓黏著層112的內應力減少而能降低其黏著力；或者，可改變步驟4的操作溫度使其上昇或下降以降低該感壓黏著層112之黏著力。在本實施例中，取出該些晶粒加厚體130之過程中，可利用一具有多點頂針之頂針機構220頂昇對應位置之切割載膜111，以使欲取出之晶粒加厚體130升高，同時形成更強的膠帶拉張效果，以降低該感壓黏著層112之黏著力並方便吸附取出。Thereafter, the component represented by step 4 can stretch the cutting carrier film 111 of the multilayer temporary crystal back support structure 110 and reduce the adhesion of the pressure sensitive adhesive layer 112 as shown in FIG. 2D to take out the crystal grains. Thick body 130. When the cutting carrier film 111 is stretched, the pressure-sensitive adhesive layer 112 is integrally connected to the cutting carrier film 111 in an uncut mode, and the internal stress of the pressure-sensitive adhesive layer 112 is reduced to reduce the adhesion; or The operating temperature of step 4 can be changed to rise or fall to lower the adhesion of the pressure-sensitive adhesive layer 112. In the embodiment, during the process of taking out the grain thickening bodies 130, the thimble mechanism 220 having a multi-point thimble can be used to lift the corresponding cutting film 111 at the corresponding position to make the grain thickening body to be taken out. 130 is raised, and a stronger tape stretching effect is formed at the same time to reduce the adhesion of the pressure-sensitive adhesive layer 112 and facilitate the adsorption and removal.
步驟5為進行非直接接觸晶粒之覆晶接合操作。如第2E圖所示，利用一接合治具230吸附接觸上述被取出之晶粒加厚體130之該晶粒厚度補償層113，可經過翻轉並往一基板140下壓，藉以接合該晶粒加厚體130之該些凸出電極124至該基板140。在本實施例中，該基板140係可為一具有扇出重配置線路層141之虛晶圓120， 使得該覆晶接合製程可整合於扇出型晶圓級封裝製程(fan-out wafer level packaging)並具有縮小其封裝厚度以設置更微小化外部端子之功效。其中，該扇出重配置線路層141係連接複數個墊間距較小的扇入墊143與複數個墊間距較大的扇出墊142，而該些扇入墊143係位於覆晶接合區內(即基板上被晶粒覆蓋的區域)而與對應之凸出電極124接合，該些扇出墊142係位於覆晶接合區之外。Step 5 is a flip chip bonding operation that does not directly contact the die. As shown in FIG. 2E, the die thickness compensation layer 113 which is in contact with the removed crystal grain thickening body 130 by a bonding jig 230 can be inverted and pressed down to a substrate 140 to bond the die. The protruding electrodes 124 of the body 130 are thickened to the substrate 140. In this embodiment, the substrate 140 can be a dummy wafer 120 having a fan-out reconfiguration circuit layer 141. The flip chip bonding process can be integrated into a fan-out wafer level packaging and has the effect of reducing the thickness of the package to set a more miniaturized external terminal. The fan-out reconfiguration circuit layer 141 is connected to a plurality of fan-in pads 143 having a small pad pitch and a plurality of fan-out pads 142 having a large pad pitch, and the fan-in pads 143 are located in the flip-chip bonding region. (i.e., the region of the substrate covered by the die) is bonded to the corresponding bump electrode 124, which is located outside the flip chip bond region.
之後，步驟6、7所表示元件可如第2F圖所示，形成一填充膠體150於該些晶粒加厚體130與該基板140之間，以密封該些凸出電極124。當該填充膠體150係為具有高流動性之底部填充膠時，步驟6為執行在步驟5之後；當該填充膠體150係為非導電膠(NCP)或異方性導電膠(ACP)時，步驟5與步驟6為同時完成，即該填充膠體150預先形成於該基板140上，當「非直接接觸晶粒之覆晶接合」之步驟5中該些晶粒加厚體130覆晶接合至該基板140，同時完成該填充膠體150形成於該些晶粒加厚體130與該基板140之間。之後，可利用加熱烘烤方式固化該填充膠體150，使得該填充膠體150為成份穩定且不再流動，進而穩固地結合該晶粒123與該基板140。Thereafter, the components shown in steps 6 and 7 can be formed between the die-thickened bodies 130 and the substrate 140 as shown in FIG. 2F to seal the bump electrodes 124. When the filling colloid 150 is an underfill having high fluidity, step 6 is performed after step 5; when the filling colloid 150 is a non-conductive paste (NCP) or an anisotropic conductive paste (ACP), Step 5 and step 6 are completed simultaneously, that is, the filling colloid 150 is formed on the substrate 140 in advance, and the grain thickening body 130 is flip-chip bonded to the substrate 5 in the step 5 of "indirectly contacting the die-bonding of the crystal grains" to The filling layer 150 is formed between the grain thickening body 130 and the substrate 140 at the same time. Thereafter, the filling gel 150 can be cured by a heat baking method, so that the filling gel 150 is stable in composition and no longer flows, thereby firmly bonding the die 123 and the substrate 140.
最後，步驟8所表示元件可如第2G圖所示，在固化該填充膠體150之後，藉由一照光裝置240以照光方式降低該光感黏著層114之黏著力，並由該已接合晶粒123 之上方剝離該晶粒厚度補償層113。如第2H圖所示，已接合晶粒123之上方晶粒厚度補償層113已被移除。在本實施例中，該光感黏著層114係為UV可固化性，而該照光裝置240發出之光線係為紫外光(UV light)。Finally, the component shown in step 8 can be as shown in FIG. 2G. After curing the filling gel 150, the adhesion of the photo-adhesive layer 114 is reduced by an illumination device 240, and the bonded die is removed. 123 The grain thickness compensation layer 113 is peeled off above. As shown in FIG. 2H, the upper crystal grain thickness compensation layer 113 of the bonded die 123 has been removed. In this embodiment, the photo-adhesive layer 114 is UV curable, and the light emitted by the illumination device 240 is UV light.
因此，本發明之一種補償晶粒厚度之覆晶接合製程能改善習知覆晶接合時晶粒變形與焊點斷裂之問題，並且製程中所使用的多層暫時性晶背支撐結構之任一部份皆完全不會存在最終覆晶接合產品內。Therefore, the flip chip bonding process for compensating for the grain thickness of the present invention can improve the problem of grain deformation and solder joint breakage during conventional flip chip bonding, and any part of the multilayer temporary crystal back support structure used in the process. The parts are completely free of the final flip chip bonding product.
再如第2H圖所示，前述之覆晶接合製程可另包含步驟9，設置複數個外部端子170於該基板140之該扇出重配置線路層141之該些扇出墊142。該些外部端子170係可包含複數個銲球，即使選用較小直徑的銲球，該些外部端子170之高度仍可極輕易地超於覆晶接合高度(即超過已接合晶粒之背面)，以便於對外接合。As shown in FIG. 2H, the flip chip bonding process may further include a step of providing a plurality of external terminals 170 on the fan-out pads 142 of the fan-out reconfiguration circuit layer 141 of the substrate 140. The external terminals 170 may comprise a plurality of solder balls. Even if a smaller diameter solder ball is selected, the height of the external terminals 170 can be extremely easily exceeded by the flip chip bonding height (ie, beyond the back surface of the bonded die). In order to facilitate external engagement.
依據本發明之第二較佳實施例，另一種補償晶粒厚度之覆晶接合製程大致與第一較佳實施例相同，重複步驟不再贅述。如第4圖所示，而本覆晶接合製程中，每一晶粒123係可具有複數個連接至該些凸出電極124之矽穿孔125，並構成於一包含有晶粒厚度補償層113並以光感黏著層114黏接之晶粒加厚體130，進行非直接接觸晶粒之覆晶接合(即步驟5)時，利用一接合治具230吸附接觸該晶粒加厚體130之該晶粒厚度補償層113並藉以接合該晶粒加厚體130之該些凸出電極124至一基板。在非直接接觸晶粒之覆晶接合步驟中，下方供覆晶 接合之基板係可為另一具有矽穿孔125之晶粒123，以凸出電極124電性導通上下堆疊晶粒123之矽穿孔125，該些凸出電極124係位於晶粒堆疊間隙，其內預先填充一填充膠體150並予以固化之。因此，該覆晶接合製程係可整合於TSV(矽穿孔)晶粒之3D堆疊封裝製程，在同一堆疊體(3D cube)中可堆疊更多的TSV晶粒。在本實施例中，堆疊晶粒123的晶片厚度可小於或接近晶粒堆疊間隙，使得更多數量的晶粒123可接合在一基板160上。According to the second preferred embodiment of the present invention, another flip chip bonding process for compensating for the grain thickness is substantially the same as that of the first preferred embodiment, and the repeated steps are not described again. As shown in FIG. 4, in the flip chip bonding process, each of the crystal grains 123 may have a plurality of germanium vias 125 connected to the bump electrodes 124, and is formed in a grain thickness compensation layer 113. And the die-bonding layer 130 bonded by the photosensitive adhesive layer 114 is subjected to flip chip bonding (ie, step 5) of indirect contact with the die, and the bonding die 230 is used to adsorb and contact the grain thickening body 130. The grain thickness compensation layer 113 is used to bond the protruding electrodes 124 of the grain thickening body 130 to a substrate. In the flip chip bonding step of indirect contact with the die, the underlying capping crystal The bonded substrate may be another die 123 having a meandering via 125, and the protruding electrode 124 electrically conducts the via holes 125 of the upper and lower stacked die 123, and the protruding electrodes 124 are located in the die stack gap. A filling gel 150 is pre-filled and cured. Therefore, the flip chip bonding process can be integrated into a 3D stacked package process of TSV (germanium perforated) grains, and more TSV grains can be stacked in the same stack (3D cube). In this embodiment, the wafer thickness of the stacked die 123 can be less than or close to the die stack gap such that a greater number of die 123 can be bonded to a substrate 160.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
1‧‧‧提供多層暫時性晶背支撐結構1‧‧‧Provide multi-layer temporary crystal back support structure
2‧‧‧貼合晶圓與多層暫時性晶背支撐結構2‧‧‧Finished wafer and multilayer temporary crystal back support structure
3‧‧‧切割以形成包含晶粒厚度補償層之晶粒加厚體3‧‧‧Cutting to form a grain thickening body comprising a grain thickness compensation layer
4‧‧‧取出晶粒加厚體4‧‧‧Remove the grain thickening body
5‧‧‧非直接接觸晶粒之覆晶接合5‧‧‧Face-chip bonding without direct contact with grains
6‧‧‧形成填充膠體6‧‧‧ forming a filling gel
7‧‧‧固化填充膠體7‧‧‧Cure filled colloid
8‧‧‧剝離已接合晶粒上之晶粒厚度補償層8‧‧‧ Stripping the grain thickness compensation layer on the bonded die
9‧‧‧設置外部端子於基板上9‧‧‧Set external terminals on the substrate
110‧‧‧多層暫時性晶背支撐結構110‧‧‧Multilayer temporary crystal back support structure
111‧‧‧切割載膜111‧‧‧ cutting carrier film
112‧‧‧感壓黏著層112‧‧‧ Pressure-sensitive adhesive layer
113‧‧‧晶粒厚度補償層113‧‧‧ grain thickness compensation layer
114‧‧‧光感黏著層114‧‧‧Light adhesive layer
115‧‧‧離形膜115‧‧‧Fractal film
120‧‧‧晶圓120‧‧‧ wafer
121‧‧‧正面121‧‧‧ positive
122‧‧‧背面122‧‧‧Back
123‧‧‧晶粒123‧‧‧ grain
124‧‧‧凸出電極124‧‧‧ protruding electrode
124A‧‧‧銅柱124A‧‧‧Bronze Column
124B‧‧‧銲料124B‧‧‧ solder
125‧‧‧矽穿孔125‧‧‧矽 piercing
130‧‧‧晶粒加厚體130‧‧‧ grain thickening
140‧‧‧基板140‧‧‧Substrate
141‧‧‧扇出重配置線路層141‧‧‧Fan out reconfiguration line layer
142‧‧‧扇出墊142‧‧‧Fan mat
143‧‧‧扇入墊143‧‧‧Fan
150‧‧‧填充膠體150‧‧‧filled colloid
160‧‧‧基板160‧‧‧Substrate
170‧‧‧外部端子170‧‧‧External terminals
210‧‧‧晶圓切割刀具210‧‧‧ Wafer Cutting Tools
220‧‧‧頂針機構220‧‧‧ thimble mechanism
230‧‧‧接合治具230‧‧‧Jigs
240‧‧‧照光裝置240‧‧‧Lighting device
第1圖：依據本發明之第一較佳具體實施例，繪示一種補償晶粒厚度之覆晶接合製程之流程示意圖。1 is a schematic flow chart showing a flip chip bonding process for compensating for a crystal grain thickness according to a first preferred embodiment of the present invention.
第2A至2H圖：依據本發明之第一較佳具體實施例，該覆晶接合製程在各步驟中之元件截面示意圖。2A to 2H are schematic cross-sectional views showing the elements of the flip chip bonding process in each step in accordance with a first preferred embodiment of the present invention.
第3圖：依據本發明之第一較佳具體實施例，所提供之晶圓之正面示意圖。Figure 3 is a front elevational view of a wafer provided in accordance with a first preferred embodiment of the present invention.
第4圖：依據本發明之第二較佳具體實施例，繪示另一種補償晶粒厚度之覆晶接合製程在其非直接接 觸晶粒之覆晶接合步驟中之元件截面示意圖。Figure 4: According to a second preferred embodiment of the present invention, another flip chip bonding process for compensating for grain thickness is shown indirectly A schematic cross-sectional view of the element in the flip chip bonding step of the touch crystal.
111‧‧‧切割載膜111‧‧‧ cutting carrier film
112‧‧‧感壓黏著層112‧‧‧ Pressure-sensitive adhesive layer
113‧‧‧晶粒厚度補償層113‧‧‧ grain thickness compensation layer
114‧‧‧光感黏著層114‧‧‧Light adhesive layer
123‧‧‧晶粒123‧‧‧ grain
124‧‧‧凸出電極124‧‧‧ protruding electrode
130‧‧‧晶粒加厚體130‧‧‧ grain thickening
210‧‧‧晶圓切割刀具210‧‧‧ Wafer Cutting Tools
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101143020A TWI484546B (en) | 2012-11-19 | 2012-11-19 | Flip-chip bonding process for compensating die thickness |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101143020A TWI484546B (en) | 2012-11-19 | 2012-11-19 | Flip-chip bonding process for compensating die thickness |
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| Publication Number | Publication Date |
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| TW201421555A TW201421555A (en) | 2014-06-01 |
| TWI484546B true TWI484546B (en) | 2015-05-11 |
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| TW101143020A TWI484546B (en) | 2012-11-19 | 2012-11-19 | Flip-chip bonding process for compensating die thickness |
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| KR101800367B1 (en) * | 2016-08-24 | 2017-11-28 | 한국기계연구원 | Method of transferring a micro-device and Micro-device substrate manufactured by the same |
| TWI833447B (en) * | 2022-11-15 | 2024-02-21 | 英業達股份有限公司 | A pressing device for improving the shaking of a foot pad and a method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070158024A1 (en) * | 2006-01-11 | 2007-07-12 | Symbol Technologies, Inc. | Methods and systems for removing multiple die(s) from a surface |
| US20110156279A1 (en) * | 2009-12-24 | 2011-06-30 | Nitto Denko Corporation | Film for flip chip type semiconductor back surface |
| JP2011171711A (en) * | 2010-01-21 | 2011-09-01 | Hitachi Chem Co Ltd | Adhesive film for semiconductor wafer processing |
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2012
- 2012-11-19 TW TW101143020A patent/TWI484546B/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070158024A1 (en) * | 2006-01-11 | 2007-07-12 | Symbol Technologies, Inc. | Methods and systems for removing multiple die(s) from a surface |
| US20110156279A1 (en) * | 2009-12-24 | 2011-06-30 | Nitto Denko Corporation | Film for flip chip type semiconductor back surface |
| JP2011171711A (en) * | 2010-01-21 | 2011-09-01 | Hitachi Chem Co Ltd | Adhesive film for semiconductor wafer processing |
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| TW201421555A (en) | 2014-06-01 |
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