TWI482277B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI482277B
TWI482277B TW102116155A TW102116155A TWI482277B TW I482277 B TWI482277 B TW I482277B TW 102116155 A TW102116155 A TW 102116155A TW 102116155 A TW102116155 A TW 102116155A TW I482277 B TWI482277 B TW I482277B
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region
semiconductor device
potential
floating electrode
layer
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TW102116155A
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TW201413946A (zh
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Hajime Akiyama
Akira Okada
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Mitsubishi Electric Corp
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Description

半導體裝置
本發明是關於半導體裝置，特別是關於電力用的半導體裝置。
電力用的半導體裝置的一種，有縱型的半導體裝置。在縱型的半導體裝置，是在正面側與背面側之間，進行電流的導通(打開狀態)與遮斷(關閉狀態)。在半導體基板的正面側，形成有配置著IGBT(Insulated Gate Bipolar Transistor；絕緣閘雙極性電晶體)等的開關元件等的區域。此區域是在導通時主電流流動的區域，稱為主動區。
半導體裝置是有高耐壓需求的電力裝置時，在半導體基板的正面側，形成有其主動區、以及以主動區為中心區將其包圍的終端構造部。終端構造部為了保持半導體裝置的耐壓特性，而為包含耐壓層的構造。具有保護環區的保護環構造、或是具有低表面電場(reduced surface field；RESURF)層的低表面電場構造等，適用作為這樣的終端構造部。
在半導體裝置中，為了保護主動區及終端構造部免受外部的環境破壞，通常會形成絕緣性的保護膜來覆蓋這些主動區及終端構造部。作為保護膜者，是使用例如氧化矽或氮化矽之類的絕緣膜。另外，會使用樹脂類的材料。再者，亦有 情況是形成層狀地形成複數種材料之樣態的保護膜。
在半導體的組裝步驟等中，會有從外部將電荷導入至保護膜之上的情況。在導入電荷之下，會發生局部性的電場集中，而產生電場分佈的偏移。因此，會有使預定的耐壓程度降低而無法確保耐壓特性的問題點。對於此問題點，在專利文獻1(特開2008-103530號公報)中，提出了減低上述之電荷的影響的半導體裝置。
然而，在習知的半導體裝置中，有以下的問題。亦即在半導體裝置中，在終端構造部中，在保護環區與通道停止區之間的區域，形成有絕緣體區域。因此，會有終端構造部的區域擴大的問題。
本發明是為了解決上述問題點而成，其目的為提供一種半導體裝置，其不會使終端構造部擴大而充分確保耐壓。
本發明相關的半導體裝置，具有第一導電型的半導體基板、元件形成區、電場緩和區與絕緣性的保護膜。第一導電型的半導體基板，具有相互對向的第一主表面及第二主表面。元件形成區，是形成於半導體基板的第一主表面側中的既定區域，配置有既定的半導體元件以在第一主表面之側與第二主表面之側之間導通電流。電場緩和區，是在半導體基板的第一主表面中之元件形成區的側方，以連接元件形成區的樣態形成。絕緣性的保護膜，是被形成為覆蓋第一主表面側，並具有既定的介電常數。上述電場緩和區具有絕緣區、第一導電型的 通道停止區、複數個浮置電極與第二導電型區域。絕緣區，是從第一主表面延伸至既定深度而形成，其介電常數低於既定的介電常數。第一導電型的通道停止區，是形成在相對於絕緣區之元件形成區所在那一側的相反側，並與絕緣區相隔一距離。複數個浮置電極是以在連結上述元件形成區與上述通道停止區之間的方向，具有結合電容的樣態而配置。第二導電型區域，是從絕緣區延伸至更深的區域而形成。
根據本發明相關的半導體裝置，不會使作為終端構造部的電場緩和區擴大而可以充分地確保耐壓。
本發明的上述及其他目的、特徵、局面以及優點，會根據與所附圖示有關連而被理解之此發明相關的以下詳細說明，而更加明確。
1‧‧‧半導體裝置
2‧‧‧半導體基板
3‧‧‧n-層
4‧‧‧n+緩衝層
5‧‧‧p+集極層
6‧‧‧集極
10‧‧‧主動區
11‧‧‧IGBT
12‧‧‧溝槽
13‧‧‧p基極層
14‧‧‧n+射極層
15‧‧‧閘氧化膜
16‧‧‧閘極埋入電極
17‧‧‧射極
20‧‧‧終端構造部
21‧‧‧p型保護環區
22‧‧‧通道停止區
23‧‧‧低表面電場層
26‧‧‧多孔質氧化膜區
27a‧‧‧浮置電極
27b‧‧‧浮置電極
27c‧‧‧浮置電極
28‧‧‧溝槽
30‧‧‧第一絕緣膜
31‧‧‧第二絕緣膜
41‧‧‧電荷
102‧‧‧半導體基板
103‧‧‧n-層
104‧‧‧n+緩衝層
105‧‧‧p+集極層
106‧‧‧集極
110‧‧‧主動區
112‧‧‧溝槽
113‧‧‧p基極層
114‧‧‧n+射極層
115‧‧‧閘氧化膜
116‧‧‧閘極埋入電極
117‧‧‧射極
120‧‧‧終端構造部
121‧‧‧保護環區
122‧‧‧通道停止區
130‧‧‧第一絕緣膜
131‧‧‧第二絕緣膜
135‧‧‧保護環電極
141‧‧‧附著電荷
A‧‧‧點線框
C‧‧‧結合電容
第1圖是本發明的實施形態1相關的半導體裝置的剖面圖。
第2圖是同實施形態中，用以說明半導體裝置的動作的第一剖面圖。
第3圖是同實施形態中，用以說明半導體裝置的動作的第二剖面圖。
第4圖是比較例相關的半導體裝置的剖面圖。
第5圖是用以說明比較例相關的半導體裝置的問題點之部分剖面圖。
第6圖是同實施形態中，用以說明半導體裝置的作用效果的部分剖面圖。
第7圖是同實施形態中，變形例1相關的半導體裝置的剖面圖。
第8圖是同實施形態中，用以說明變形例1相關的半導體裝置的作用效果的部分剖面圖。
第9圖是同實施形態中，變形例2相關的半導體裝置的剖面圖。
第10圖是同實施形態中，用以說明變形例2相關的半導體裝置的作用效果的部分剖面圖。
第11圖是同實施形態中，變形例3相關的半導體裝置的剖面圖。
第12圖是同實施形態中，用以說明變形例3相關的半導體裝置的作用效果的部分剖面圖。
第13圖是本發明的實施形態2相關的半導體裝置的剖面圖。
第14圖是同實施形態中，用以說明半導體裝置的作用效果的部分剖面圖。
第15圖是同實施形態中，變形例1相關的半導體裝置的剖面圖。
第16圖是同實施形態中，用以說明變形例1相關的半導體裝置的作用效果的部分剖面圖。
第17圖是同實施形態中，變形例2相關的半導體裝置的剖面圖。
第18圖是同實施形態中，用以說明變形例2相關的半導體裝置的作用效果的部分剖面圖。
 實施形態1
針對本發明的實施形態1相關的半導體裝置作說明。如第1圖所示，在半導體裝置1中，從半導體基板2的一個表面延伸既定的深度而形成有n-層3。在n-層3的既定的區域，形成有主電流流動的主動區10。主動區10是作為元件形成區，在主動區10中，形成有IGBT 11作為開關元件的一例。
在主動區10中，形成有p基極層13。從p基極層13的表面到達n-層3的溝槽12，是被形成來貫通p基極層13。在溝槽12中，在溝槽12的側壁上夾置閘氧化膜15而形成有閘極埋入電極16。另外，從p基極層13的表面延伸到既定深度，形成有n+射極層14。另外在第1圖中，為了簡化圖式，是顯示在主動區10形成一個IGBT 11的情況。
在主動區10的側方，形成有作為電場緩和區的終端構造部20，以在半導體基板2的表面中圍繞主動區10。終端構造部20是對施加於主動區10的電壓保持耐壓的區域。在終端構造部20中，形成有多孔質氧化膜區26、p型保護環區21及n+型的通道停止區22。
作為絕緣區的多孔質氧化膜區26，是被形成來與主動區10接觸。此多孔質氧化膜區26是藉由陽極化成反應使矽多孔化(多孔質化)後，藉由氣體氧化的進行而形成。多孔質氧化膜區26的剖面是呈現層狀。多孔質氧化膜區26的介電常數，是低於後文敘述的第一絕緣膜30及第二絕緣膜31的介電常數的值。
另外，多孔質氧化膜區26是被形成為延伸至比溝槽12的底還深的區域，作為厚膜氧化膜區。另一方面，多孔質氧化膜區26較好為不從半導體基板2的正面突出至上方的構造。若以形成多孔質氧化膜區的前後(氧化的前後)的體積變化為R，已知下列的關係式。
R=2.2×(多孔質矽的密度)/(單晶矽的密度)
在此處，由於單晶矽的密度約2.3g/cm2 ，若多孔質矽的密度為約1.0g/cm2 程度，R的值為1，可以在氧化前後將體積維持一定。
保護環區21是作為耐壓層，從多孔質氧化膜區26的底部的部分延伸至更深的區域而形成。通道停止區22是形成在相對於多孔質氧化膜區26之主動區10所在那一側的相反側，並與多孔質氧化膜區26相隔一距離。
以連接於多孔質氧化膜區26的表面的方式，形成複數個浮置電極27a。浮置電極27a，是以在連結主動區10與通道停止區22的方向相互隔著間隔而配置。在半導體基板2的一個表面形成第一絕緣膜30，而覆蓋此浮置電極27a。在主動區10的上部，以連接於第一絕緣膜30的方式形成有電性連接於n+射極層14的射極17。在多孔質氧化膜區26的上方，以連接於第一絕緣膜30的方式形成有複數個浮置電極27b。
如後文敘述，在位於相對下方的浮置電極27a與位於相對上方的浮置電極27b之間，形成結合電容C。浮置電極27a及浮置電極27b，是以在連結主動區10與通道停止區22之間的方向具有結合電容C的方式配置。此時，浮置電極27a與浮置電 極27b，在平面視圖上有若干重疊是被允許的，但基本上是被配置為交互不重疊。以覆蓋此浮置電極27b及射極17的方式，形成有作為保護膜的第二絕緣膜31。
另一方面，從半導體基板2的另一個表面延伸至既定深度而形成有p+集極層5。還有，形成n+緩衝層4而與此p+集極層5接觸。以與p+集極層接觸的方式形成集極6。實施形態1相關的半導體裝置1是如上所述一般而構成。
接下來，針對上述的半導體裝置1的動作作說明。首先，針對打開(ON)動作作說明。在閘極埋入電極16，藉由施加閥值電壓以上的既定電壓，在位於閘極埋入電極16的附近之p基極層13的部分形成通道(n型)，打開MOS(Metal Oxide Semiconductor；金屬-氧化物-半導體)通道。在MOS通道為打開之下，電子從n+射極層14經過通道而注入至n-層3。
另一方面，電洞從p+集極層5注入至n-層3。在n-層3，受到電子與電洞的注入而引起導電率變調，集極6與射極17之間的電壓下降，成為打開狀態。在打開狀態，如第2圖所示，成為電流(參考箭號)從集極6向射極17流動之情況。
接下來，針對關閉(turn-off)動作作說明。藉由使施加於閘極埋入電極16的電壓為低於閥值電壓的電壓，停止電子與電洞往n-層3的注入。之後，累積於n-層3的電洞，是從p基極層13排出至射極17。另一方面，電子則排出至集極6。在將電子與電洞排出而空乏化的部分成為可保持耐壓的時間點，成為關閉(off)狀態。
在關閉狀態，在射極17與集極6之間，有例如數百 伏特程度的電位差。此時的電位勢的等高線的描繪(概略)，藉由第3圖中的點線來顯示。另外，關閉狀態中的空乏層端以一點鍊線來顯示。在上述的半導體裝置中，在作為保護膜的第二絕緣膜31的表面，即使遭到來自外部的電荷(外亂電荷)的附著這類的情況，電位勢的等高線仍不會變形而可以保持耐壓。針對這點，交替說明比較例相關的半導體裝置。
在比較例相關的半導體裝置100(參考第4圖)中，未形成多孔質氧化膜區及複數個浮置電極，在終端構造部，僅形成保護環區及通道停止區。如第4圖所示，在半導體基板102的一個表面側的主動區110中，形成有n-層103、p基極層113、n+射極層114、溝槽112、閘極埋入電極116及閘氧化膜115。在終端構造部120中，形成有保護環區121及通道停止區122。
形成第一絕緣膜130，而覆蓋p基極層113及保護環區121等。以與此第一絕緣膜的表面連接的方式，形成射極117與保護環電極135。以覆蓋此射極117及保護環電極135的方式，形成第二絕緣膜131作為保護膜。在半導體基板102的另一個表面側，形成有n+緩衝層104、p+集極層105以及集極106。
接下來，針對動作作說明。在打開(ON)動作中，在閘極埋入電極116，藉由施加閥值電壓以上的既定電壓，打開MOS通道。藉由打開MOS通道，將電子與電洞注入至n-層103而引起導電率變調，集極106與射極117之間的電壓下降，成為打開狀態。
接下來，在關閉(turn-off)動作中。藉由使施加於閘極埋入電極116的電壓為低於閥值電壓的電壓，關閉MOS通 道。藉由MOS通道的關閉，而停止電子與電洞往n-層3的注入。之後，累積於n-層103的電洞，是排出至射極117，電子則排出至集極106。在將電子與電洞排出而空乏化的部分成為可保持耐壓的時間點，成為關閉(off)狀態。
而在半導體裝置中，為了保護而免受外部的環境破壞，會在半導體裝置的表面形成保護膜(第二絕緣膜131)。保護膜，是使用例如氧化矽或氮化矽之類的絕緣膜。另外，會使用樹脂類的材料。再者，亦有情況是藉由形成層狀地形成複數種材料來作保護。在此保護膜，會有藉由來自外部的污染等，使電荷導入(附著)於半導體裝置的保護膜的情況。另外，在半導體的組裝步驟等中，會有在保護膜的表面附著電荷的情況。
一旦電荷附著於保護膜，半導體裝置為關閉的狀態中的電位勢的等高線會受到影響。如第5圖所示，一旦在作為保護膜的第二絕緣膜131附著電荷141，例如如點線框A內所示，會產生電位勢的等高線(請參考點線)的分布中較密的部分，而會有電場集中的情況。一旦電場集中，先前預定的耐壓會有變動，而會有耐壓變低的情況。一旦耐壓變低，就變得無法保持耐壓特性。
相對於比較例，在實施形態1相關的半導體裝置1中，在形成有多孔質氧化膜區26與浮置電極27a、27b之下，可以抑制電位勢的等高線的變形。如第6圖所示，一旦在作為保護膜的第二絕緣膜31附著電荷41，在第二絕緣膜的附近會產生電位勢的等高線(請參考點線)有較疏之處與較密之處。這一點，與比較例相關半導體裝置的情況雷同。
在實施形態1相關的半導體裝置1中，如第6圖所示，浮置電極27a與浮置電極27b作為結合電容C，以在連結主動區10與通道停止區22之間的方向具有結合電容C的樣態配置。藉此，主動區10與通道停止區22之間的電位勢受到電位分割，而緩和電位勢的等高線(請參考點線)的較密之處。
另外，使多孔質氧化膜區26的介電常數，低於第一絕緣膜30與第二絕緣膜31的介電常數。此多孔質氧化膜區26是作為厚膜氧化膜區，形成得比IGBT的溝槽12還深。因此，即使在電荷41附著處的附近中電位勢的等高線有較密之處(變形)，在多孔質氧化膜區26中，會使電位勢的等高線相互離間，使電位勢的等高線(請參考點線)成某種程度均等地配置。藉此，在保護耐壓的保護環區21中，解決了電位勢的等高線(請參考點線)的變形，而可以保持作為半導體裝置的耐壓特性。
此外，浮置電極27a、27b以及多孔質氧化膜區26，是配置於形成有保護環區21的區域。藉此，不會使終端構造部20擴大，而可以保持耐壓特性。
變形例1
作為實施形態1相關的半導體裝置的變形例1，針對在終端構造部具有低表面電場層作為耐壓層之低表面電場構造的半導體裝置作說明。如第7圖所示，在半導體裝置1中，形成有p型的低表面電場層23而從側方與下方圍繞多孔質氧化膜區26。低表面電場層23是被形成為連接於主動區10的p基極層13。此外，關於這些以外的構成，則與第1圖所示的半導體裝置1雷同，在相同構件賦予相同的元件符號而不再重複其說 明。
接下來，針對動作簡單地作說明。在打開(ON)動作中，在閘極埋入電極16，藉由施加閥值電壓以上的既定電壓，打開MOS通道，將電子與電洞注入至n-層3而引起導電率變調，集極6與射極17之間的電壓下降，成為打開狀態。
接下來，在關閉(turn-off)動作中，藉由使施加於閘極埋入電極16的電壓為低於閥值電壓的電壓，關閉MOS通道，使累積於n-層3的電洞排出至射極17，電子則排出至集極6，成為關閉(off)狀態。
在變形例1相關的半導體裝置1中，在終端構造部20形成有浮置電極27a、27b與多孔質氧化膜區26。藉此如第8圖所示，電荷(外亂電荷)41附著於作為保護膜的第二絕緣膜31，在關閉狀態中，即使在第二絕緣膜31的附近產生電位勢的等高線有較疏之處與較密之處(變形)，電位勢的變形不會及於低表面電場層23，而可以保持作為半導體裝置的耐壓特性。
亦即如前所述，藉由浮置電極27a與浮置電極27b造成的結合電容C，主動區10與通道停止區22之間的電位勢受到電位分割，而緩和電位勢的等高線(請參考點線)的較密之處。
另外，在相較於第二絕緣膜31等介電常數相對較低的多孔質氧化膜區26中，會使電位勢的等高線相互離間，使電位勢的等高線成某種程度均等地配置。藉此，在保護耐壓的低表面電場層23中，解決了電位勢的等高線的變形，而可以保持作為半導體裝置的耐壓特性。
變形例2
作為實施形態1相關的半導體裝置的變形例2，針對在終端構造部具有溝槽構造的半導體裝置作說明。
如第9圖所示，在半導體裝置1中，形成有複數個溝槽28而貫通多孔質氧化膜區26。複數個溝槽28是在連結主動區10與通道停止區22之間的方向相互隔著間隔而配置。形成有保護環區21作為耐壓層，而從側方與下方圍繞從多孔質氧化膜區26往下方突出的溝槽28的部分。
以連續沿著溝槽28的內壁的全周的方式，形成有浮置電極27c。另外，以將溝槽28埋入的方式，形成有第一絕緣膜30。此外，關於這些以外的構成，則與第1圖所示的半導體裝置1雷同，在相同構件賦予相同的元件符號而不再重複其說明。
接下來，針對動作簡單地作說明。在打開(ON)動作中，在閘極埋入電極16，藉由施加閥值電壓以上的既定電壓，打開MOS通道，將電子與電洞注入至n-層3而引起導電率變調，集極6與射極17之間的電壓下降，成為打開狀態。
接下來，在關閉(turn-off)動作中，藉由使施加於閘極埋入電極16的電壓為低於閥值電壓的電壓，關閉MOS通道，使累積於n-層3的電洞排出至射極17，電子則排出至集極6，成為關閉(off)狀態。
在變形例2相關的半導體裝置1中，在終端構造部20形成有浮置電極27c與多孔質氧化膜區26。藉此如第10圖所示，電荷(外亂電荷)41附著於作為保護膜的第二絕緣膜31，在關閉狀態中，即使在第二絕緣膜31的附近產生電位勢的等高線 有較疏之處與較密之處(變形)，電位勢的變形不會及於保護環區21，而可以保持作為半導體裝置的耐壓特性。
亦即與前述的浮置電極27a、27b的情況雷同，藉由複數個浮置電極27c造成的結合電容C，主動區10與通道停止區22之間的電位勢受到電位分割，而緩和電位勢的等高線的較密之處。
另外，在相較於第二絕緣膜31等介電常數相對較低的多孔質氧化膜區26中，會使電位勢的等高線相互離間，使電位勢的等高線成某種程度均等地配置。藉此，在保護耐壓的保護環區21中，解決了電位勢的等高線的變形，而可以保持作為半導體裝置的耐壓特性。
變形例3
作為實施形態1相關的半導體裝置的變形例3，針對在終端構造部具有溝槽構造的其他半導體裝置作說明。
如第11圖所示，在半導體裝置1中，形成有複數個溝槽28而貫通多孔質氧化膜區26。複數個溝槽28是在連結主動區10與通道停止區22之間的方向相互隔著間隔而配置。形成有保護環區21作為耐壓層，而從側方與下方圍繞從多孔質氧化膜區26往下方突出的溝槽28的部分。
在溝槽28的底部的部分，形成有浮置電極27a。另外，在溝槽28的開口端附近的多孔質氧化膜區26的表面，形成有浮置電極27b。以將溝槽28埋入的方式，形成有第一絕緣膜30。此外，關於這些以外的構成，則與第1圖所示的半導體裝置1雷同，在相同構件賦予相同的元件符號而不再重複其說明。
接下來，針對動作簡單地作說明。在打開(ON)動作中，在閘極埋入電極16，藉由施加閥值電壓以上的既定電壓，打開MOS通道，將電子與電洞注入至n-層3而引起導電率變調，集極6與射極17之間的電壓下降，成為打開狀態。
接下來，在關閉(turn-off)動作中，藉由使施加於閘極埋入電極16的電壓為低於閥值電壓的電壓，關閉MOS通道，使累積於n-層3的電洞排出至射極17，電子則排出至集極6，成為關閉(off)狀態。
在變形例3相關的半導體裝置1中，在終端構造部20形成有浮置電極27a、27b與多孔質氧化膜區26。藉此如第12圖所示，電荷41附著於作為保護膜的第二絕緣膜31，在關閉狀態中，即使在第二絕緣膜31的附近產生電位勢的等高線有較疏之處與較密之處(變形)，電位勢的變形不會及於保護環區21，而可以保持作為半導體裝置的耐壓特性。
亦即如前所述，藉由浮置電極27a與浮置電極27b造成的結合電容C，主動區10與通道停止區22之間的電位勢受到電位分割，而緩和電位勢的等高線的較密之處。
另外，在相較於第二絕緣膜31等介電常數相對較低的多孔質氧化膜區26中，會使電位勢的等高線相互離間，使電位勢的等高線成某種程度均等地配置。藉此，在保護耐壓的保護環區21中，解決了電位勢的等高線的變形，而可以保持作為半導體裝置的耐壓特性。
實施形態2
針對本發明的實施形態2相關的半導體裝置作說 明。如第13圖所示，在半導體裝置1中，將多孔質氧化膜區26形成為從p基極層13之側朝向通道停止區22之側，階段狀(階梯式)地徐徐地深入較深的位置。此外，關於這些以外的構成，則與第1圖所示的半導體裝置1雷同，在相同構件賦予相同的元件符號而不再重複其說明。
接下來，針對動作簡單地作說明。在打開(ON)動作中，在閘極埋入電極16，藉由施加閥值電壓以上的既定電壓，打開MOS通道，將電子與電洞注入至n-層3而引起導電率變調，集極6與射極17之間的電壓下降，成為打開狀態。
接下來，在關閉(turn-off)動作中，藉由使施加於閘極埋入電極16的電壓為低於閥值電壓的電壓，關閉MOS通道，使累積於n-層3的電洞排出至射極17，電子則排出至集極6，成為關閉(off)狀態。
在實施形態2相關的半導體裝置1中，在終端構造部20形成有浮置電極27a、27b與多孔質氧化膜區26。藉此如第14圖所示，電荷41附著於作為保護膜的第二絕緣膜31，在關閉狀態中，即使在第二絕緣膜31的附近產生電位勢的等高線有較疏之處與較密之處(變形)，電位勢的變形不會及於保護環區21，而可以保持作為半導體裝置的耐壓特性。
亦即如實施形態1中的說明，藉由浮置電極27a與浮置電極27b造成的結合電容C，主動區10與通道停止區22之間的電位勢受到電位分割，而緩和電位勢的等高線的較密之處。
另外，在相較於第二絕緣膜31等介電常數相對較低的多孔質氧化膜區26中，會使電位勢的等高線相互離間，使 電位勢的等高線成某種程度均等地配置。藉此，在保護耐壓的保護環區21中，解決了電位勢的等高線的變形，而可以保持作為半導體裝置的耐壓特性。
還有，在上述的半導體裝置1中，是將多孔質氧化膜區26形成為從p基極層13之側朝向通道停止區22之側，階段狀(階梯式)地徐徐地深入較深的位置。也就是將多孔質氧化膜區26形成為朝向通道停止區22之側而階梯性地變厚。藉此，可將位於保護環區21的正下方的電位勢的彎曲點，徐徐地導向較深的位置。藉此，在半導體裝置的端部(晶片的端部)中，抑制電位勢的等高線的緊密配置，可以獲得更穩定的耐壓特性。
另外，在上述的半導體裝置中，是針對將多孔質氧化膜區26形成為從p基極層13之側朝向通道停止區22之側而階段狀(階梯式)地徐徐地深入較深的位置之情況作說明，但是多孔質氧化膜區26亦可被形成為位於使位於p基極層13之側的部分比位於通道停止區22之側的部分還要深的區域。
變形例1
作為實施形態2相關的半導體裝置的變形例1，針對在終端構造部具有低表面電場層作為耐壓層之低表面電場構造的半導體裝置作說明。如第15圖所示，在半導體裝置1中，形成有p型的低表面電場層23作為耐壓層而從側方與下方圍繞被形成為階梯性變厚的多孔質氧化膜區26。低表面電場層23是被形成為連接於主動區10的p基極層13。此外，關於這些以外的構成，則與第13圖所示的半導體裝置1雷同，在相同構件賦予相同的元件符號而不再重複其說明。
接下來，針對動作簡單地作說明。在打開(ON)動作中，在閘極埋入電極16，藉由施加閥值電壓以上的既定電壓，打開MOS通道，將電子與電洞注入至n-層3而引起導電率變調，集極6與射極17之間的電壓下降，成為打開狀態。
接下來，在關閉(turn-off)動作中，藉由使施加於閘極埋入電極16的電壓為低於閥值電壓的電壓，關閉MOS通道，使累積於n-層3的電洞排出至射極17，電子則排出至集極6，成為關閉(off)狀態。
在變形例1相關的半導體裝置1中，在終端構造部20形成有浮置電極27a、27b與多孔質氧化膜區26。藉此如第16圖所示，電荷41附著於作為保護膜的第二絕緣膜31，在關閉狀態中，即使在第二絕緣膜31的附近產生電位勢的等高線有較疏之處與較密之處(變形)，電位勢的變形不會及於低表面電場層23，而可以保持作為半導體裝置的耐壓特性。
亦即如前所述，藉由浮置電極27a與浮置電極27b造成的結合電容C，主動區10與通道停止區22之間的電位勢受到電位分割，而緩和電位勢的等高線的較密之處。
另外，在相較於第二絕緣膜31等介電常數相對較低的多孔質氧化膜區26中，會使電位勢的等高線相互離間，使電位勢的等高線成某種程度均等地配置。藉此，在保護耐壓的低表面電場層23中，解決了電位勢的等高線的變形，而可以保持作為半導體裝置的耐壓特性。
還有，是將多孔質氧化膜區26形成為朝向通道停止區22之側而階梯性地變厚，可將位於低表面電場層23的正下 方的電位勢的彎曲點，徐徐地導向較深的位置。藉此，在半導體裝置的端部(晶片的端部)中，抑制電位勢的等高線的緊密配置，可以獲得更穩定的耐壓特性。
變形例2
作為實施形態2相關的半導體裝置的變形例2，針對在終端構造部具有溝槽構造的半導體裝置作說明。如第17圖所示，在半導體裝置1中，形成有複數個溝槽28而貫通被形成為階梯性地變厚的多孔質氧化膜區26。複數個溝槽28是在連結主動區10與通道停止區22之間的方向相互隔著間隔而配置。形成有保護環區21作為耐壓層，而從側方與下方圍繞從多孔質氧化膜區26往下方突出的溝槽28的部分。
以連續沿著溝槽28的內壁的全周的方式，形成有浮置電極27c。另外，以將溝槽28埋入的方式，形成有第一絕緣膜30。此外，關於這些以外的構成，則與第13圖所示的半導體裝置1雷同，在相同構件賦予相同的元件符號而不再重複其說明。
接下來，針對動作簡單地作說明。在打開(ON)動作中，在閘極埋入電極16，藉由施加閥值電壓以上的既定電壓，打開MOS通道，將電子與電洞注入至n-層3而引起導電率變調，集極6與射極17之間的電壓下降，成為打開狀態。
接下來，在關閉(turn-off)動作中，藉由使施加於閘極埋入電極16的電壓為低於閥值電壓的電壓，關閉MOS通道，使累積於n-層3的電洞排出至射極17，電子則排出至集極6，成為關閉(off)狀態。
在變形例2相關的半導體裝置1中，在終端構造部20形成有浮置電極27c與多孔質氧化膜區26。藉此如第18圖所示，電荷41附著於作為保護膜的第二絕緣膜31，在關閉狀態中，即使在第二絕緣膜31的附近產生電位勢的等高線有較疏之處與較密之處(變形)，電位勢的變形不會及於保護環區21，而可以保持作為半導體裝置的耐壓特性。
亦即與前述的浮置電極27a、27b的情況雷同，藉由浮置電極27c造成的結合電容C，主動區10與通道停止區22之間的電位勢受到電位分割，而緩和電位勢的等高線的較密之處。
另外，在相較於第二絕緣膜31等介電常數相對較低的多孔質氧化膜區26中，會使電位勢的等高線相互離間，使電位勢的等高線成某種程度均等地配置。藉此，在保護耐壓的保護環區21中，解決了電位勢的等高線的變形，而可以保持作為半導體裝置的耐壓特性。
還有，將多孔質氧化膜區26形成為朝向通道停止區22之側而階梯性地變厚，可將位於保護環區21的正下方的電位勢的彎曲點，徐徐地導向較深的位置。藉此，在半導體裝置的端部(晶片的端部)中，抑制電位勢的等高線的緊密配置，可以獲得更穩定的耐壓特性。
另外，在上述各實施形態中，作為形成於作為元件形成區的主動區之半導體元件，是舉出IGBT作為例子來作說明。作為半導體元件者，亦可適用其他之平面型二極體、平面型金屬-氧化物-半導體電晶體、溝槽閘極型金屬-氧化物- 半導體電晶體、平面型IGBT、平面型/溝槽型CoolMOS(登錄商標)、平面型/溝槽型閘極控制閘流電晶體栓鎖裝置(gate-controlled thyristor latch device)等。
另外，作為絕緣區，是舉出多孔質氧化膜區作為例子來作說明。作為絕緣區者，只要滿足厚膜、介電常數比保護膜低、其介電常數穩定之要件，不限於多孔質氧化膜區。
本發明可有效地應用於高耐壓電力裝置。
以上詳細地說明、示範本發明，但這些內容僅為用於例示，不應成為限制，要明確地理解的是，發明的範圍應藉由所附申請專利範圍來解釋。
1‧‧‧半導體裝置
2‧‧‧半導體基板
3‧‧‧n-層
4‧‧‧n+緩衝層
5‧‧‧p+集極層
6‧‧‧集極
10‧‧‧主動區
11‧‧‧IGBT
12‧‧‧溝槽
13‧‧‧p基極層
14‧‧‧n+射極層
15‧‧‧閘氧化膜
16‧‧‧閘極埋入電極
17‧‧‧射極
20‧‧‧終端構造部
21‧‧‧p型保護環區
22‧‧‧通道停止區
26‧‧‧多孔質氧化膜區
27a‧‧‧浮置電極
27b‧‧‧浮置電極
30‧‧‧第一絕緣膜
31‧‧‧第二絕緣膜

Claims (8)

  1. 一種半導體裝置，包含：第一導電型的半導體基板，具有相互對向的第一主表面及第二主表面；元件形成區，形成於上述半導體基板的上述第一主表面側中的既定區域，配置有既定的半導體元件以在上述第一主表面之側與上述第二主表面之側之間導通電流；電場緩和區，在上述半導體基板的上述第一主表面中之上述元件形成區的側方，以連接上述元件形成區的樣態形成；以及絕緣性的保護膜，被形成為覆蓋上述第一主表面側，並具有既定的介電常數；其中上述電場緩和區具有：絕緣區，從上述第一主表面延伸至既定深度而形成，其介電常數低於上述保護膜的介電常數；第一導電型的通道停止區，形成在相對於上述絕緣區之上述元件形成區所在那一側的相反側，並與上述絕緣區相隔一距離；複數個浮置電極，以在連結上述元件形成區與上述通道停止區之間的方向具有結合電容的樣態配置；以及第二導電型區域，從上述絕緣區延伸至更深的區域而形成。
  2. 如申請專利範圍第1項所述之半導體裝置，其中上述絕緣區是多孔質氧化膜區域。
  3. 如申請專利範圍第1項所述之半導體裝置，其中上述複數個 浮置電極包含：配置在相對下側的第一浮置電極；以及配置在相對上側的第二浮置電極；其中上述第一浮置電極及上述第二浮置電極，是以藉由上述第一浮置電極與上述第二浮置電極的電容結合在上述方向具有結合電容的樣態配置。
  4. 如申請專利範圍第1項所述之半導體裝置，更包含複數個溝槽，上述複數個溝槽是在上述方向相隔一間隔而形成的同時，貫通上述絕緣區而分別到達上述第二導電型區域，其中上述複數個浮置電極是各自被形成為覆蓋上述複數個溝槽的各自的內壁。
  5. 如申請專利範圍第3項所述之半導體裝置，更包含複數個溝槽，上述複數個溝槽是在上述方向相隔一間隔而形成的同時，貫通上述絕緣區而分別到達上述第二導電型區域，其中上述第一浮置電極是各自被形成為覆蓋上述複數個溝槽的各自的內壁的部分；以及上述第二浮置電極是形成於上述溝槽的開口端中的上述絕緣區的部分。
  6. 如申請專利範圍第1項所述之半導體裝置，其中上述絕緣區是被形成為位在上述通道停止區之側的部分比位在上述元件形成區之側的部分還深。
  7. 如申請專利範圍第1項所述之半導體裝置，其中上述第二導 電型區域是在上述方向相隔一間隔形成之保護環區域。
  8. 如申請專利範圍第1項所述之半導體裝置，其中上述第二導電型區域是從側方與下方包圍上述絕緣區而形成的低表面電場(reduced surface field；RESURF)區。
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