TWI482218B - 高介電常數閘極介電材料的形成方法與半導體元件 - Google Patents

高介電常數閘極介電材料的形成方法與半導體元件 Download PDF

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TWI482218B
TWI482218B TW097141560A TW97141560A TWI482218B TW I482218 B TWI482218 B TW I482218B TW 097141560 A TW097141560 A TW 097141560A TW 97141560 A TW97141560 A TW 97141560A TW I482218 B TWI482218 B TW I482218B
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Taiwan
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dielectric constant
high dielectric
forming
constant gate
material according
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TW097141560A
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TW200935518A (en
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Yang Hui Ou
Everaert Jean-Luc
Nyns Laura
Vos Rita
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Taiwan Semiconductor Mfg Co Ltd
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Description

高介電常數閘極介電材料的形成方法與半導體元件
本發明係有關於積體電路的製備方法，且特別是有關於一種沉積高介電常數材料於基材上的方法，藉此提供一適合高介電常數材料沉積之界面層，更特別是關於製備閘極介電結構時沉積高介電常數材料之方法。
目前需要縮小(降低)半導體元件之尺寸，以增加半導體晶片之上的元件密度，使得半導體元件操作得更快且消耗較少的功率。
二氧化矽最常作為半導體元件之閘極介電材料。然而，將二氧化矽應用作為閘極介電材料時，隨著二氧化矽厚度的下降，伴隨對氧化過程的嚴格限制。使用這些介電材料時，是需要控制整個晶圓之次埃(sub－angstrom)均勻度與厚度。
再者，當介電層厚度降低的同時，量子穿隧效應(quantum tunneling effects)傾向增加，造成不想要的電流流經閘極與通道之間。
近來關於降低元件之尺寸，許多研究已經致力開發另一種介電常數材料，其形成的厚度大於二氧化矽，且仍然具有相同之場效表現。這些材料通常稱為高介電常數(high－k)材料，因為其介電常數值高於二氧化矽之介電常數值(3.9)。
此種高介電常數(high－k)材料的相對性能通常表示為等效氧化層厚度(Equivalent oxide thickness,EOT)，因為此種替代材料層可以更厚，但其仍然提供與相對較薄之二氧化矽層同樣的電性效果。
然而，使用較高介電常數材料之缺點在於，其容易提供較差品質之界面。較差品質之界面容易損害最終閘極電極微結構之電性表現，於上述例子中，高介電常數材料係直接沉積於矽基材之上。
因此，先前技術WO 2005/013349中提及介電材料(例如二氧化矽或類似之材料)可提供一緩衝層(或界面或橋樑)介於半導體晶圓和高介電常數材料之間，當使用高介電常數材料時，用以改善其電性表現。
不幸地，很難發展超薄之界面層(例如厚度低於10埃)，且又具有均勻性。
缺乏均勻性可能會損害最終元件之電性特性。
為了整合高介電常數材料到目前CMOS製程系統中，良好品質(平坦、平滑、均勻且展現連續界面氧化物成長)之界面層將有利於半導體基材和高介電常數材料之界面。
此處的挑戰在於，將半導體晶圓基材(特別是二氧化矽晶圓基材)和高介電常數材料之間的界面層品質最佳化，因該處的品質將決定最終電晶體之性能表現與可靠度(reliablity)。
本發明的目的之一就是提供一種改善且替代之方法，其能解決先前技術之缺點。
本發明的另一目的就是提供一種方法，其特別能產生一種均勻超薄之界面層，此界面層適合沉積具有高介電常數之材料(例如高介電常數(high－k)材料)。
再者，本發明之目的在於改善介於半導體基材(或晶圓)和介電層之間的界面，特別是沉積一高介電常數材料於基材之上。
本發明提供一種高介電常數閘極介電材料的形成方法，包括下列步驟：提供一半導體基材；清洗該基材；對該基材進行一熱處理；沉積一高介電常數材料，其中該熱處理於一無氧化環境中進行，導致形成一薄界面層。
較佳者，上述清洗基材包括一最終之氫氟酸處理。
較佳者，於本發明的方法中，熱處理之溫度約高於700℃，較佳約高於1000℃，更佳約高於1050℃。
較佳者，於本發明的方法中，其中該無氧化環境包括一鈍氣，更佳包括氦氣及/或氬氣。
較佳者，於本發明的方法中，更包括加入部分氫氣到無氧化環境中。
較佳者，於本發明的方法中，其中該部分氫氣之體積約少於10%，較佳約介於1%~10%。
較佳者，該無氧化環境中不包括氮氣。
較佳者，於本發明的方法中，其中熱處理之時間約 少於2分鐘，較佳約少於1分鐘，更佳約少於40秒。
較佳者，依照本發明的方法，其中於熱處理之後，形成一薄化學氧化層。
較佳者，上述之薄化學氧化層之形成藉由施加一濕式臭氧(O3 )/最終去離子水(DIW)處理或一UV增強式氧化物成長法(UV－enhanced oxide growth method)。
較佳者，依照本發明的方法中，其中高介電常數材料為任何一種介電常數值(k)高於二氧化矽之介電材料。
較佳者，上述之高介電常數材料係藉由原子層沉積法(Atomic Layer Deposition)沉積而得。
較佳者，於本發明的方法中，其中沉積該高介電常數材料之後，接著進行一沉積後退火處理。
較佳者，上述之薄界面層之厚度較佳約少於0.6 nm。
依照本發明所述之方法，可用於形成的高介電常數閘極介電材料。
較佳者，上述之半導體元件，其包括一高介電常數閘極介電材料，其中高介電常數閘極介電材料包括一約少於0.6 nm之薄界面層。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
本發明係基於意外發現一實行本發明之方法，包括 於含有鈍氣之無氧化環境中進行熱處理，以形成一薄界面層。
本發明所謂之“無氧化環境”係指沒有氧氣的環境。此環境較佳包括一鈍氣環境或鈍氣混合物，以及視需要地包括其他添加劑。
特別是，添加氫氣於包含鈍氣環境或鈍氣混合物之無氧環境中，可增加上述薄界面層之表面平滑度。
於本發明中，熱處理之步驟係進行於清洗基材之後，以及未沉積高介電常數材料之前。
本發明所謂之“高介電常數”係指任何介電材料，其具有一介電常數值k(相對於真空下)高於3.9(此為二氧化矽之介電常數)，且較佳高於8.0。
於包含鈍氣之無氧化環境中施加熱處理，會形成一薄界面層。
上述之界面層可能包括氧化矽和次氧化物(SiOx,0<x≦2)。
本發明新穎之處在於形成一均勻(平滑或平整)薄的(厚度小於10埃)界面層，其具有合理之縫隙(leakage)且能增強電荷載子(charge carrier)的遷移率，然而使用先前技術卻會得到低品質之界面層(粗糙(既不平整，不平滑，也不均勻)且沒有連續之界面氧化層成長)，造成較高的縫隙(leakage)與較高的界面陷阱密度(interface trap density,Dit)，且最終結果造成半導體元件較差的性能表現。
已知當裸矽基材上曝露於含有氧氣的環境中時，自身氧化層(native oxide)會成長於裸矽基材上。
此種自身氧化層本質上是SiO和SiO2 的異質混合物。
此種自身氧化層的品質與厚度在整個基材表面上是不一致的，因此，於矽基材表面上的這些自身氧化薄膜會阻礙對超薄閘極氧化薄膜厚度的準確控制。
因此，除了清潔其他物質以外，主要用於清潔基材上的自身氧化物，以避免污染以及為了產生優異的電性表現。
清潔基材經常包括最終之氫氟酸(HF)疏水處理，用以抑制氧自由基(redical)和矽結合。
上述之最終氫氟酸疏水處理，亦稱為IMEC－foob，是先使用臭氧和去離子水(O3 /DIW)之氧化步驟，接著使用一氧化物移除步驟(使用HF/HCl)。最後，用去離子水(去離子水摻鹽酸)潤洗，再進行含有異丙醇和氮氣之馬南哥尼乾燥法(Marangoni drying)。
此最終氫氟酸處理(IMEC－foob)造成表面無氧化物。
但是，經由最終氫氟酸(IMEC－foob)之清潔所產生之無氧化物的表面，其無法提供適合後續沉積高介電常數(high－k)材料所需要之末端OH鍵。
因此，本發明建議基材經過清潔步驟後，接著於無氧化環境中進行一熱處理。
上述之熱處理會形成一均勻薄氧化物及/或次氧化物 的界面層，其位於閘極介電層與半導體基材之間。
上述薄界面氧化物/次氧化物層，又稱為鈍氣中薄界面層，藉由於無氧化環境中施加一熱處理而得。
第1圖為一流程圖，用以說明依照本發明之方法於半導體製備過程中的各階段步驟。
上述方法中包括於半導體主體中形成隔離結構，例如淺溝隔離結構(Shallow Trench Isolation,STI)。
開始製備閘極之步驟，首先進行一最終氫氟酸疏水處理以清潔半導體主體之上表面，此清洗步驟進行於無氧化環境中進行熱處理步驟之前。
於一包括鈍氣之無氧化環境中，進行上述熱處理步驟以產生高品質薄界面層於半導體主體之上。
接著，視需要地形成一化學氧化物，藉由濕式O3 /最終去離子水(DIW)清潔處理(亦稱為IMEC－clean)或UV增強氧化物成長法，造成表面具有一薄化學氧化層。
當界面層形成之後，高介電常數(high－k)閘極介電層沉積於界面層之上。此高介電常數(high－k)閘極介電層可包括一或多層高介電常數(high－k)介電材料。
視需要地對高介電常數(high－k)介電材料進行一沉積後退火處理。
一導電金屬閘極接觸(或閘極電極)形成於高介電常數(high－k)閘極介電層之上，因而形成閘極結構或閘極堆疊。
此閘極電極可包括一或多層導電材料。
再者，多晶矽覆蓋層(capping layer)沉積於閘極接觸之上。
閘極接觸、高介電常數(high－k)閘極介電層與界面層接著一起被圖案化形成一閘極結構。
藉由離子佈值、擴散摻雜適當的n或p雜質，以形成半導體主體之源極/汲極區域並進行內連線製程。
當形成淺溝隔離結構時，藉由乾式蝕刻於基材中形成溝槽，再填充介電材料以提供電性之絕緣。
此閘極介電材料可以是一高介電常數(high－k)材料，例如氧化鉿，氧化鋁或氧化鋯。
閘極電極(或閘極接觸)可由半導體材料構成，例如多晶矽、矽化鍺、鍺、金屬矽化物或擇自於下述群組之金屬材料：金屬、金屬氮化物、金屬碳氮化物以及上述之組合(例如鈦(Ti)、鉭(Ta)、鎢(W)、釕(Ru)、氮(碳)化鈦(Ti(C)N)、氮(碳)化鉭(Ta(C)N)、氮(碳)化鎢(W(C)N)。
閘極結構分隔兩側之源極與汲極，其中源極與汲極接觸通道區域(channel region)之相對兩側。
側壁間隔物(sidewall spacer)形成閘極結構側壁，側壁間隔物通常與源極和汲極的邊界對齊。這些側壁間隔物可由例如氧化矽、氮化矽及/或碳化矽所組成。
依照本發明之一較佳實施例，形成高介電常數(high－k)閘極介電材料之方法，包括以下步驟：提供一半導體基材，清洗該基材，於無氧化環境中進行一熱處理，以及接著沉積一高介電常數(high－k)材料。
依照本發明之方法，於無氧化環境中進行一熱處理，尚包括鈍氣混合物，造成一薄界面層之形成。
再者，此均勻薄界面層，由施加熱處理而得，其具有適合的表面末端，因此能使表面適合高介電常數(high－k)材料之沉積，且減少EOT。
上述之均勻薄界面層，提供改良之界面特性，此界面層介於矽結構與高介電常數(high－k)材料之間，藉由下述沉積步驟而得。
於包含鈍氣混合物之無氧化環境中進行之熱處理，較佳進行於一快速熱處理(rapid thermal process,RTP)腔體中。
上述熱處理進行於約高於700℃之溫度，較佳約高於1000℃，更佳約高於1050℃。
上述熱處理之期間較佳約少於2分鐘，更佳約少於1分鐘，又更佳約少於40秒。
依照本發明之方法，熱處理可以進行於爐管中(例如LPCVD低壓化學氣相沉積反應爐)，或使用瞬間退火(spike anneal)。當於LPCVD反應爐中進行熱處理時，需要較長期間(至少10分鐘至幾小時)，而瞬間退火一般約於1050℃中進行1秒鐘。
進行熱處理期間，一包括氧化矽與次氧化物(SiOx,0<x≦2)均勻薄的層被揭開(unraveled)於基材表面上。
進行熱處理期間，上述之無氧化環境之鈍氣較佳為氦氣(He)及/或氬氣(Ar)。
氮氣不適合加入無氧化環境中，當其併入於界面且增加界面狀態密度時，會導致通道遷移率之降低，影響此元件之電性特性。
較佳者，加入部分氫氣到包括鈍氣之無氧化環境中。
較佳者部分氫氣之體積約少於10%，較佳介於1~10%之間。
無氧化環境之壓力較佳介於10到20托耳(torr)。
依照本發明之方法，會獲得薄界面層之厚度約少於0.6 nm。
再者，依照本發明之方法獲得的高品質界面層，其平整(或平滑或均勻)且呈現連續的界面氧化物成長。
於本發明之方法中，形成上述之薄界面層，接著後續沉積一高介電常數(high－k)材料。
上述之高介電常數(high－k)材料之沉積可使用本技藝人士所知之沉積技術，較佳為原子層沉積法(Atomic Layer Deposition,ALD)、金屬有機氣相沉積法(Metal－Organic Chemical Vapor Deposition,MOCVD)、分子束磊晶法(Molecular Beam Epitaxy,MBE)、化學氣相沉積法(Chemical Vapor Deposition,CVD)或物理氣相沉積法(Physical Vapor Deposition,PVD)。
高介電常數(high－k)材料之例子包括，但不限於二元之金屬氧化物，包括ZrO2 、HfO2 、La2 O3 、Y2 O3 、TiO2 ，以及其矽化鹽類和鋁酸鹽類；金屬氧氮化物包括AlON、ZrON、HfON、LaON、YON等，以及其矽酸鹽和鋁酸鹽 類例如ZrSiON、HfSiON、LaSiON、YSiON；鈣鈦礦型之氧化物，包括鈦酸鹽系統之材料，例如鈦酸鋇、鈦酸鍶、碳酸鋇鍶((BaSr)TiO3 ,BST)
較佳者，高介電常數(high－k)材料之沉積視需要地伴隨一沉積後退火處理以進一步降低界面陷阱密度(interface trap density,Dit)。
於一實施例中，於無氧化環境中之熱處理之後，立即進行高介電常數(high－k)材料之沉積步驟。
於另一實施例中，於無氧化環境中之熱處理之後，視需要地進行化學氧化成長步驟。
化學成長氧化物係將裸露之半導體表面和較佳為薄界面層與液體及/或氣體化學物接觸以氧化其表面。
依照本發明，化學氧化物之形成較佳藉由進行濕式例如臭氧(O3 )/最終之去離子水(DIW)(IMEC－clean)之清潔處理或UV增強式氧化物成長法，兩種方法可擇一選擇。
上述之濕式臭氧(O3 )/最終去離子水(DIW)清潔，亦稱為IMEC－cleam，是先使用臭氧和去離子水(O3 /DIW)，接著使用一氧化物移除步驟(使用HF/HCl)。最後，用臭氧化之去離子(臭氧/去離子水摻鹽酸)潤洗，再進行含有異丙醇和氮氣之馬南哥尼乾燥法(Marangoni drying)。
上述之濕式臭氧(O3 )/最終去離子水(DIW)清潔(IMEC－clean)，會使表面留下一非常乾淨且薄化學氧化物層。
上述之UV增強式氧化物成長法是於空氣中進行UV 照射以成長一薄氧化層。氬氣連續地注入基材之上，以降低空氣中之氧化物成長的速度。
利用上述之UV增強式氧化物成長法而得之化學氧化層，其厚度薄於用濕式臭氧(O3 )/最終去離子水(DIW)清潔(IMEC－clean)而得之氧化層。
藉由進行濕式臭氧(O3 )/最終去離子水(DIW)清潔(IMEC－clean)或UV增強式氧化物成長法而得之化學氧化物層，可提供除了施加熱處理所造成之效果之外，另外能使表面具有後續沉積高介電常數(high－k)材料所需要的合適的末端(例如OH鍵)。
因此，總氧化層來自於兩種貢獻，其一來自於無氧化環境中進行熱處理而得之界面層，另一來自於進行濕式臭氧(O3 )/最終去離子水(DIW)清潔(IMEC－clean)或UV增強式氧化物成長法而得之化學氧化層。
只進行化學氧化物沉積，而未進行一熱處理，會得到有縫隙(leakage)、較差品質之化學氧化物(對照下列討論之第3圖與第6圖)，其不適合後續沉積高介電常數(high－k)材料，因此得到低品質之半導體元件。
接著，視需要地進行化學氧化物形成步驟之後，進行ALD高介電常數(high－k)材料之沉積步驟。
上述之半導體基材較佳為矽基材或包含矽晶圓或矽層之絕緣層上覆矽基材(silicon－on－insulator,SOI)，例如多晶矽、磊晶矽或非晶矽，具有或不具有導電之摻雜物。
上述之半導體基材可以為任何半導體基材，只要此 基材能抵抗本發明所需要的高溫。
此基材可能包括各種絕緣區域，例如淺溝隔離區域(Shallow Trench Isolation,STI)、局部氧化區(Local Oxidation of Silicon,LOCOS)或其他類似之隔離區域，其形成於基材或上述之表面上。
第2圖顯示依照本發明之不同表面處理步驟，由AR－XPS測量到界面層與沉積高介電常數(high－k)介電材料HfO2 之厚度。
於第2圖中之界面層(interfacial layer,IL)，係藉由於無氧化環境中之熱處理而得，或藉由化學氧化物成長法搭配或不搭配前者之熱處理而得。
第2圖中標出熱處理法不同的條件，包括無氧化環境的成份與溫度。
上述化學氧化層係藉由進行濕式臭氧(O3 )/最終去離子水(DIW)清潔(IMEC－clean)或UV增強式氧化物成長法(第2圖中標示為UV/Air/Ar)而得。
第2圖顯示界面層與高介電常數(high－k)之HfO2 材料層兩者只進行熱處理步驟，兩者之厚度具有非常好之結果。
例如H2 /He/1050℃熱處理與He/1050℃熱處理形成超薄之界面層，其厚度分別為0.4 nm和0.5 nm。
再者，如第2圖所示，H2 /He/1050℃熱處理幫助限制後續之化學氧化物成長。
因此，依照本發明之方法可用於達到EOT縮小化。
藉由進行熱處理搭配UV增強式氧化物成長法所形成之界面層，其總氧化物之厚度亦少於只利用UV增強式氧化物成長法所得之厚度。
但是，如第3圖所示，相較於熱處理搭配UV增強式氧化物成長法，進行UV增強式氧化物成長法得到較低之HfO2 覆蓋率(coverage)。可能之解釋在於，UV增強式氧化物方法無法於表面上顯示足夠的、合適的活化官能基末端(例如OH鍵)，因此對於後續高介電常數(high－k)材料沉積步驟時，表面為粗糙且低品質成核層(nucleation)，因此，造成後續元件的電性特性出問題。
的確，第3圖顯示依照本發明之方法，其HfO2 覆蓋率對應氧化物之厚度關係圖。
藉由進行熱處理，與視需要地進行化學氧化物形成法(UV增強式氧化物成長法或濕式臭氧(O3 )/最終去離子水(DIW)清潔(IMEC－clean))。
形成上述界面層後，進行例如5次ALD HfO2 單層沉積之循環。
一般的ALD技術與HfO2 之ALD對界面層表面條件特別敏感，因此，進行HfO2 之ALD時，依據界面層之粗糙度、界面層表面之活性官能基末端(例如OH鍵)與界面層之連續性/均勻性(例如無島狀類似物)對界面層之品質進行評估。
據此，具有較多OH官能基末端且較平滑(較低粗糙度)的界面層表面，較有利於HfO2 之ALD沉積。
如第3圖所示，藉由熱處理形成界面層(不論搭配或不搭配進行UV增強式氧化物成長法)提供較佳之HfO2 覆蓋率，因此為較佳品質、平滑之界面層。
上述之HfO2 覆蓋率亦高於利用臭氧(O3 )/最終去離子水(DIW)化學氧化物成長法(不論搭配或不搭配熱處理形成界面層)而得之HfO2 覆蓋率，且特別能改善只進行UV增強式氧化物成長法獲得之較差的覆蓋率。
第4圖顯示依照本發明之不同表面處理步驟而依序成長(step－by－step)之氧化層厚度(藉由光學測厚儀(Ellipsometry)測量)。
每一次進行清潔步驟(IMFOOB)後，於無氧化環境中進行熱處理或一化學氧化物成長(濕式臭氧(O3 )/最終去離子水(DIW)清潔(IMEC－clean)或UV/Air/Ar)，或上述之組合。
由熱處理所形成之界面層，第4圖中指出不同的實驗條件，包括無氧化環境之組成和溫度。
化學氧化物係由UV增強式氧化物成長法或由濕式臭氧(O3 )/最終去離子水(DIW)清潔(IMEC－clean)而得。
第4圖測出的總氧化層厚度，包括於無氧化環境中進行熱處理而得之界面層，與由UV增強式氧化物成長法或由濕式臭氧(O3 )/最終去離子水(DIW)清潔(IMEC－clean)而得之化學氧化物層。
在此須注意的是，由光學測厚儀所測之氧化層厚度，其準確度不如由AR－XPS所測。
事實上，由光學測厚儀所測之厚度會厚於由AR－XPS所測之厚度。
但是，第4圖所顯示之趨勢符合第2圖之結果。
第5圖顯示藉由原子力顯微鏡(Atomic Force Microscope,AFM)測得之表面粗糙度。
第5圖所測量為進行熱處理而得之界面層及/或進行氧化物成長法而得之化學氧化物。
由熱處理形成之界面層，第5圖中指出不同的實驗條件，包括無氧化環境之組成和溫度。
化學氧化物係由UV增強式氧化物成長法或由濕式臭氧(O3 )/最終去離子水(DIW)清潔(IMEC－clean)而得。
如第5圖所示，只由UV增強式氧化物成長法或只由濕式臭氧(O3 )/最終去離子水(DIW)清潔(IMEC－clean)而得之化學氧化層，不進行熱(預)處理形成界面層，會得到相對較粗糙之氧化層表面。例如，由濕式臭氧(O3 )/最終去離子水(DIW)清潔(IMEC－clean)而得之化學氧化層，其Rms＝0.18 nm，而由UV增強式氧化物成長法而得之化學氧化層，其Rms＝0.14 nm，其中每一次Rms測量之範圍為1×1μm。
相反地，進行H2 /He/1050℃熱處理形成界面層有助於平滑界面層之表面，且當化學氧化層沉積於其上時，對於1×1μm之範圍，Rms值達到0.08~0.09nm，。
再者，低溫處理(例如700℃)將會降低表面平滑度之表現(對於1×1μm之範圍，Rms＝0.146nm)。
如第6圖所示，只進行熱處理，或只有化學氧化物成長，或結合熱處理與化學氧化物成長(UV增強式氧化物標示為UV/Air/Ar/1s)所得之元件的電容對應電壓曲線圖。
電容(MOS)為一種P型基材，其具有TaN/TiN金屬閘極電極。
進行H2 /He/1050℃之熱處理及/或進行UV增強式氧化物成長法，接著藉由40次ALD單層HfO2 沉積循環。
由第6圖得知，只進行UV增強式氧化物成長法會得到非常多縫隙(leakage)，且薄氧化層。
此種多縫隙(leakage)可由形成第一界面層所抑制，不論搭配或不搭配UV增強式氧化物成長法。
第7圖顯示形成薄界面層可能之機制。包括HF－last疏水性處理之清潔步驟，會留下氫原子末端的表面(Si－H鍵，如第7a圖)，此會抑制氧原子自由基與矽上層結合。有水的存在時(潤洗過程中)，溶氧及/或OH－ 自由基可能攻擊內層之Si－Si鍵，而不破壞Si－H鍵，留下SiOx次氧化物於(無氧化物)表面之下。當進行熱處理期間，包含氧化矽與次氧化物(SiOx,0<x≦2)之薄層被揭開(unraveled)於矽表面上(第7b圖)。此薄層是連續的(沒有島狀物形成)，均勻且疏水性，是一種適合介於基材和藉由ALD沉積高介電常數(high－k)材料(例如Hf氧化物)之間的界面層。
因此，依照本發明之方法，產生一均勻超薄界面層， 其位於高介電常數材料(high－k)底下。
依照本發明之方法，能產生均勻且薄的、具有適當的末端(例如OH鍵)之界面層，使其能夠相容於後續高介電常數(high－k)材料之沉積。
再者，實行本發明之方法，能改善界面層之粗糙度與品質。
同時，於本發明之架構下，能增進於半導體元件中的電荷載子遷移率。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
第1圖為一系列流程圖，用以說明依照本發明之方法製備表面的流程。
第2圖為利用角度解析X－光光電子光譜儀(AR－XPS)測量之厚度圖，用以顯示本發明之界面層與用不同方法沉積之高介電常數(high－k)材料HfO2 層之厚度。
第3圖顯示HfO2 覆蓋率相對於氧化物厚度。
第4圖藉由光學測厚儀測量依序形成之氧化層厚度。
第5圖藉由原子力顯微鏡確認表面粗糙度。
第6圖顯示利用不同表面處理而得之電容對應電壓圖。
第7圖顯示形成薄界面層可能之機制。

Claims (22)

  1. 一種高介電常數閘極介電材料的形成方法，包括下列步驟：提供一半導體基材；清洗該基材；對該基材進行一熱處理，其中該熱處理於一無氧化環境中進行，導致形成一薄界面層；以及沉積一高介電常數材料。
  2. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中清洗該基材包括一最終之氫氟酸處理。
  3. 如申請專利範圍第1項或第2項所述之高介電常數閘極介電材料的形成方法，其中該熱處理之溫度約高於700℃。
  4. 如申請專利範圍第1項或第2項所述之高介電常數閘極介電材料的形成方法，其中該熱處理之溫度約高於1000℃。
  5. 如申請專利範圍第1項或第2項所述之高介電常數閘極介電材料的形成方法，其中該熱處理之溫度約高於1050℃。
  6. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中該無氧化環境包括一鈍氣。
  7. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中該無氧化環境包括氦氣及/或氬 氣。
  8. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中更包括加入部分氫氣到該無氧化環境中。
  9. 如申請專利範圍第8項所述之高介電常數閘極介電材料的形成方法，其中該部分氫氣之體積約少於10%。
  10. 如申請專利範圍第8項所述之高介電常數閘極介電材料的形成方法，其中該部分氫氣之體積約介於1%~10%。
  11. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中於該無氧化環境中不包括氮氣。
  12. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中該熱處理之時間約少於2分鐘。
  13. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中該熱處理之時間約少於1分鐘。
  14. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中該熱處理之時間約少於40秒。
  15. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中於該熱處理之後，形成一薄化學氧化層。
  16. 如申請專利範圍第15項所述之高介電常數閘極介電材料的形成方法，其中該薄化學氧化層之形成藉由施加一濕式臭氧(O3 )/最終去離子水(DIW)處理或一UV增強式氧化物成長法(UV-enhanced oxide growth method)。
  17. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中該高介電常數材料為任何一種介電常數值(k)高於二氧化矽之介電材料。
  18. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中該高介電常數材料係藉由原子層沉積法(Atomic Layer Deposition)沉積而得。
  19. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中沉積該高介電常數材料之後，接著進行一沉積後退火處理。
  20. 如申請專利範圍第1項所述之高介電常數閘極介電材料的形成方法，其中該薄界面層之厚度約少於0.6nm。
  21. 一種半導體元件，其包括依照申請專利範圍第1項所述之方法所形成的高介電常數閘極介電材料。
  22. 一種半導體元件，其包括一高介電常數閘極介電材料，其中該高介電常數閘極介電材料包括一約少於0.6nm之薄界面層，且其中該薄界面層的表面具有相容於高介電常數材料之沉積的一官能基末端。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060072680A (ko) * 2004-12-23 2006-06-28 주식회사 하이닉스반도체 반도체 장치의 커패시터 및 그 제조방법
US20110068368A1 (en) * 2009-09-18 2011-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device comprising a honeycomb heteroepitaxy
TWI408822B (zh) * 2009-12-31 2013-09-11 Lu Sheng Hong Thin silicon solar cell and its manufacturing method
US8564066B2 (en) 2010-06-18 2013-10-22 International Business Machines Corporation Interface-free metal gate stack
CN102468152B (zh) * 2010-11-01 2013-12-04 中芯国际集成电路制造(上海)有限公司 栅介质层和晶体管的制作方法
US8735244B2 (en) 2011-05-02 2014-05-27 International Business Machines Corporation Semiconductor device devoid of an interfacial layer and methods of manufacture
US8492290B2 (en) * 2011-06-21 2013-07-23 International Business Machines Corporation Fabrication of silicon oxide and oxynitride having sub-nanometer thickness
CN103295891B (zh) * 2012-03-02 2016-03-16 中芯国际集成电路制造(上海)有限公司 栅介质层的制作方法、晶体管的制作方法
JP2014187238A (ja) * 2013-03-25 2014-10-02 Toyoda Gosei Co Ltd Ｍｉｓ型半導体装置の製造方法
US9281249B2 (en) * 2014-01-15 2016-03-08 Globalfoundries Inc. Decoupling measurement of layer thicknesses of a plurality of layers of a circuit structure
CN104821276B (zh) * 2014-01-30 2018-08-10 中芯国际集成电路制造(上海)有限公司 Mos晶体管的制作方法
US20170358658A1 (en) * 2014-09-26 2017-12-14 Intel Corporation Metal oxide metal field effect transistors (momfets)
JP6456764B2 (ja) * 2015-04-28 2019-01-23 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ 半導体装置の製造方法、基板処理装置およびプログラム
US10727055B2 (en) * 2017-02-10 2020-07-28 International Business Machines Corporation Method to increase the lithographic process window of extreme ultra violet negative tone development resists
US20210193468A1 (en) * 2019-05-03 2021-06-24 Applied Materials, Inc. Treatments To Improve Device Performance
EP4302320A1 (en) * 2021-03-04 2024-01-10 Applied Materials, Inc. Treatments to improve device performance
CN115579279A (zh) 2021-07-06 2023-01-06 联华电子股份有限公司 半导体装置制造过程中的清洁程序方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000059023A1 (en) * 1999-03-26 2000-10-05 Advanced Micro Devices, Inc. Method for fabricating high permitivity dielectric stacks having low buffer oxide
US6245311B1 (en) * 1998-06-09 2001-06-12 Shin-Etsu Handotai Co., Ltd. Method for heat treatment of silicon wafer and silicon wafer
US20020058424A1 (en) * 2000-11-10 2002-05-16 Rotondaro Antonio L. P. Method to improve the uniformity and reduce the surface roughness of the silicon dielectric interface
WO2003041124A2 (en) * 2001-08-31 2003-05-15 Asm International N.V. Method of fabricating a gate stack at low temperature
US20040266117A1 (en) * 2003-06-30 2004-12-30 Hwang Hyun Sang Method of manufacturing high-k gate dielectric by use of annealing in high-pressure hydrogen atmosphere
US20050130442A1 (en) * 2003-12-11 2005-06-16 Visokay Mark R. Method for fabricating transistor gate structures and gate dielectrics thereof
US20050161434A1 (en) * 2002-03-29 2005-07-28 Tokyo Electron Limited Method for forming insulation film
TWI239390B (en) * 1999-11-05 2005-09-11 Axcelis Tech Inc Method for detecting an endpoint for an oxygen free plasma process
TW200604253A (en) * 2004-05-11 2006-02-01 Jsr Corp Method for forming organic silica-based film, organic silica-based film, wiring structure, semiconductor device and composition for forming film
US20060234515A1 (en) * 2003-12-18 2006-10-19 Tokyo Electron Limited Film forming method

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10231196A (ja) * 1996-12-17 1998-09-02 Sony Corp 酸化物積層構造の製造方法および有機金属化学気相成長装置
US20060177987A1 (en) * 1997-05-09 2006-08-10 Bergman Eric J Methods for forming thin oxide layers on semiconductor wafers
US6020024A (en) * 1997-08-04 2000-02-01 Motorola, Inc. Method for forming high dielectric constant metal oxides
US6328809B1 (en) * 1998-10-09 2001-12-11 Scp Global Technologies, Inc. Vapor drying system and method
JP3399413B2 (ja) * 1999-09-13 2003-04-21 日本電気株式会社 酸窒化膜およびその形成方法
US6448192B1 (en) * 2001-04-16 2002-09-10 Motorola, Inc. Method for forming a high dielectric constant material
US6737302B2 (en) * 2001-10-31 2004-05-18 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for field-effect transistor
US6821873B2 (en) * 2002-01-10 2004-11-23 Texas Instruments Incorporated Anneal sequence for high-κ film property optimization
JP3778432B2 (ja) * 2002-01-23 2006-05-24 東京エレクトロン株式会社 基板処理方法および装置、半導体装置の製造装置
DE10240408A1 (de) * 2002-09-02 2004-03-25 Advanced Micro Devices, Inc., Sunnyvale Transistorelement mit einem Anisotropen Gate-Dielektrikum MI großem ε
US6809370B1 (en) * 2003-07-31 2004-10-26 Texas Instruments Incorporated High-k gate dielectric with uniform nitrogen profile and methods for making the same
JP2007500941A (ja) 2003-07-31 2007-01-18 エフエスアイ インターナショナル インコーポレイテッド 高度に均一な酸化物層、とりわけ超薄層の調節された成長
US7075161B2 (en) * 2003-10-23 2006-07-11 Agilent Technologies, Inc. Apparatus and method for making a low capacitance artificial nanopore
FR2864457B1 (fr) * 2003-12-31 2006-12-08 Commissariat Energie Atomique Procede de nettoyage par voie humide d'une surface notamment en un materiau de type silicium germanium.
US20060121742A1 (en) * 2004-12-07 2006-06-08 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US7494852B2 (en) * 2005-01-06 2009-02-24 International Business Machines Corporation Method for creating a Ge-rich semiconductor material for high-performance CMOS circuits
US7393736B2 (en) * 2005-08-29 2008-07-01 Micron Technology, Inc. Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics
JP2007294874A (ja) * 2006-03-31 2007-11-08 Sanyo Electric Co Ltd 半導体装置および半導体装置の製造方法
US7939396B2 (en) * 2006-06-09 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Base oxide engineering for high-K gate stacks
US20080032510A1 (en) * 2006-08-04 2008-02-07 Christopher Olsen Cmos sion gate dielectric performance with double plasma nitridation containing noble gas
US20080237694A1 (en) * 2007-03-27 2008-10-02 Michael Specht Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module
US7855153B2 (en) * 2008-02-08 2010-12-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
EP2786427A4 (en) * 2011-12-01 2016-08-17 Quarkstar Llc SOLID BODY LIGHTING DEVICE AND METHOD OF MANUFACTURING THEREOF
US9018639B2 (en) * 2012-10-26 2015-04-28 Dow Corning Corporation Flat SiC semiconductor substrate

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6245311B1 (en) * 1998-06-09 2001-06-12 Shin-Etsu Handotai Co., Ltd. Method for heat treatment of silicon wafer and silicon wafer
WO2000059023A1 (en) * 1999-03-26 2000-10-05 Advanced Micro Devices, Inc. Method for fabricating high permitivity dielectric stacks having low buffer oxide
TWI239390B (en) * 1999-11-05 2005-09-11 Axcelis Tech Inc Method for detecting an endpoint for an oxygen free plasma process
US20020058424A1 (en) * 2000-11-10 2002-05-16 Rotondaro Antonio L. P. Method to improve the uniformity and reduce the surface roughness of the silicon dielectric interface
WO2003041124A2 (en) * 2001-08-31 2003-05-15 Asm International N.V. Method of fabricating a gate stack at low temperature
US20050161434A1 (en) * 2002-03-29 2005-07-28 Tokyo Electron Limited Method for forming insulation film
US20040266117A1 (en) * 2003-06-30 2004-12-30 Hwang Hyun Sang Method of manufacturing high-k gate dielectric by use of annealing in high-pressure hydrogen atmosphere
US20050130442A1 (en) * 2003-12-11 2005-06-16 Visokay Mark R. Method for fabricating transistor gate structures and gate dielectrics thereof
US20060234515A1 (en) * 2003-12-18 2006-10-19 Tokyo Electron Limited Film forming method
TW200604253A (en) * 2004-05-11 2006-02-01 Jsr Corp Method for forming organic silica-based film, organic silica-based film, wiring structure, semiconductor device and composition for forming film

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