TWI481193B - Electronic device - Google Patents
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Description
本發明是有關於一種電子元件，且特別是有關於一種具有矽控整流器的電子元件。This invention relates to an electronic component, and more particularly to an electronic component having a controlled rectifier.
靜電放電(electrostatic discharge，ESD)往往是造成積體電路發生靜電過度應力(electrostatic overstress)或是永久性損毀的主要原因，因此具有ESD防護能力的電子元件廣泛地應用在各類型的積體電路中。再者，此類型的電子元件通常設有矽控整流器(silicon controlled rectifier，SCR)，以利用矽控整流器可以快速導通的特性來達到ESD防護能力。Electrostatic discharge (ESD) is often the main cause of electrostatic overstress or permanent damage in integrated circuits. Therefore, electronic components with ESD protection are widely used in various types of integrated circuits. . Furthermore, this type of electronic component is usually provided with a silicon controlled rectifier (SCR) to achieve ESD protection by utilizing the characteristics of the step-controlled rectifier that can be quickly turned on.
因應先天條件的限制，具有矽控整流器的電子元件將存在一閂鎖效應(latch-up effect)，進而影響其ESD防護能力。舉例來說，當電子元件因應靜電訊號而觸發其內部矽控整流器時，矽控整流器將進入至一負電阻區，進而提供一電流路徑來導引大量的靜電電流。然而，倘若此時的矽控整流器被閂鎖在負電阻區，則矽控整流器將無法返回至正常的截止區。亦即，此時的矽控整流器將無法正常地切斷其所提供的電流路徑，進而致使電子元件喪失應有的ESD防護能力。Due to the limitations of innate conditions, electronic components with controlled rectifiers will have a latch-up effect, which in turn affects their ESD protection. For example, when an electronic component triggers its internal voltage-controlled rectifier in response to an electrostatic signal, the voltage-controlled rectifier will enter a negative resistance region, thereby providing a current path to direct a large amount of electrostatic current. However, if the step-controlled rectifier at this time is latched in the negative resistance region, the controlled rectifier will not be able to return to the normal cut-off region. That is to say, the current-controlled rectifier at this time will not be able to normally cut off the current path provided by it, thereby causing the electronic component to lose its ESD protection capability.
習知技術通常是利用多個矽控整流器相互疊接在一起的架構，來提高矽控整流器的保持電壓(holding voltage)，進而避免矽控整流器被閂鎖住。然而，此種作法將會導致電子元件之佈局面積與成本的增加。Conventional techniques typically employ an architecture in which a plurality of step-controlled rectifiers are stacked one on another to increase the holding voltage of the step-controlled rectifier, thereby preventing the step-controlled rectifier from being latched. However, such an approach would result in an increase in the layout area and cost of the electronic components.
本發明提供一種電子元件，利用切換單元來致使矽控整流器浮接。如此一來，本發明無須將矽控整流器疊接即可避免矽控整流器被閂鎖住，進而有助於降低電子元件的佈局面積與成本。The present invention provides an electronic component that utilizes a switching unit to cause a controlled rectifier to float. In this way, the invention can avoid the latching of the step-controlled rectifier without the need to stack the step-controlled rectifiers, thereby helping to reduce the layout area and cost of the electronic components.
本發明提出一種電子元件，具有第一端與第二端，並包括控制單元、矽控整流器以及切換單元。控制單元偵測來自電子元件之第一端的正脈衝訊號。此外，當控制單元偵測到正脈衝訊號時，控制單元在一預設時間後產生一重置脈衝。矽控整流器具有第一陽極端、第二陽極端、第一陰極端與第二陰極端。切換單元電性連接電子元件的第一端與第二端以及矽控整流器，並提供多個傳輸路徑。此外，當切換單元接收到重置脈衝時，切換單元切斷這些傳輸路徑，以致使第一陽極端、第二陽極端、第一陰極端與第二陰極端浮接。The invention provides an electronic component having a first end and a second end, and comprising a control unit, a controlled rectifier and a switching unit. The control unit detects a positive pulse signal from the first end of the electronic component. In addition, when the control unit detects a positive pulse signal, the control unit generates a reset pulse after a predetermined time. The tamper rectifier has a first anode end, a second anode end, a first cathode end and a second cathode end. The switching unit electrically connects the first end and the second end of the electronic component and the controlled rectifier, and provides a plurality of transmission paths. Further, when the switching unit receives the reset pulse, the switching unit cuts off the transmission paths such that the first anode end, the second anode end, the first cathode end and the second cathode end float.
在本發明之一實施例中，當上述之切換單元尚未接收到重置脈衝時，切換單元導通這些傳輸路徑，以致使第一陽極端與第二陽極端導通至電子元件的第一端，且第一陰極端與第二陰極端導通至電子元件的第二端。In an embodiment of the present invention, when the switching unit has not received the reset pulse, the switching unit turns on the transmission paths to cause the first anode end and the second anode end to conduct to the first end of the electronic component, and The first cathode end and the second cathode end are electrically connected to the second end of the electronic component.
在本發明之一實施例中，上述之控制單元包括偵測器與延遲器。偵測器用以偵測正脈衝訊號，並在偵測到正脈衝訊號時產生偵測脈衝。延遲器接收偵測脈衝，並將偵測脈衝延遲一預設時間後予以輸出，以作為重置脈衝。In an embodiment of the invention, the control unit includes a detector and a delay. The detector is configured to detect a positive pulse signal and generate a detection pulse when a positive pulse signal is detected. The delay device receives the detection pulse and delays the detection pulse for a predetermined time to output as a reset pulse.
在本發明之一實施例中，上述之偵測器包括第一電阻、第一電容以及反相器。第一電阻的第一端電性連接電子元件的第一端。第一電容的第一端電性連接第一電阻的第二端，且第一電容的第二端電性連接電子元件的第二端。反相器具有輸入端、輸出端、第一電源端與第二電源端。其中，反相器的輸入端電性連接第一電阻的第二端，反相器的輸出端用以產生偵測脈衝，反相器的第一電源端電性連接電子元件的第一端，反相器的第二電源端電性連接電子元件的第二端。In an embodiment of the invention, the detector includes a first resistor, a first capacitor, and an inverter. The first end of the first resistor is electrically connected to the first end of the electronic component. The first end of the first capacitor is electrically connected to the second end of the first resistor, and the second end of the first capacitor is electrically connected to the second end of the electronic component. The inverter has an input end, an output end, a first power end and a second power end. The input end of the inverter is electrically connected to the second end of the first resistor, and the output end of the inverter is used to generate a detection pulse, and the first power end of the inverter is electrically connected to the first end of the electronic component, The second power terminal of the inverter is electrically connected to the second end of the electronic component.
基於上述，本發明是利用切換單元將矽控整流器浮接。如此一來，將可迫使矽控整流器返回截止區，進而避免矽控整流器被閂鎖住。換言之，與習知技術相較之下，本發明無須將矽控整流器疊接即可避免矽控整流器被閂鎖住，因此本發明有助於降低電子元件的佈局面積與成本。Based on the above, the present invention uses a switching unit to float the pilot rectifier. As a result, the controlled rectifier can be forced to return to the cut-off region, thereby preventing the controlled rectifier from being latched. In other words, compared with the prior art, the present invention can prevent the tamper-controlled rectifier from being latched without stacking the tamper-controlled rectifier, and thus the present invention contributes to reducing the layout area and cost of the electronic component.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1為依據本發明之一實施例之電子元件的示意圖。參照圖1，電子元件100具有第一端TM1與第二端TM2，並包括控制單元110、矽控整流器120以及切換單元130。為了說明方便起見，圖1僅繪示出矽控整流器120的等效電路圖，且如圖1所示，矽控整流器120的等效電路包括PNP電晶體MP1、NPN電晶體MN1、電阻R11與電阻R12。此外，矽控整流器120具有第一陽極端121、第二陽極端122、第一陰極端123與第二陰極端124。1 is a schematic diagram of an electronic component in accordance with an embodiment of the present invention. Referring to FIG. 1, the electronic component 100 has a first end TM1 and a second end TM2, and includes a control unit 110, a controlled rectifier 120, and a switching unit 130. For convenience of description, FIG. 1 only shows an equivalent circuit diagram of the 矽 control rectifier 120, and as shown in FIG. 1, the equivalent circuit of the 矽 control rectifier 120 includes a PNP transistor MP1, an NPN transistor MN1, a resistor R11 and Resistor R12. In addition, the voltage controlled rectifier 120 has a first anode end 121, a second anode end 122, a first cathode end 123 and a second cathode end 124.
參照圖1，控制單元110包括偵測器111與延遲器112，且切換單元130包括開關SW1~SW4。其中，偵測器111電性連接電子元件100的第一端TM1與第二端TM2。延遲器112電性連接偵測器111與開關SW1~SW4。此外，切換單元130透過開關SW1~SW4提供多個傳輸路徑。開關SW1電性連接在電子元件100的第一端TM1與矽控整流器120的第一陽極端121之間。開關SW2電性連接在電子元件100的第一端TM1與矽控整流器120的第二陽極端122之間。開關SW3電性連接在電子元件100的第二端TM2與矽控整流器120的第一陰極端123之間。開關SW4電性連接在電子元件100的第二端TM2與矽控整流器120的第二陰極端124之間。Referring to FIG. 1, the control unit 110 includes a detector 111 and a delay 112, and the switching unit 130 includes switches SW1 SW SW4. The detector 111 is electrically connected to the first end TM1 and the second end TM2 of the electronic component 100. The delay device 112 is electrically connected to the detector 111 and the switches SW1 SWSW4. Further, the switching unit 130 provides a plurality of transmission paths through the switches SW1 to SW4. The switch SW1 is electrically connected between the first end TM1 of the electronic component 100 and the first anode end 121 of the step-controlled rectifier 120. The switch SW2 is electrically connected between the first end TM1 of the electronic component 100 and the second anode end 122 of the step-controlled rectifier 120. The switch SW3 is electrically connected between the second end TM2 of the electronic component 100 and the first cathode end 123 of the controlled rectifier 120. The switch SW4 is electrically connected between the second end TM2 of the electronic component 100 and the second cathode end 124 of the controlled rectifier 120.
在說明電子元件100的運作之前，先假設電子元件100應用在一積體電路中。此外，此積體電路包括一焊墊與一接地配線，且電子元件100透過其兩端TM1與TM2串接在焊墊與接地配線之間。在整體運作上，偵測器111會偵測來自電子元件100之第一端TM1的正脈衝訊號。此外，當正脈衝訊號被偵測到時，偵測器111會傳送偵測脈衝PU1至延遲器112。延遲器112將接收偵測脈衝PU1，並將偵測脈衝PU1延遲一預設時間TP後予以輸出，以作為重置脈衝PU2。Before explaining the operation of the electronic component 100, it is assumed that the electronic component 100 is applied in an integrated circuit. In addition, the integrated circuit includes a pad and a ground wire, and the electronic component 100 is connected in series between the pad and the ground wire through the two ends TM1 and TM2. In the overall operation, the detector 111 detects a positive pulse signal from the first end TM1 of the electronic component 100. In addition, when the positive pulse signal is detected, the detector 111 transmits the detection pulse PU1 to the delay 112. The delayer 112 will receive the detection pulse PU1 and delay the detection pulse PU1 for a predetermined time TP to output as the reset pulse PU2.
如此一來，開關SW1~SW4將會依據重置脈衝PU2而斷開其兩端，進而致使矽控整流器120的4個端子121~124維持在浮接(floating)的狀態。換言之，在一般狀態下，矽控整流器120是串接在電子元件100的兩端TM1與TM2之間。然而，當電子元件100的第一端TM1接收到正脈衝訊號時，亦即當靜電事件發生時，控制單元110會先透過偵測器111產生偵測脈衝PU1。此外，當偵測脈衝PU1被延遲一預設時間TP後，亦即當靜電事件發生一段時間後，控制單元110將透過延遲器112輸出重置脈衝PU2至切換單元130，進而致使矽控整流器120的4個端子121~124浮接。As a result, the switches SW1~SW4 will be disconnected from both ends according to the reset pulse PU2, thereby causing the four terminals 121-124 of the step-controlled rectifier 120 to remain in a floating state. In other words, in the normal state, the voltage controlled rectifier 120 is connected in series between the two ends TM1 and TM2 of the electronic component 100. However, when the first terminal TM1 of the electronic component 100 receives the positive pulse signal, that is, when an electrostatic event occurs, the control unit 110 first generates the detection pulse PU1 through the detector 111. In addition, after the detection pulse PU1 is delayed by a predetermined time TP, that is, after a static event occurs for a period of time, the control unit 110 outputs a reset pulse PU2 to the switching unit 130 through the delay device 112, thereby causing the step-up rectifier 120 to be caused. The four terminals 121~124 are floating.
舉例來說，圖2為依據本發明之一實施例的波形時序圖，其中S21為偵測器111的輸出訊號，S22為延遲器112的輸出訊號。如圖2所示，在時間區間T21內，靜電事件尚未發生，因此偵測器111無法偵測到來自電子元件100之第一端TM1的正脈衝訊號。此時，偵測器111不會產生偵測脈衝PU1，進而致使開關SW1~SW4維持在導通的狀態下。藉此，矽控整流器120的第一陽極端121與第二陽極端122將可透過開關SW1與SW2電性連接至電子元件100的第一端TM1，且矽控整流器120的第一陰極端123與第二陰極端124將可透過開關SW3與SW4電性連接至電子元件100的第二端TM2。換言之，在時間區間T21內，矽控整流器120是串接在電子元件100的兩端TM1與TM2之間。For example, FIG. 2 is a waveform timing diagram of an embodiment of the present invention, wherein S21 is an output signal of the detector 111, and S22 is an output signal of the delay unit 112. As shown in FIG. 2, in the time interval T21, the electrostatic event has not occurred, so the detector 111 cannot detect the positive pulse signal from the first terminal TM1 of the electronic component 100. At this time, the detector 111 does not generate the detection pulse PU1, thereby causing the switches SW1 to SW4 to remain in the on state. Thereby, the first anode end 121 and the second anode end 122 of the voltage controlled rectifier 120 electrically connect the permeable switches SW1 and SW2 to the first end TM1 of the electronic component 100, and the first cathode end 123 of the rectifier 120 is controlled. And the second cathode end 124 electrically connects the permeable switches SW3 and SW4 to the second end TM2 of the electronic component 100. In other words, in the time interval T21, the voltage-controlled rectifier 120 is connected in series between the two ends TM1 and TM2 of the electronic component 100.
當靜電事件發生時，偵測器111將會偵測到來自電子元件100之第一端TM1的正脈衝訊號。此時，偵測器111將產生偵測脈衝PU1，且延遲器112會將偵測脈衝PU1延遲一預設時間TP後予以輸出，以作為重置脈衝PU2。值得一提的是，在延遲器112還沒輸出重置脈衝PU2之前，亦即在時間區間T22內，矽控整流器120依舊是串接在電子元件100的兩端TM1與TM2之間。因此，矽控整流器120將會因應正脈衝訊號而從截止區切換至負電阻區，進而提供一電流路徑來將大量的靜電電流導引至接地配線。When an electrostatic event occurs, the detector 111 will detect a positive pulse signal from the first terminal TM1 of the electronic component 100. At this time, the detector 111 will generate the detection pulse PU1, and the delay unit 112 delays the detection pulse PU1 by a predetermined time TP and outputs it as the reset pulse PU2. It is worth mentioning that before the delay 112 has not output the reset pulse PU2, that is, in the time interval T22, the controlled rectifier 120 is still connected in series between the two ends TM1 and TM2 of the electronic component 100. Therefore, the voltage controlled rectifier 120 will switch from the cut-off region to the negative resistance region in response to the positive pulse signal, thereby providing a current path to direct a large amount of electrostatic current to the ground wiring.
此外，在時間區間T22內，矽控整流器120可能會被閂鎖在負電阻區。因此，為了避免上述狀況，當靜電事件發生一段時間後，亦即在時間區間T23內，延遲器112將輸出重置脈衝PU2至切換單元130。此時，切換單元130中的開關SW1~SW4將切換至不導通的狀態，進而致使矽控整流器120的4個端子121~124浮接。如此一來，流經矽控整流器120的電流將逐漸降低至保持電流(holding current)以下，進而致使矽控整流器120從負電阻區返回截止區。之後，當延遲器112停止輸出重置脈衝PU2時，亦即在時間區間T24內，矽控整流器120將又串接在電子元件100的兩端TM1與TM2之間，並維持在截止區中。Further, within the time interval T22, the pilot rectifier 120 may be latched in the negative resistance region. Therefore, in order to avoid the above situation, the delayer 112 will output the reset pulse PU2 to the switching unit 130 after a period of time of the electrostatic event, that is, within the time interval T23. At this time, the switches SW1 SW SW4 in the switching unit 130 will switch to the non-conducting state, thereby causing the four terminals 121 - 124 of the step-controlled rectifier 120 to float. As a result, the current flowing through the pilot rectifier 120 will gradually decrease below the holding current, thereby causing the pilot rectifier 120 to return from the negative resistance region to the cutoff region. Thereafter, when the delay 112 stops outputting the reset pulse PU2, that is, in the time interval T24, the voltage-controlled rectifier 120 is again connected in series between the two ends TM1 and TM2 of the electronic component 100, and is maintained in the cut-off region.
總體而言，切換單元130可透過開關SW1~SW4提供多個傳輸路徑。此外，在一般狀況下，切換單元130無法接收到重置脈衝PU2，因此開關SW1~SW4導通，亦即此時的切換單元130將導通所述多個傳輸路徑。如此一來，矽控整流器120將串接在電子元件100的兩端TM1與TM2之間。相對地，當電子元件100的第一端TM1接收到正脈衝訊號時，亦即當靜電事件發生時，串接在電子元件100之兩端TM1與TM2的矽控整流器120將可導引靜電電流。In general, the switching unit 130 can provide multiple transmission paths through the switches SW1 SW SW4. In addition, under normal conditions, the switching unit 130 cannot receive the reset pulse PU2, and therefore the switches SW1 SW SW4 are turned on, that is, the switching unit 130 at this time will turn on the plurality of transmission paths. As such, the voltage controlled rectifier 120 will be connected in series between the two ends TM1 and TM2 of the electronic component 100. In contrast, when the first terminal TM1 of the electronic component 100 receives the positive pulse signal, that is, when an electrostatic event occurs, the voltage controlled rectifier 120 connected to the TM1 and TM2 at both ends of the electronic component 100 can guide the electrostatic current. .
再者，當靜電事件發生一段時間後，控制單元110將會產生重置脈衝PU2。此時，開關SW1~SW4將不導通，亦即此時的切換單元130將依據重置脈衝PU2切斷所述多個傳輸路徑。如此一來，矽控整流器120的4個端子121~124將浮接，進而迫使矽控整流器120返回截止區。換言之，本實施例無須將矽控整流器120與其它矽控整流器相互疊接，即可避免矽控整流器120被閂鎖住。因此，本實施例將有助於降低電子元件100的佈局面積與成本。Furthermore, the control unit 110 will generate a reset pulse PU2 when a static event occurs for a period of time. At this time, the switches SW1 SW SW4 will not be turned on, that is, the switching unit 130 at this time will cut off the plurality of transmission paths according to the reset pulse PU2. As a result, the four terminals 121-124 of the voltage controlled rectifier 120 will float, thereby forcing the controlled rectifier 120 to return to the cut-off region. In other words, in this embodiment, the step-controlled rectifier 120 and the other step-controlled rectifiers are not overlapped with each other, so that the step-controlled rectifier 120 can be prevented from being latched. Therefore, the present embodiment will contribute to reducing the layout area and cost of the electronic component 100.
為了致使本領域具有通常知識者能更了解本實施例，以下將針對控制單元110的電路結構以及矽控整流器120的佈局結構做更進一步的說明。In order to make the present disclosure more familiar to those skilled in the art, the circuit structure of the control unit 110 and the layout structure of the control rectifier 120 will be further described below.
圖3為依據本發明之一實施例之控制單元的電路示意圖。參照圖3，偵測器111包括電阻R31、電容C31以及反相器IN3，且延遲器112包括電阻R32與電容C32。其中，電阻R31的第一端電性連接電子元件100的第一端TM1。電容C31的第一端電性連接電阻R31的第二端，且電容C31的第二端電性連接電子元件100的第二端TM2。3 is a circuit diagram of a control unit in accordance with an embodiment of the present invention. Referring to FIG. 3, the detector 111 includes a resistor R31, a capacitor C31, and an inverter IN3, and the delay 112 includes a resistor R32 and a capacitor C32. The first end of the resistor R31 is electrically connected to the first end TM1 of the electronic component 100. The first end of the capacitor C31 is electrically connected to the second end of the resistor R31, and the second end of the capacitor C31 is electrically connected to the second end TM2 of the electronic component 100.
此外，反相器IN3具有一輸入端、一輸出端、一第一電源端與一第二電源端。其中，反相器IN3的輸入端電性連接電阻R31的第二端，反相器IN3的輸出端用以產生偵測脈衝PU1，反相器IN3的第一電源端電性連接電子元件100的第一端TM1，且反相器IN3的第二電源端電性連接電子元件100的第二端TM2。再者，就延遲器112來說，電阻R32的第一端電性連接偵測器111，且電阻R32的第二端用以輸出重置脈衝PU2。電容C32的第一端電性連接電阻R32的第二端，且電容C32的第二端電性連接電子元件100的第二端TM2。In addition, the inverter IN3 has an input end, an output end, a first power supply end and a second power supply end. The input end of the inverter IN3 is electrically connected to the second end of the resistor R31, and the output end of the inverter IN3 is used to generate the detecting pulse PU1. The first power end of the inverter IN3 is electrically connected to the electronic component 100. The first end TM1 and the second power end of the inverter IN3 are electrically connected to the second end TM2 of the electronic component 100. Moreover, in the case of the delay device 112, the first end of the resistor R32 is electrically connected to the detector 111, and the second end of the resistor R32 is used to output the reset pulse PU2. The first end of the capacitor C32 is electrically connected to the second end of the resistor R32, and the second end of the capacitor C32 is electrically connected to the second end TM2 of the electronic component 100.
在操作上，當電子元件100的第一端TM1接收到正脈衝訊號時，反相器IN3將被啟動。此外，由於正脈衝訊號的頻率很高，因此由電阻R31與電容C31所組成的低通濾波器將傳送至一低位準訊號至反相器IN3。藉此，反相器IN3將可對應地產生一偵測脈衝PU1，亦即高位準訊號。此外，延遲器112可透過電阻R32與電容C32的阻抗值來調整預設時間的大小。藉此，延遲器112將接收偵測脈衝PU1，並將偵測脈衝PU1延遲一預設時間後予以輸出，以作為重置脈衝PU2。In operation, when the first terminal TM1 of the electronic component 100 receives the positive pulse signal, the inverter IN3 will be activated. In addition, since the frequency of the positive pulse signal is high, the low pass filter composed of the resistor R31 and the capacitor C31 is transmitted to a low level signal to the inverter IN3. Thereby, the inverter IN3 will correspondingly generate a detection pulse PU1, that is, a high level signal. In addition, the delay 112 can adjust the magnitude of the preset time by the impedance value of the resistor R32 and the capacitor C32. Thereby, the delayer 112 will receive the detection pulse PU1 and delay the detection pulse PU1 for a predetermined time to output as the reset pulse PU2.
圖4為依據本發明之一實施例之矽控整流器的剖面示意圖。參照圖4，矽控整流器120包括P型基底410、N型井區421、N+型摻雜區431、P+型摻雜區441、N型井區422、N+型摻雜區432以及P+型摻雜區442。在配置上，N型井區421與N型井區422配置於P型基底410內。N+型摻雜區431與P+型摻雜區441配置於N型井區421內。此外，N+型摻雜區432部分配置於N型井區422內，且P+型摻雜區442配置於P型基底410內。再者，N+型摻雜區431、P+型摻雜區441、N+型摻雜區432與P+型摻雜區442交替配置。4 is a cross-sectional view of a tamper-controlled rectifier in accordance with an embodiment of the present invention. Referring to FIG. 4, the controlled rectifier 120 includes a P-type substrate 410, an N-type well region 421, an N+-type doped region 431, a P+-type doped region 441, an N-type well region 422, an N+-type doped region 432, and a P+ type doping. Miscellaneous area 442. In configuration, the N-type well region 421 and the N-type well region 422 are disposed within the P-type substrate 410. The N+ doping region 431 and the P+ doping region 441 are disposed in the N-type well region 421. In addition, the N+ type doped region 432 is partially disposed in the N-type well region 422, and the P+-type doped region 442 is disposed in the P-type substrate 410. Furthermore, the N+ doping region 431, the P+ doping region 441, the N+ doping region 432, and the P+ doping region 442 are alternately arranged.
請同時參照圖1與圖4。就佈局結構來看，P+型摻雜區441、N型井區421以及P型基底410將形成縱向的PNP電晶體MP1。此外，N型井區421、P型基底410以及N+型摻雜區432將形成橫向的NPN電晶體MN1。此外，電阻R11是N型井區421所貢獻的等效電阻，且電阻R12是P型基底410所貢獻的等效電阻。再者，在電性連接上，N+型摻雜區431電性連接第一陽極端121，P+型摻雜區441電性連接第二陽極端122，N+型摻雜區432電性連接第一陰極端123，且P+型摻雜區442電性連接第二陰極端124。Please refer to FIG. 1 and FIG. 4 at the same time. As far as the layout structure is concerned, the P+ doping region 441, the N-type well region 421, and the P-type substrate 410 will form a longitudinal PNP transistor MP1. In addition, the N-type well region 421, the P-type substrate 410, and the N+-type doped region 432 will form a lateral NPN transistor MN1. Further, the resistor R11 is an equivalent resistance contributed by the N-type well region 421, and the resistor R12 is an equivalent resistance contributed by the P-type substrate 410. Furthermore, in the electrical connection, the N+ doping region 431 is electrically connected to the first anode terminal 121, the P+ doping region 441 is electrically connected to the second anode terminal 122, and the N+ doping region 432 is electrically connected to the first. The cathode terminal 123 and the P+ type doping region 442 are electrically connected to the second cathode terminal 124.
綜上所述，本發明是利用切換單元適時地將矽控整流器的4個端子浮接。如此一來，將可迫使矽控整流器返回截止區，進而避免矽控整流器被閂鎖在負電阻區。換言之，本發明無須將矽控整流器與其它矽控整流器相互疊接，即可避免矽控整流器被閂鎖住。因此，本發明有助於降低電子元件的佈局面積與成本。In summary, the present invention utilizes the switching unit to float the four terminals of the step-controlled rectifier in a timely manner. As a result, the controlled rectifier can be forced to return to the cut-off region, thereby preventing the controlled rectifier from being latched in the negative resistance region. In other words, the present invention eliminates the need for the tamper-controlled rectifier to be overlapped with other 矽-controlled rectifiers to prevent the 矽-controlled rectifier from being latched. Therefore, the present invention contributes to reducing the layout area and cost of electronic components.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100．．．電子元件100. . . Electronic component
TM1．．．第一端TM1. . . First end
TM2．．．第二端TM2. . . Second end
110．．．控制單元110. . . control unit
111．．．偵測器111. . . Detector
112．．．延遲器112. . . Delayer
120．．．矽控整流器120. . . Voltage controlled rectifier
MP1．．．PNP電晶體MP1. . . PNP transistor
MN1．．．NPN電晶體MN1. . . NPN transistor
R11、R12．．．電阻R11, R12. . . resistance
121．．．第一陽極端121. . . First anode end
122．．．第二陽極端122. . . Second anode end
123．．．第一陰極端123. . . First cathode end
124．．．第二陰極端124. . . Second cathode end
130．．．切換單元130. . . Switching unit
SW1~SW4．．．開關SW1~SW4. . . switch
PU1．．．偵測脈衝PU1. . . Detection pulse
PU2．．．重置脈衝PU2. . . Reset pulse
S21．．．偵測器的輸出訊號S21. . . Detector output signal
S22．．．延遲器的輸出訊號S22. . . Delay output signal
T21~T24．．．時間區間T21~T24. . . Time interval
TP．．．預設時間TP. . . Preset time
R31、R32．．．電阻R31, R32. . . resistance
C31、C32．．．電容C31, C32. . . capacitance
IN3．．．反相器IN3. . . inverter
410．．．P型基底410. . . P-type substrate
421、422．．．N型井區421, 422. . . N type well area
431、432．．．N+型摻雜區431, 432. . . N+ doped region
441、442．．．P+型摻雜區441, 442. . . P+ doped region
圖1為依據本發明之一實施例之電子元件的示意圖。1 is a schematic diagram of an electronic component in accordance with an embodiment of the present invention.
圖2為依據本發明之一實施例的波形時序圖。2 is a waveform timing diagram in accordance with an embodiment of the present invention.
圖3為依據本發明之一實施例之控制單元的電路示意圖。3 is a circuit diagram of a control unit in accordance with an embodiment of the present invention.
圖4為依據本發明之一實施例之矽控整流器的剖面示意圖。4 is a cross-sectional view of a tamper-controlled rectifier in accordance with an embodiment of the present invention.
100．．．電子元件100. . . Electronic component
TM1．．．第一端TM1. . . First end
TM2．．．第二端TM2. . . Second end
110．．．控制單元110. . . control unit
111．．．偵測器111. . . Detector
112．．．延遲器112. . . Delayer
120．．．矽控整流器120. . . Voltage controlled rectifier
MP1．．．PNP電晶體MP1. . . PNP transistor
MN1．．．NPN電晶體MN1. . . NPN transistor
R11、R12．．．電阻R11, R12. . . resistance
121．．．第一陽極端121. . . First anode end
122．．．第二陽極端122. . . Second anode end
123．．．第一陰極端123. . . First cathode end
124．．．第二陰極端124. . . Second cathode end
130．．．切換單元130. . . Switching unit
SW1~SW4．．．開關SW1~SW4. . . switch
PU1．．．偵測脈衝PU1. . . Detection pulse
PU2．．．重置脈衝PU2. . . Reset pulse
Claims (8)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6031405A (en) * | 1997-10-07 | 2000-02-29 | Winbond Electronics Corporation | ESD protection circuit immune to latch-up during normal operation |
| US6555878B2 (en) * | 2001-03-14 | 2003-04-29 | Chartered Semiconductor Manufacturing Ltd. | Umos-like gate-controlled thyristor structure for ESD protection |
| US20040100745A1 (en) * | 2002-11-21 | 2004-05-27 | Industrial Technology Research Institute | Silicon-controlled rectifier with dynamic holding voltage for on-chip electrostatic discharge protection |
| US20050286295A1 (en) * | 2004-06-25 | 2005-12-29 | Kapre Ravindra M | Memory cell array latchup prevention |
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2011
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6031405A (en) * | 1997-10-07 | 2000-02-29 | Winbond Electronics Corporation | ESD protection circuit immune to latch-up during normal operation |
| US6555878B2 (en) * | 2001-03-14 | 2003-04-29 | Chartered Semiconductor Manufacturing Ltd. | Umos-like gate-controlled thyristor structure for ESD protection |
| US20040100745A1 (en) * | 2002-11-21 | 2004-05-27 | Industrial Technology Research Institute | Silicon-controlled rectifier with dynamic holding voltage for on-chip electrostatic discharge protection |
| US20050286295A1 (en) * | 2004-06-25 | 2005-12-29 | Kapre Ravindra M | Memory cell array latchup prevention |
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