TWI481002B - Stack package structure and method of forming the same - Google Patents
Stack package structure and method of forming the same Download PDFInfo
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- TWI481002B TWI481002B TW101122749A TW101122749A TWI481002B TW I481002 B TWI481002 B TW I481002B TW 101122749 A TW101122749 A TW 101122749A TW 101122749 A TW101122749 A TW 101122749A TW I481002 B TWI481002 B TW I481002B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- Semiconductor Memories (AREA)
Description
本發明係有關一種半導體封裝件，尤指一種具堆疊結構之封裝件及其製法。The present invention relates to a semiconductor package, and more particularly to a package having a stacked structure and a method of fabricating the same.
早期多晶片封裝結構係為採用並排式(side-by-side)多晶片封裝結構，其係將兩個以上之晶片彼此並排地安裝於一共同基板之主要安裝面。晶片與共同基板上導電線路間之連接一般係藉由導線銲接方式(wire bonding)達成。然而該並排式多晶片封裝構造之缺點為封裝成本太高及封裝結構尺寸太大，因該共同基板之面積會隨著晶片數目的增加而增加。The early multi-chip package structure used a side-by-side multi-chip package structure in which two or more wafers were mounted side by side on a main mounting surface of a common substrate. The connection between the wafer and the conductive traces on the common substrate is typically achieved by wire bonding. However, the side-by-side multi-chip package construction has the disadvantage that the package cost is too high and the package structure size is too large, since the area of the common substrate increases as the number of wafers increases.
為解決上述習知問題，近年來為使用垂直式之堆疊方法來安裝所增加的晶片，其堆疊的方式按照其晶片之設計，打線製程各有不同，但若該晶片被設計為銲墊集中於一邊時，例如記憶卡之電子裝置中所設之快閃記憶體晶片(flash memory chip)或動態隨機存取記憶體晶片(Dynamic Random Access Memory，DRAM)等，為了打線之便利性，其堆疊方式係以交錯式進行。In order to solve the above-mentioned conventional problems, in recent years, in order to install the added wafers by using a vertical stacking method, the stacking method is different according to the design of the wafer, and the wiring process is different, but if the wafer is designed as a bonding pad, One side, for example, a flash memory chip or a dynamic random access memory (DRAM) provided in an electronic device of a memory card, etc., for stacking convenience It is carried out in an interlaced manner.
如第1A及1B圖所示之美國專利第6,538,331號所揭示之交錯式堆疊晶片結構1，係將一第一記憶體晶片11安裝於一承載件10上，再將複數第二記憶體晶片12以一偏移之距離而不妨礙第一記憶體晶片11上之打線作業為原則下呈交錯式堆疊於該第一記憶體晶片11上，且於最上層 之第二記憶體晶片12上設置一控制晶片(controller)13，並透過複數金屬線14,15將該第一、第二記憶體晶片11,12及控制晶片13電性連接至該承載件10。The interleaved stacked wafer structure 1 disclosed in U.S. Patent No. 6,538,331, the first memory wafer 11 is mounted on a carrier 10, and the plurality of second memory chips 12 are mounted. Stacked on the first memory wafer 11 in an interleaved manner on the basis of an offset distance without hindering the wire bonding operation on the first memory wafer 11. A control chip 13 is disposed on the second memory chip 12, and the first and second memory chips 11, 12 and the control wafer 13 are electrically connected to the carrier 10 through the plurality of metal wires 14, 15. .
然而，因一般控制晶片13之平面尺寸係遠小於該記憶體晶片之平面尺寸，故該控制晶片13利用金屬線15作電性連接時，該些金屬線15勢必跨越該控制晶片13下方之第一與第二記憶體晶片11,12，如此極易造成該金屬線15觸碰用以連接該第一及第二記憶體晶片11,12與該承載件10之金屬線14，而發生短路問題，同時亦增加打線作業之困難度。However, since the planar size of the general control wafer 13 is much smaller than the planar size of the memory chip, when the control wafer 13 is electrically connected by the metal wires 15, the metal wires 15 are bound to cross the under the control wafer 13. The first and second memory chips 11, 12 are so easily caused to contact the metal wires 15 for connecting the first and second memory chips 11, 12 and the metal wires 14 of the carrier 10, and a short circuit problem occurs. At the same time, it also increases the difficulty of the wire-laying operation.
於此，業界遂發展出將一控制晶片23置於一承載件20與一第一記憶體晶片21之間的交錯式堆疊晶片結構2，如第2圖所示，並運用膠膜包線(Film over Wire,FOW)技術，使膠體27先設於該第一記憶體晶片21上，再以該具有膠體27之第一記憶體晶片21下放至部分該控制晶片23及其上之金屬線25，以包覆該部分金屬線15，而避免該控制晶片23上之金屬線25受該第一與第二記憶體晶片21,22擠壓而損毀。此外，亦可避免習知連接控制晶片23之金屬線25因打線而誤觸用以連接該第一及第二記憶體晶片21,22與承載件20之金屬線，藉以避免金屬線間短路之問題。Herein, the industry has developed an interleaved stacked wafer structure 2 in which a control wafer 23 is placed between a carrier 20 and a first memory wafer 21, as shown in FIG. 2, and is coated with a film ( The film over wire (FOW) technology is such that the colloid 27 is first disposed on the first memory chip 21, and then the first memory chip 21 having the colloid 27 is lowered onto a portion of the control wafer 23 and the metal line 25 thereon. The portion of the metal line 15 is covered to prevent the metal line 25 on the control wafer 23 from being crushed by the first and second memory chips 21, 22. In addition, it is also possible to prevent the metal wires 25 of the connection control chip 23 from being accidentally touched by the wires for connecting the first and second memory chips 21, 22 and the carrier 20 to avoid short circuit between the wires. problem.
惟，該控制晶片23之平面尺寸係遠小於該第一與第二記憶體晶片21,22之平面尺寸，故該控制晶片23需相對該第一記憶體晶片21之位置偏移放置，以利於該控制晶片 23進行打線製程，卻因而造成該些第一與第二記憶體晶片21,22容易凸出該控制晶片23過多尺寸而傾斜，導致無法進行後續製程，如打線製程，甚至該些第一與第二記憶體晶片21,22會撞擊該承載件20而損壞。However, the planar size of the control wafer 23 is much smaller than the planar dimensions of the first and second memory chips 21, 22. Therefore, the control wafer 23 is placed offset from the first memory chip 21 to facilitate the placement. Control chip 23 performing the wire bonding process, thereby causing the first and second memory chips 21, 22 to easily protrude from the control chip 23 by excessive size and tilting, resulting in failure to perform subsequent processes, such as wire bonding processes, and even the first and the first The two memory wafers 21, 22 will collide with the carrier 20 and be damaged.
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.
鑑於上述習知技術之種種缺失，本發明係提供一種具堆疊結構之封裝件，係包括：一承載件；至少一控制晶片，係接置於該承載件上，且利用複數導線電性連接該承載件；膠體，係形成於該承載件上，以完全包覆該控制晶片；一第一半導體元件，係設置於該膠體上，且該第一半導體元件係藉由複數第一金屬線電性連接該承載件；以及至少一第二半導體元件，係呈錯位方式堆疊於該第一半導體元件上，且該第二半導體元件係藉由複數第二金屬線電性連接該承載件。In view of the above-mentioned various deficiencies of the prior art, the present invention provides a package having a stacked structure, comprising: a carrier; at least one control chip is attached to the carrier, and electrically connected by a plurality of wires a carrier; a colloid is formed on the carrier to completely cover the control wafer; a first semiconductor component is disposed on the colloid, and the first semiconductor component is electrically connected by a plurality of first wires Connecting the carrier; and at least one second semiconductor component is stacked on the first semiconductor component in a dislocation manner, and the second semiconductor component is electrically connected to the carrier by a plurality of second metal wires.
本發明復提供一種具堆疊結構之封裝件之製法，係包括：接置至少一控制晶片於一承載件上，且利用複數導線電性連接該承載件；形成膠體於該承載件上，以完全包覆該控制晶片；設置一第一半導體元件於該膠體上，且該第一半導體元件係藉由複數第一金屬線電性連接該承載件；以及將至少一第二半導體元件呈錯位方式堆疊於該第一半導體元件上，且該第二半導體元件係藉由複數第二金屬線電性連接該承載件。The invention provides a method for manufacturing a package having a stacked structure, comprising: connecting at least one control wafer to a carrier, and electrically connecting the carrier with a plurality of wires; forming a colloid on the carrier to completely Coating the control wafer; disposing a first semiconductor component on the colloid, wherein the first semiconductor component is electrically connected to the carrier by a plurality of first metal wires; and stacking the at least one second semiconductor component in a dislocation manner On the first semiconductor component, the second semiconductor component is electrically connected to the carrier by a plurality of second metal wires.
前述之封裝件及其製法中，該控制晶片之平面尺寸係小於該第一半導體元件之平面尺寸。In the foregoing package and method of manufacturing the same, the planar size of the control wafer is smaller than the planar size of the first semiconductor component.
前述之封裝件及其製法中，該膠體之高度大於該控制晶片之厚度。In the foregoing package and method of manufacturing the same, the height of the gel is greater than the thickness of the control wafer.
前述之封裝件及其製法中，該膠體復包覆部分該導線。In the above package and the method of manufacturing the same, the gel covers a portion of the wire.
前述之封裝件及其製法中，該第一及第二半導體元件係為記憶體晶片。In the above package and method of manufacturing the same, the first and second semiconductor elements are memory chips.
前述之封裝件及其製法中，復包括形成該膠體之前，形成至少一凸塊於該承載件上。In the foregoing package and method of manufacturing the same, at least one bump is formed on the carrier before forming the colloid.
前述之凸塊係為條狀或柱狀，且該第一半導體元件復設置於該凸塊上，又該凸塊之高度係大於該控制晶片之厚度。The bump is formed in a strip shape or a column shape, and the first semiconductor component is disposed on the bump, and the height of the bump is greater than the thickness of the control wafer.
前述之封裝件及其製法中，該錯位形式係為交錯式或階梯式。In the aforementioned package and its manufacturing method, the misalignment form is staggered or stepped.
另外，前述之封裝件及其製法中，復包括形成封裝材於該承載件上，以包覆該控制晶片、第一半導體元件、第二半導體元件、導線、第一及第二金屬線。In addition, in the foregoing package and the method of manufacturing the same, the package material is formed on the carrier to cover the control wafer, the first semiconductor component, the second semiconductor component, the wires, the first and second metal wires.
由上可知，本發明之封裝件及其製法，係藉由該膠體先完全包覆該控制晶片，再放置該第一半導體元件於該膠體上，使該膠體能支撐該第一半導體元件，故相較於習知技術，本發明能克服該些半導體元件相對該控制晶片偏移過多而傾斜之問題，進而避免該些半導體元件撞擊該承載件而損壞之情事。It can be seen that the package of the present invention and the method for manufacturing the same are characterized in that the first semiconductor element is completely coated on the gel by the colloid, and the colloid can support the first semiconductor element. Compared with the prior art, the present invention can overcome the problem that the semiconductor elements are tilted too much with respect to the control wafer, thereby avoiding the damage of the semiconductor elements striking the carrier.
再者，該控制晶片置於晶片結構中之最底層，故於進行打線製程時，導線無需跨越該第一與第二半導體元件，故可避免習知金屬線觸碰記憶體晶片而發生短路之問題，因而能提升產品之可靠度。Furthermore, the control wafer is placed at the bottom of the wafer structure, so that the wire does not need to cross the first and second semiconductor components during the wire bonding process, so that the conventional metal wire can be prevented from being short-circuited by touching the memory chip. Problems can improve the reliability of the product.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.
第3A至3F圖係為本發明之具堆疊結構之封裝件3之製法的剖面示意圖。3A to 3F are schematic cross-sectional views showing the manufacturing method of the package 3 having the stacked structure of the present invention.
如第3A圖所示，接置一控制晶片33於一承載件30上，再形成複數凸塊36於該承載件30上。亦可先形成凸塊36於承載件30上後，再進行控制晶片33之接置製程。As shown in FIG. 3A, a control wafer 33 is attached to a carrier member 30, and a plurality of bumps 36 are formed on the carrier member 30. Alternatively, the bumps 36 may be formed on the carrier 30 before the connection process of the control wafer 33 is performed.
於本實施例中，該承載件30可為一球柵陣列式(BGA)基板、平面柵陣列式(LGA)基板或導線架，且該承載件30具有線路300並定義有置晶區A，以令該些凸塊36圍繞該置晶區A周圍，且該控制晶片33位於該置晶區A內，如第4A及4B圖所示。In this embodiment, the carrier 30 can be a ball grid array (BGA) substrate, a planar gate array (LGA) substrate or a lead frame, and the carrier 30 has a line 300 and defines a crystal area A, The bumps 36 are surrounded around the crystallographic region A, and the control wafer 33 is located in the crystallographic region A, as shown in FIGS. 4A and 4B.
再者，該控制晶片33具有相對之作用面33a與非作用面33b，該作用面33a之四邊均設有複數銲墊330，如第4A及4B圖所示。Furthermore, the control wafer 33 has an opposite active surface 33a and a non-active surface 33b. The active surface 33a is provided with a plurality of pads 330 on four sides thereof, as shown in FIGS. 4A and 4B.
又，該凸塊36,36’係為條狀或柱狀，如第4A及4B圖所示，且該凸塊36,36’之高度h大於該控制晶片33之厚度t。Further, the bumps 36, 36' are strip-shaped or columnar as shown in Figs. 4A and 4B, and the height h of the bumps 36, 36' is larger than the thickness t of the control wafer 33.
另外，形成該些凸塊36,36’之製程係為點膠製程，但並不限於此，且以下製程係以第4A圖之凸塊36為例。Further, the process of forming the bumps 36, 36' is a dispensing process, but is not limited thereto, and the following process is exemplified by the bump 36 of Fig. 4A.
如第3B圖所示，進行打線製程，係以複數導線35電性連接該控制晶片33之銲墊330與該承載件30之線路300(及電性連接墊)。As shown in FIG. 3B, the wire bonding process is performed by electrically connecting the pad 330 of the control chip 33 and the line 300 (and the electrical connection pad) of the carrier 30 with a plurality of wires 35.
於本實施例中，該些導線35係為金屬線，例如金或銅。In this embodiment, the wires 35 are metal wires such as gold or copper.
如第3C圖所示，進行填膠製程，係形成膠體37於該承載件30之置晶區A上，且利用膠膜包線(Filmover Wife,FOW)技術，以完全包覆該控制晶片33，且包覆部分該導線35之端部，例如，使該導線35之頂端包埋於該膠體37中。As shown in FIG. 3C, the filling process is performed to form a colloid 37 on the crystallized area A of the carrier 30, and the film is covered by a Film Over Wife (FOW) technique to completely coat the control wafer 33. And covering a portion of the end of the wire 35, for example, the top end of the wire 35 is embedded in the colloid 37.
於本實施例中，該膠體37之高度L大於該控制晶片33之厚度t。In the present embodiment, the height L of the colloid 37 is greater than the thickness t of the control wafer 33.
再者，該膠體37之高度L等於該凸塊36之高度hMoreover, the height L of the colloid 37 is equal to the height h of the bump 36.
又，該膠體37之材質與該凸塊36之材質可為相同或不同，並無特別限制。Moreover, the material of the colloid 37 and the material of the bump 36 may be the same or different, and are not particularly limited.
另外，藉由該些凸塊36之設計，可防止該膠體37於固化前發生溢膠，以避免該膠體37污染該承載件30上之其他元件或線路300。In addition, by the design of the bumps 36, the colloid 37 can be prevented from overflowing before curing, so as to prevent the colloid 37 from contaminating other components or lines 300 on the carrier 30.
如第3D圖所示，設置一第一半導體元件31於該膠體37與該凸塊36上，且該第一半導體元件31係藉由複數第一金屬線34a電性連接至該承載件30之線路300。As shown in FIG. 3D, a first semiconductor component 31 is disposed on the adhesive body 37 and the bump 36, and the first semiconductor component 31 is electrically connected to the carrier 30 by a plurality of first metal wires 34a. Line 300.
於本實施例中，該控制晶片33之平面尺寸S係小於該第一半導體元件之31平面尺寸W。In this embodiment, the planar size S of the control wafer 33 is smaller than the 31 planar dimension W of the first semiconductor component.
再者，藉由該凸塊36支撐該第一半導體元件31，使該控制晶片33能免受該第一半導體元件31之壓迫而崩壞，且不需等待該膠體37硬化即可設置該第一半導體元件31，以節省工時。Furthermore, the first semiconductor element 31 is supported by the bump 36, so that the control wafer 33 can be prevented from being crushed by the pressing of the first semiconductor element 31, and the first layer can be set without waiting for the gel 37 to be hardened. A semiconductor component 31 to save man-hours.
於其它實施例中，亦可不需設置該凸塊36，但須待該膠體37硬化後，才能設置該第一半導體元件31。In other embodiments, the bump 36 may not be provided, but the first semiconductor component 31 may be disposed after the gel 37 is hardened.
如第3E圖所示，將複數第二半導體元件32呈錯位方式(如圖中之交錯式(Zigzag))堆疊於該第一半導體元件31上，且該第二半導體元件32係藉由複數第二金屬線34b電性連接至該承載件30之線路300。As shown in FIG. 3E, a plurality of second semiconductor elements 32 are stacked in a staggered manner (such as a zigzag pattern) on the first semiconductor element 31, and the second semiconductor element 32 is formed by a plurality of The two metal wires 34b are electrically connected to the line 300 of the carrier 30.
於本實施例中，該第一及第二半導體元件31,32係為記憶體晶片。In the embodiment, the first and second semiconductor elements 31, 32 are memory chips.
再者，由該第一與第二半導體元件31,32所構成之錯 位式堆疊結構3a之位置係對應該置晶區A。Furthermore, the error caused by the first and second semiconductor elements 31, 32 The position of the bit stack structure 3a corresponds to the crystal zone A.
另外，於其它實施例中，該第一半導體元件31與該些第二半導體元件32亦可呈階梯式堆疊。In addition, in other embodiments, the first semiconductor component 31 and the second semiconductor components 32 may also be stacked in a stepwise manner.
如第3F圖所示，形成封裝材38於該承載件30上，以包覆該第一半導體元件31、第二半導體元件32、控制晶片33、凸塊36、導線35、第一及第二金屬線34a,34b。As shown in FIG. 3F, a package 38 is formed on the carrier 30 to cover the first semiconductor component 31, the second semiconductor component 32, the control wafer 33, the bumps 36, the wires 35, the first and the second Metal wires 34a, 34b.
本發明之製法中，先將該膠體37完全包覆該控制晶片33，再放置該第一半導體元件31於該膠體37上，故即使該控制晶片33相對該第一半導體元件31之位置偏移放置，仍可藉由該膠體37支撐該錯位式堆疊結構3a，因而有效克服該錯位式堆疊結構3a相對該控制晶片33偏移過多而傾斜之問題，且能避免該些第一與第二半導體元件31,32撞擊該承載件30而損壞之情事。In the manufacturing method of the present invention, the colloid 37 is completely coated on the control wafer 33, and the first semiconductor component 31 is placed on the colloid 37, so that the position of the control wafer 33 is offset from the first semiconductor component 31. The dislocation stack structure 3a can still be supported by the colloid 37, thereby effectively overcoming the problem that the dislocation stack structure 3a is tilted too much with respect to the control wafer 33, and the first and second semiconductors can be avoided. The elements 31, 32 strike the carrier 30 and are damaged.
再者，藉由先設置控制晶片33，再堆疊其它晶片，故該控制晶片33之作用面33a四邊之銲墊330皆可使用，使該控制晶片33之功能得以完全發揮。Furthermore, by first setting the control wafer 33 and stacking other wafers, the pads 330 on the four sides of the active surface 33a of the control wafer 33 can be used, so that the function of the control wafer 33 can be fully utilized.
又，該控制晶片33置於晶片結構中之最底層，故可縮短導線35之長度，而無需跨越該錯位式堆疊結構3a，因而大幅節省該導線35之使用量，以達到節省材料成本之目的。Moreover, the control wafer 33 is placed at the bottom of the wafer structure, so that the length of the wire 35 can be shortened without crossing the misaligned stack structure 3a, thereby greatly reducing the amount of the wire 35 used to save material cost. .
另外，該控制晶片33於進行打線製程時，因無需跨越該錯位式堆疊結構3a，故可避免習知金屬線觸碰記憶體晶片而發生短路之問題，因而能提升產品之可靠度。In addition, when the control wafer 33 is subjected to the wire bonding process, since it is not necessary to cross the misalignment stack structure 3a, the problem that the conventional metal wire touches the memory chip and short-circuit can be avoided, thereby improving the reliability of the product.
本發明復提供一種具堆疊結構之封裝件3，係包括： 一承載件30、一控制晶片33、膠體37、一第一半導體元件31、複數第二半導體元件32、複數凸塊36,36’以及封裝材38。The present invention provides a package 3 having a stacked structure, comprising: A carrier member 30, a control wafer 33, a colloid 37, a first semiconductor component 31, a plurality of second semiconductor components 32, a plurality of bumps 36, 36', and a package 38.
所述之控制晶片33係接置於該承載件30上，且利用複數導線35電性連接該承載件30，又該控制晶片33之平面尺寸S係小於該第一半導體元件31之平面尺寸W。The control wafer 33 is connected to the carrier 30, and is electrically connected to the carrier 30 by using a plurality of wires 35. The planar size S of the control wafer 33 is smaller than the planar size of the first semiconductor component 31. .
所述之凸塊36,36’係為條狀或柱狀且形成於該承載件30上，又該凸塊36,36’之高度h大於該控制晶片33之厚度t。The bumps 36, 36' are strip-shaped or column-shaped and formed on the carrier 30, and the height h of the bumps 36, 36' is greater than the thickness t of the control wafer 33.
所述之膠體37係形成於該承載件30上，以完全包覆該控制晶片33，且包覆部分該導線35，又該膠體37之高度L大於該控制晶片33之厚度t。The colloid 37 is formed on the carrier 30 to completely cover the control wafer 33 and cover a portion of the wire 35. The height L of the colloid 37 is greater than the thickness t of the control wafer 33.
所述之第一半導體元件31係設置於該凸塊36,36’與膠體37上，且該第一半導體元件31係藉由複數第一金屬線34a電性連接該承載件30，又該第一及第二半導體元件31,32係為記憶體晶片。The first semiconductor component 31 is disposed on the bumps 36, 36' and the colloid 37, and the first semiconductor component 31 is electrically connected to the carrier 30 by a plurality of first metal wires 34a. The first and second semiconductor elements 31, 32 are memory chips.
所述之第二半導體元件32係呈交錯方式堆疊於該第一半導體元件31上，且該第二半導體元件32係藉由複數第二金屬線34b電性連接該承載件30。The second semiconductor component 32 is stacked on the first semiconductor component 31 in a staggered manner, and the second semiconductor component 32 is electrically connected to the carrier 30 by a plurality of second metal wires 34b.
所述之封裝材38係形成於該承載件30上，以包覆該第一半導體元件31、第二半導體元件32、控制晶片33、凸塊36,36’、導線35、第一及第二金屬線34a,34b。The package material 38 is formed on the carrier 30 to cover the first semiconductor component 31, the second semiconductor component 32, the control wafer 33, the bumps 36, 36', the wires 35, the first and the second Metal wires 34a, 34b.
綜上所述，本發明之具堆疊結構之封裝件及其製法，主要藉由該膠體完全包覆該控制晶片，使該膠體能支撐該 第一半導體元件，故能有效克服該半導體元件相對該控制晶片偏移過多而傾斜之問題，且能避免該些半導體元件撞擊該承載件而損壞之情事。In summary, the package with the stacked structure of the present invention and the method for manufacturing the same are mainly used to completely cover the control wafer by the colloid, so that the colloid can support the The first semiconductor component can effectively overcome the problem that the semiconductor component is tilted too much with respect to the control wafer, and can avoid damage caused by the semiconductor components colliding with the carrier.
再者，藉由先設置控制晶片，使該控制晶片之作用面之銲墊皆可使用，故該控制晶片之功能能完全發揮。Furthermore, by first providing the control wafer, the pads of the active surface of the control wafer can be used, so that the function of the control chip can be fully utilized.
又，該控制晶片置於晶片結構中之最底層，係能縮短該導線之長度，而無需跨越錯位式堆疊結構，不僅可大幅節省該導線之使用量，以達到節省材料成本之目的，且於進行打線製程時，可避免金屬線觸碰半導體元件而發生短路之問題，故能提升產品之可靠度。Moreover, the control wafer is placed at the bottom of the wafer structure, which can shorten the length of the wire without crossing the misaligned stack structure, thereby not only greatly saving the use of the wire, but also saving material cost, and When the wire bonding process is performed, the problem that the metal wire touches the semiconductor component and the short circuit occurs can be avoided, so that the reliability of the product can be improved.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
1,2‧‧‧交錯式堆疊晶片結構1,2‧‧‧Interleaved stacked wafer structure
10,20,30‧‧‧承載件10,20,30‧‧‧carriers
11,21‧‧‧第一記憶體晶片11, 21‧‧‧ First memory chip
12,22‧‧‧第二記憶體晶片12,22‧‧‧Second memory chip
13,23,33‧‧‧控制晶片13,23,33‧‧‧Control chip
14,15,25‧‧‧金屬線14,15,25‧‧‧metal wire
27,37‧‧‧膠體27, 37‧‧ ‧ colloid
3‧‧‧具堆疊結構之封裝件3‧‧‧Packages with stacked structures
3a‧‧‧錯位式堆疊結構3a‧‧‧Displacement stacking structure
300‧‧‧線路300‧‧‧ lines
31‧‧‧第一半導體元件31‧‧‧First semiconductor component
32‧‧‧第二半導體元件32‧‧‧Second semiconductor component
33a‧‧‧作用面33a‧‧‧Action surface
33b‧‧‧非作用面33b‧‧‧Non-active surface
330‧‧‧銲墊330‧‧‧ solder pads
34a‧‧‧第一金屬線34a‧‧‧First metal wire
34b‧‧‧第二金屬線34b‧‧‧second metal wire
35‧‧‧導線35‧‧‧Wire
36,36’‧‧‧凸塊36,36’‧‧‧Bumps
38‧‧‧封裝材38‧‧‧Package
L,h‧‧‧高度L, h‧‧‧ height
t‧‧‧厚度T‧‧‧thickness
A‧‧‧置晶區A‧‧‧ crystal zone
S,W‧‧‧平面尺寸S, W‧‧‧ planar size
第1A至1B圖係為係為美國專利第6,538,331號所揭示之交錯式堆疊晶片結構之剖面及平面示意圖；第2圖係為習知交錯式堆疊晶片結構之剖視示意圖；第3A至3F圖係為本發明具堆疊結構之封裝件之製法的剖視示意圖；以及第4A至4B圖係為第3B圖之不同實施例之上視示意圖。1A to 1B are schematic cross-sectional and plan views of the interleaved stacked wafer structure disclosed in U.S. Patent No. 6,538,331; FIG. 2 is a schematic cross-sectional view of a conventional interleaved stacked wafer structure; FIGS. 3A to 3F A schematic cross-sectional view showing a method of manufacturing a package having a stacked structure of the present invention; and FIGS. 4A to 4B are top views of different embodiments of FIG. 3B.
3‧‧‧具堆疊結構之封裝件3‧‧‧Packages with stacked structures
30‧‧‧承載件30‧‧‧Carrier
31‧‧‧第一半導體元件31‧‧‧First semiconductor component
32‧‧‧第二半導體元件32‧‧‧Second semiconductor component
33‧‧‧控制晶片33‧‧‧Control chip
34a‧‧‧第一金屬線34a‧‧‧First metal wire
34b‧‧‧第二金屬線34b‧‧‧second metal wire
35‧‧‧導線35‧‧‧Wire
36‧‧‧凸塊36‧‧‧Bumps
37‧‧‧膠體37‧‧‧colloid
38‧‧‧封裝材38‧‧‧Package
Claims (20)
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| TW200924082A (en) * | 2007-11-30 | 2009-06-01 | Siliconware Precision Industries Co Ltd | Multiple chips stack structure and method for fabricating the same |
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