TWI480881B - One-time programmable memory, electronics system, and method for providing one-time programmable memory - Google Patents
One-time programmable memory, electronics system, and method for providing one-time programmable memory Download PDFInfo
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Description
本發明係有關於一種可編程記憶體元件，特別是記憶體陣列之可編程電阻元件。 The present invention relates to a programmable memory element, particularly a programmable resistive element of a memory array.
可編程電阻元件通常是指元件之電阻狀態可在編程後改變。電阻狀態可以由電阻值來決定。例如，電阻性元件可以是單次性可編程(One-Time Programmable,OTP)元件(如電性熔絲)，而編程方法可以施用高電壓，來產生高電流通過OTP元件。當高電流藉由將編程選擇器導通而流過OTP元件，OTP元件將被燒成高或低電阻狀態(取決於是熔絲或反熔絲)而加以編程。 A programmable resistive element generally means that the resistive state of the component can be changed after programming. The resistance state can be determined by the resistance value. For example, the resistive element can be a One-Time Programmable (OTP) component (such as an electrical fuse), and the programming method can apply a high voltage to generate a high current through the OTP component. When a high current flows through the OTP component by turning the programming selector on, the OTP component will be programmed to be fired in a high or low resistance state (depending on whether it is a fuse or an antifuse).
電性熔絲是一種常見的OTP，而這種可編程電阻元件，可以是多晶矽、矽化多晶矽、矽化物、熱隔離的主動區、金屬、金屬合金或它們的組合。金屬可以是鋁、銅或其他過渡金屬。其中最常用的電性熔絲是矽化的多晶矽，用互補式金氧半導體晶體管(CMOS)的閘極製成，用來作為內連接(interconnect)。電性熔絲也可以是一個或多個接點(contact)或層間接點(via)，而不是小片段的 內連接。高電流可把接點或層間接點燒成高電阻狀態。電性熔絲可以是反熔絲，其中高電壓使電阻降低，而不是提高電阻。反熔絲可由一個或多個接點或層間接點組成，並含有絕緣體於其間。反熔絲也可由CMOS閘極耦合於CMOS本體，其含有閘極氧化層當做為絕緣體。 Electrical fuses are a common type of OTP, and such programmable resistive elements can be polycrystalline germanium, germanium polysilicon, germanium, thermally isolated active regions, metals, metal alloys, or combinations thereof. The metal can be aluminum, copper or other transition metal. The most commonly used electrical fuse is a deuterated polysilicon, made of a gate of a complementary MOS transistor (CMOS), used as an interconnect. Electrical fuses can also be one or more contacts or vias instead of small segments. Internal connection. High current can burn contacts or layers indirectly to a high resistance state. The electrical fuse can be an anti-fuse, where a high voltage reduces the resistance rather than increasing the resistance. The antifuse may be composed of one or more contacts or layer indirect points and has an insulator therebetween. The antifuse can also be coupled to the CMOS body by a CMOS gate that contains a gate oxide layer as an insulator.
一種傳統的可編程電阻式記憶存儲單元如圖1所示。存儲單元10包含電阻元件11和N型金氧半導體晶體管(NMOS)編程選擇器12。電阻元件11一端耦合到NMOS的汲極，另一端耦合到正電壓V+。NMOS 12的閘極耦合到選擇信號SEL，源極耦合到負電壓V-。當高電壓加在V+而低電壓加在V-時，電阻元件10則可被編程，經由提高編程選擇信號SEL來打開NMOS 12。一種最常見的電阻元件是矽化多晶矽，乃是在同時製作MOS閘極時用的同樣材料。NMOS編程選擇器12的面積需要足夠大，以使所需的編程電流可持續幾微秒。矽化多晶矽的編程電流通常是從幾毫安(對寬度約40奈米的熔絲)至20毫安(對寬度約0.6微米熔絲)。因此使用矽化多晶矽的電性熔絲存儲單元往往需有大的面積。 A conventional programmable resistive memory storage unit is shown in FIG. The memory cell 10 includes a resistive element 11 and an N-type MOS transistor (NMOS) programming selector 12. The resistive element 11 is coupled at one end to the drain of the NMOS and at the other end to a positive voltage V+. The gate of NMOS 12 is coupled to select signal SEL and the source is coupled to a negative voltage V-. When a high voltage is applied to V+ and a low voltage is applied to V-, the resistive element 10 can be programmed to turn on the NMOS 12 by raising the program select signal SEL. One of the most common resistive components is deuterated polysilicon, which is the same material used in the fabrication of MOS gates at the same time. The area of the NMOS programming selector 12 needs to be large enough to allow the required programming current to last for a few microseconds. The programming current for deuterated polysilicon is typically from a few milliamps (for a fuse of about 40 nanometers in width) to 20 milliamps (for a fuse of about 0.6 micrometers in width). Therefore, an electrical fuse storage unit using a deuterated polysilicon tends to have a large area.
如圖2a所示，相變記憶體(PCM)是另一種傳統的可編程電阻元件20。PCM存儲單元包含相變材料(Phase Change Material)薄膜21和一個當作編程選擇器的雙極性電晶體22，其具有P+射極23，N型基極27和P型基體為集極25。相變薄膜21一端耦合到雙極性電晶體22的射極23，另一端耦合到正電壓V+。雙極性電晶體22的N型基極27耦合到負電壓V-。集極25耦合到接地。在V+和V-間施加適當且持續適當的時間的電壓，相變薄膜21可被編程成高或低電阻狀態，根據電壓和持續時間而定。按照慣例，編程一個相變 記憶體成高電阻狀態(或重設狀態)大約需要持續50ns的3V電壓，消耗大約300uA的電流。編程相變記憶體成低電阻狀態(或設置狀態)需要持續300ns左右的2V電壓，消耗大約100uA的電流。這種存儲單元需要特殊製程來妥善隔離每個存儲單元，因而需要比標準CMOS邏輯製程多3-4道光罩，而使得它的製作比較貴。 As shown in Figure 2a, phase change memory (PCM) is another conventional programmable resistive element 20. The PCM memory cell includes a phase change material film 21 and a bipolar transistor 22 as a program selector having a P+ emitter 23, the N-type base 27 and the P-type substrate being the collector 25. The phase change film 21 is coupled at one end to the emitter 23 of the bipolar transistor 22 and at the other end to a positive voltage V+. The N-type base 27 of the bipolar transistor 22 is coupled to a negative voltage V-. The collector 25 is coupled to ground. Applying a voltage between V+ and V- for a suitable and continuous period of time, the phase change film 21 can be programmed to a high or low resistance state, depending on the voltage and duration. By convention, programming a phase change The memory is in a high-resistance state (or reset state) requiring approximately 3 volts of continuous voltage of 50 ns, consuming approximately 300 uA of current. Programming the phase change memory into a low-resistance state (or set state) requires a 2V voltage of approximately 300ns and consumes approximately 100uA of current. This type of memory cell requires a special process to properly isolate each memory cell, thus requiring 3-4 more masks than standard CMOS logic processes, making it more expensive to make.
圖2b所示為另一種相變記憶體(PCM)的可編程電阻元件。相變記憶體材料有相變薄膜21'和二極體22'。相變薄膜21'被耦合在二極體陽極22'和正電壓V+之間。二極體的陰極22'被耦合到負電壓V-。施加適當的電壓在V+和V-之間持續一段適當的時間，相變薄膜21'可以被編程為高或低電阻狀態，根據電壓和持續時間而定。請見“Kwang-Jin Lee et al.,“A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput,”International Solid-State Circuit Conference,2007,pp.472-273”，圖2b所示為使用二極體作為相變記憶體(PCM)存儲單元的編程選擇器的例子。雖然這項技術可以減少PCM存儲單元尺寸到只有6.8F2(F代表特徵大小)，二極體需要非常複雜的製造過程，如選擇性磊晶成長(SEG)。如此一來對嵌入式PCM的應用，將變的非常昂貴。 Figure 2b shows a programmable resistive element of another phase change memory (PCM). The phase change memory material has a phase change film 21' and a diode 22'. The phase change film 21' is coupled between the diode anode 22' and the positive voltage V+. The cathode 22' of the diode is coupled to a negative voltage V-. Applying the appropriate voltage between V+ and V- for an appropriate period of time, the phase change film 21' can be programmed to a high or low resistance state, depending on voltage and duration. See "Kwang-Jin Lee et al., "A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput," International Solid-State Circuit Conference, 2007, pp. 472-273", Figure 2b shows An example of a programming selector using a diode as a phase change memory (PCM) memory cell. Although this technology can reduce the size of PCM memory cells to only 6.8F2 (F stands for feature size), diodes require very complex manufacturing processes such as Selective Epitaxial Growth (SEG). As a result, the application of embedded PCM will become very expensive.
圖3a和3b所示為一些從內連接(Interconnect)製作成之電性熔絲元件81和85的實施例。內連接扮演一種特定類型的電阻元件。電阻元件有三個部分：陽極，陰極，和本體。陽極和陰極提供電阻元件的連接到其他部分的電路，使電流可以從陽極流動通過本體到陰極。本體的寬度決定了電流密度，進而決定編程電流的電遷移臨界值。圖3a顯示了一種傳統的電性熔絲元件81，包含陽極80 ，陰極82，和本體83。這實施例有一大型而對稱的陽極和陰極。圖3b顯示了另一種傳統的電性熔絲元件85，包含陽極84，陰極86，和本體87。這實施例有大型陽極和小型陰極的一種非對稱形狀，以根據極性和貯藏效應來提高電遷移效應。極性效應意味著電遷移總是從陰極開始。而貯藏效應的影響是小型陰極可使電遷移比較容易發生。因為當電遷移發生時，較小的面積可有較少的離子可補充空隙。圖3a和3b裏的熔絲元件81和85是相對比較大的結構，這使得它們不適合一些應用。 Figures 3a and 3b show some embodiments of electrical fuse elements 81 and 85 fabricated from interconnects. The inner connection acts as a specific type of resistive element. The resistive element has three parts: the anode, the cathode, and the body. The anode and cathode provide circuitry for the connection of the resistive element to other portions such that current can flow from the anode through the body to the cathode. The width of the body determines the current density, which in turn determines the electromigration threshold for the programming current. Figure 3a shows a conventional electrical fuse element 81 comprising an anode 80 , cathode 82, and body 83. This embodiment has a large and symmetrical anode and cathode. Figure 3b shows another conventional electrical fuse element 85 comprising an anode 84, a cathode 86, and a body 87. This embodiment has an asymmetrical shape of large anodes and small cathodes to increase electromigration effects based on polarity and storage effects. The polarity effect means that electromigration always starts from the cathode. The effect of the storage effect is that small cathodes can make electromigration easier to occur. Because when electromigration occurs, the smaller area can have fewer ions to replenish the void. The fuse elements 81 and 85 in Figures 3a and 3b are relatively large structures which make them unsuitable for some applications.
本發明之一目的為提供使用二極體作為編程選擇器的可編程電阻元件存儲單元，其中可編程的電阻元件可以使用標準CMOS邏輯製程，以減少存儲單元的大小和成本。 It is an object of the present invention to provide a programmable resistive element memory cell that uses a diode as a program selector, wherein the programmable resistive element can be fabricated using standard CMOS logic processes to reduce the size and cost of the memory cell.
依據本發明另一實施例，一種單次性可編程記憶體，包括：多個單次性可編程存儲單元，至少有一單次性可編程存儲單元包括：一單次性可編程元件被耦合到第一電源電壓線；及一二極體包括至少有一第一主動區和一第二主動區，其中該第一主動區具有第一類型摻雜，該第二主動區具擁有第二類型的摻雜，第一主動區域提供該了二極體的一第一端而該第二主動區提供該二極體的一第二端，該第一主動區和該第二主動區二者皆存在一共同的井裏，該第一主動區被耦合到單次性可編程元件，而該第二主動區被耦合到一第二電源電壓線；其中該第一和第二主動區是從互補式金氧半導體晶體管電晶體(CMOS)元件的源極或汲極來製造，而井是從CMOS井來製造。其中，單次性可編程元件被配置為可編程，經由施加電壓到該第一和第二電源電壓線而改變電阻為不同的邏 輯狀態；其中該單次性可編程元件是由電性熔絲構成。 In accordance with another embodiment of the present invention, a single-shot programmable memory includes: a plurality of single-shot programmable memory cells, at least one single-shot programmable memory cell including: a single-shot programmable component coupled to a first power voltage line; and a diode includes at least a first active region and a second active region, wherein the first active region has a first type of doping, and the second active region has a second type of doping The first active region provides a first end of the diode and the second active region provides a second end of the diode, and both the first active region and the second active region are present In a common well, the first active region is coupled to a single-shot programmable component, and the second active region is coupled to a second supply voltage line; wherein the first and second active regions are from a complementary gold A source or a drain of an oxy-semiconductor transistor (CMOS) device is fabricated, and a well is fabricated from a CMOS well. Wherein the single-shot programmable element is configured to be programmable, changing the resistance to a different logic by applying a voltage to the first and second supply voltage lines A state in which the single-time programmable element is composed of an electrical fuse.
依據本發明另一實施例，一種電子系統，包括：一種處理器；及一單次性可編程記憶體可操作地連接到處理器，這單次性可編程記憶體包括至少數個單次性可編程存儲單元來提供數據存儲，每個單次性可編程存儲單元包括：一單次性可編程元件被耦合到第一電源電壓線；及一二極體包含至少一第一主動區和一第二主動區隔離于第一主動區，其中該第一主動區具有第一類型摻雜，該第二主動區具有第二類型摻雜，該第一主動區提供該二極體的第一端，該第二主動區提供該二極體的第二端，該第一和第二主動區二者皆存在一個共同的井裏，該第一主動區被耦合到該單次性可編程元件而該第二主動區被耦合到一第二電源電壓線；其中該第一和第二主動區是從CMOS元件的源極或汲極來製造，而井是從CMOS井來製造的；其中，該單次性可編程元件被配置為可編程，經由施加電壓到該第一和第二電源電壓線而改變單次性可編程元件到不同的邏輯狀態；其中該單次性可編程元件是由電性熔絲構成。 In accordance with another embodiment of the present invention, an electronic system includes: a processor; and a single-shot programmable memory operatively coupled to the processor, the single-shot programmable memory including at least a plurality of singularities a programmable memory cell to provide data storage, each of the one-time programmable memory cells comprising: a single-shot programmable component coupled to the first supply voltage line; and a diode comprising at least one first active region and one The second active region is isolated from the first active region, wherein the first active region has a first type of doping, the second active region has a second type of doping, and the first active region provides a first end of the diode The second active region provides a second end of the diode, and both the first and second active regions are in a common well, the first active region being coupled to the single-shot programmable component The second active region is coupled to a second supply voltage line; wherein the first and second active regions are fabricated from a source or drain of a CMOS device, and the well is fabricated from a CMOS well; wherein Single-shot programmable components are configured to be editable , Via application of a voltage to the first and second power supply voltage line and a single programmable element changes to a different logic state; wherein the single element is composed of an electrically programmable fuse.
依據本發明另一實施例，一種提供單次性可編程記憶體之方法，包括：提供多個單次性可編程存儲單元，至少有一單次性可編程存儲單元包括至少(i)一單次性可編程元件被耦合到第一電源電壓線；及(ii)一二極體包含至少一第一主動區和一第二主動區，該第一主動區具有第一類型摻雜，該第二主動區具有第二類型摻雜，該第一主動區提供該二極體的第一端，該第二主動區提供該二極體的第二端，該第一和第二主動區二者皆從CMOS元件的源極或汲極來製造，並且存在一個共同的井裏，該井是從CMOS 井製造來的，該第一主動區被耦合到該單次性可編程電阻元件而該第二主動區被耦合到一第二個電源電壓線，及經由施加電壓到第一和第二個電壓線，以編程一邏輯狀態到至少一該單次性可編程存儲單元；其中該單次性可編程元件是由電性熔絲構成。 In accordance with another embodiment of the present invention, a method of providing a one-time programmable memory, comprising: providing a plurality of single-shot programmable memory cells, at least one single-shot programmable memory cell comprising at least (i) a single pass The programmable element is coupled to the first supply voltage line; and (ii) a diode includes at least a first active region and a second active region, the first active region having a first type of doping, the second The active region has a second type of doping, the first active region provides a first end of the diode, and the second active region provides a second end of the diode, both the first and second active regions Manufactured from the source or drain of a CMOS component, and there is a common well that is from CMOS Manufactured from the well, the first active region is coupled to the single-shot programmable resistance element and the second active region is coupled to a second supply voltage line, and via applying a voltage to the first and second voltages a line to program a logic state to at least one of the one-time programmable memory cells; wherein the single-shot programmable component is comprised of an electrical fuse.
本發明之可編程電阻性元件記憶體可降低編程電流，且可使用標準CMOS邏輯製程，以減少存儲單元的大小和成本。 The programmable resistive element memory of the present invention can reduce programming current and can use standard CMOS logic processes to reduce the size and cost of the memory cells.
10‧‧‧存儲單元 10‧‧‧ storage unit
11‧‧‧電阻元件 11‧‧‧Resistive components
12‧‧‧NMOS編程選擇器 12‧‧‧ NMOS programming selector
20,20’‧‧‧可編程電阻元件 20,20'‧‧‧Programmable Resistive Components
21,21’‧‧‧相變薄膜 21,21'‧‧‧ phase change film
22‧‧‧雙極性電晶體 22‧‧‧Bipolar transistor
23‧‧‧P+射極 23‧‧‧P+ emitter
27‧‧‧N型基極 27‧‧‧N type base
25‧‧‧集極 25‧‧‧
22'‧‧‧二極體 22'‧‧‧ Diode
81,85‧‧‧電性熔絲元件 81,85‧‧‧Electrical fuse components
80,84‧‧‧陽極 80,84‧‧‧Anode
82,86‧‧‧陰極 82,86‧‧‧ cathode
83,87‧‧‧本體 83,87‧‧‧Ontology
30‧‧‧存儲單元 30‧‧‧storage unit
30a‧‧‧電阻元件 30a‧‧‧resistive components
30b‧‧‧二極體 30b‧‧‧ diode
32,32’,32”‧‧‧二極體 32,32’,32”‧‧‧dipole
33,33’,33”‧‧‧P+主動區 33,33’,33”‧‧‧P+ active zone
34,34’,34”‧‧‧N井 34,34’,34”‧‧‧N Well
37,37’,37”‧‧‧N+主動區 37,37’,37”‧‧N+ active zone
36,36’‧‧‧淺溝槽隔離 36,36’‧‧‧Shallow trench isolation
31',31”‧‧‧主動區 31', 31" ‧ ‧ active area
39’‧‧‧閘極 39’‧‧‧ gate
39”‧‧‧矽化物阻擋層 39"‧‧‧ Telluride barrier
35,35’,35”‧‧‧基體 35,35’,35”‧‧‧ base
45‧‧‧接面二極體 45‧‧‧Connected diode
31-1,31-2,31-3‧‧‧島狀區 31-1, 31-2, 31-3‧‧‧ islands
39-1,39-2,39-3‧‧‧MOS閘極 39-1, 39-2, 39-3‧‧‧ MOS gate
矽區40-1和矽區40-2 4040-1 and 4040-2
33-1,2,3,‧‧‧P+主動區 33-1, 2, 3, ‧‧‧P+ active zone
37-1,2,3‧‧‧N+主動區 37-1, 2, 3‧‧‧N+ active zone
38'‧‧‧P+植入層 38'‧‧‧P+ implant layer
88‧‧‧電性熔絲元件 88‧‧‧Electrical fuse element
89‧‧‧陽極 89‧‧‧Anode
90‧‧‧陰極 90‧‧‧ cathode
91‧‧‧本體 91‧‧‧Ontology
92‧‧‧P+植入層 92‧‧‧P+ implant layer
40,50,60,60’,70,60”,60”’‧‧‧二極體 40, 50, 60, 60', 70, 60", 60" ‧ ‧ ‧ diode
43,44,,51,73,74,64’‧‧‧主動區 43,44,,51,73,74,64’‧‧‧active area
49,59,79‧‧‧STI 49,59,79‧‧‧STI
42,52,62’‧‧‧熔絲元件 42,52,62’‧‧‧Fuse components
46,76‧‧‧金屬 46,76‧‧‧Metal
47,67’,77,67‧‧‧P+植入層 47,67’,77,67‧‧‧P+ implant layer
45,55,75,65’‧‧‧N井 45,55,75,65’‧‧‧N well
54,64,64’‧‧‧周邊主動區 54,64,64’‧‧‧around active area
53,63,63’‧‧‧中央主動區 53,63,63’‧‧‧Central Active Area
58‧‧‧假MOS閘極 58‧‧‧False MOS gate
68‧‧‧環型MOS閘極 68‧‧‧ring MOS gate
68’‧‧‧環型矽化物阻擋層 68'‧‧‧ ring-shaped telluride barrier
71‧‧‧單接點 71‧‧‧ single contact
69‧‧‧第一層金屬熔絲 69‧‧‧First layer of metal fuse
62'‧‧‧陽極 62'‧‧‧Anode
66'‧‧‧第一層金屬本體 66'‧‧‧First metal body
70‧‧‧第一層間接點(via1)熔絲存儲單元 70‧‧‧First indirect point (via1) fuse storage unit
73a,73b‧‧‧N型井接點(主動區) 73a, 73b‧‧‧N type well contact (active area)
79‧‧‧Via1熔絲存儲單元 79‧‧‧Via1 fuse storage unit
79a‧‧‧via1 79a‧‧‧via1
76‧‧‧第一層金屬 76‧‧‧First metal
72‧‧‧第二層金屬 72‧‧‧Second metal
74‧‧‧主動區 74‧‧‧active area
77‧‧‧P+植入層 77‧‧‧P+ implant layer
78‧‧‧STI 78‧‧‧STI
75‧‧‧N井 75‧‧‧N Well
90‧‧‧二維陣列 90‧‧‧Two-dimensional array
91‧‧‧主動區 91‧‧‧active area
96‧‧‧層間接點熔絲存儲單元 96‧‧‧ layer indirect point fuse storage unit
92‧‧‧假CMOS閘極 92‧‧‧False CMOS Gate
99‧‧‧接點 99‧‧‧Contacts
97‧‧‧N+植入層 97‧‧‧N+ implant layer
94‧‧‧P+植入層 94‧‧‧P+ implant layer
100‧‧‧可編程電阻記憶體 100‧‧‧Programmable Resistor Memory
101‧‧‧陣列 101‧‧‧Array
110‧‧‧記憶體存儲單元 110‧‧‧ memory storage unit
111‧‧‧電阻元件 111‧‧‧Resistive components
112‧‧‧二極體 112‧‧‧ diode
150-i‧‧‧字元線驅動器 150-i‧‧‧ character line driver
170-j‧‧‧位元線BLj 170-j‧‧‧ bit line BLj
LWLBi‧‧‧局部字元線 LWLBi‧‧‧local word line
S700-S760,S800-S870‧‧‧步驟 S700-S760, S800-S870‧‧‧ steps
700‧‧‧處理器系統 700‧‧‧Processor System
740‧‧‧記憶體 740‧‧‧ memory
744‧‧‧可編程電阻元件 744‧‧‧Programmable resistance element
742‧‧‧存儲單元陣列 742‧‧‧Memory Cell Array
710‧‧‧中央處理單元 710‧‧‧Central Processing Unit
715‧‧‧共同匯流排 715‧‧‧Common bus
720‧‧‧輸入輸出單元 720‧‧‧Input and output unit
730‧‧‧硬盤驅動器 730‧‧‧ Hard disk drive
750‧‧‧光碟 750‧‧‧DVD
740‧‧‧記憶體 740‧‧‧ memory
760‧‧‧其他記憶體 760‧‧‧Other memory
圖1顯示一傳統的可編程電阻式記憶存儲單元電路圖。 Figure 1 shows a circuit diagram of a conventional programmable resistive memory storage unit.
圖2a顯示相變記憶體(PCM)用的另一傳統可編程電阻式元件電路圖，其採用雙極型晶體管作為編程選擇器。 Figure 2a shows a circuit diagram of another conventional programmable resistive element for phase change memory (PCM) that uses a bipolar transistor as a programming selector.
圖2b顯示一傳統相變記憶體(PCM)電路圖，其採用二極管作為編程選擇器。 Figure 2b shows a conventional phase change memory (PCM) circuit diagram using a diode as a programming selector.
圖3a和3b分別展示從內連接(interconnect)製作的一電性熔絲元件之實施例示意圖。 3a and 3b show schematic views of an embodiment of an electrical fuse element fabricated from an interconnect, respectively.
圖4顯示一方塊圖，其包含根據本發明之使用接面二極體的記憶存儲單元。 Figure 4 shows a block diagram comprising a memory storage unit using junction diodes in accordance with the present invention.
圖5a顯示一接面二極體的橫截面。根據此實施例，二極體用淺溝槽隔離(STI)來隔離陽極和陰極，並當編程選擇器。 Figure 5a shows a cross section of a junction diode. According to this embodiment, the diode is isolated from the anode and cathode by shallow trench isolation (STI) and when the selector is programmed.
圖5b顯示了一接面二極體的橫截面。根據此實施例，二極體用假CMOS閘極來隔離陽極和陰極，並當編程選擇器。圖5c顯示一接面二極體的橫截面。根據此實施例，二極體用矽化阻擋層(SBL)來隔離陽極和陰極，並當編程選擇器。 Figure 5b shows a cross section of a junction diode. According to this embodiment, the diode isolates the anode and cathode with a dummy CMOS gate and when the selector is programmed. Figure 5c shows a cross section of a junction diode. According to this embodiment, the diode is separated from the anode and cathode by a deuteration barrier (SBL) and when the selector is programmed.
圖6a顯示一接面二極體的橫截面。根據此實施例，二極體用絕緣矽基體(SOI)技術裏的假CMOS閘極來隔離陽極和陰極，並當編程選擇器。 Figure 6a shows a cross section of a junction diode. According to this embodiment, the diode is isolated from the anode and cathode by a dummy CMOS gate in an insulating germanium (SOI) technique and when the selector is programmed.
圖6b顯示一接面二極體的橫截面。根據此實施例，此二極體用翅式場效應電晶體(FINFET)技術裏假CMOS閘極來隔離陽極和陰極，並當編程選擇器。 Figure 6b shows a cross section of a junction diode. According to this embodiment, the diode is insulated with a dummy CMOS gate in a fin field effect transistor (FINFET) technique to isolate the anode and cathode, and when programming the selector.
圖7a顯示一電性熔絲元件的一實施例示意圖。 Figure 7a shows a schematic diagram of an embodiment of an electrical fuse element.
圖7b顯示一電性熔絲的頂視圖。此電性熔絲耦合到一個四面都是淺溝槽隔離(STI)的接面二極體。 Figure 7b shows a top view of an electrical fuse. The electrical fuse is coupled to a junction diode that is shallow trench isolation (STI) on all four sides.
圖7c顯示一電性熔絲的頂視圖。此電性熔絲耦合到一個二面是淺溝槽隔離(STI)，而另外二面是假CMOS隔離的接面二極體。 Figure 7c shows a top view of an electrical fuse. The electrical fuse is coupled to a two-sided shallow trench isolation (STI) and the other two sides are dummy CMOS isolated junction diodes.
圖7d顯示一電性熔絲的頂視圖。此電性熔絲耦合到一個四面都是假CMOS隔離的接面二極體。 Figure 7d shows a top view of an electrical fuse. The electrical fuse is coupled to a junction diode that is all four sides are pseudo CMOS isolated.
圖7e顯示一電性熔絲的頂視圖。此電性熔絲耦合到一個四面都是矽化物阻擋層隔離的接面二極體。 Figure 7e shows a top view of an electrical fuse. The electrical fuse is coupled to a junction diode that is isolated on all four sides by a germanide barrier.
圖7f顯示一個接點(contact)耦合在電阻元件和接面二極體的P端接點，而金屬填在同一個單一接點裏。 Figure 7f shows a contact coupled to the P-terminal junction of the resistive element and the junction diode, with the metal filled in the same single contact.
圖8a顯示一金屬熔絲耦合到一接面二極體的頂視圖。此接面二極體四面都是假CMOS閘極隔離。 Figure 8a shows a top view of a metal fuse coupled to a junction diode. This junction diode is surrounded by dummy CMOS gates.
圖8b顯示一金屬熔絲耦合到一接面二極體的頂視圖。此接面二極體有4個存儲單元共用一邊一個的N井接點。 Figure 8b shows a top view of a metal fuse coupled to a junction diode. The junction diode has four memory cells sharing one N-well contact.
圖8c顯示一層間接點熔絲(via fuse)耦合到一接面二極體的頂視圖。此接面二極體有4個存儲單元共用一邊一個的N井接點。 Figure 8c shows a top view of a layer of via fuse coupled to a junction diode. The junction diode has four memory cells sharing one N-well contact.
圖8d顯示一層間接點熔絲二維陣列的頂視圖。這些層間接點熔絲使用P+/N井二極體。 Figure 8d shows a top view of a two-dimensional array of indirect point fuses. These layer indirect fuses use P+/N well diodes.
圖9顯示一可編程電阻式記憶體的一部分。根據此一實施例，由n行和(m+1)列的單二極體存儲單元與n個字元線驅動器一起構成。 Figure 9 shows a portion of a programmable resistive memory. According to this embodiment, a single diode memory cell of n rows and (m+1) columns is constructed with n word line drivers.
圖10a描繪一方法來編程可編程電阻式記憶體的流程圖。 Figure 10a depicts a flow diagram of a method for programming a programmable resistive memory.
圖10b描繪一方法來讀取可編程電阻式記憶體的流程圖。 Figure 10b depicts a flow diagram of a method for reading a programmable resistive memory.
圖11顯示一種處理器(Processor)的系統的實施例示意圖。 Figure 11 shows a schematic diagram of an embodiment of a system of processors.
在本發明之實施例中，P+/N井接面二極體係作為可編程電阻式元件的編程選擇器。此二極體可以包括在N井裏的P+和N+主動區(Active regions)。由於P+和N+主動區和N井都是以現成的標準CMOS邏輯製程，這些元件可用有效率及符合成本效益的方法做成，且不須額外的光罩或製程步驟以節省成本。這可編程電阻式元件可以包括在電子系統裏。 In an embodiment of the invention, the P+/N well junction diode system acts as a programming selector for the programmable resistive component. This diode can include P+ and N+ active regions in the N well. Since the P+ and N+ active regions and the N-well are both off-the-shelf standard CMOS logic processes, these components can be fabricated in an efficient and cost-effective manner without the need for additional masks or process steps to save cost. This programmable resistive element can be included in an electronic system.
圖4所示為依據一實施例的使用接面二極體的記憶體存儲單元30的方塊圖。特別是，存儲單元30包括電阻元件30a和二極體30b。電阻元件30a可耦合在接面二極體30b的陽極和正電壓V+之間。接面二極體30b的陰極可耦合到負電壓V-。在一實施例裏，記憶體存儲單元30可以是熔絲存儲單元，且包含作為電性熔絲的電阻元 件30a。接面二極體30b可以作為編程選擇器。接面二極體可以從使用P型基體的標準CMOS製程的P+/N井來製作。作為二極體陽極和陰極的P+和N+主動區就是CMOS元件的源極或汲極。N井就是用來嵌入PMOS元件的CMOS井。另外，接面二極體可以由使用N型基體的CMOS製程裏的N+/P井來構造。電阻元件30a和接面二極體30b於電源電壓V+和V-之間的連接方式是可互換的。經由一適當的時間裏施加適當的電壓(其在V+和V-之間)，電阻元件30a可根據電壓和持續時間被編程為高或低電阻狀態，因此編程記憶體存儲單元30可存儲數據值(例如，數據的位元)。二極體的P+和N+主動區可以使用假CMOS閘極，淺溝槽隔離(STI)，局部氧化(LOCOS)，或矽化物阻擋層(SBL)來隔離。如果沒有矽化物靠近第一和第二主動區的邊界，第一和第二個主動區可以對接(butted)或用摻雜低劑量的主動區來分隔這兩種主動區。 4 is a block diagram of a memory storage unit 30 using junction diodes in accordance with an embodiment. In particular, the memory unit 30 includes a resistive element 30a and a diode 30b. The resistive element 30a can be coupled between the anode of the junction diode 30b and a positive voltage V+. The cathode of junction diode 30b can be coupled to a negative voltage V-. In an embodiment, the memory storage unit 30 may be a fuse storage unit and include a resistance element as an electrical fuse. Piece 30a. Junction diode 30b can be used as a programming selector. The junction diode can be fabricated from a standard CMOS process P+/N well using a P-type substrate. The P+ and N+ active regions as the diode anode and cathode are the source or drain of the CMOS component. Well N is a CMOS well used to embed PMOS components. Alternatively, the junction diode can be constructed from an N+/P well in a CMOS process using an N-type substrate. The connection between the resistive element 30a and the junction diode 30b between the supply voltages V+ and V- is interchangeable. By applying an appropriate voltage (between V+ and V-) over a suitable time, the resistive element 30a can be programmed to a high or low resistance state depending on the voltage and duration, so the programmed memory storage unit 30 can store the data value. (for example, the bit of data). The P+ and N+ active regions of the diode can be isolated using a dummy CMOS gate, shallow trench isolation (STI), local oxidation (LOCOS), or a germanide barrier layer (SBL). If no germanide is near the boundary of the first and second active regions, the first and second active regions may be butted or doped with a low dose active region to separate the active regions.
電性熔絲的存儲單元可以作為說明關鍵實現概念的範例。圖5a顯示二極體32的橫截面，在可編程電阻元件裏使用淺溝槽隔離的P+/N井二極體做為編程選擇器。分別構成二極體32的P和N終端的P+主動區33和N+主動區37就是在標準CMOS邏輯製程裏的PMOS和NMOS的源極或汲極。N+主動區37被耦合到N井34，此N井在標準CMOS邏輯製程裏嵌入PMOS。淺溝槽隔離36隔離不同元件的主動區。電阻元件(沒有顯示在5a圖)，如電性熔絲，可以一端耦合到P+主動區33而另一端耦合到高電壓電源V+。為了編程這種可編程電阻式元件，高電壓加在V+，低電壓或地電位施加到N+主動區37。因此，高電流過熔絲元件和二極體32來編程電阻元件。 The storage unit of the electrical fuse can be used as an example to illustrate the key implementation concepts. Figure 5a shows a cross section of a diode 32 in which a shallow trench isolated P+/N well diode is used as a programming selector in a programmable resistive element. The P+ active region 33 and the N+ active region 37, which respectively constitute the P and N terminals of the diode 32, are the source or drain of the PMOS and NMOS in a standard CMOS logic process. The N+ active region 37 is coupled to an N-well 34 that embeds a PMOS in a standard CMOS logic process. Shallow trench isolation 36 isolates the active regions of the different components. A resistive element (not shown in Figure 5a), such as an electrical fuse, can be coupled to the P+ active region 33 at one end and to the high voltage power supply V+ at the other end. To program such a programmable resistive component, a high voltage is applied to V+, a low voltage or ground potential is applied to the N+ active region 37. Therefore, a high current is passed through the fuse element and the diode 32 to program the resistive element.
圖5b顯示了另一接面二極體32’實施例的一截面圖，其當做編程 選擇器並以假CMOS閘極隔離。淺溝槽隔離36'提供其他主動區的隔離。主動區31'係以淺溝槽隔離36'來加以定義。這裡的N+和P+主動區37'和33'進一步分別由假CMOS閘極39'、P+植入層38'和N+植入層(P+植入層38'之互補)混合來加以定義，構成二極體32'的N和P端。該二極體32’被製作成類似PMOS的元件，且包含了37'、39'、33'及34'作為源極、閘極、汲極和N井，除了源極37’上覆蓋有N+植入層，而非真正的PMOS所覆蓋的P+植入層38'。假MOS閘極39'最好是偏壓在一固定的電壓，其目的為在製作過程中當作P+主動區33'和N+主動區37'之間的隔離。N+主動區37'被耦合到N井34'，此井在標準CMOS邏輯製程裏是嵌入PMOS的本體。P基體35'是P型矽的基體。電阻元件(圖5b中沒有顯示)，如電性熔絲，可以一端被耦合到P+區33'而另一端被耦合到一高電壓電源V+。為了編程這種可編程電阻元件，高電壓施加在V+，而低電壓或接地到N+主動區37'。因此，高電流流過熔絲元件與二極體32’來編程電阻元件。這實施例有理想的小尺寸和低電阻。 Figure 5b shows a cross-sectional view of another junction diode 32' embodiment as programming The selector is isolated with a dummy CMOS gate. Shallow trench isolation 36' provides isolation of other active regions. The active region 31' is defined by a shallow trench isolation 36'. Here, the N+ and P+ active regions 37' and 33' are further defined by a mixture of a dummy CMOS gate 39', a P+ implant layer 38', and an N+ implant layer (complementary to the P+ implant layer 38'), respectively. N and P ends of the polar body 32'. The diode 32' is fabricated as a PMOS-like component and includes 37', 39', 33', and 34' as source, gate, drain, and N wells, except that the source 37' is covered with N+ The implant layer, rather than the P+ implant layer 38' covered by a true PMOS. The dummy MOS gate 39' is preferably biased at a fixed voltage for the purpose of isolation between the P+ active region 33' and the N+ active region 37' during fabrication. The N+ active region 37' is coupled to the N-well 34', which is a body embedded in the PMOS in a standard CMOS logic process. The P substrate 35' is a matrix of P-type germanium. A resistive element (not shown in Figure 5b), such as an electrical fuse, can be coupled to P+ region 33' at one end and to a high voltage supply V+ at the other end. To program such a programmable resistive element, a high voltage is applied to V+ and a low voltage or ground is applied to the N+ active region 37'. Therefore, a high current flows through the fuse element and the diode 32' to program the resistance element. This embodiment has an ideal small size and low resistance.
圖5c所示另一實施例的橫截面，其中接面二極體32”以矽化物阻擋層(SBL)39”隔離並作為編程選擇器。圖5c類似圖5b，然而在圖5b裏的假CMOS閘極39’被圖5c裏的矽化物阻擋層39“所取代，以阻止矽化物生長在主動區31“的頂部。如果沒有假CMOS閘極或矽化物阻擋層，N+和P+主動區將由主動區域31“表面的矽化物而被短路。 A cross-section of another embodiment, shown in Figure 5c, in which the junction diode 32" is isolated by a telluride barrier (SBL) 39" and serves as a programming selector. Figure 5c is similar to Figure 5b, however the dummy CMOS gate 39' in Figure 5b is replaced by a telluride blocking layer 39" in Figure 5c to prevent the growth of germanide on top of the active region 31". If there is no dummy CMOS gate or germanium blocking layer, the N+ and P+ active regions will be shorted by the germanium on the surface of the active region 31.
圖6a所示另一實施例的橫截面，其中接面二極體32”被當編程選擇器，並採用絕緣矽基體(SOI)的技術。在SOI技術中，基體 35"是如二氧化矽或類似材料的絕緣體，此絕緣體包含薄層矽生長在頂部。所有NMOS和PMOS都在矽井裏，由二氧化矽或類似的材料隔離彼此和基體35"。一整件(one-piece)主動區31"經由假CMOS閘極39’、P+植入層38”和N+植入層(P+植入層38”之互補)的混合分為N+主動區37"、P+主動區33"和本體34"。因此N+主動區37"和P+主動區33"分別構成接面二極體32”的N端和P端。N+主動區37"及P+主動區33"可以分別和標準CMOS邏輯製程裏NMOS和PMOS的源極或汲極相同。同樣，假CMOS閘極39‘可以和標準CMOS製程建構的CMOS閘極相同。假MOS閘極39’可以偏壓在一固定的電壓，其目的為在製作過程中當作P+主動區33”和N+主動區37”之間的隔離。N+主動區37”被耦合到低電壓V-和N井34，此N井在標準CMOS邏輯製程裏是嵌入PMOS的本體。電阻元件(圖6a中沒有顯示)，如電性熔絲，可以一端被耦合到P+主動區33”而另一端被耦合到高電壓電源V+。為了編程這種電性熔絲存儲單元，高和低電壓分別施加在V+和V-，導通大電流流過熔絲元件與接面二極體32”來編程電阻元件。CMOS隔離技術的其他實施例，如淺溝槽隔離(STI)，假CMOS閘極，或矽化物阻擋層(SBL)在一至四邊或任何一邊，可以很容易應用到相應的CMOS SOI技術。 Figure 6a shows a cross section of another embodiment in which the junction diode 32" is used as a programming selector and employs a technique of insulating germanium (SOI). In SOI technology, the substrate The 35" is an insulator such as cerium oxide or the like, which contains a thin layer of germanium grown on top. All NMOS and PMOS are in the well, separated from each other and the substrate 35" by cerium oxide or the like. A one-piece active region 31" is divided into N+ active regions 37" by a mixture of a dummy CMOS gate 39', a P+ implant layer 38", and a complement of the N+ implant layer (P+ implant layer 38). , P + active area 33" and body 34". Therefore, the N+ active region 37" and the P+ active region 33" respectively constitute the N terminal and the P terminal of the junction diode 32". The N+ active region 37" and the P+ active region 33" can respectively be combined with the NMOS and PMOS in the standard CMOS logic process. The source or drain is the same. Similarly, the dummy CMOS gate 39' can be the same as the CMOS gate constructed in a standard CMOS process. The dummy MOS gate 39' can be biased at a fixed voltage for the purpose of fabrication. As the isolation between the P+ active region 33" and the N+ active region 37", the N+ active region 37" is coupled to the low voltage V- and N wells 34, which are embedded in the PMOS body in a standard CMOS logic process. A resistive element (not shown in Figure 6a), such as an electrical fuse, can be coupled to the P+ active region 33" at one end and to the high voltage supply V+ at the other end. To program such an electrical fuse storage unit, Gaohe The low voltage is applied to V+ and V-, respectively, and a large current is passed through the fuse element and the junction diode 32" to program the resistance element. Other embodiments of CMOS isolation techniques, such as shallow trench isolation (STI), dummy CMOS gates, or germanium blocking layers (SBL) on one to four sides or on either side, can be readily applied to corresponding CMOS SOI technologies.
圖6b顯示另一接面二極體45實施例的一截面圖，該接面二極體45為使用翅式場效應電晶體(FinFET)技術的編程選擇器。FinFET是指翅式(FIN)為基本的多閘極電晶體。FinFET技術類似傳統的CMOS，但是具有高瘦矽島，其升高在矽基體上以作為CMOS元件的主體。主體像傳統CMOS，分為源極，汲極和多晶矽或非鋁金屬閘 極的通道。主要的區別是在FinFET技術中，MOS元件的本體被提升到基板之上，島狀區的高度即是通道的寬度，然而電流的流動方向仍然是在平行於矽的表面。圖6b顯示FinFET技術的一例子，矽基體35是個外延層，建在類似SOI絕緣層或其他高電阻矽基體之上。矽基體35可以被蝕刻成幾個高大的長方形島狀區31-1、31-2和31-3。經由適當的閘極氧化層成長，島狀區31-1、31-2及31-3可分別以MOS閘極39-1、39-2和39-3來覆蓋升高的島狀區的兩邊及定義源極和汲極區。源極和汲極區形成於島狀區31-1、31-2及31-3，然後填充矽，如填充於矽區40-1和矽區40-2，讓合併的源極和汲極面積大到足以放下接點。在圖6b中，矽區40-1和矽區40-2的填充區域只是用來說明及顯露橫截面，例如填充區域可以填充到島狀區31-1、31-2和31-3的表面。在此實施例，主動區33-1,2,3和37-1,2,3被P+植入層38'和N+植入層(P+植入層38'之互補)分別覆蓋來構成接面二極體45的P和N端，而不是像傳統FinFET的PMOS全部被P+植入層38'覆蓋。N+主動區37-1,2,3被耦合到低電壓電源V-。電阻元件(圖6b中沒有顯示)，如電性熔絲，一端被耦合到P+主動區33-1,2,3，另一端被耦合到高電壓電源V+。為了編程這種電性熔絲，高和低電壓分別施加在V+和V-上，以導通大電流流過電阻元件與接面二極體45，來編程電阻元件。CMOS主體技術隔離的其他實施例，如淺溝槽隔離(STI)、假CMOS閘極或矽化物阻擋層(SBL)，可以很容易應用到相應的FinFET技術。 Figure 6b shows a cross-sectional view of another embodiment of a junction diode 45 that is a programming selector using a fin field effect transistor (FinFET) technology. FinFET is a basic multi-gate transistor with a fin (FIN). The FinFET technology is similar to conventional CMOS, but has a high thin island that is raised on the germanium substrate to serve as the body of the CMOS component. The main body is like a traditional CMOS, divided into source, bungee and polysilicon or non-aluminum metal gates. Extreme passage. The main difference is that in FinFET technology, the body of the MOS device is lifted onto the substrate. The height of the island is the width of the channel, but the direction of current flow is still parallel to the surface of the crucible. Figure 6b shows an example of a FinFET technique in which the germanium substrate 35 is an epitaxial layer built on top of an SOI insulating layer or other high resistance germanium substrate. The ruthenium substrate 35 can be etched into several tall rectangular island regions 31-1, 31-2, and 31-3. The island regions 31-1, 31-2, and 31-3 can cover both sides of the raised island region with MOS gates 39-1, 39-2, and 39-3, respectively, through the growth of the appropriate gate oxide layer. And define the source and drain regions. The source and drain regions are formed in island regions 31-1, 31-2, and 31-3, and then filled with germanium, such as filled in germanium 40-1 and germanium 40-2, allowing the combined source and drain The area is large enough to put down the joint. In Fig. 6b, the filling regions of the crotch region 40-1 and the crotch region 40-2 are only used to illustrate and reveal the cross section, for example, the filling region may be filled to the surfaces of the island regions 31-1, 31-2 and 31-3. . In this embodiment, the active regions 33-1, 2, 3 and 37-1, 2, 3 are respectively covered by the P+ implant layer 38' and the N+ implant layer (the complement of the P+ implant layer 38') to form the junction. The P and N terminals of diode 45, rather than the PMOS like a conventional FinFET, are all covered by P+ implant layer 38'. The N+ active regions 37-1, 2, 3 are coupled to a low voltage power supply V-. Resistive elements (not shown in Figure 6b), such as electrical fuses, are coupled at one end to P+ active regions 33-1, 2, 3 and at the other end to a high voltage supply V+. To program such an electrical fuse, high and low voltages are applied across V+ and V-, respectively, to conduct a large current through the resistive element and junction diode 45 to program the resistive element. Other embodiments of CMOS body technology isolation, such as shallow trench isolation (STI), dummy CMOS gate or germanium blocking layer (SBL), can be readily applied to the corresponding FinFET technology.
圖7a為根據另一實施例的電性熔絲元件88的頂視圖。這電性熔絲元件88可以如圖4所示當作為電阻元件使用。電性熔絲元件88包 括陽極89、陰極90及本體91。在此實施例，電性熔絲元件88是棒狀且包含大的陽極89和小的陰極90來減少陰極面積。陽極89和陰極90可從本體91突出來以形成接點。陽極89和陰極90接點的數量可以是一個，以使面積非常小。然而，陽極89接點面積往往較大，這樣陽極89比陰極90大，可使陽極89能更抗拒電遷移。熔絲的本體91可以有0.5-6個方形，就是長度與寬度的比例約為6到0.5，來達到存儲單元面積和編程電流的最佳化。熔絲元件88有P+植入層92覆蓋本體91的一部分和陰極90，而N+植入層覆蓋其餘的面積。當在頂部矽化物因電遷移、離子擴散和矽化物分解等其他效應耗盡時，這實施例使得熔絲元件88表現像反向偏壓二極體來增加編程後電阻。為了使記憶體單元變小，同時降低了整體傳導路徑的電阻，在可編程電阻元件或二極管的接點，可以在一個記憶體單元內不超過兩個。同樣，可編程電阻元件或二極管的接點面積可以大於記憶體陣列以外的接點。 Figure 7a is a top view of an electrical fuse element 88 in accordance with another embodiment. This electrical fuse element 88 can be used as a resistive element as shown in FIG. Electrical fuse element 88 package The anode 89, the cathode 90 and the body 91 are included. In this embodiment, the electrical fuse element 88 is rod shaped and includes a large anode 89 and a small cathode 90 to reduce the cathode area. The anode 89 and the cathode 90 may protrude from the body 91 to form a joint. The number of contacts of the anode 89 and the cathode 90 may be one to make the area very small. However, the anode 89 junction area tends to be larger, such that the anode 89 is larger than the cathode 90, allowing the anode 89 to be more resistant to electromigration. The body 91 of the fuse may have a width of 0.5-6 squares, that is, a ratio of length to width of about 6 to 0.5 to optimize the memory cell area and programming current. The fuse element 88 has a P+ implant layer 92 covering a portion of the body 91 and the cathode 90, while the N+ implant layer covers the remaining area. This embodiment causes the fuse element 88 to behave like a reverse biased diode to increase the post-programmable resistance when the top telluride is depleted by other effects such as electromigration, ion diffusion, and hydrazine decomposition. In order to make the memory cell smaller and reduce the resistance of the overall conduction path, the contact point of the programmable resistance element or diode can be no more than two in one memory cell. Similarly, the contact area of the programmable resistive element or diode can be larger than the contacts outside the memory array.
可實現上述實施例的電性熔絲元件包含了多晶矽、多晶矽矽化、熱隔離的主動區、局部互連(Local Interconnect)或其他CMOS閘極材料。特別是一些電性熔絲元件允許P+和N+植入後可以在編程後創建出二極體，如多晶矽、隔熱隔離的主動區或金屬閘CMOS的閘。例如，如果金屬閘極CMOS具有多晶矽在金屬合金層之間的三明治結構，金屬合金層可以被由佈局產生的光罩阻擋，以在熔絲元件裏產生二極體。在SOI或如SOI的製程裏，電性熔絲也可以從熱隔離的主動區來構造。在熱隔離主動區的兩端，這樣的熔絲可以被植入N+、P+、或N+和P+摻雜。此熔絲如果一部分被植入N+摻雜和一部分P+摻雜，當頂部的矽化物被編程後耗盡，熔絲可以形 成像反向偏壓的二極體。依此方式構建的熔絲元件，熔絲可以被合併成二極體主動區的一部分，使熔絲和二極體形成在一單一的主動區以省面積。有一些製程可以提供局部互連，這是由矽化物製造過程中的副產品可和多晶矽與主動區直接互連以省接點。如此，電性熔絲元件可以和二極體的主動區直接連接而沒有任何接點，以節省面積。在CMOS的製程裏建構電性熔絲元件有很多變化，上述的討論是用於說明目的，其變化及其組合的一部分，都是實施例而落入本發明的範圍。 The electrical fuse element that can implement the above embodiments includes polysilicon, polysilicon, thermally isolated active regions, local interconnects, or other CMOS gate materials. In particular, some electrical fuse components allow P+ and N+ implants to create diodes after programming, such as polysilicon, thermally isolated active regions, or gated CMOS gates. For example, if the metal gate CMOS has a sandwich structure of polysilicon between the metal alloy layers, the metal alloy layer can be blocked by a mask created by the layout to create a diode in the fuse element. In SOI or processes such as SOI, electrical fuses can also be constructed from thermally isolated active regions. At both ends of the thermally isolated active region, such fuses can be implanted with N+, P+, or N+ and P+ doping. If a portion of the fuse is implanted with N+ doping and a portion of P+ doping, the fuse can be shaped when the top germanide is programmed to be depleted. Imaging a reverse biased diode. In the fuse element constructed in this way, the fuses can be combined into a part of the active region of the diode, so that the fuse and the diode are formed in a single active area to save area. There are processes that provide local interconnects that can be directly interconnected with the active region by the by-products of the telluride manufacturing process to save points. In this way, the electrical fuse element can be directly connected to the active area of the diode without any contacts to save area. There are many variations in the construction of electrical fuse elements in the CMOS process. The above discussion is for illustrative purposes, and variations and combinations thereof are part of the embodiments and fall within the scope of the invention.
圖7b、7c、7d、7e和7f顯示由不同的隔離和熔絲元件之實施例的P+/N井二極體的頂視圖。沒有隔離，P+和N+主動區將經由長在頂部的矽化物短路在一起。隔離可以經由淺溝槽隔離(STI)、假CMOS閘極或矽化物阻擋層(SBL)從一至四邊或任何邊的組合來提供。當作二極體的P端和N端的P+和N+主動區，就是CMOS元件的源極或汲極。P+和N+所在的N井，就是在標準CMOS製程裏用來嵌入PMOS相同的N井。在許多個存儲單元裏二極體的N+主動區可被共用。但為簡單起見，圖7b-7f對一P+主動區只顯示一N+主動區。 Figures 7b, 7c, 7d, 7e and 7f show top views of P+/N well diodes from embodiments of different isolation and fuse elements. Without isolation, the P+ and N+ active regions will be shorted together via the telluride grown at the top. The isolation may be provided via a shallow trench isolation (STI), a dummy CMOS gate, or a telluride blocking layer (SBL) from one to four sides or a combination of any of the sides. The P+ and N+ active regions, which are the P and N terminals of the diode, are the source or drain of the CMOS device. The N well where P+ and N+ are located is used to embed the same N well of the PMOS in a standard CMOS process. The N+ active regions of the diodes can be shared in many memory cells. However, for simplicity, Figures 7b-7f show only one N+ active zone for a P+ active zone.
圖7b顯示另一實施例的位於電性熔絲存儲單元中的P+/N井二極體40之一頂視圖。此電性熔絲存儲單元具有主動區43和44而且有STI 49隔離於四邊。熔絲元件42經由金屬46被耦合到主動區43。主動區43和44分別被P+植入層47和N+植入層(P+植入層47的互補)所覆蓋，來構成二極體40的P端和N端。二極體40的主動區43和44存在一N井45裏，同樣的N井可用於嵌入PMOS於標準的CMOS製程裏。在此實施例，P+主動區43和N+主動區44被STI 49四面包圍 。由於STI 49比P+和N+主動區更深，在P+主動區43和N+主動區44之間的二極體電阻會很高。 Figure 7b shows a top view of another embodiment of a P+/N well diode 40 in an electrical fuse storage unit. The electrical fuse storage unit has active regions 43 and 44 and has an STI 49 isolated from four sides. Fuse element 42 is coupled to active region 43 via metal 46. The active regions 43 and 44 are covered by a P+ implant layer 47 and an N+ implant layer (complementary to the P+ implant layer 47), respectively, to form the P terminal and the N terminal of the diode 40. The active regions 43 and 44 of the diode 40 are present in an N-well 45, and the same N-well can be used to embed the PMOS in a standard CMOS process. In this embodiment, the P+ active region 43 and the N+ active region 44 are surrounded by STI 49. . Since the STI 49 is deeper than the P+ and N+ active regions, the diode resistance between the P+ active region 43 and the N+ active region 44 can be high.
圖7c顯示另一實施例的位於電性熔絲存儲單元中的P+/N井二極體50之頂視圖。此電性熔絲存儲單元具有二邊STI 49和另二邊假CMOS閘極隔離的主動區53和54。此電性熔絲單元包含一在右一在左的二個STI 59漕溝的主動區51，和經由在頂部和底部的兩個CMOS閘極被區分為周邊主動區54和中央主動區53。中央主動區53被P+植入層57覆蓋，而周邊主動區域被N+植入層覆蓋，其構成了二極體的P端和N端。主動區51存在一N井55裏，同樣的N井可用於嵌入PMOS於標準CMOS製程裏。熔絲元件52被耦合到P+主動區53。假MOS閘極58最好是被偏壓到一固定的電壓。在此實施例，P+主動區53和N+主動區54被STI 59包圍在左右兩側而假MOS閘極58在頂部和底部。由假MOS閘極58所提供的隔離比STI的隔離可提供較低的電阻，因為在P+主動區53和N+主動區54的距離較窄，並且在矽表面下沒有氧化物阻止電流路徑。 Figure 7c shows a top view of another embodiment of a P+/N well diode 50 in an electrical fuse storage unit. The electrical fuse storage unit has active sides 53 and 54 separated by two sides STI 49 and the other two sides of the dummy CMOS gate. The electrical fuse unit includes an active region 51 of two STI 59 trenches on the right and left, and is divided into a peripheral active region 54 and a central active region 53 via two CMOS gates at the top and bottom. The central active region 53 is covered by a P+ implant layer 57, while the peripheral active region is covered by an N+ implant layer, which constitutes the P terminal and the N terminal of the diode. The active area 51 has an N-well of 55, and the same N-well can be used to embed PMOS in a standard CMOS process. Fuse element 52 is coupled to P+ active region 53. The dummy MOS gate 58 is preferably biased to a fixed voltage. In this embodiment, the P+ active region 53 and the N+ active region 54 are surrounded by the STI 59 on the left and right sides and the dummy MOS gate 58 is at the top and bottom. Isolation of the isolation ratio STI provided by the dummy MOS gate 58 provides lower resistance because the distance between the P+ active region 53 and the N+ active region 54 is narrower and there is no oxide blocking current path under the surface of the germanium.
圖7d顯示另一實施例的位於電性熔絲存儲單元中的P+/N井二極體60之頂視圖。此電性熔絲存儲單元具假CMOS閘極在四面隔離。單件主動區被環型MOS閘極68分為中央主動區63和周邊主動區64。分別地，中央主動區63被P+植入層67覆蓋，而周邊主動區域64被N+植入層(P+植入層67的互補)所覆蓋，而構成了二極體60的P端和N端。主動區61存在一N井裏，同樣的N井可用於嵌入PMOS於標準CMOS製程裏。熔絲元件62經由金屬66被耦合到P+主動區63。假MOS閘極68可以被偏壓到一固定的電壓，以提供在P+主動區63和N+主動區64的四面隔離。這實施例提供低電阻於二極體60的P 和N端之間。 Figure 7d shows a top view of another embodiment of a P+/N well diode 60 in an electrical fuse storage unit. This electrical fuse storage unit has a dummy CMOS gate isolated on all four sides. The single active region is divided into a central active region 63 and a peripheral active region 64 by a ring MOS gate 68. Separately, the central active region 63 is covered by the P+ implant layer 67, while the peripheral active region 64 is covered by the N+ implant layer (complementary to the P+ implant layer 67) to form the P and N ends of the diode 60. . The active area 61 is present in an N well, and the same N well can be used to embed PMOS in a standard CMOS process. Fuse element 62 is coupled to P+ active region 63 via metal 66. The dummy MOS gate 68 can be biased to a fixed voltage to provide four-sided isolation between the P+ active region 63 and the N+ active region 64. This embodiment provides a low resistance to the P of the diode 60. Between the N and the N.
圖7e顯示了一P+/N井二極體60’的頂視圖，在電性熔絲存儲單元裏的另一實施例。此電性熔絲存儲單元具有以矽化物阻擋層(SBL)68'提供四面隔離的主動區63'和64'。單件主動區被環型矽化物阻擋層(SBL)68'分為中央主動區63'和周邊主動區64'。中央主動區63'和周邊主動區64'分別被P+植入層67'和N+植入層(P+植入層67’的互補)所覆蓋，來構成了二極體60'的P端和N端。P+植入層67'和N+植入層之間的邊界大約在環型矽化物阻擋層(SBL)68'中間。主動區61'存在一N井65'裏。熔絲元件62'經由金屬66'被耦合到P+主動區63'。環型矽化物阻擋層(SBL)68'阻擋矽化物在P+主動區63'和N+主動區64'的頂部上形成。在此實施例，P+主動區63'和N+主動區64'被P/N接面四面隔離。這實施例具有於二極體60'的P和N端間之低電阻，雖然矽化物阻擋層(SBL)可能比MOS閘極寬。在另一實施例裏，在P+植入層67'和N+植入層之間存有空隙，雖然P+植入層67'和N+植入層都被環型矽化物阻擋層(SBL)68'所覆蓋。 Figure 7e shows a top view of a P+/N well diode 60', another embodiment in an electrical fuse storage unit. The electrical fuse memory cell has active regions 63' and 64' that are provided with four sides isolation with a telluride blocking layer (SBL) 68'. The single piece active region is divided into a central active region 63' and a peripheral active region 64' by a ring-shaped telluride barrier layer (SBL) 68'. The central active region 63' and the peripheral active region 64' are respectively covered by the P+ implant layer 67' and the N+ implant layer (complementary to the P+ implant layer 67') to form the P terminal and the N of the diode 60'. end. The boundary between the P+ implant layer 67' and the N+ implant layer is approximately in the middle of the ring-shaped telluride barrier layer (SBL) 68'. The active zone 61' exists in an N-well 65'. Fuse element 62' is coupled to P+ active region 63' via metal 66'. A ring-shaped telluride barrier (SBL) 68' barrier telluride is formed on top of the P+ active region 63' and the N+ active region 64'. In this embodiment, the P+ active region 63' and the N+ active region 64' are isolated by four sides of the P/N junction. This embodiment has a low resistance between the P and N terminals of the diode 60', although the telluride blocking layer (SBL) may be wider than the MOS gate. In another embodiment, a void exists between the P+ implant layer 67' and the N+ implant layer, although both the P+ implant layer 67' and the N+ implant layer are surrounded by a ring-shaped germanide blocking layer (SBL) 68'. Covered.
圖7f顯示了另一實施例之頂視圖，其中P+/N井二極體70在一電性熔絲存儲單元裏，含有一單接點。被STI 79隔離的主動區73和74分別被P+植入層77和N+植入層(P+植入層77的互補)所覆蓋，構成了二極體70的P端和N端。主動區73和74皆存在一N井75裏，同樣的N井可用於嵌入標準CMOS製程裏的PMOS。熔絲元件72經由一單接點71裏的金屬76而被耦合到P+主動區73。這單接點71跟在圖7b、7c、7d和7e裏的雙接點是完全不同，其中一接點經由金屬而連接熔絲元件，然後另一接點經由金屬而連接另一P+主動區。本 實施例經由一單接點裏的金屬來直接連接一熔絲元件到一P+主動區，存儲單元的面積可大幅減少。此熔絲元件之實施例，可由CMOS閘極來構建，包括多晶矽、矽化多晶矽或非鋁金屬的CMOS閘極，其允許熔絲元件和主動區經由金屬在上的單一接點。 Figure 7f shows a top view of another embodiment in which the P+/N well diode 70 contains a single contact in an electrical fuse storage unit. The active regions 73 and 74 separated by the STI 79 are covered by the P+ implant layer 77 and the N+ implant layer (complementary to the P+ implant layer 77), respectively, forming the P terminal and the N terminal of the diode 70. Both active regions 73 and 74 have an N-well 75, and the same N-well can be used to embed PMOS in a standard CMOS process. Fuse element 72 is coupled to P+ active region 73 via metal 76 in a single contact 71. This single contact 71 is completely different from the double contacts in Figures 7b, 7c, 7d and 7e, where one contact connects the fuse element via metal and then the other contact connects another P+ active area via metal . this In an embodiment, a fuse element is directly connected to a P+ active region via a metal in a single contact, and the area of the memory cell can be greatly reduced. Embodiments of this fuse element can be constructed from CMOS gates, including polysilicon, deuterated polysilicon or non-aluminum metal CMOS gates that allow the fuse element and active region to pass through a single point of contact on the metal.
在一般情況下，多晶矽或矽化多晶矽熔絲更常被用來當作電性熔絲，因為它比金屬，或接點/層間接點需要較低的編程電流。然而金屬熔絲具有一定優勢，如更小的尺寸和編程後大電阻比例。使用金屬的熔絲元件可直接連接到P+主動區，從而比多晶矽熔絲減少了額外的接點。在特徵尺寸小於65奈米的先進CMOS技術，金屬熔絲的編程電壓可低於3.3V，這使得金屬熔絲為一可行的解決方案。 In general, polysilicon or germanium polysilicon fuses are more commonly used as electrical fuses because they require lower programming current than metal, or contact/layer indirect points. However, metal fuses have certain advantages, such as smaller size and large resistance ratio after programming. The use of metal fuse elements can be directly connected to the P+ active region, thereby reducing the number of additional contacts compared to polysilicon fuses. In advanced CMOS technology with feature sizes less than 65 nanometers, the metal fuse can be programmed at voltages below 3.3V, making metal fuses a viable solution.
圖8a顯示P+/N井二極體60“的一頂視圖，擁有第一層金屬(metal1)熔絲具有假CMOS閘極的隔離。單件主動區被環型MOS閘極68隔離成中央主動區63和周邊主動區64。分別地，中央主動區63被P+植入層67所覆蓋，周邊主動區64被N+植入層(P+植入層67的互補)所覆蓋，以構成了二極體60”的P端和N端。主動區61存在一N井裏，同樣的N井可用於嵌入標準CMOS製程的PMOS裏。第一層金屬熔絲元件62"直接被耦合到P+區域63。環型MOS閘極68提供假CMOS閘極隔離，可以被偏壓到一固定的電壓，並能提供P+主動區63和N+主動區64之間四邊的隔離。在此個實施例中，金屬熔絲的長寬比約為0.5-6。 Figure 8a shows a top view of the P+/N well diode 60" with the first metal (metal1) fuse with a dummy CMOS gate isolation. The single active region is isolated by the ring MOS gate 68 to be centrally active. Region 63 and peripheral active region 64. Separately, central active region 63 is covered by P+ implant layer 67, and peripheral active region 64 is covered by N+ implant layer (complementary to P+ implant layer 67) to form a pole The P end and the N end of the body 60". The active area 61 is present in an N well, and the same N well can be used to embed a PMOS in a standard CMOS process. The first layer of metal fuse element 62" is directly coupled to P+ region 63. Ring MOS gate 68 provides dummy CMOS gate isolation, can be biased to a fixed voltage, and can provide P+ active region 63 and N+ active The isolation between the four sides of the region 64. In this embodiment, the metal fuse has an aspect ratio of about 0.5-6.
如果二極體導通電流並不大，圖8a裏金屬熔絲的大小可進一步減少。圖8b顯示一排金屬熔絲存儲單元60’"的一頂視圖。照此實施例，擁有四個金屬熔絲存儲單元，在每一邊共享一N井接觸。 第一層金屬熔絲69有陽極62'、第一層金屬本體66'和陰極(耦合到主動區64’)，主動區64’被P+植入層67’所覆蓋並作為二極體的P端。主動區61'存在一N井65'裏。另一主動區63'被N+植入層(P+植入層67’的互補)所覆蓋以當作二極體的N端。四個二極體被STI 68'所隔離，並在每一邊各分享一N+主動區63'。N+主動區63'由水平方向的第二層金屬(metal2)所連接，而二極體陽極則是由垂直方向的第三層金屬(metal3)所連接。如果第一層金屬用於編程，在傳導路徑裏的其它類型的金屬線應更寬。同樣，更多的接點和層間接點應放置在傳導路徑來抵抗不當的編程。圖8b之金屬熔絲採用第一層金屬僅為說明目的，對此技術熟知者可知上述說明可以適用於任何金屬，如第二，三，或四層金屬，或在其他實施例。同樣，對此技術熟知者可知本發明可適用於不同的隔離或不同金屬的結構。而且共享一個N+主動區的存儲單元數目可能會在其他實施例裏有所改變。 If the diode conduction current is not large, the size of the metal fuse in Figure 8a can be further reduced. Figure 8b shows a top view of a row of metal fuse storage units 60'". In this embodiment, there are four metal fuse storage units sharing an N-well contact on each side. The first layer of metal fuse 69 has an anode 62', a first layer of metal body 66' and a cathode (coupled to active region 64'), and active region 64' is covered by P+ implant layer 67' and acts as a diode P end. The active zone 61' exists in an N-well 65'. The other active region 63' is covered by the N+ implant layer (complementary to the P+ implant layer 67') to serve as the N-terminal of the diode. The four diodes are isolated by the STI 68' and share an N+ active zone 63' on each side. The N+ active region 63' is connected by a horizontal second metal layer (metal2), and the diode anode is connected by a vertical third metal layer (metal3). If the first layer of metal is used for programming, the other types of metal lines in the conduction path should be wider. Similarly, more contacts and layer indirect points should be placed in the conduction path to resist improper programming. The use of the first layer of metal in the metal fuse of Figure 8b is for illustrative purposes only, and it will be apparent to those skilled in the art that the above description can be applied to any metal, such as a second, third, or four layer metal, or in other embodiments. Also, it will be apparent to those skilled in the art that the present invention is applicable to different isolated or different metal structures. Moreover, the number of memory cells sharing an N+ active zone may vary in other embodiments.
對特徵尺寸小於65奈米的先進CMOS技術，接點(Contact)或層間接點(Via)熔絲變為更加可行的技術，因為小的接點/層間接點使編程電流相對較低。圖8c顯示了一排四個由第一層間接點(via1)熔絲存儲單元70的頂視圖，依照此一實施例，其共享N型井接點73a和73b。Via1熔絲存儲單元79具有一via179a被耦合到第一層金屬76和第二層金屬72。第二層金屬72經由via2被耦合到垂直方向當位元線的第三層金屬。第一層金屬76被耦合到一主動區74，主動區74被P+植入層77所覆蓋並當作是一二極體71的P端。主動區73a和73b被N+植入層(P+植入層77的互補)所覆蓋且被當作是在via1熔絲存儲單元79裏二極體71的N端。此外，主動區73a和 73b被當作是在四個熔絲存儲單元70裏的二極體的共同N端，被耦合到水平方向的第四層金屬(metal4)的字元線。該主動區74、73a以及73b存在同一N井75裏。Via1熔絲存儲單元70裏的四個二極體彼此之間有STI 78隔離。如果是要編程via1，更多其他的接點和更多其他類型的層間接點應被放置在傳導路徑裏。並且傳導路徑裏的其他金屬線該比較寬而且包含大的圍繞在接點/層間接點的四周來抵抗不當的編程。圖8c裏，以Via1當作層間接點熔絲是用於說明目的，對此技術熟知者可知上述說明可適用於任何類型的接點或層間接點，如第二、第三、第或四層間連接點via2、via3或via4等。同樣，對此技術熟知者可知本發明之二極體P端和N端有不同的隔離和不同的金屬的結構。而且共享一N+主動區的存儲單元數目可能會在其他實施例裏改變。 For advanced CMOS technologies with feature sizes less than 65 nanometers, contact or layer indirect (Via) fuses become a more viable technique because the small contact/layer indirect points make the programming current relatively low. Figure 8c shows a top view of a row of four first indirect point (via1) fuse storage units 70, which in accordance with this embodiment share N-well contacts 73a and 73b. The Via1 fuse storage unit 79 has a via 179a coupled to the first layer of metal 76 and the second layer of metal 72. The second layer of metal 72 is coupled via via2 to the third layer of metal in the vertical direction as the bit line. The first layer of metal 76 is coupled to an active region 74 that is covered by the P+ implant layer 77 and is considered to be the P terminal of a diode 71. The active regions 73a and 73b are covered by the N+ implant layer (complementary to the P+ implant layer 77) and are considered to be the N-terminal of the diode 71 in the via1 fuse storage unit 79. In addition, the active area 73a and 73b is considered to be the common N-terminal of the diodes in the four fuse storage units 70, coupled to the word line of the fourth metal (metal4) in the horizontal direction. The active zones 74, 73a and 73b are located in the same N well 75. The four diodes in the Via1 fuse storage unit 70 are STI 78 isolated from each other. If you want to program via1, more other contacts and more other types of layer indirect points should be placed in the conduction path. And the other metal lines in the conduction path should be relatively wide and contain large surrounds around the junction/layer indirect points to resist improper programming. In Fig. 8c, the use of Via1 as a layer indirect fuse is for illustrative purposes, and it is well known to those skilled in the art that the above description can be applied to any type of contact or layer indirect point, such as second, third, fourth or fourth. Inter-layer connection points via2, via3 or via4. Similarly, it is known to those skilled in the art that the P and N ends of the diode of the present invention have different isolation and different metal structures. Moreover, the number of memory cells sharing an N+ active zone may change in other embodiments.
圖8d顯示另一實施例之頂視圖，其顯示具有假CMOS閘極隔離之4x5via1熔絲陣列。圖8c顯示一排層間接點熔絲，可擴展成一二維陣列90(如圖8d所示)。陣列90有四列主動區91，每列存在一個單獨的N井裏，而五行層間接點熔絲存儲單元96被假CMOS閘極92隔離於主動區間。每個層間接點熔絲(via fuse)存儲單元96有一接點99在主動區上被P+植入層94所覆蓋，以作為一二極體的P端，其更被耦合到垂直方向的第二層金屬位元線。陣列90裏兩邊的主動區被N+植入層97所覆蓋，以作為在同一列二極體的N端，其更被耦合到水平方向的第三層金屬當字元線。為了編程一層間接點熔絲，可選擇並施加電壓到所要的字元線和位元線，來導通電流從metal2位元線、via1、metal1、接點、P+主動區及N+主動區，到第三層金屬字元線。為了確保只有via1被編程，其他金屬 可以較寬而且其他類型的層間接點或其他接點的數目可不止一個。為了簡化繪圖，metal1-via1-metal2連接可參照圖8c，因此不會顯示於8d圖中的每個存儲單元。對此技術熟知者可知不同類型的接點或層間接點可作為本發明電阻元件，而且不同金屬的結構可在其他實施例裏改變。同樣，在行和列裏存儲單元的數目，在一陣列裏行和列的數目，或在N+主動區之間存儲單元的數目可在其他實施例裏改變。 Figure 8d shows a top view of another embodiment showing a 4x5via1 fuse array with dummy CMOS gate isolation. Figure 8c shows a row of indirect point fuses that can be expanded into a two dimensional array 90 (as shown in Figure 8d). Array 90 has four columns of active regions 91, each column having a separate N-well, and five-layer indirect-point fuse storage unit 96 being isolated from the active interval by dummy CMOS gate 92. Each layer of the via fuse memory unit 96 has a contact 99 over the active area covered by the P+ implant layer 94 to serve as the P terminal of a diode, which is further coupled to the vertical direction. Two-layer metal bit line. The active regions on both sides of array 90 are covered by N+ implant layer 97 as the N-side of the same column of diodes, which is further coupled to the third layer of metal as a word line in the horizontal direction. In order to program an indirect point fuse, a voltage can be selected and applied to the desired word line and bit line to conduct current from the metal2 bit line, via1, metal1, contact, P+ active region and N+ active region, to Three-layer metal word line. To ensure that only via1 is programmed, other metals It can be wider and the number of other types of layer indirect points or other contacts can be more than one. In order to simplify the drawing, the metal1-via1-metal2 connection can be referred to FIG. 8c, and thus will not be shown in each of the memory cells in the 8d figure. It will be appreciated by those skilled in the art that different types of contacts or layer indirect points can be used as the resistive elements of the present invention, and the structure of the different metals can be varied in other embodiments. Similarly, the number of memory cells in rows and columns, the number of rows and columns in an array, or the number of memory cells between N+ active regions can vary in other embodiments.
根據另一實施例，可編程電阻元件可用於建立記憶體。根據此一實施例，圖9顯示了可編程電阻記憶體100的一部分，由n行x(m+1)列的單二極體存儲單元110的一陣列101和n個字元線驅動器150-i(其中i=0,1,...,n-1)所構建。記憶體陣列101有m個正常列和一參考列，共用一感應放大器做差動感應。對那些記憶體存儲單元110於同一列的每個記憶體存儲單元110有一電阻元件111被耦合到當編程選擇器的一二極體112的P端和到一位元線BLj 170-j(j=0,1,..m-1)或參考位元線BLR0 175-0。對那些記憶體存儲單元110在同一行的二極體112的N端經由局部字元線LWLBi 154-i,(i=0,1,…,n-1)被耦合到一字元線WLBi 152-i，。每個字元線WLBi被耦合到至少一局部字元線LWLBi，此處i=0,1,…,n-1。該局部字元線LWLBi 154-i通常由高電阻材料，如N井或多晶矽構建，來連接存儲單元，然後耦合到WLBi(例如，低電阻金屬WLBi)經由接點或層間接點，緩衝器，或後解碼器172-i，其中i=0,1,...,n-1。當使用二極體作為編程選擇器，可能需要緩衝器或後解碼器172-i，因為有電流流過WLBi，特別是當一WLBi驅動多個存儲單元來同時編程和讀取，於 其他實施例。該字元線WLBi是由字元線驅動器150-i所驅動，為了編程和讀取其電源電壓vddi可以在不同的電壓之間被切換。每個BLj 170-j或BLR0 175-0都經由一Y-write通道閘120-j或125被耦合到一電源電壓VDDP來編程，分別由被選中的YSWBj(j=0,1,..,m-1)或YSWRB0。在Y-write通道閘120-j(j=0,1,…,m-1)或125可以由PMOS所建構，雖然NMOS，二極體，或雙極型元件可以在一些實施例裏使用。每個BL或BLR0經由一Y-read通道閘130-j或135被耦合到數據線DLj或參考數據線DLR0，分別由YSRj(j=0,1,..,m-1)或YSRR0所選定。在記憶體陣列101這一部分，m正常的數據線DLj(j=0,1,…,m-1)被連接到一感應放大器140的一輸入端160。該參考數據線DLR0提供了感應放大器140的另一輸入端161(一般在參考部分裏不需要多工器)。感應放大器140的輸出端是Q0。 According to another embodiment, a programmable resistive element can be used to create a memory. In accordance with this embodiment, FIG. 9 shows a portion of a programmable resistive memory 100 having an array 101 of single-diode memory cells 110 of n rows x (m+1) columns and n word line drivers 150- i (where i = 0, 1, ..., n-1) is constructed. The memory array 101 has m normal columns and a reference column, and shares a sense amplifier for differential sensing. For each memory storage unit 110 of the memory storage unit 110 in the same column, a resistive element 111 is coupled to the P terminal of a diode 112 of the programming selector and to a bit line BLj 170-j (j =0, 1, ..m-1) or reference bit line BLR0 175-0. For those memory cells 110, the N-terminal of the diode 112 in the same row is coupled to a word line WLBi 152 via a local word line LWLBi 154-i, (i = 0, 1, ..., n-1). -i,. Each word line WLBi is coupled to at least one local word line LWLBi, where i = 0, 1, ..., n-1. The local word line LWLBi 154-i is typically constructed of a high resistance material, such as a N-well or polysilicon, to connect the memory cells and then coupled to WLBi (eg, low-resistance metal WLBi) via contacts or layer indirect points, buffers, Or post decoder 172-i, where i = 0, 1, ..., n-1. When using a diode as a programming selector, a buffer or post decoder 172-i may be required because current flows through WLBi, especially when a WLBi drives multiple memory cells for simultaneous programming and reading. Other embodiments. The word line WLBi is driven by the word line driver 150-i, and can be switched between different voltages in order to program and read its supply voltage vddi. Each BLj 170-j or BLR0 175-0 is programmed via a Y-write channel gate 120-j or 125 to a supply voltage VDDP, respectively, by the selected YSWBj (j=0,1,.. , m-1) or YSWRB0. The Y-write channel gate 120-j (j = 0, 1, ..., m-1) or 125 may be constructed by a PMOS, although an NMOS, diode, or bipolar element may be used in some embodiments. Each BL or BLR0 is coupled to data line DLj or reference data line DLR0 via a Y-read channel gate 130-j or 135, selected by YSRj (j = 0, 1, .., m-1) or YSRR0, respectively. . In the portion of the memory array 101, m normal data lines DLj (j = 0, 1, ..., m-1) are coupled to an input 160 of a sense amplifier 140. The reference data line DLR0 provides the other input 161 of the sense amplifier 140 (generally no multiplexer is required in the reference portion). The output of sense amplifier 140 is Q0.
要編程一存儲單元，特定的WLBi和YSWBj被開啟而一高電壓被提供到VDDP，其中i=0,1,..,n-1而j=0,1,...,m-1。在一些實施例裏，經由打開WLRBi(i=0,1,...,n-1)和YSWRB0，參考存儲單元可以被編程為0或1。要讀取一存儲單元，數據列線DLj 160可以由啟用特定的WLBi和YSRj，(其中i=0,1,...,n-1，和j=0,1,...,m-1)來選到，而一參考數據線DLR0 161可以由啟用特定的一參考存儲單元來選到，皆被耦合到感應放大器140。此感應放大器140可以被用來感應和比較DL和DLR0與接地之間的電阻差異，同時關閉所有YSWBj和YSWRB0，其中j=0,1,..,m-1。 To program a memory cell, the particular WLBi and YSWBj are turned on and a high voltage is supplied to VDDP, where i = 0, 1, .., n-1 and j = 0, 1, ..., m-1. In some embodiments, the reference memory cell can be programmed to 0 or 1 by turning on WLRBi (i = 0, 1, ..., n-1) and YSWRB0. To read a memory cell, the data column line DLj 160 can be enabled by a specific WLBi and YSRj, (where i = 0, 1, ..., n-1, and j = 0, 1, ..., m- 1) Selected, and a reference data line DLR0 161 can be selected by enabling a particular reference memory unit, both coupled to sense amplifier 140. This sense amplifier 140 can be used to sense and compare the difference in resistance between DL and DLR0 and ground, while turning off all YSWBj and YSWRB0, where j = 0, 1, .., m-1.
圖10a和10b顯示一流程圖實施例，分別描繪可編程電阻式記憶體 的編程方法S700和讀取方法S800。方法S700和S800描述了在可編程電阻式記憶體情況下，如圖9的可編程電阻記憶體100的編程和讀取。此外，雖然說是一步驟流程，對此技術熟知者可知至少一些步驟可能會以不同的順序進行，包括同時或跳過。 Figures 10a and 10b show a flow chart embodiment depicting programmable resistive memory Programming method S700 and reading method S800. Methods S700 and S800 describe the programming and reading of the programmable resistive memory 100 of FIG. 9 in the case of a programmable resistive memory. Moreover, although it is a one-step process, it will be apparent to those skilled in the art that at least some of the steps may be performed in a different order, including simultaneous or skipping.
圖10a所示為用於可編程電阻記憶體之一編程方法S700的流程圖。根據此實施例，在第一步驟S710，選擇適當的電源選擇器以施加高電壓電源到字元線和位元線驅動器。在第二步驟S720，根據可編程電阻元件的類型，在控制邏輯(在圖9裏沒有顯示)裏進行分析要被編程的數據。對於電性熔絲，由於為單次性可編程元件(OTP)，所以編程通常意味著燒錄熔絲到非原始狀態，而且是不可逆轉的。編程電壓和持續時間往往是由外部控制信號決定，而不是從記憶體內部產生。在第三步驟S730，選擇一存儲單元的一列，所以相對的局部字元線可被開啟。在第四步驟S740，停用感應放大器，以節省電源和防止干擾到編程的運作。在第五步驟S750，存儲單元的一行(群)，可以被選定並且相對應的Y-write通道閘可以被打開來耦合所選的位元線到一電源電壓。在最後一步驟S760，在一已建立的傳導路徑來驅動所需的電流一段所需要的時間來完成編程的運作。對於大多數可編程電阻記憶體，這傳導路徑是由一高壓電源，通過被選的一位元線(群)，電阻元件，作為編程選擇器(群)的二極體，以及一局部字元線驅動器(群)的NMOS下拉元件到接地。 Figure 10a shows a flow chart for a method S700 for programming a resistive memory. According to this embodiment, in a first step S710, an appropriate power supply selector is selected to apply a high voltage power supply to the word line and bit line drivers. In a second step S720, the data to be programmed is analyzed in the control logic (not shown in Figure 9) depending on the type of programmable resistive element. For electrical fuses, programming is usually a one-time programmable element (OTP), which usually means burning the fuse to a non-original state and is irreversible. The programming voltage and duration are often determined by external control signals rather than from within the memory. In a third step S730, a column of a memory cell is selected so that the opposite local word line can be turned on. In a fourth step S740, the sense amplifier is deactivated to save power and prevent interference to the programmed operation. In a fifth step S750, a row (group) of memory cells can be selected and the corresponding Y-write channel gate can be opened to couple the selected bit line to a supply voltage. At the last step S760, the programmed operation is completed by an established conduction path to drive the required current for a desired period of time. For most programmable resistor memories, this conduction path is made up of a high voltage power supply, through a selected bit line (group), a resistive element, as a diode of the programming selector (group), and a local character. Line driver (group) NMOS pull-down component to ground.
圖10b所示為依據另一實施例，用於編程電阻記憶體讀取方法S800之流程圖於。在第一步驟S810，提供合適的電源選擇器來選電源電壓給局部字元線驅動器，感應放大器和其他電路。在第二 步驟S820，所有Y-write通道閘，例如位元線編程選擇器，可以被關閉。在第三步驟S830，所需的局部字元線驅動器(群)可以被選，使作為編程選擇器(群)的二極體(群)具有傳導路徑到接地。在第四步驟S840，啟動感應放大器(群)和準備感應的輸入信號。在第五步驟S850，數據線和參考數據線被預先充電到可編程電阻元件存儲單元的V-電壓。在第六步驟S860，選所需的Y-read通道閘，使所需的位元線(群)被耦合到感應放大器的一輸入端。一傳導路徑於是被建立，從位元線(群)到所要的存儲單元的電阻元件，作為編程選擇器(群)的二極體(群)和局部字元線驅動器(群)的下拉元件到接地。這同樣適用於參考分支。在最後一步驟S870，感應放大器可以比較讀取電流與參考電流的差異來決定邏輯輸出是0或1以完成讀取操作。 Figure 10b shows a flow chart for programming a resistive memory read method S800 in accordance with another embodiment. In a first step S810, a suitable power selector is provided to select the supply voltage to the local word line driver, sense amplifier and other circuitry. In the second In step S820, all Y-write channel gates, such as bit line programming selectors, can be turned off. In a third step S830, the desired local word line driver (group) can be selected such that the diodes (groups) as programming selectors (groups) have a conductive path to ground. In a fourth step S840, the sense amplifier (group) and the input signal ready for sensing are activated. In a fifth step S850, the data line and the reference data line are precharged to the V-voltage of the programmable resistive element memory cell. In a sixth step S860, the desired Y-read pass gate is selected such that the desired bit line (group) is coupled to an input of the sense amplifier. A conduction path is then established, from the bit line (group) to the desired resistive element of the memory cell, as a diode (group) of the programming selector (group) and a pull-down element of the local word line driver (group) to Ground. The same applies to the reference branch. At the last step S870, the sense amplifier can compare the difference between the read current and the reference current to determine whether the logic output is 0 or 1 to complete the read operation.
圖11顯示了一處理器系統700的一實施例。根據此實施例，處理器系統700可以包括可編程電阻元件744，如在一存儲單元陣列742裏，而在記憶體740裏。處理器系統700可以例如屬於一電腦系統。電腦系統可以包括中央處理單元(CPU)710，它經由共同匯流排715來和多種記憶體和周邊裝置溝通，如輸入輸出單元720、硬盤驅動器730、光碟750、記憶體740和其他記憶體760。其他記憶體760是一種傳統的記憶體如靜態存取記憶體(SRAM)，動態存取記憶體(DRAM)或快閃記憶體(flash)，通常經由記憶體控制器來和與中央處理單元710溝通。中央處理單元710一般是一種微處理器，數位信號處理器，或其他可編程數位邏輯元件。記憶體740最好是以積體電路來構造，其中包括至少有可編程電阻元件744的記憶體陣列742。通常，記憶體740經由記憶體控制器來接 觸中央處理單元710。如果需要，可合併記憶體740與處理器(例如中央處理單元710)在單片積體電路。 FIG. 11 shows an embodiment of a processor system 700. In accordance with this embodiment, processor system 700 can include a programmable resistive element 744, such as in a memory cell array 742, in memory 740. Processor system 700 can, for example, belong to a computer system. The computer system can include a central processing unit (CPU) 710 that communicates with various memory and peripheral devices via a common bus 715, such as input and output unit 720, hard disk drive 730, optical disk 750, memory 740, and other memory 760. The other memory 760 is a conventional memory such as a static access memory (SRAM), a dynamic access memory (DRAM) or a flash memory, usually connected to the central processing unit 710 via a memory controller. communication. Central processing unit 710 is typically a microprocessor, digital signal processor, or other programmable digital logic element. Memory 740 is preferably constructed in an integrated circuit that includes a memory array 742 having at least programmable resistive elements 744. Usually, the memory 740 is connected via a memory controller. The central processing unit 710 is touched. If desired, the memory 740 can be combined with a processor (e.g., central processing unit 710) in a monolithic integrated circuit.
本發明可以部分或全部實現於積體電路，在印刷電路板(PCB)上，或在系統上。該可編程電阻元件可以是熔絲，反熔絲，或新出現的非揮發行性記憶體。熔絲可以是矽化或非矽化多晶矽熔絲，熱隔離的主動區熔絲，金屬熔絲，接點熔絲，或層間接點熔絲。反熔絲可以是閘極氧化層崩潰反熔絲，介電質於其間的接點或層間接點反熔絲。新出現的非揮發行性記憶體可以是磁性存取記憶體(MRAM)、相變記憶體(PCM)、導電橋隨機存取記憶體(CBRAM)或電阻隨機存取記憶體(RRAM)。雖然編程的機制不同，其邏輯狀態可由不同的電阻值來區分。以上的說明和圖畫，只是用來說明認為是示範的實現。 The invention may be implemented in part or in whole in an integrated circuit, on a printed circuit board (PCB), or on a system. The programmable resistive element can be a fuse, an anti-fuse, or an emerging non-volatile memory. The fuse may be a deuterated or non-deuterated polysilicon fuse, a thermally isolated active region fuse, a metal fuse, a contact fuse, or a layer indirect fuse. The antifuse may be a gate oxide breakdown antifuse, a dielectric or a layer indirect antifuse therebetween. Emerging non-volatile memory devices can be magnetic access memory (MRAM), phase change memory (PCM), conductive bridge random access memory (CBRAM) or resistive random access memory (RRAM). Although the programming mechanism is different, its logic state can be distinguished by different resistance values. The above description and drawings are only intended to illustrate the realization of the demonstration.
惟，以上所述，僅為本發明較佳具體實施例之詳細說明與圖式，惟本發明之特徵並不侷限於此，並非用以限制本發明，本發明之所有範圍應以下述之申請專利範圍為準，凡合於本發明申請專利範圍之精神與其類似變化之實施例，皆應包含於本發明之範疇中，任何熟悉該項技藝者在本發明之領域內，可輕易思及之變化或修飾皆可涵蓋在以下本案之專利範圍。 However, the above description is only for the detailed description and the drawings of the preferred embodiments of the present invention, and the present invention is not limited thereto, and is not intended to limit the present invention. The scope of the patent application is intended to be included in the scope of the present invention, and any one skilled in the art can readily appreciate it in the field of the present invention. Variations or modifications may be covered by the patents in this case below.
30‧‧‧存儲單元 30‧‧‧storage unit
30a‧‧‧電阻元件 30a‧‧‧resistive components
30b‧‧‧二極體 30b‧‧‧ diode
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Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10923204B2 (en) | 2010-08-20 | 2021-02-16 | Attopsemi Technology Co., Ltd | Fully testible OTP memory |
| US10229746B2 (en) | 2010-08-20 | 2019-03-12 | Attopsemi Technology Co., Ltd | OTP memory with high data security |
| US9711237B2 (en) | 2010-08-20 | 2017-07-18 | Attopsemi Technology Co., Ltd. | Method and structure for reliable electrical fuse programming |
| US10916317B2 (en) | 2010-08-20 | 2021-02-09 | Attopsemi Technology Co., Ltd | Programmable resistance memory on thin film transistor technology |
| US9818478B2 (en) | 2012-12-07 | 2017-11-14 | Attopsemi Technology Co., Ltd | Programmable resistive device and memory using diode as selector |
| US10192615B2 (en) | 2011-02-14 | 2019-01-29 | Attopsemi Technology Co., Ltd | One-time programmable devices having a semiconductor fin structure with a divided active region |
| US10586832B2 (en) | 2011-02-14 | 2020-03-10 | Attopsemi Technology Co., Ltd | One-time programmable devices using gate-all-around structures |
| TW201417102A (en) | 2012-10-23 | 2014-05-01 | Ind Tech Res Inst | Resistive random-access memory devices |
| TWI608483B (en) * | 2012-12-07 | 2017-12-11 | 上峰科技股份有限公司 | Circuit and system of 3d programmable resistive device and memory using diode as selector |
| US9922720B2 (en) * | 2013-03-07 | 2018-03-20 | Intel Corporation | Random fuse sensing |
| EP3327724B1 (en) * | 2013-09-21 | 2020-10-28 | Shine C. Chung | Circuit and system of using junction diode as program selector for one-time programmable devices |
| CN104464816B (en) * | 2013-09-21 | 2019-03-01 | 上峰科技股份有限公司 | Single programmable memory body and its operating method and programmed method and electronic system |
| CN106374039B (en) * | 2015-07-22 | 2019-03-12 | 旺宏电子股份有限公司 | Memory device and its manufacturing method |
| CN107579087B (en) * | 2016-07-04 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | Memory cell array structure and electronic device |
| US10535413B2 (en) | 2017-04-14 | 2020-01-14 | Attopsemi Technology Co., Ltd | Low power read operation for programmable resistive memories |
| US10726914B2 (en) | 2017-04-14 | 2020-07-28 | Attopsemi Technology Co. Ltd | Programmable resistive memories with low power read operation and novel sensing scheme |
| US11062786B2 (en) | 2017-04-14 | 2021-07-13 | Attopsemi Technology Co., Ltd | One-time programmable memories with low power read operation and novel sensing scheme |
| US11615859B2 (en) | 2017-04-14 | 2023-03-28 | Attopsemi Technology Co., Ltd | One-time programmable memories with ultra-low power read operation and novel sensing scheme |
| US10770160B2 (en) | 2017-11-30 | 2020-09-08 | Attopsemi Technology Co., Ltd | Programmable resistive memory formed by bit slices from a standard cell library |
| US10325991B1 (en) * | 2017-12-06 | 2019-06-18 | Nanya Technology Corporation | Transistor device |
| CN109994137A (en) * | 2019-03-20 | 2019-07-09 | 浙江大学 | A kind of no write de-lay method of single tube list resistance random access memory array |
| CN111739570B (en) * | 2019-03-25 | 2022-05-31 | 中电海康集团有限公司 | SOT-MRAM memory cell and SOT-MRAM memory |
| US11107859B2 (en) * | 2019-08-05 | 2021-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell with unipolar selectors |
| GB2587089B (en) * | 2019-09-03 | 2021-12-15 | Attopsemi Tech Co Ltd | One-time programmable memories with low power read operation and novel sensing scheme |
| CN115240746A (en) * | 2021-04-23 | 2022-10-25 | 长鑫存储技术有限公司 | OTP memory and manufacturing method thereof, and OTP circuit |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054344A (en) * | 1998-10-30 | 2000-04-25 | Taiwan Semiconductor Manufacturing Company | OTP (open trigger path) latchup scheme using buried-diode for sub-quarter micron transistors |
| US20020196659A1 (en) * | 2001-06-05 | 2002-12-26 | Hurst Terril N. | Non-Volatile memory |
| EP1367596A1 (en) * | 2002-05-31 | 2003-12-03 | Hewlett-Packard Company | Cross-point diode ROM |
| US20060244036A1 (en) * | 2005-04-29 | 2006-11-02 | Texas Instruments Incorporated | One time programmable EPROM fabrication in STI CMOS technology |
| US20070057323A1 (en) * | 2005-09-12 | 2007-03-15 | International Business Machines Corporation | Silicon-on-insulator (soi) read only memory (rom) array and method of making a soi rom |
| US20080036033A1 (en) * | 2006-08-10 | 2008-02-14 | Broadcom Corporation | One-time programmable memory |
| TW200816208A (en) * | 2006-09-27 | 2008-04-01 | Novelics Llc | One-time-programmable memory |
| TW200820260A (en) * | 2006-10-28 | 2008-05-01 | Alpha & Omega Semiconductor | Circuit configurations and methods for manufacturing five-volt one time programmable (OTP) memory arrays |
| US7411810B2 (en) * | 2005-12-11 | 2008-08-12 | Juhan Kim | One-time programmable memory |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6130044A (en) * | 1984-07-20 | 1986-02-12 | Nippon Denso Co Ltd | Semiconductor chip inspection method |
| JP2671503B2 (en) * | 1989-06-01 | 1997-10-29 | トヨタ自動車株式会社 | Painting method |
| JPH09134974A (en) * | 1995-09-08 | 1997-05-20 | Fujitsu Ltd | Ferroelectric memory device |
| US20030075778A1 (en) * | 1997-10-01 | 2003-04-24 | Patrick Klersy | Programmable resistance memory element and method for making same |
| TW388129B (en) * | 1998-03-06 | 2000-04-21 | Nation Science Council | Novel process for producing polysilicon interlayer contact of polysilicon TFT SRAM |
| JP2000323669A (en) * | 1999-03-10 | 2000-11-24 | Sanyo Electric Co Ltd | Semiconductor nonvolatile memory device |
| US6400540B1 (en) * | 1999-03-12 | 2002-06-04 | Sil.Able Inc. | Clamp circuit to prevent ESD damage to an integrated circuit |
| US6541316B2 (en) * | 2000-12-22 | 2003-04-01 | The Regents Of The University Of California | Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction |
| JP2002368136A (en) * | 2001-06-06 | 2002-12-20 | Sony Corp | Semiconductor memory device and production method therefor |
| US6707729B2 (en) * | 2002-02-15 | 2004-03-16 | Micron Technology, Inc. | Physically alternating sense amplifier activation |
| US7511982B2 (en) * | 2004-05-06 | 2009-03-31 | Sidense Corp. | High speed OTP sensing scheme |
| US7212432B2 (en) * | 2004-09-30 | 2007-05-01 | Infineon Technologies Ag | Resistive memory cell random access memory device and method of fabrication |
| US7423897B2 (en) * | 2004-10-01 | 2008-09-09 | Ovonyx, Inc. | Method of operating a programmable resistance memory array |
| US8179711B2 (en) * | 2004-10-26 | 2012-05-15 | Samsung Electronics Co., Ltd. | Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell |
| US7035141B1 (en) * | 2004-11-17 | 2006-04-25 | Spansion Llc | Diode array architecture for addressing nanoscale resistive memory arrays |
| US7391064B1 (en) * | 2004-12-01 | 2008-06-24 | Spansion Llc | Memory device with a selection element and a control line in a substantially similar layer |
| US8183665B2 (en) * | 2005-11-15 | 2012-05-22 | Nantero Inc. | Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same |
| US8217490B2 (en) * | 2005-05-09 | 2012-07-10 | Nantero Inc. | Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same |
| US7433247B2 (en) * | 2005-09-26 | 2008-10-07 | Macronix International Co., Ltd. | Method and circuit for reading fuse cells in a nonvolatile memory during power-up |
| US7436695B2 (en) * | 2006-11-21 | 2008-10-14 | Infineon Technologies Ag | Resistive memory including bipolar transistor access devices |
| KR100909537B1 (en) * | 2007-09-07 | 2009-07-27 | 주식회사 동부하이텍 | Semiconductor device and manufacturing method thereof |
| JP4482039B2 (en) * | 2008-01-11 | 2010-06-16 | 株式会社東芝 | Resistance change memory |
| US20100091546A1 (en) * | 2008-10-15 | 2010-04-15 | Seagate Technology Llc | High density reconfigurable spin torque non-volatile memory |
| US20100108980A1 (en) * | 2008-11-03 | 2010-05-06 | Industrial Technology Research Institute | Resistive memory array |
| KR20100064715A (en) * | 2008-12-05 | 2010-06-15 | 삼성전자주식회사 | Nonvolatile memory device using variable resistive element |
| US8089137B2 (en) * | 2009-01-07 | 2012-01-03 | Macronix International Co., Ltd. | Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method |
| CN101667460A (en) * | 2009-10-12 | 2010-03-10 | 中国科学院微电子研究所 | One-time programmable memory based on variable-resistance memory and preparation method thereof |
-
2011
- 2011-08-18 TW TW100129640A patent/TWI452680B/en active
- 2011-08-18 TW TW100129641A patent/TWI462107B/en active
- 2011-08-18 TW TW100129642A patent/TWI480881B/en active
- 2011-08-22 CN CN201110244400.3A patent/CN102376739B/en active Active
- 2011-08-22 CN CN201110244362.1A patent/CN102385917B/en active Active
- 2011-08-22 CN CN201110244390.3A patent/CN102385932B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6054344A (en) * | 1998-10-30 | 2000-04-25 | Taiwan Semiconductor Manufacturing Company | OTP (open trigger path) latchup scheme using buried-diode for sub-quarter micron transistors |
| US20020196659A1 (en) * | 2001-06-05 | 2002-12-26 | Hurst Terril N. | Non-Volatile memory |
| EP1367596A1 (en) * | 2002-05-31 | 2003-12-03 | Hewlett-Packard Company | Cross-point diode ROM |
| US20060244036A1 (en) * | 2005-04-29 | 2006-11-02 | Texas Instruments Incorporated | One time programmable EPROM fabrication in STI CMOS technology |
| US20070057323A1 (en) * | 2005-09-12 | 2007-03-15 | International Business Machines Corporation | Silicon-on-insulator (soi) read only memory (rom) array and method of making a soi rom |
| US7411810B2 (en) * | 2005-12-11 | 2008-08-12 | Juhan Kim | One-time programmable memory |
| US20080036033A1 (en) * | 2006-08-10 | 2008-02-14 | Broadcom Corporation | One-time programmable memory |
| TW200816208A (en) * | 2006-09-27 | 2008-04-01 | Novelics Llc | One-time-programmable memory |
| TW200820260A (en) * | 2006-10-28 | 2008-05-01 | Alpha & Omega Semiconductor | Circuit configurations and methods for manufacturing five-volt one time programmable (OTP) memory arrays |
Non-Patent Citations (1)
| Title |
|---|
| Ming-Dou Ker , Kun-Hsien Lin and Che-Hao Chuang,"MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process", International Symposium on VLSI Technology, Systems, and Applications, 2003 * |
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