TWI478488B

TWI478488B - Broad-band active delay line and thereof method

Info

Publication number: TWI478488B
Application number: TW098144680A
Authority: TW
Inventors: Chia-Liang Lin; Hsin Che Chiang
Original assignee: Realtek Semiconductor Corp
Priority date: 2009-12-24
Filing date: 2009-12-24
Publication date: 2015-03-21
Also published as: TW201123711A

Description

寬頻帶主動式延遲線電路及其相關方法Wideband active delay line circuit and related method

本發明係關於一種延遲線電路(delay line)，特別是一種具有主動式延遲線之方法與裝置。The present invention relates to a delay line, and more particularly to a method and apparatus having an active delay line.

延遲線電路(DELAY LINE)是一種用以接收一類比信號並據以產生複數個輸出信號，其中該複數個輸出信號本質上相似於或相同於該輸入信號，僅是在時間軸上被一致性的移動(uniformly displaced in time)，換言之，該複數個輸出信號分別被延遲了不同數量的單位時間間隔(time spacing)。例加：一個延遲線電路接收一個頻率1GHz的類比輸入信號，並被延遲不同數量的100ps時間間隔。該延遲線電路包括有被序列串接的複數個遲單元(delay cell)以分別產生該複數個輸出信號。只要該複數個遲單元(delay cell)在本質上(substantially)是相同(例如：電路架構、電路元件的特性、尺寸相同)時，該複數個輸出信號在本質上是相似的，僅是在時間軸上被一致性的移動(uniformly displaced in time)。然而，在實際情形下，該延遲單元皆有其頻限制(例如：具有最小的延遲時間)，因此，在輸出類比信號的時間間隔是與頻率有關(frequency dependent)的。在從直流(DC)到高頻範圍內，一個理想的寬頻帶延遲單元的單位時間間隔應該是維持實質上相同的(substantially the same)。傳統的寬頻帶延遲單元係使用複數個傳導線(transmission lines)或是電感-電容(L-C)網路。然而，從積體電路實施面來看，傳導線或是電感-電容(L-C)網路皆是會造成大的電路備局面積。另一傳統的主動式延遲線係使用了複數個電晶體以完成延遲的功能。然，從積體電路實施面來看，該主動式延遲線雖有效地達到減少電路面積的目的，卻在不消耗過高功率去加快電路速度的情形下，其頻寬上有極大的限制。換言之，一個功率效率較高的寬頻帶主動式延遲線是迫切需要的。A delay line circuit (DELAY LINE) is a type for receiving an analog signal and generating a plurality of output signals, wherein the plurality of output signals are substantially similar to or the same as the input signal, and are only consistent on the time axis. Uniformly displaced in time, in other words, the plurality of output signals are delayed by a different number of time intervals. Example: A delay line circuit receives an analog input signal at 1 GHz and is delayed by a different number of 100 ps intervals. The delay line circuit includes a plurality of delay cells serially connected in series to respectively generate the plurality of output signals. As long as the plurality of delay cells are substantially the same (eg, circuit architecture, characteristics of circuit elements, and dimensions are the same), the plurality of output signals are substantially similar in time only The axis is uniformly displaced in time. However, in practical situations, the delay unit has its frequency limit (e.g., has the smallest delay time), and therefore, the time interval at which the analog signal is output is frequency dependent. In the range from direct current (DC) to high frequency, the unit time interval of an ideal wideband delay unit should be substantially the same. Conventional broadband delay units use a plurality of transmission lines or inductor-capacitor (L-C) networks. However, from the perspective of integrated circuit implementation, conductive lines or inductor-capacitor (L-C) networks can cause large circuit backup areas. Another traditional active extension The late line uses a number of transistors to perform the delay function. However, from the perspective of the implementation of the integrated circuit, the active delay line effectively achieves the purpose of reducing the circuit area, but the bandwidth is extremely limited without consuming excessive power to speed up the circuit. In other words, a power-efficient broadband active delay line is urgently needed.

因此，本發明目的之一在於提出一種延遲線電路以及相關方法，以解決上述先前技術之問題。Accordingly, it is an object of the present invention to provide a delay line circuit and related method to solve the problems of the prior art described above.

因此，本發明目的之一在於提出一種延遲線電路以及相關方法。Accordingly, one of the objects of the present invention is to provide a delay line circuit and related methods.

依據本發明之一實施例，一延遲電路用以延遲輸入信號來產生一輸出信號，該延遲電路包括有：一第一加總電路，係接收一輸入信號以及一輸出信號，並輸出一中間信號；以及一第二加總電路，係接收該輸入信號以及該中間信號，並輸出該輸出信號。According to an embodiment of the present invention, a delay circuit is configured to delay an input signal to generate an output signal. The delay circuit includes: a first summing circuit that receives an input signal and an output signal, and outputs an intermediate signal. And a second summing circuit that receives the input signal and the intermediate signal and outputs the output signal.

依據本發明之一實施例，一種延遲電路包括有：複數個延遲單元以串聯方式相耦接，其中，每一延遲單元包括有一回授迴路以及一前饋路徑來擴大該延遲電路的操作頻率範圍。According to an embodiment of the invention, a delay circuit includes: a plurality of delay units coupled in series, wherein each delay unit includes a feedback loop and a feedforward path to expand an operating frequency range of the delay circuit .

依據本發明之一實施例，一種用來延遲一輸入信號的方法，該方法係應用於一電路中，該方法包括有：接收該輸入信號以及一輸出信號；對該輸入信號以及該輸出信號進行一第一權重加法(weighted sum)來產生一中間信號；接收該輸入信號以及該中間信號；以及對該輸入信號以及該中間信號進行一第二權重加法(weighted sum)來產生該輸出信號。According to an embodiment of the invention, a method for delaying an input signal is applied to a circuit, the method comprising: receiving the input signal and an output signal; And the output signal performs a first weighted sum to generate an intermediate signal; receiving the input signal and the intermediate signal; and performing a second weighted sum on the input signal and the intermediate signal This output signal is generated.

藉由閱讀以下本發明之實施例說明以及參照各圖式，本技術領域具有通常知識者可更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The object, technical content, features, and effects achieved by the present invention will become more readily apparent to those of ordinary skill in the art of the invention.

本發明主張美國申請案(申請案號：12/421,647，申請日為2009年04月10日)以及美國申請案(申請案號：12/434,690，申請日為2009年05月04日)之國際優先權。且該二件申請案之內容為本案所引用參考。The present invention claims that the US application (application number: 12/421,647, application date is April 10, 2009) and the US application (application number: 12/434,690, application date is May 4, 2009) priority. And the contents of the two applications are cited in the case.

請參酌本案圖式以閱讀底下的詳細說明，其中本案圖式係以舉例說明的方式，來介紹本發明各種不同的實施例，並供瞭解如何實現本發明。本發明實施例提供了充足的內容，以供本技術領域且有通常知識者來實施本案所揭露之實施例，或實施依本案所揭露之內容所衍生之實施例。須注意的是，該些實施例彼此間並不互斥，且部分實施例可與其它一或多個實施例作適當結合，以形成新的實施例，亦即本發明之實施並不侷限於以下所揭露之實施例。The detailed description of the present invention is set forth by way of example only, and the accompanying claims The embodiments of the present invention provide sufficient content for those skilled in the art and those skilled in the art to implement the embodiments disclosed herein, or the embodiments derived from the disclosure. It should be noted that the embodiments are not mutually exclusive, and some embodiments may be combined with other one or more embodiments to form a new embodiment, that is, the implementation of the present invention is not limited thereto. The embodiments disclosed below.

請參照圖1，其係本發明之一延遲單元100之一實施例之功能方塊圖。該延遲單元100包括有：一第一加總放大器121以及一第二加總放大器(或稱加總電路、放大器)122。該第一加總放大器121接收一輸入信號x以及一輸出信號y，並產生一中間信號z；該第二加總放大器122接收該輸入信號x以及該中間信號z來產生該輸出信號y。Please refer to FIG. 1, which is a functional block diagram of an embodiment of a delay unit 100 of the present invention. The delay unit 100 includes a first summing amplifier 121 and a second summing amplifier (or summing circuit, amplifier) 122. The first summing amplifier 121 receives an input signal x and an output signal y and generates an intermediate signal z; the second summing amplifier 122 receives the input signal x and the intermediate signal z to generate the output signal y.

前述第一加總放大器121所執行之權重加總函數(weighted-sum function)可以下列數學式(1)表示之：Z (s )=(a ₁ ．X (s )+a ₂ ．Y (s ))．G ₁ (s ) (1)The weighted-sum function performed by the aforementioned first summing amplifier 121 can be expressed by the following mathematical formula (1): Z ( s ) = ( a ₁ . X ( s ) + a ₂ . Y ( s )). G ₁ ( s ) (1)

其中X (s )、Y (s )以及Z(s )分別代表x 、y 與z 之拉普拉斯轉換(Laplace transform)，a ₁ 與a ₂ 則分別代表該二加總輸入值x 、y之權重，至於G ₁ (s )則係第一加總放大器121之頻率響應。另外，第二加總放大器212所執行之權重加總函數則可以下列數學式(2)來表示之：Y (s )=(a ₃ ．X (s )+a ₄ ．Z (s ))．G ₂ (s ) (2)Where X ( s ), Y ( s ), and Z( s ) represent the Laplace transform of x , y, and z , respectively, and a ₁ and a ₂ represent the total input values x and y, respectively. The weight, as for G ₁ ( s ), is the frequency response of the first summing amplifier 121. In addition, the weight sum function performed by the second summing amplifier 212 can be expressed by the following mathematical formula (2): Y ( s ) = ( a ₃ . X ( s ) + a ₄ . Z ( s )). G ₂ ( s ) (2)

其中a ₃ 與a ₄ 分別代表該二加總輸入值x 與z 之權重，G ₂ (s )則係第二加總放大器122之頻率響應。將前述數學式(1)、數學式(2)結合，可得如下所示之數學式(3)：Y (s )=X (s )．[a ₃ ．G ₂ (s )+a ₁ ．a ₄ ．G ₁ (s )．G ₂ (s )]/[1-a ₂ ．a ₄ ．G ₁ (s )．G ₂ (s )] (3))Where a ₃ and a ₄ represent the weights of the total input values x and z , respectively, and G ₂ ( s ) is the frequency response of the second summing amplifier 122. Combining the above mathematical formula (1) and mathematical formula (2), the mathematical formula (3) shown below can be obtained: Y ( s ) = X ( s ). [ a ₃ . G ₂ ( s ) + a ₁ . a ₄ . G ₁ ( s ). G ₂ ( s )]/[1- a ₂ . a ₄ . G ₁ ( s ). G ₂ ( s )] (3))

該延遲單元100的轉換函數H (s )=Y (s )/X (s )，如數學式(4)所示：H (s )=[a ₃ ．G ₂ (s )+a ₁ ．a ₄ ．G ₁ (s )．G ₂ (s )]/[1-a ₂ ．a ₄ ．G ₁ (s )．G ₂ (s )] (4)在一實施例中，a ₁ ,a ₃ ，與a ₄ 是正值，a ₂ 是負值。在此實施例中，該延遲單元100包括有一負迴授迴路，該負迴授迴路之作用表現在轉換函式的分母項(即數學式(4)之[1-a ₂ ．a ₄ ．G ₁ (s )．G ₂ (s )])。如一般控制理論所認知，負回授係一種擴展(extending)系統可操作頻寬(operational bandwidth)的有效方法。另外，該延遲單元100包括有一前饋路徑，該前饋路徑之作用則表現在轉換函式(即數學式(4))的分子項。前饋路徑是一種快速路徑，因為它有效地繞效地繞過第一加總放大器121。由於本發明之延遲單元100使用了負迴授迴路以及前饋路徑，所以，該延遲單元100具有很高的頻寬。The transfer function H ( s ) of the delay unit 100 = Y ( s ) / X ( s ), as shown in the mathematical formula (4): H ( s ) = [ a ₃ . G ₂ ( s ) + a ₁ . a ₄ . G ₁ ( s ). G ₂ ( s )]/[1- a ₂ . a ₄ . G ₁ ( s ). G ₂ ( s )] (4) In one embodiment, a ₁ , a ₃ , and a ₄ are positive values, and a ₂ is a negative value. In this embodiment, the delay unit 100 includes a negative feedback loop, and the negative feedback loop functions as a denominator of the conversion function (ie, [1- a ₂ . a ₄ . G of the mathematical formula (4)). ₁ ( s ). G ₂ ( s )]). As recognized by general control theory, negative feedback is an effective way to extend the operational bandwidth of an extended system. In addition, the delay unit 100 includes a feedforward path, and the action of the feedforward path is represented by a molecular term of the conversion function (ie, equation (4)). The feedforward path is a fast path because it effectively bypasses the first summing amplifier 121. Since the delay unit 100 of the present invention uses a negative feedback loop and a feedforward path, the delay unit 100 has a very high bandwidth.

如一般所認知的，加總放大器有各種不同的實施範例。故，於此本說明書僅各以至少一個實施範例進行說明。As is generally recognized, summing amplifiers have a variety of different implementation examples. Therefore, the description herein is only described in each of the at least one embodiment.

圖2顯示了圖1中前述延遲單元100中的第一加總放大器211之範例電路200。於本實施例中，使用了一差動電路之佈局，其中信號係以一正端信號(以下標「+」來表示)以及一負端信號(以下標「-」來表示)來實現。舉例來說，前述信號x 係以正端信號x ₊ 與負端信號x _- 來表示，且信號x 則係等於該正端信號x ₊ 與該負端信號x _- 間之差異。該電路200包含：一第一差動對，其包含二個MOS(例如是：NMOS(n通道金氧半導體))電晶體M₁₊ 與M_1- ；一第二差動對，其包含二個MOS(例如是：NMOS)電晶體M₂₊ 與M_2- ；一第一電流源I₁ ；一第二電流源I₂ ；以及一電阻對R₁₊ 及R_1- 。透過本案揭露可知，V_SS 係指一第一虛擬定電位電路(fixed-potential circuit)節點，通常係指接地點；V_DD 係指一第二虛擬定電位電路節點，通常係指電源供應點。另外，前述第一差動對M₁₊ 、M_1- 係由第一電流源I₁ 所偏壓，並用來接收以及放大前述輸入信號x ，進而提供一放大輸出至前述電阻對R₁₊ 、R_1- ，其中該電阻對R₁₊ 、R_1- 係作為負載之用。又，前述第二差動對M₂₊ 、M_2- 係由第二電流源I₂ 所偏壓，並用來接收以及放大前述輸出信號y ，進而提供一放大輸出至電阻對R₁₊ 、R_1- 。再者，既然該電阻對R₁₊ 、R_1- 係第一差動對M₁₊ 、M_1- 與第二差動對M₂₊ 、M_2- 之共同負載，此二差動對之放大輸出會被加總起來，再產生前述中間信號z 。於本例中，參照前述數學式(1)，係數a ₁ 為一正值，該正值係由該第一差動對M₁₊ 、M_1- 的尺寸(size)以及第一電流源I₁ 的強度 (magnitude)所決定；係數a ₂ 則為一負值，該負值由該第二差動對M₂₊ 、M_2- 的尺寸以及第二電流源I₂ 的強度(或稱為〝大小〞)來決定。2 shows an example circuit 200 of the first summing amplifier 211 in the aforementioned delay unit 100 of FIG. In the present embodiment, the layout of a differential circuit is used, in which the signal is realized by a positive terminal signal (hereinafter referred to as "+") and a negative terminal signal (hereinafter indicated by "-"). For example, the aforementioned signal x is represented by a positive terminal signal x ₊ and a negative terminal signal x ₋ , and the signal x is equal to a difference between the positive terminal signal x ₊ and the negative terminal signal x ₋ . The circuit 200 includes: a first differential pair comprising two MOSs (eg, NMOS (n-channel MOS)) transistors M ₁₊ and M _1- ; a second differential pair comprising two MOS (for example: NMOS) transistors M ₂₊ and M _2- ; a first current source I ₁ ; a second current source I ₂ ; and a resistor pair R ₁₊ and R _1- . As can be seen from the disclosure, V _SS refers to a first virtual fixed-potential circuit node, usually referred to as a grounding point; V _DD refers to a second virtual constant potential circuit node, usually referred to as a power supply point. In addition, the first differential pair M ₁₊ , M _1- is biased by the first current source I ₁ and used to receive and amplify the input signal x , thereby providing an amplified output to the resistor pair R ₁₊ , R _1- , wherein the resistance pair R ₁₊ , R _1- is used as a load. Moreover, the second differential pair M ₂₊ , M _2- is biased by the second current source I ₂ and used to receive and amplify the output signal y to provide an amplified output to the resistor pair R ₁₊ , R _1- . Furthermore, since the resistance pair R ₁₊ , R ₁ is a common load of the first differential pair M ₁₊ , M _1- and the second differential pair M ₂₊ , M _2- , the two differential pairs The amplified outputs are summed to produce the aforementioned intermediate signal z . In this example, referring to the above mathematical formula (1), the coefficient a ₁ is a positive value, which is the size of the first differential pair M ₁₊ , M _1- and the first current source I. ₁ intensity (Magnitude) is determined; a _2, compared with a negative coefficient of the negative value of the second differential pair M _2+, M _2- size and strength of the second current source I ₂ (or referred to as 〝 size 〞) to decide.

圖3A顯示了圖1之前述延遲單元100中的第二加總放大器122之範例電路300。本實施例亦使用一差動電路之佈局。該電路300包含：一第一差動對，其包含二個MOS(例如是：NMOS)電晶體M₃₊ 與M_3- ；一第二差動對，其包含二個MOS(例如是：NMOS)電晶體M₄₊ 與M_4- ；一第一電流源I₃ ；一第二電流源I₄ ；以及一電阻對R₂₊ 及R_2- 。上述第一差動對M₃₊ 、M_3- 係由第一電流源I₃ 所偏壓，並用來接收以及放大前述輸入信號x ，進而提供一放大輸出至前述電阻對R₂₊ 、R_2- ，其中該電阻對R₂₊ 、R_2- 係作為負載之用。又，前述第二差動對M₄₊ 、M_4- 係由第二電流源I₄ 所偏壓，並用來接收以及放大前述中間信號z ，進而提供一放大輸出至電阻對R₂₊ 、R_2- 。再者，既然該電阻對R₂₊ 、R_2- 係第一差動對M₃₊ 、M_3- 與第二差動對M₄₊ 、M_4- 的共同負載，此二差動對之放大輸出也會被加總起來，再產生該輸出信號y 。於本例中，參照前述數學式(2)，係數a ₃ 為一正值，該正值係由該第一差動對M₃₊ 、M_3- 的尺寸以及第一電流源I₃ 的強度來決定；至於係數a ₄ 則為一負值，該負值由該第二差動對M₄₊ 、M_4- 的尺寸以及第二電流源I₄ 的強度來決定。另一實施例(未顯示於圖式)，該中間信號z沒有直接提供作為該第二差動對M₄₊ -M_4- 的輸入。一緩衝電路310被使用且被置於該第一加總放大器121之中間信號z與該第二加總放大器122之該第二差動對M₄₊ -M_4- 之間。如圖3B所示，該緩衝電路310包括有一第三差動對M₅₊ -M_5- 用來接收前述中間信號z ，進而產生一已緩衝信號z' ，該已緩衝信號z' 被作為該第二差動對之輸入。該緩衝電路310還包括有一第三電流源I5用以偏壓該第三差動對M₅₊ -M_5- 。該緩衝電路310還包括有另一電阻對R₃₊ 、RR_3- 係作為該第三差動對M₅₊ -M_5- 。的負載以輸出該已緩衝信號z' 。3A shows an example circuit 300 of a second summing amplifier 122 in the aforementioned delay unit 100 of FIG. This embodiment also uses the layout of a differential circuit. The circuit 300 includes: a first differential pair comprising two MOS (eg, NMOS) transistors M ₃₊ and M _3- ; a second differential pair comprising two MOSs (eg, NMOS) The transistors M ₄₊ and M ₄ ; a first current source I ₃ ; a second current source I ₄ ; and a resistor pair R ₂₊ and R ₂₋ . Said first differential pair M _3+, M _3--based, and for receiving and amplifying the input signal x by the _three first bias current source I, thereby providing an amplified output to the resistors of the R _2+, R _{2 -} , where the resistance pair R ₂₊ , R _2- is used as a load. In addition, the second differential pair M _4+, M _4- system by the second current source I ₄ biased, and for receiving and amplifying the intermediate Z signal, thereby providing an amplified output to the resistors of the R _2+, R _2- . Furthermore, since the resistance pair R ₂₊ , R ₂ is a common load of the first differential pair M ₃₊ , M ₃₋ and the second differential pair M ₄₊ , M ₄ , the two differential pairs The amplified output is also summed up to produce the output signal y . In this example, referring to the above mathematical formula (2), the coefficient a ₃ is a positive value which is the size of the first differential pair M ₃₊ , M ₃₋ and the intensity of the first current source I ₃ . The coefficient a ₄ is a negative value determined by the size of the second differential pair M ₄₊ , M _4- and the intensity of the second current source I ₄ . In another embodiment (not shown), the intermediate signal z is not directly provided as an input to the second differential pair M ₄₊ -M _4- . A buffer circuit 310 is used and is placed between the intermediate signal z of the first summing amplifier 121 and the second differential pair M _{4+ -} M _{4- of} the second summing amplifier 122. As shown in FIG. 3B, the buffer circuit 310 includes a third differential pair M ₅₊ -M ₅ for receiving the intermediate signal z , thereby generating a buffered signal z ' , which is used as the buffered signal z ' The second differential pair is input. The buffer circuit 310 further includes a third current source I5 for biasing the third differential pair M ₅₊ -M _5- . The buffer circuit 310 further includes another resistor pair R ₃₊ , RR _3- as the third differential pair M ₅₊ -M _5- . The load is output to the buffered signal z ' .

請注意：圖2之電路200以及圖3之電路300係僅是舉例說明用，並非是本發明之限制。本技術領域的人員可依據數學式(1)及(2)的特性，利用電腦輔助設計、硬體描述語言(例如：VHDL、VERLOG)或是其他工具，即可設計出的各種變化、實施方式或電路來。因此，能滿足數學式(1)及(2)的各種變化、實施方式或電路，皆是屬於本發明欲保護的標的。Please note that the circuit 200 of FIG. 2 and the circuit 300 of FIG. 3 are for illustrative purposes only and are not limiting of the invention. Those skilled in the art can design various changes and implementation manners according to the characteristics of the mathematical formulas (1) and (2) by using computer-aided design, hardware description language (for example, VHDL, VERLOG) or other tools. Or the circuit comes. Therefore, various changes, embodiments, or circuits that satisfy the mathematical expressions (1) and (2) are subject to the subject matter of the present invention.

此外，圖4所顯示之5階延遲線400僅是一個範例非是其限制(例如是其他階的延遲線)。該5階延遲線400包括有5個電路特性相同或相似的延遲單元401~405(以串聯方式相耦接)，用以接收輸入信號x以及產生5個輸出信號y₁ 、y₂ 、…、y₅ 。該5階延遲線400還包括有一虛擬負載(dummy load)405，作為該最後延遲單元405的終止(termination)，以使得此5個延遲單元具有相同或相似的負載阻抗。一實施例，該延遲單元401~405的每一個皆包括有一負回授迴路以及一前饋路徑。例如是圖1中的延遲單元100的實施方式。In addition, the fifth-order delay line 400 shown in FIG. 4 is only an example and is not a limitation thereof (for example, delay lines of other orders). The fifth-order delay line 400 includes five delay units 401 to 405 having the same or similar circuit characteristics (coupled in series) for receiving the input signal x and generating five output signals y ₁ , y ₂ , . y ₅ . The 5th order delay line 400 also includes a dummy load 405 as a termination of the last delay unit 405 such that the 5 delay units have the same or similar load impedance. In one embodiment, each of the delay units 401-405 includes a negative feedback loop and a feedforward path. This is for example the embodiment of the delay unit 100 in FIG.

以上所述者，僅係本發明之較佳實施例而已，當不能以上述內容限定本發明實施之範圍，例如：可以PMOS電晶體或是其他種類電晶體取代NMOS電晶體。即大凡依本發明申請專利範圍及發明說明內容所作之等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。The above is only the preferred embodiment of the present invention, and the scope of the present invention cannot be limited by the above, for example, a PMOS transistor or other type of transistor can be substituted for the NMOS transistor. That is, the equivalent changes and modifications made by the invention in the scope of the invention and the scope of the invention are still within the scope of the invention.

100‧‧‧延遲單元100‧‧‧Delay unit

121、200‧‧‧第一加總電路121, 200‧‧‧ first total circuit

122、300‧‧‧第二加總電路122, 300‧‧‧second total circuit

400‧‧‧5階延遲線電路400‧‧‧5th order delay line circuit

401~405‧‧‧延遲單元401~405‧‧‧Delay unit

410‧‧‧虛擬負載(dummy load)410‧‧‧dummy load

圖1係依據本發明所繪製之寬頻帶主動式延遲單元的功能方塊圖之圖式。1 is a block diagram of a functional block diagram of a broadband active delay unit depicted in accordance with the present invention.

圖2係顯示圖1之第一加總放大器的一實施例的電路圖之圖式。2 is a circuit diagram showing an embodiment of the first summing amplifier of FIG. 1.

圖3A係顯示圖1之第二加總放大器的一實施例的電路圖之圖式。3A is a circuit diagram showing an embodiment of the second summing amplifier of FIG. 1.

圖3B係顯示可與圖3A之第二加總放大器相結合的一緩衝電路的電路圖之圖式。Figure 3B is a circuit diagram showing a snubber circuit that can be combined with the second summing amplifier of Figure 3A.

圖4係依據本發明之包含複數個寬頻帶主動式延遲單元之延遲線電路的功能方塊圖。4 is a functional block diagram of a delay line circuit including a plurality of wideband active delay cells in accordance with the present invention.

100．．．延遲單元100. . . Delay unit

121．．．第一加總電路121. . . First summing circuit

122．．．第二加總電路122. . . Second summing circuit

Claims

一種延遲電路，用以延遲輸入信號來產生一輸出信號，該延遲電路包含：一第一加總電路，係接收該輸入信號以及該輸出信號，並輸出一中間信號；以及一第二加總電路，係接收該輸入信號以及該中間信號，並輸出該輸出信號。 A delay circuit for delaying an input signal to generate an output signal, the delay circuit comprising: a first summing circuit receiving the input signal and the output signal, and outputting an intermediate signal; and a second summing circuit Receiving the input signal and the intermediate signal, and outputting the output signal.

如申請專利範圍第1項所述之電路，其中該第一加總電路還包含：一第一差動對及一第二差動對，用以分別接收該輸入信號以及該輸出信號。 The circuit of claim 1, wherein the first summing circuit further comprises: a first differential pair and a second differential pair for respectively receiving the input signal and the output signal.

如申請專利範圍第2項所述之電路，其中該第一差動對及該第二差動對係耦接一負載，用以產生該中間信號。 The circuit of claim 2, wherein the first differential pair and the second differential pair are coupled to a load for generating the intermediate signal.

如申請專利範圍第3項所述之電路，還包括有：二電流源，係分別提供電流至該第一差動對及該第二差動對，以偏壓該第一差動對及該第二差動對。 The circuit of claim 3, further comprising: two current sources respectively supplying current to the first differential pair and the second differential pair to bias the first differential pair and the The second differential pair.

如申請專利範圍第1或2項所述之電路，其中該第二加總電路還包含：一第三差動對及一第四差動對，用以分別接收該輸入信號以及該中間信號。 The circuit of claim 1 or 2, wherein the second summing circuit further comprises: a third differential pair and a fourth differential pair for receiving the input signal and the intermediate signal, respectively.

如申請專利範圍第5項所述之電路，還包括有：一共有負載，係產生該輸出信號。 The circuit of claim 5, further comprising: a common load, the output signal is generated.

如申請專利範圍第1項所述之電路，其中該該的轉移函數為H (s )=[a ₃ ．G ₂ (s )+a ₁ ．a ₄ ．G ₁ (s )．G ₂ (s )]/[1-a ₂ ．a ₄ ．G ₁ (s )．G ₂ (s )]，其中，a ₁ 與a ₂ 係分別為該第一加總電路的二個輸入的權重(weight)，a ₃ 與a ₄ 係分別為該第二加總電路的二個輸入的權重，G ₁ (s )與G ₂ (s )係分別為該第一加總電路與該第二加總電路的頻率響應。The circuit of claim 1, wherein the transfer function is H ( s ) = [ a ₃ . G ₂ ( s ) + a ₁ . a ₄ . G ₁ ( s ). G ₂ ( s )]/[1- a ₂ . a ₄ . G ₁ ( s ). G ₂ ( s )], wherein a ₁ and a ₂ are the weights of the two inputs of the first summing circuit, respectively, and a ₃ and a ₄ are respectively two of the second summing circuits The input weights, G ₁ ( s ) and G ₂ ( s ) are the frequency responses of the first summing circuit and the second summing circuit, respectively.

如申請專利範圍第8項所述之電路，其中a ₁ ,a ₃ ，與a ₄ ar是正值，以及a ₂ 是負值。The circuit of claim 8, wherein a ₁ , a ₃ , and a ₄ ar are positive values, and a ₂ is a negative value.

如申請專利範圍第1項所述之電路，其中該電路包括有一前饋路徑。 The circuit of claim 1, wherein the circuit includes a feedforward path.

如申請專利範圍第1或10項所述之電路，其中該電路包括有一回授路徑。 The circuit of claim 1 or 10, wherein the circuit includes a feedback path.

一種延遲電路，包括有：複數個延遲單元以串聯方式相耦接，其中，每一延遲單元包括有一回授迴路以及一前饋路徑來擴大該延遲電路的操作頻率範圍。 A delay circuit includes: a plurality of delay units coupled in series, wherein each delay unit includes a feedback loop and a feedforward path to expand an operating frequency range of the delay circuit.

如申請專利範圍第12項所述之電路，其中該負回授迴路包括有：一第一加總電路、一第二加總電路，該第二加總電路的輸出端係與該第一加總電路的輸入端相耦接。 The circuit of claim 12, wherein the negative feedback loop comprises: a first summing circuit and a second summing circuit, the output of the second summing circuit is coupled to the first plus The input terminals of the main circuit are coupled.

如申請專利範圍第13項所述之電路，其中該前饋路徑包括有：該第二加總電路。 The circuit of claim 13, wherein the feedforward path comprises: the second summing circuit.

一種用來延遲一輸入信號的方法，該方法係應用於一電路中，該方法包括有；接收該輸入信號以及一輸出信號；對該輸入信號以及該輸出信號進行一第一權重加法(weighted sum)來產生一中間信號；接收該輸入信號以及該中間信號；以及對該輸入信號以及該中間信號進行一第二權重加法(weighted sum)來產生該輸出信號。 A method for delaying an input signal, the method being applied to a circuit, the method comprising: receiving the input signal and an output signal; performing a first weight addition on the input signal and the output signal (weighted sum Generating an intermediate signal; receiving the input signal and the intermediate signal; and performing a second weighted sum on the input signal and the intermediate signal to generate the output signal.

如申請專利範圍第15項所述之方法，其中在接收該輸入信號以及該輸出信號之步驟中還包括：利用該電路的一第一差動對與一第二差動對來分別接收該輸入信號以及該輸出信號。 The method of claim 15, wherein the step of receiving the input signal and the output signal further comprises: A first differential pair and a second differential pair of the circuit are used to receive the input signal and the output signal, respectively.

如申請專利範圍第16項所述之方法，其中在對該輸入信號以及該輸出信號進行該第一權重加法之步驟中還包括：利用該電路的一第一負載來執行該第一權重加法。 The method of claim 16, wherein the step of performing the first weight addition on the input signal and the output signal further comprises performing the first weight addition using a first load of the circuit.

如申請專利範圍第15項所述之方法，其中在接收該輸入信號以及該中間信號之步驟中還包括：利用該電路的一第三差動對與一第四差動對來分別接收該輸入信號與該中間信號。 The method of claim 15, wherein the step of receiving the input signal and the intermediate signal further comprises: receiving the input by using a third differential pair and a fourth differential pair of the circuit respectively Signal and the intermediate signal.

如申請專利範圍第18項所述之方法，其中在對該輸入信號以及該中間信號進行該第二權重加法之步驟中還包括：利用該電路的一第二負載來執行該第二權重加法。 The method of claim 18, wherein the step of performing the second weight addition on the input signal and the intermediate signal further comprises: performing the second weight addition using a second load of the circuit.

如申請專利範圍第15項所述之方法，該電路包括有有一回授迴路以及一前饋路徑。 The method of claim 15, wherein the circuit includes a feedback loop and a feedforward path.