TWI478326B - Semiconducting multi-layer structure and method for manufacturing the same - Google Patents
Semiconducting multi-layer structure and method for manufacturing the same Download PDFInfo
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本發明是有關於一種半導體多層結構及其製造方法，且特別是有關於一種記憶體之半導體多層結構及其製造方法之裝置。The present invention relates to a semiconductor multilayer structure and a method of fabricating the same, and more particularly to a semiconductor multilayer structure of a memory and a device for fabricating the same.
隨著電子產品的開發與市場銷售的成長，記憶體的需求也跟著提高。記憶體有許多不同種類，例如可粗略分為非揮發性記憶體(Non-Volatile Memory，NVM)及揮發性記憶體(Volatile Memory，VM)。With the development of electronic products and the growth of market sales, the demand for memory has also increased. There are many different types of memory, such as a non-volatile memory (Non-Volatile Memory, NVM) and a volatile memory (VM).
動態隨機存取記憶體(DRAM)或快取記憶體(Cache Memory)係屬於揮發性記憶體(Volatile Memory)，其存取速度較快。不過，由於儲存在非揮發性記憶體裡的資料不會因為電流的關閉而消失，因此，非揮發性記憶體可當成是如硬碟一般的資訊儲存元件。依記憶體內的資料是否能在使用電腦時隨時改寫為標準，非揮發性記憶體中又可分為ROM(Read Only Memory)和Flash(快閃記憶體)兩大類。目前Flash正廣泛應用在各種不同領域，尤其是手機、數位相機、MP3播放器等行動產品。Dynamic random access memory (DRAM) or Cache Memory is a volatile memory (Volatile Memory) with faster access speed. However, since the data stored in the non-volatile memory does not disappear due to the current being turned off, the non-volatile memory can be regarded as an information storage component such as a hard disk. Whether the data in the memory can be rewritten as a standard at any time when using the computer, the non-volatile memory can be divided into two categories: ROM (Read Only Memory) and Flash (Flash Memory). Currently, Flash is widely used in various fields, especially mobile phones, digital cameras, MP3 players and other mobile products.
為了讓記憶體在有限的體積下具有更高儲存容量，發展出一種高容量儲存型三維(3D)記憶體，元件之間的間距更為緊密，且單位面積的元件密度更高。In order to make the memory have a higher storage capacity under a limited volume, a high-capacity storage type three-dimensional (3D) memory has been developed, the spacing between components is closer, and the density of components per unit area is higher.
本發明係有關於一種半導體多層結構及其製造方法。此種半導體多層結構，不需要摻雜離子即可以形成電流通道。The present invention relates to a semiconductor multilayer structure and a method of fabricating the same. Such a semiconductor multilayer structure can form a current path without doping ions.
根據本發明之第一方面，提出一種半導體多層結構，包括複數層第一導電層、複數層第一絕緣層及一第二導電層。此些第一導電層彼此間隔地設置，每一個第一導電層具有一上表面、與上表面相對而設之一下表面及兩側壁。第一絕緣層，環繞於第一導電層之周圍，且每一個第一絕緣層至少覆蓋每一個第一導電層之上表面的一部分、下表面的一部分以及兩側壁。第二導電層覆蓋第一導電層與第一絕緣層。According to a first aspect of the present invention, a semiconductor multilayer structure is provided comprising a plurality of first conductive layers, a plurality of first insulating layers, and a second conductive layer. The first conductive layers are spaced apart from each other, and each of the first conductive layers has an upper surface, a lower surface opposite to the upper surface, and two side walls. The first insulating layer surrounds the first conductive layer, and each of the first insulating layers covers at least a portion of the upper surface of each of the first conductive layers, a portion of the lower surface, and both sidewalls. The second conductive layer covers the first conductive layer and the first insulating layer.
根據本發明之第二方面，提出一種半導體多層結構的製造方法，此方法包括以下步驟。形成複數層第一導電層，彼此間隔地設置，每一個第一導電層具有一上表面、與上表面相對而設之一下表面及兩側壁。形成複數層第一絕緣層，環繞於第一導電層之周圍，且每一個第一絕緣層至少覆蓋每一個第一導電層之上表面的一部分、下表面的一部分以及兩側壁。形成一第二導電層，覆蓋第一導電層與第一絕緣層。According to a second aspect of the present invention, a method of fabricating a semiconductor multilayer structure is provided, the method comprising the following steps. A plurality of first conductive layers are formed, spaced apart from each other, each of the first conductive layers having an upper surface, a lower surface opposite the upper surface, and two side walls. A plurality of first insulating layers are formed to surround the first conductive layer, and each of the first insulating layers covers at least a portion of the upper surface of each of the first conductive layers, a portion of the lower surface, and both sidewalls. Forming a second conductive layer covering the first conductive layer and the first insulating layer.
根據本發明之第三方面，提出一種半導體多層結構，半導體多層結構用於一記憶體裝置。半導體多層結構包括 複數層導電層、複數層閘氧化層及一閘極層。此些導電層，彼此間隔而設，每一個導電層具有一上表面、與上表面相對而設之一下表面及一側壁。此些閘氧化層，環繞於導電層之周圍，且每一個閘氧化層至少覆蓋每一個導電層之上表面的一部分、下表面的一部分以及側壁。閘極層覆蓋導電層與閘氧化層。According to a third aspect of the present invention, a semiconductor multilayer structure for a memory device is proposed. Semiconductor multilayer structure includes a plurality of conductive layers, a plurality of gate oxide layers, and a gate layer. The conductive layers are spaced apart from each other, and each of the conductive layers has an upper surface, a lower surface opposite to the upper surface, and a sidewall. The gate oxide layers surround the conductive layer, and each of the gate oxide layers covers at least a portion of the upper surface of each of the conductive layers, a portion of the lower surface, and sidewalls. The gate layer covers the conductive layer and the gate oxide layer.
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:
請參考第1圖，其繪示依照本發明一實施例之記憶體裝置的局部示意圖。如第1圖所示，記憶體裝置10具有陣列區12、指叉狀結構13及半導體多層結構14。記憶體裝置10例如係一三維反及閘(NAND)快閃記憶體，x軸、y軸及z軸相互垂直。半導體多層結構14包括第一導電層142、第一絕緣層144、一第二導電層146、第二絕緣層148、通孔140a、140b、140c及140d及第三導電層141a、141b、141c及141d。Please refer to FIG. 1 , which is a partial schematic view of a memory device according to an embodiment of the invention. As shown in FIG. 1, the memory device 10 has an array region 12, a finger-like structure 13, and a semiconductor multilayer structure 14. The memory device 10 is, for example, a three-dimensional NAND flash memory, and the x-axis, the y-axis, and the z-axis are perpendicular to each other. The semiconductor multilayer structure 14 includes a first conductive layer 142, a first insulating layer 144, a second conductive layer 146, a second insulating layer 148, via holes 140a, 140b, 140c, and 140d, and third conductive layers 141a, 141b, and 141c. 141d.
第一導電層142例如係包括多晶矽，第一絕緣層144例如係氧化物所形成之閘氧化層，第二導電層146例如係一輔助閘極(assist gate)層，覆蓋第一導電層142及第一絕緣層144。第二絕緣層148可以包括一氧化物，第二絕緣層148與第一導電層142交錯排列。於一實施例 中，可以不需要第二絕緣層148，藉由指叉狀結構13，支撐間隔設置的第一導電層142。The first conductive layer 142 includes, for example, a polysilicon layer, the first insulating layer 144 is, for example, a gate oxide layer formed of an oxide, and the second conductive layer 146 is, for example, an auxiliary gate layer covering the first conductive layer 142 and The first insulating layer 144. The second insulating layer 148 may include an oxide, and the second insulating layer 148 is staggered with the first conductive layer 142. In an embodiment The second conductive layer 148 may be omitted, and the first conductive layer 142 disposed at intervals may be supported by the interdigitated structure 13.
通孔140a~140d例如係一接觸窗(contact)，相鄰之通孔140a~140d的深度不相同，分別貫穿至第一導電層142中至少其中一層。舉例來說，如第1圖所示，半導體多層結構14設有四個通孔140a~140d，分別以不同深度貫穿半導體多層結構14至所對應的第一導電層142。可以依序增加通孔140a~140d所貫穿的層數。亦即，通孔140a貫穿至由上而下之第一層第一導電層142，通孔140b貫穿至由上而下之第二層第一導電層142，通孔140c貫穿至由上而下之第三層第一導電層142，通孔140d貫穿至由上而下之第四層第一導電層142。通孔140a~140d的數目係與第一導電層142的層數有關，通孔140a~140d分別填充而設有第三導電層141a~141d，第三導電層141a~141d例如係導電接觸層，用以電性連接至對應的第一導電層142。於此實施例中，係僅以四層堆疊的第一導電層142為例作說明。當然，第一導電層142的層數可以依照製程及產品需求作增減，並不作限制。The through holes 140a-140d are, for example, a contact, and the adjacent through holes 140a-140d have different depths and penetrate through at least one of the first conductive layers 142, respectively. For example, as shown in FIG. 1, the semiconductor multilayer structure 14 is provided with four through holes 140a-140d penetrating the semiconductor multilayer structure 14 to the corresponding first conductive layer 142 at different depths. The number of layers through which the through holes 140a to 140d are penetrated may be sequentially increased. That is, the through hole 140a penetrates through the first layer of the first conductive layer 142 from top to bottom, the through hole 140b penetrates to the second layer of the first conductive layer 142 from top to bottom, and the through hole 140c penetrates from top to bottom The third layer of the first conductive layer 142, the through hole 140d penetrates to the fourth layer of the first conductive layer 142 from top to bottom. The number of the via holes 140a-140d is related to the number of layers of the first conductive layer 142, the via holes 140a-140d are respectively filled with the third conductive layers 141a-141d, and the third conductive layers 141a-141d are, for example, conductive contact layers. It is electrically connected to the corresponding first conductive layer 142. In this embodiment, the first conductive layer 142 stacked in four layers is taken as an example for illustration. Of course, the number of layers of the first conductive layer 142 can be increased or decreased according to the process and product requirements, and is not limited.
於此實施例中，為了讓記憶體的容量提升，且體積微型化，元件之間的間距可以緊密設置，且提高單位面積的元件密度。因此，透過電壓的施加，第一導電層142之間可在無離子佈植的狀況下自動形成接面，第1圖所示之記憶體裝置10即為此種類型之無接面(junction-free)的三維 記憶體的一種態樣。In this embodiment, in order to increase the capacity of the memory and to miniaturize the volume, the spacing between the elements can be tightly set and the component density per unit area can be increased. Therefore, by the application of the voltage, the junction between the first conductive layers 142 can be automatically formed without ion implantation, and the memory device 10 shown in FIG. 1 is a junction of this type (junction- Free) 3D A form of memory.
藉由第三導電層141a~141d所施加電位的開啟(例如係1)或關閉(例如係0)，可以決定所選擇的第一導電層142。於一實施例中，半導體多層結構14的第二導電層146可以進一步圖案化為連線層，以連線半導體多層結構14所選擇的第一導電層142至陣列區12。不過，第二導電層146例如係包括多晶矽，在沒有離子摻雜的狀況下，仍然可能有較高的阻值，影響記憶體裝置10的讀取速度。當半導體多層結構14所堆疊的層數很厚時，離子佈植製程無法將離子均勻地植入結構中。也就是說，可能上層結構接收到較高濃度的離子植入，下層結構僅接收到較低濃度的離子植入。若以每一層結構作個別的離子植入，則製程上需要使用多個光罩，耗費高昂的成本。The selected first conductive layer 142 can be determined by the turn-on (eg, 1) or off (eg, 0) potential applied by the third conductive layers 141a-141d. In one embodiment, the second conductive layer 146 of the semiconductor multilayer structure 14 can be further patterned into a wiring layer to connect the first conductive layer 142 selected by the semiconductor multilayer structure 14 to the array region 12. However, the second conductive layer 146 includes, for example, polysilicon, and in the absence of ion doping, there may still be a higher resistance value, which affects the reading speed of the memory device 10. When the number of layers stacked by the semiconductor multilayer structure 14 is very thick, the ion implantation process cannot uniformly implant ions into the structure. That is, it is possible that the upper structure receives a higher concentration of ion implantation and the lower structure receives only a lower concentration of ion implantation. If individual ion implantation is performed in each layer structure, a plurality of masks are required in the process, which is costly.
於本發明一實施例中，藉由第一導電層142及第二導電層146之間相隔第一絕緣層144的界面設計，使得電壓施加於第二導電層146後，可以誘導第一導電層142及第一絕緣層144之間的界面產生導電電子層(反轉層)，產生電流通道。如此一來，不需要藉由離子摻雜層，即可以降低第二導電層146的阻值。因此，不需要執行任何複雜的離子佈植製程，即可以有效提升記憶體的讀寫速度。In an embodiment of the invention, the interface between the first conductive layer 142 and the second conductive layer 146 is separated from the first insulating layer 144, so that after the voltage is applied to the second conductive layer 146, the first conductive layer can be induced. An interface between the 142 and the first insulating layer 144 generates a conductive electron layer (inversion layer) to generate a current path. In this way, the resistance of the second conductive layer 146 can be reduced without using an ion doped layer. Therefore, it is not necessary to perform any complicated ion implantation process, that is, the reading and writing speed of the memory can be effectively improved.
第2~5圖繪示如第1圖之半導體多層結構14，沿A-A’切線之剖面的結構製造流程圖。請先參考第2圖， 提供導電材料142’與絕緣材料148’交錯設置的結構。導電材料142’例如係包括一多晶矽，絕緣材料例如包括一氧化物。請參考第2~3圖，執行一光罩製程，以圖案化絕緣材料148’。圖案化絕緣材料148’的方式可以係以濕式蝕刻的方式，例如係利用濕蝕刻液BOE(Buffer Oxide Etch)，對未受到導電材料142’覆蓋的絕緣材料148’進行蝕刻，移除絕緣材料148’之兩側部分，以形成第二絕緣層148。經過圖案化製程後，第一導電層142之寬度係大於第二絕緣層148之寬度。2 to 5 are views showing a structural manufacturing flow chart of the cross section taken along the line A-A' of the semiconductor multilayer structure 14 of Fig. 1. Please refer to Figure 2 first. A structure in which the conductive material 142' and the insulating material 148' are alternately disposed is provided. The conductive material 142' includes, for example, a polysilicon, and the insulating material includes, for example, an oxide. Referring to Figures 2 through 3, a mask process is performed to pattern the insulating material 148'. The insulating material 148 ′ may be patterned by wet etching, for example, by using a wet etching solution BOE (Buffer Oxide Etch) to etch the insulating material 148 ′ not covered by the conductive material 142 ′ to remove the insulating material. The two side portions of 148' are formed to form a second insulating layer 148. After the patterning process, the width of the first conductive layer 142 is greater than the width of the second insulating layer 148.
請參考第3圖，第一導電層142及第二絕緣層148交錯設置。第一導電層142具有上表面S1、側壁S2及下表面S3，下表面S3與上表面S1相對而設。然後，形成第一絕緣層144環繞於第一導電層142之周圍，且第一絕緣層144至少覆蓋第一導電層142之上表面S1的一部分、側壁S2以及下表面S3的一部分。可以利用沈積絕緣層、沈積氧化物或者熱氧化的方式形成第一絕緣層144。第一絕緣層144具有一厚度h1，厚度h1係介於2奈米(nm)至500奈米(nm)。較佳地，可以選擇厚度h1介於2奈米(nm)至100奈米(nm)。Referring to FIG. 3, the first conductive layer 142 and the second insulating layer 148 are alternately arranged. The first conductive layer 142 has an upper surface S1, a side wall S2, and a lower surface S3, and the lower surface S3 is opposite to the upper surface S1. Then, the first insulating layer 144 is formed to surround the first conductive layer 142, and the first insulating layer 144 covers at least a portion of the upper surface S1 of the first conductive layer 142, the sidewall S2, and a portion of the lower surface S3. The first insulating layer 144 may be formed by depositing an insulating layer, depositing an oxide, or thermally oxidizing. The first insulating layer 144 has a thickness h1 and a thickness h1 ranging from 2 nanometers (nm) to 500 nanometers (nm). Preferably, the thickness h1 can be selected to be between 2 nanometers (nm) and 100 nanometers (nm).
請參考第4圖，形成導電材料146’。可以利用沈積多晶矽的方式，形成導電材料146’，以覆蓋第一導電層142與第一絕緣層144。請參考第4~5圖，圖案化導電材料146’以形成第二導電層146。於一實施例中，可以施加一 電壓至第二導電層146，此時，第一導電層142鄰近第一絕緣層144之接面處，會形成一反轉層(inversion layer)142a，第一導電層142的其餘部位則係一非反轉層142b。Referring to Figure 4, a conductive material 146' is formed. The conductive material 146' may be formed by depositing a polysilicon to cover the first conductive layer 142 and the first insulating layer 144. Referring to Figures 4 through 5, conductive material 146' is patterned to form second conductive layer 146. In an embodiment, one can be applied The voltage is applied to the second conductive layer 146. At this time, the first conductive layer 142 is adjacent to the junction of the first insulating layer 144, and an inversion layer 142a is formed. The rest of the first conductive layer 142 is a Non-inverting layer 142b.
如第5圖所示，第二導電層146的寬度w2，係大於第一導電層142的寬度w3及第一絕緣層144的厚度h1之總和。於一實施例中，第一絕緣層144的厚度h1例如係2nm至500nm，較佳地係2nm至100nm，可以根據反轉層142a的阻值，調整第一絕緣層144的厚度h1。第一導電層之寬度w3例如係100nm至700nm，第二導電層146的寬度w2例如係200nm至1500nm。此外，第一絕緣層144覆蓋第一導電層142之上表面S1的寬度w1例如係5奈米至1000奈米。As shown in FIG. 5, the width w2 of the second conductive layer 146 is greater than the sum of the width w3 of the first conductive layer 142 and the thickness h1 of the first insulating layer 144. In one embodiment, the thickness h1 of the first insulating layer 144 is, for example, 2 nm to 500 nm, preferably 2 nm to 100 nm, and the thickness h1 of the first insulating layer 144 may be adjusted according to the resistance of the inversion layer 142a. The width w3 of the first conductive layer is, for example, 100 nm to 700 nm, and the width w2 of the second conductive layer 146 is, for example, 200 nm to 1500 nm. Further, the width W1 of the first insulating layer 144 covering the upper surface S1 of the first conductive layer 142 is, for example, 5 nm to 1000 nm.
綜上所述，本發明上述實施例之半導體多層結構，可以應用於一三維記憶體裝置中。此種半導體多層結構不需要離子植入(Ion Implant)，也不需要經過太多繁複且高成本的光罩製程即可以製造。而且，藉由第一導電層、絕緣層及第二導電層(輔助閘極層)的接面設計，使得施加電壓至第二導電層(輔助閘極層)時，於第一導電層與絕緣層的接面處形成反轉層降低阻值，可以提升電流傳導速度，進而改善三維記憶體的讀取速度。In summary, the semiconductor multilayer structure of the above embodiment of the present invention can be applied to a three-dimensional memory device. Such a semiconductor multilayer structure does not require ion implantation (Ion Implant) and can be fabricated without going through too many complicated and costly mask processes. Moreover, by the junction design of the first conductive layer, the insulating layer and the second conductive layer (auxiliary gate layer), when the voltage is applied to the second conductive layer (auxiliary gate layer), the first conductive layer and the insulating layer are insulated The formation of the inversion layer at the junction of the layer reduces the resistance, which can increase the current conduction speed, thereby improving the reading speed of the three-dimensional memory.
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常 知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. It is common in the technical field to which the present invention pertains Those skilled in the art can make various changes and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
10‧‧‧記憶體裝置10‧‧‧ memory device
12‧‧‧陣列區12‧‧‧Array area
13‧‧‧指叉狀結構13‧‧‧-fork structure
14‧‧‧半導體多層結構14‧‧‧Semiconductor multilayer structure
140a、140b、140c、140d‧‧‧通孔140a, 140b, 140c, 140d‧‧‧ through holes
141a、141b、141c、141d、142、146‧‧‧導電層141a, 141b, 141c, 141d, 142, 146‧‧‧ conductive layer
142’‧‧‧導電材料142'‧‧‧Electrical materials
142a‧‧‧反轉層142a‧‧‧Reversal layer
142b‧‧‧非反轉層142b‧‧‧ non-inverting layer
144、148‧‧‧絕緣層144, 148‧‧‧ insulation
148’‧‧‧絕緣材料148’‧‧‧Insulation
S1、S3‧‧‧表面S1, S3‧‧‧ surface
S2‧‧‧側壁S2‧‧‧ side wall
h1‧‧‧厚度H1‧‧‧ thickness
w2‧‧‧寬度W2‧‧‧Width
x、y、z‧‧‧軸X, y, z‧‧‧ axis
A-A’‧‧‧切線A-A’‧‧‧ tangent
第1圖係繪示依照本發明一實施例之記憶體裝置的局部示意圖。1 is a partial schematic view of a memory device in accordance with an embodiment of the present invention.
第2~5圖繪示如第1圖之半導體多層結構沿A-A’切線之剖面的結構製造流程圖。2 to 5 are views showing a structural manufacturing flow chart of a cross section of the semiconductor multilayer structure taken along line A-A' of Fig. 1.
14‧‧‧半導體多層結構14‧‧‧Semiconductor multilayer structure
142、146‧‧‧導電層142, 146‧‧‧ conductive layer
142a‧‧‧反轉層142a‧‧‧Reversal layer
142b‧‧‧非反轉層142b‧‧‧ non-inverting layer
144、148‧‧‧絕緣層144, 148‧‧‧ insulation
h1‧‧‧厚度H1‧‧‧ thickness
w1、w2、w3‧‧‧寬度W1, w2, w3‧‧‧ width
Claims (7)
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| TW101128848A TWI478326B (en) | 2012-08-09 | 2012-08-09 | Semiconducting multi-layer structure and method for manufacturing the same |
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| TWI478326B true TWI478326B (en) | 2015-03-21 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6242796B1 (en) * | 1996-12-06 | 2001-06-05 | Hyundai Electronics Industries Co., Ltd. | Wiring structure of semiconductor memory device and formation method thereof |
| US20060006539A1 (en) * | 2004-06-30 | 2006-01-12 | Nec Electronics Corporation | Semiconductor device and semiconductor module employing thereof |
| TW201011900A (en) * | 2008-08-18 | 2010-03-16 | Toshiba Kk | Nonvolatile semiconductor memory device and method for manufacturing same |
| US20110147801A1 (en) * | 2009-12-18 | 2011-06-23 | Jae-Joo Shim | Three-dimensional semiconductor device and method of fabricating the same |
-
2012
- 2012-08-09 TW TW101128848A patent/TWI478326B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6242796B1 (en) * | 1996-12-06 | 2001-06-05 | Hyundai Electronics Industries Co., Ltd. | Wiring structure of semiconductor memory device and formation method thereof |
| US20060006539A1 (en) * | 2004-06-30 | 2006-01-12 | Nec Electronics Corporation | Semiconductor device and semiconductor module employing thereof |
| TW201011900A (en) * | 2008-08-18 | 2010-03-16 | Toshiba Kk | Nonvolatile semiconductor memory device and method for manufacturing same |
| US20110147801A1 (en) * | 2009-12-18 | 2011-06-23 | Jae-Joo Shim | Three-dimensional semiconductor device and method of fabricating the same |
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