TWI478244B

TWI478244B - Metal oxide semiconductor devices having doped silicon-comprising capping layers and methods for fabricating the same

Info

Publication number: TWI478244B
Application number: TW099104105A
Authority: TW
Inventors: Michael Hargrove; Frank Bin Yang; Rohit Pal
Original assignee: Globalfoundries Us Inc
Priority date: 2010-02-10
Filing date: 2010-02-10
Publication date: 2015-03-21
Also published as: TW201128713A

Description

具有經摻雜之含矽蓋層的金氧半導體裝置及其製造方法Metal oxide semiconductor device with doped capping layer and method of manufacturing same

本發明大體上係關於半導體裝置和製造半導體裝置之方法，而尤係關於具有經摻雜之含矽蓋層(下文中亦稱「摻雜含矽蓋層」)的金氧半導體裝置及製造此種金氧半導體裝置之方法。The present invention generally relates to a semiconductor device and a method of fabricating the same, and more particularly to a MOS device having a doped capping layer (hereinafter also referred to as "doped capping layer") and manufacturing the same A method of a MOS device.

多數的現今積體電路(IC)藉由使用複數個互相連接之場效電晶體(FET)(亦稱之為金氧半場效電晶體(MOSFET或MOS電晶體))來施行。一般使用P通道和N通道FET二者來形成IC，於此種情況IC稱之為互補MOS或者CMOS。有持續的傾向加入更多更複雜之電路於單一IC晶片上。為了持續此種傾向，各新的技術世代係減少於電路中各個別裝置之尺寸和裝置元件之間之間隔、或者間距(pitch)。Most current integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs) (also known as metal oxide half field effect transistors (MOSFET or MOS transistors)). The P channel and the N channel FET are generally used to form an IC, in which case the IC is referred to as a complementary MOS or CMOS. There is a continuing tendency to add more complex circuits to a single IC die. In order to continue this tendency, each new technology generation is reduced by the size of the individual devices in the circuit and the spacing, or pitch, between the device components.

當關鍵尺寸微縮時，裝置組件(component)(譬如閘極長度和閘極絕緣層之厚度)係以實質上等比例於各世代之方式被微縮。對於65nm技術世代而言，習知的閘極絕緣體材料(譬如像是熱生長二氧化矽(SiO₂ )或者沉積之氮氧化矽(SiON))當單獨使用時，開始呈現過量的漏電流並且因此只能在電晶體之閘極電極與下方通道之間提供勉強充分的電性隔離。因此，具有介電常數大於約7(本文中稱之為高k介電質)之替代性材料已經考慮使用於先進的裝置，包含先進的CMOS裝置。由高k介電質製成之閘極絕緣體能夠製成較用SiO₂ 或SiON所製成的閘極絕緣體更厚，而不會犧牲電容，並因此提供了明顯減少漏電流之好處。候用的材料包含過渡金屬氧化物、矽酸鹽、和氮氧化物，譬如氧化鉿、矽酸鉿、和氧氮化鉿。When the critical dimension is reduced, the device components (such as the gate length and the thickness of the gate insulating layer) are shrunk in a substantially equal proportion to each generation. For the 65 nm technology generation, conventional gate insulator materials, such as, for example, thermally grown cerium oxide (SiO ₂ ) or deposited cerium oxynitride (SiON), when used alone, begin to exhibit excessive leakage current and thus Only marginal and sufficient electrical isolation can be provided between the gate electrode of the transistor and the lower channel. Thus, alternative materials having dielectric constants greater than about 7 (referred to herein as high-k dielectrics) have been considered for use in advanced devices, including advanced CMOS devices. A gate insulator made of a high-k dielectric can be made thicker than a gate insulator made of SiO ₂ or SiON without sacrificing capacitance, and thus provides a significant reduction in leakage current. The candidate materials include transition metal oxides, silicates, and nitrogen oxides such as ruthenium oxide, ruthenium ruthenate, and bismuth oxynitride.

然而，結合高k介電絕緣體與傳統的多晶矽閘極電極時，對於包含45nm世代者之先進的裝置而言，常導致電晶體具有較最佳臨限電壓為高之臨限電壓(V_t )、和通道移動率和驅動電流為不合意的低。研究人員已經提出：所造成的高V_t 係相關於在高k/多晶矽介面處之缺陷。再者，已經提出：通道移動率之減少主要係導因於表面光子散射(scattering)於高k介電材料中之主要的結果。欲克服此不相容性，從如氮化鈦(TiN)之金屬製造之閘極電極層***置於高性能電晶體之閘極堆疊中之高k絕緣體與多晶矽電極之間。此種金屬閘極有效減緩於通道區域中由高k介電質所引起的光子散射，而導致驅動電流改善。金屬閘極由此克服關聯於將高k介電質用作為閘極絕緣體之問題，並且因此可以藉由使用這些材料所提供之固有的優越絕緣性而進一步微縮至較小的關鍵尺寸。However, when combined with high-k dielectric insulators and conventional polysilicon gate electrodes, for advanced devices including the 45nm generation, the transistor often has a better threshold voltage (V _t ). , and channel mobility and drive current are undesirably low. Researchers have suggested that the resulting high V _t system is related to defects at the high k/polysilicon interface. Furthermore, it has been proposed that the reduction in channel mobility is primarily due to the main result of surface photon scattering in high-k dielectric materials. To overcome this incompatibility, a gate electrode layer made of a metal such as titanium nitride (TiN) is interposed between a high-k insulator and a polysilicon electrode in a gate stack of a high performance transistor. Such a metal gate effectively slows down photon scattering caused by high-k dielectrics in the channel region, resulting in improved drive current. Metal gates thus overcome the problems associated with the use of high-k dielectrics as gate insulators, and thus can be further reduced to smaller critical dimensions by using the inherently superior insulation provided by these materials.

努力最佳化多晶矽/金屬複合物閘極電極裝置已經導致對此種閘極電極之金屬組件之組成和關聯之工作函數(work funtion)的研究。舉例而言，已經證明使用具有最佳化組成和工作函數之金屬閘極能夠獲致於所希望之V_t 或者接近所希望之V_t 進行操作之電晶體。再者，當將金屬層加到多晶矽電極時，當操作於直流(DC)模式時，因為此種閘極之低電阻，故能夠改進譬如通道驅動電流之裝置性能特性。然而，當操作於交流(AC)模式時，此種裝置之AC閘極阻抗已經顯示為不可接受之高。已經提出：高閘極阻抗也許是肇因於在閘極電極內於金屬/多晶矽介面處之缺陷。高AC閘極阻抗會由於劣化切換速度而不利地影響裝置性能，而因此不利地影響可以操作電晶體裝置之頻率。Efforts to optimize polysilicon/metal composite gate electrode devices have led to the study of the composition and associated work funtion of the metal components of such gate electrodes. For example, the use of a metal gate has been demonstrated with the best of the composition and functions of the electrode can be eligible for the actuator to the desired or close to the desired V _t V _t for the operation of the transistor. Furthermore, when a metal layer is applied to a polysilicon electrode, when operating in a direct current (DC) mode, because of the low resistance of such a gate, device performance characteristics such as channel drive current can be improved. However, the AC gate impedance of such devices has been shown to be unacceptably high when operating in alternating current (AC) mode. It has been suggested that the high gate impedance may be due to defects in the metal/polysilicon interface in the gate electrode. High AC gate impedance can adversely affect device performance due to degraded switching speeds, thus adversely affecting the frequency at which the transistor device can be operated.

因此，希望提供一種半導體裝置，其具有經摻雜之含矽蓋層插置於複合閘極電極之金屬與多晶矽層之間，以減少此種閘極之AC阻抗。而且亦希望提供製造此種半導體裝置之方法。再者，由本發明之後續的詳細說明，和所附的申請專利範圍，結合所附圖式和本發明之此先前技術，則本發明之其他所希望之特徵和特性將變得清楚。Accordingly, it is desirable to provide a semiconductor device having a doped cap layer interposed between a metal and a polysilicon layer of a composite gate electrode to reduce the AC impedance of such a gate. It is also desirable to provide a method of fabricating such a semiconductor device. Further, other desirable features and characteristics of the present invention will become apparent from the Detailed Description of the appended claims.

本發明提供用來形成包括半導體基板之半導體裝置之方法。依照一個實施例，該方法包括下列步驟：形成高k介電層以覆蓋該半導體基板；形成含金屬閘極層以覆蓋該高k介電層；形成經摻雜之含矽蓋層以覆蓋該含金屬閘極層；以及沉積含矽閘極層以覆蓋該經摻雜之含矽蓋層。The present invention provides a method for forming a semiconductor device including a semiconductor substrate. In accordance with an embodiment, the method includes the steps of: forming a high-k dielectric layer to cover the semiconductor substrate; forming a metal-containing gate layer to cover the high-k dielectric layer; forming a doped capping layer to cover the a metal-containing gate layer; and depositing a germanium-containing gate layer to cover the doped germanium-containing cap layer.

依照另一個範例實施例，提供用來於具有第一區域和第二區域之半導體基板上製造半導體裝置之其他方法。該方法包括下列步驟：形成通道層，該通道層包括覆蓋該半導體基板之該第二區域之受壓縮應力之半導體材料；形成高k介電層以覆蓋該半導體基板之該第一區域和該通道層；沉積含金屬閘極層以覆蓋該高k介電層；形成經摻雜之矽蓋層以覆蓋該含金屬閘極層；形成含矽閘極層以覆蓋該經摻雜之矽蓋層；以及加熱該基板。In accordance with another exemplary embodiment, other methods are provided for fabricating a semiconductor device on a semiconductor substrate having a first region and a second region. The method includes the steps of: forming a channel layer comprising a compressively stressed semiconductor material overlying the second region of the semiconductor substrate; forming a high-k dielectric layer to cover the first region of the semiconductor substrate and the channel Depositing a metal-containing gate layer to cover the high-k dielectric layer; forming a doped cap layer to cover the metal-containing gate layer; forming a germanium-containing gate layer to cover the doped cap layer And heating the substrate.

提供一種具有覆蓋半導體基板之閘極堆疊的半導體裝置。依照另一個範例實施例，該閘極堆疊包括：高k介電層，配置成覆蓋該半導體基板；含金屬閘極層，配置成覆蓋該高k介電層；經摻雜之含矽蓋層，配置成覆蓋該含金屬閘極層；以及含矽閘極層，覆蓋該經摻雜之含矽蓋層。A semiconductor device having a gate stack overlying a semiconductor substrate is provided. According to another exemplary embodiment, the gate stack includes: a high-k dielectric layer configured to cover the semiconductor substrate; a metal-containing gate layer configured to cover the high-k dielectric layer; and a doped capping layer Configuring to cover the metal-containing gate layer; and a germanium-containing gate layer covering the doped germanium-containing cap layer.

本發明之下列詳細說明本質上僅僅為範例，並不打算用來限制本發明或者本發明之應用和使用。再者，並不欲受前面之先前技術(background of the invention)或下列之實施方式(detail description of the invention)中所表現之任何理論之限制。The following detailed description of the invention is intended to be illustrative and not restrictive Furthermore, there is no desire to be bound by any theory expressed in the foregoing background of the invention or the detailed description of the invention.

本發明之各種實施例說明用以製造具有下述閘極電極之NMOS和PMOS電晶體(NFET或PFET)的方法，其中，該閘極具有經摻雜之矽或者摻雜之金屬矽化物蓋層以減少於此種裝置中之閘極阻抗。於這些實施例中，這些方法包含形成摻雜之矽蓋層插置於複合電晶體閘極堆疊之金屬與多晶矽閘極電極之間。摻雜之矽蓋層係提供一個導電性過渡層(conductive transitional layer)，其可減少咸信是造成不希望之高閘極阻抗的一個原因之此介面之缺陷。於一些該等實施例中，經摻雜之矽蓋層結合矽化物形成用金屬蓋層而使用，其中，該金屬蓋層插置於經摻雜之矽蓋層與多晶矽閘極層之間。當基板於後續的製程過程中被充分加熱時，經摻雜之矽蓋層和矽化物形成用金屬蓋層反應以形成金屬矽化物層。此種金屬矽化物層亦減少界面的缺陷並且進一步增加閘極電極的導電率。金屬矽化物蓋層結構因此可以進一步將閘極阻抗減少至低於單獨使用摻雜之矽蓋層所能得到之水準。Various embodiments of the invention illustrate a method for fabricating an NMOS and PMOS transistor (NFET or PFET) having a gate electrode having a doped germanium or doped metal telluride cap layer To reduce the gate impedance in such devices. In these embodiments, the methods include forming a doped cap layer interposed between the metal of the composite transistor gate stack and the polysilicon gate electrode. The doped cap layer provides a conductive transitional layer that reduces the defect that this interface is one of the causes of undesirably high gate impedance. In some such embodiments, the doped cap layer is used in conjunction with a metal cap layer for telluride formation, wherein the cap layer is interposed between the doped cap layer and the polysilicon gate layer. The doped cap layer and the telluride forming metal cap layer react to form a metal telluride layer as the substrate is sufficiently heated during subsequent processing. Such a metal telluride layer also reduces interface defects and further increases the conductivity of the gate electrode. The metal telluride cap layer structure can thus further reduce the gate impedance to a level lower than that achieved by using a doped cap layer alone.

第1至9圖示意地顯示依照本發明之範例實施例半導體MOS電晶體裝置10之一部分之剖面圖和用來製造此種半導體裝置方法。本文中所述之該實施例適用於N通道MOS(NMOS)和P通道MOS(PMOS)電晶體，除非其特別說明實施例僅適用於其中一種電晶體。雖然第1至9圖中顯示製造了一個MOS電晶體，但是應該了解到能夠使用所描述之方法製造任何數目之此種電晶體。製造MOS組件之各種步驟已為眾所熟知，因此，為了簡便起見，本文中對於許多習知的步驟僅簡單提及，或者將其整個省略而不提供已熟知製程之細節。1 through 9 are schematic views showing a cross-sectional view of a portion of a semiconductor MOS transistor device 10 and a method for fabricating such a semiconductor device in accordance with an exemplary embodiment of the present invention. This embodiment described herein is applicable to N-channel MOS (NMOS) and P-channel MOS (PMOS) transistors unless it is specifically illustrated that the embodiment is applicable to only one of the transistors. Although it is shown in Figures 1 through 9 that a MOS transistor is fabricated, it should be understood that any number of such transistors can be fabricated using the methods described. The various steps of fabricating MOS components are well known and, therefore, for the sake of brevity, many well-known steps are simply mentioned herein or omitted entirely without providing details of well-known processes.

參照第1圖，本方法一開始先提供後續將在其上或其內形成半導體裝置10之半導體基板14。半導體基板14能夠是矽、鍺、譬如砷化鎵之III-V族之材料、或其他的半導體材料。下文中為了方便，但非有限制之意，將半導體基板14稱之為矽基板。本文中所用的術語“矽基板”包含典型使用於半導體工業之相當純的矽以及與其他的元素(譬如鍺、碳等)混合之矽。矽基板可以是塊體矽晶圓(bulk silicon wafer)，或者如所例示，可以是絕緣層12上之薄矽層16(通常已知為絕緣體上覆矽)，該絕緣層12依次由載體晶圓11支撐。矽基板14之至少表面部分被摻雜雜質，例如，藉由形成N型井區域和P型井區域而摻雜雜質，以分別製造P通道(PMOS)電晶體和N通道(NMOS)電晶體。Referring to Fig. 1, the method initially provides a semiconductor substrate 14 on which semiconductor device 10 will be subsequently formed or formed. The semiconductor substrate 14 can be a material of the III-V group of germanium, germanium, germanium, such as gallium arsenide, or other semiconductor material. Hereinafter, for convenience, but without limitation, the semiconductor substrate 14 will be referred to as a germanium substrate. The term "tantalum substrate" as used herein encompasses the relatively pure ruthenium typically used in the semiconductor industry and is mixed with other elements such as ruthenium, carbon, and the like. The germanium substrate may be a bulk silicon wafer or, as exemplified, a thin germanium layer 16 (generally known as an insulator overlying germanium) on the insulating layer 12, the insulating layer 12 being sequentially supported by a carrier crystal Round 11 support. At least a surface portion of the germanium substrate 14 is doped with impurities, for example, by forming an N-type well region and a P-type well region to dope impurities to fabricate a P-channel (PMOS) transistor and an N-channel (NMOS) transistor, respectively.

將閘極絕緣層22形成為覆蓋矽基板14。典型的情況是，閘極絕緣層22能夠是熱生長於薄矽層16之表面21上之二氧化矽(SiO₂ )之層。或可取而代之，以及針對其他類型之半導體基板，閘極絕緣層22可以是氧化矽(SiO_x )(此處x為大於0之數)、氮化矽、或氮氧化矽之沉積層。氮化矽和氮氧化矽之沉積薄膜可以是化學計量的組成或非化學計量的組成，但是於其任一情況，為了方便起見此種薄膜下文中將分別稱之為Si₃ N₄ 和SiON。能夠藉由例如化學氣相沉積(CVD)、低壓化學氣相沉積(LPCVD)、或者電漿增強化學氣相沉積(PECVD)製程來沉積閘極絕緣層。閘極絕緣層22較佳由經覆蓋性地沉積(blanket-deposited)之SiON層形成，並且具有從大約0.8奈米(nm)至大約1.2nm之範圍的厚度，而最佳為大約0.8nm厚。The gate insulating layer 22 is formed to cover the germanium substrate 14. Typically, the gate insulating layer 22 can be a layer of cerium oxide (SiO ₂ ) that is thermally grown on the surface 21 of the thin layer 16. Instead or as well as for other types of semiconductor substrate, a gate insulating layer 22 may be a silicon oxide (of SiO _x) (where x is a number of from greater than 0), silicon nitride, silicon oxynitride, or the deposited layer. The deposited film of tantalum nitride and yttrium oxynitride may be a stoichiometric composition or a non-stoichiometric composition, but in any case, for convenience, the film will hereinafter be referred to as Si ₃ N ₄ and SiON, respectively. . The gate insulating layer can be deposited by, for example, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD) processes. The gate insulating layer 22 is preferably formed of a blanket-deposited SiON layer and has a thickness ranging from about 0.8 nanometers (nm) to about 1.2 nm, and most preferably about 0.8 nm thick. .

仍參照第1圖，在形成閘極絕緣層22後，將高k閘極絕緣層24覆蓋性地沉積而覆蓋在閘極絕緣層22上。較佳的情況是，高k閘極絕緣層24由經沉積之高介電常數(高k)絕緣材料(譬如鉿之氧化物，包含氧化矽鉿(HfSi_x O_y )、氧化鉿(HfO₂ )、和氮氧化鉿(HfO_x N_y )、或氮氧化矽鉿(HfSi_x O_y N_z )(此處x、y、z為大於0)、氧化鋅(ZnO₂ )等)形成，而最佳由HfO₂ 形成。可以藉由例如CVD、LPCVD、PECVD、物理氣相沉積(PVD)、或原子層沉積(ALD)沉積高k閘極絕緣層24。選擇用於高k閘極絕緣層24之材料具有大於約7.0之介電常數，而較佳為至少大約12。高k閘極絕緣層24具有從大約1.4nm至大約2.4nm之厚度，而較佳為大約1.7nm厚。Still referring to FIG. 1, after the gate insulating layer 22 is formed, the high-k gate insulating layer 24 is deposited overlying to cover the gate insulating layer 22. Preferably, the high-k gate insulating layer 24 is formed of a deposited high dielectric constant (high-k) insulating material (such as lanthanum oxide, including hafnium oxide (HfSi _x O _y ), hafnium oxide (HfO ₂ ). ), and yttrium oxynitride (HfO _x N _y ), or yttrium oxynitride (HfSi _x O _y N _z ) (where x, y, z are greater than 0), zinc oxide (ZnO ₂ ), etc., Optimally formed by HfO ₂ . The high-k gate insulating layer 24 can be deposited by, for example, CVD, LPCVD, PECVD, physical vapor deposition (PVD), or atomic layer deposition (ALD). The material selected for the high-k gate insulating layer 24 has a dielectric constant greater than about 7.0, and preferably at least about 12. The high-k gate insulating layer 24 has a thickness of from about 1.4 nm to about 2.4 nm, and is preferably about 1.7 nm thick.

然後將含金屬閘極電極層48沉積而覆蓋在高k閘極絕緣層24上。含金屬閘極電極層48可以由鑭(La)或鑭合金、鋁(Al)或鋁合金、鎂(Mg)或鎂合金、譬如氮化鈦(TiN)或氮化鋁鈦(TiAlN)之鈦(Ti)基材料、譬如氮化鉭(TaN)、氮化鋁鉭(TaAlN)、或碳化鉭(Ta₂ C)之鉭(Ta)基材料、氮化鎢(WN)等形成，而較佳為TiN。可以使用PVD或CVD製程實施含金屬閘極電極層48之沉積。含金屬閘極電極層48較佳具有從大約2.5nm至大約7nm之厚度，而最佳為大約3.5nm厚。A metal-containing gate electrode layer 48 is then deposited overlying the high-k gate insulating layer 24. The metal-containing gate electrode layer 48 may be made of lanthanum (La) or hafnium alloy, aluminum (Al) or aluminum alloy, magnesium (Mg) or magnesium alloy, such as titanium nitride (TiN) or titanium aluminum nitride (TiAlN). (Ti)-based material, such as tantalum nitride (TaN), tantalum nitride (TaAlN), tantalum (Ta ₂ C) tantalum (Ta) based material, tungsten nitride (WN), etc., preferably Is TiN. The deposition of the metal-containing gate electrode layer 48 can be performed using a PVD or CVD process. The metal-containing gate electrode layer 48 preferably has a thickness of from about 2.5 nm to about 7 nm, and most preferably about 3.5 nm.

該方法繼續覆蓋性地沉積經摻雜之矽蓋層52而覆蓋含金屬閘極電極層48。因為不希望讓原生氧化物(native oxide)形成於含金屬閘極電極層48之外表面50，因此基板較佳保持在實質的無氧環境中(譬如，像是在真空下，若於含金屬閘極電極層48之沉積期間使用)，直到經摻雜之矽蓋層52之沉積後。於沉積製程過程中，用P型或N型元素於原位摻雜經摻雜之矽蓋層52。可以使用之P型摻雜劑包含硼(B)，而N型摻雜劑包含磷(P)、砷(As)、或銻(Sb)。於一個實施例中，經摻雜之矽蓋層52具有從大約5奈米(nm)至大約10nm範圍之厚度，而較佳為大約8nm厚。於另一個實施例中，層52之摻雜濃度為從每立方公分大約1.0×10¹⁹ 至大約1.0×10²⁰ 原子(at/cm³ )。The method continues to cover the doped cap layer 52 overlying the metal gate electrode layer 48. Since it is not desirable to form a native oxide on the outer surface 50 of the metal-containing gate electrode layer 48, the substrate is preferably maintained in a substantially oxygen-free environment (e.g., under vacuum, if contained in a metal Used during deposition of the gate electrode layer 48) until deposition of the doped cap layer 52. The doped cap layer 52 is doped in situ with a P-type or N-type element during the deposition process. The P-type dopant that can be used contains boron (B), and the N-type dopant contains phosphorus (P), arsenic (As), or antimony (Sb). In one embodiment, the doped cap layer 52 has a thickness ranging from about 5 nanometers (nm) to about 10 nm, and preferably about 8 nm thick. In another embodiment, layer 52 has a doping concentration of from about 1.0 x 10 ¹⁹ to about 1.0 x 10 ²⁰ atoms (at/cm ³ ) per cubic centimeter.

仍參照第1圖，形成含矽閘極電極層60以覆蓋經摻雜之矽蓋層52。用於含矽閘極電極層60之材料可以包括非晶矽或多晶矽，而較佳包括多晶矽。含矽閘極電極層60較佳為經沉積為未摻雜之多晶矽層，並且藉由離子植入後續地摻雜雜質。可以使用之雜質摻雜劑包含B、As、P、及Sb。可以藉由例如由矽烷(SiH₄ )之氫還原而進行之LPCVD沉積含矽閘極電極層60。Still referring to FIG. 1, a germanium-containing gate electrode layer 60 is formed to cover the doped cap layer 52. The material for the germanium-containing gate electrode layer 60 may include amorphous germanium or polycrystalline germanium, and preferably includes polycrystalline germanium. The germanium-containing gate electrode layer 60 is preferably deposited as an undoped polysilicon layer and subsequently doped with impurities by ion implantation. Impurity dopants that can be used include B, As, P, and Sb. The germanium-containing gate electrode layer 60 can be deposited by LPCVD, for example, by hydrogen reduction of decane (SiH ₄ ).

在含矽閘極電極層60之沉積後，可以依於所使用之整體製程而形成額外的層。這些層包含硬遮罩層64，其被覆蓋性地沉積成覆蓋含矽閘極電極層60。硬遮罩層64具有適合用作為硬遮罩之組成和厚度，以蝕刻覆蓋基板14之各層。可以用作為硬遮罩層64之範例材料包含TiN和較佳地包含Si₃ N₄ 或SiOx。After deposition of the germanium-containing gate electrode layer 60, additional layers may be formed depending on the overall process used. These layers comprise a hard mask layer 64 that is overlaid to cover the germanium-containing gate electrode layer 60. The hard mask layer 64 has a composition and thickness suitable for use as a hard mask to etch the layers covering the substrate 14. An exemplary material that can be used as the hard mask layer 64 comprises TiN and preferably Si ₃ N ₄ or SiOx.

然後使用合適的光學微影術和各向異性的蝕刻製程(譬如反應性離子蝕刻(RIE)製程序列)圖案化硬遮罩層64，以形成硬遮罩68，如第2圖所示。硬遮罩68接著使用為用於蝕刻層22、24、48、52和60的蝕刻遮罩，然後隨同任何餘留的光阻被去除。在此種蝕刻和去除之後，所得到的是包括閘極絕緣體74、高k閘極絕緣體76、含金屬閘極電極86、經摻雜之矽蓋88、和矽閘極電極92之閘極堆疊70，如第3圖所示。The hard mask layer 64 is then patterned using a suitable optical lithography process and an anisotropic etch process such as a reactive ion etch (RIE) program to form a hard mask 68, as shown in FIG. The hard mask 68 is then used as an etch mask for etching the layers 22, 24, 48, 52, and 60, and then removed with any remaining photoresist. After such etching and removal, what is obtained is a gate stack including a gate insulator 74, a high-k gate insulator 76, a metal-containing gate electrode 86, a doped cap 88, and a gate electrode 92. 70, as shown in Figure 3.

依照另一個實施例，於形成含矽閘極電極層60之前，沉積矽化物形成用金屬蓋層56以覆蓋經摻雜之矽蓋層52，如第4圖所示。矽化物形成用金屬蓋層56可以包括任何能夠與矽反應以形成金屬矽化物的金屬，譬如，像是鎳(Ni)、鉑(Pt)、鈷(Co)、或鈦(Ti)，或者它們的任何組合。於一個實施例中，矽化物形成用金屬蓋層56包括Ni和包含大約5至15原子百分比(atomic %)之Pt，而較佳包含大約5至10原子百分比之Pt。此種組成之NiPt薄膜能夠藉由使用具有所希望之組成之標靶而適用於PVD系統中。沉積矽化物形成用金屬蓋層56至從大約4nm至大約12nm之厚度，而較佳為大約5nm至10nm之間之厚度。於形成矽化物形成用金屬蓋層56後，可以接著沉積含矽閘極電極層60和硬遮罩層64，如以上所述。In accordance with another embodiment, a metallization layer 56 for telluride formation is deposited to cover the doped cap layer 52 prior to forming the germanium-containing gate electrode layer 60, as shown in FIG. The metallization layer 56 for telluride formation may include any metal capable of reacting with ruthenium to form a metal ruthenium, such as, for example, nickel (Ni), platinum (Pt), cobalt (Co), or titanium (Ti), or Any combination. In one embodiment, the metallization layer 56 for telluride formation comprises Ni and a Pt comprising from about 5 to 15 atomic percent, and preferably from about 5 to 10 atomic percent Pt. Such a composition of NiPt film can be applied to a PVD system by using a target having a desired composition. The metallization layer 56 for forming a telluride is deposited to a thickness of from about 4 nm to about 12 nm, and preferably between about 5 nm and 10 nm. After forming the metal cap layer 56 for telluride formation, the germanium-containing gate electrode layer 60 and the hard mask layer 64 may be deposited, as described above.

依照另一個實施例中(其在當裝置10被製造為PFET裝置時特別有效)，於形成閘極絕緣層22之前，將包含單晶材料之通道層18選擇性磊晶生長於矽表面21之一部分上而得到第5圖中所示之結構。對於PFET裝置而言，通道層18可以包括適合用作為PFET通道之任何的受壓縮應力之半導體材料，譬如像是鍺化矽(SiGe)、鍺(Ge)、或磷化銦(InP)，較佳為包括SiGe。若裝置10將為NFET裝置，則可取而代之選擇性地磊晶生長受拉張應力之單晶半導體材料。受壓縮應力之SiGe層能夠例如藉由在將Ge添加到矽烷(SiH₄ )或二氯甲矽烷(SiH₂ Cl₂ )下之這些反應劑的還原作用而被磊晶生長。如有需要，可以藉由將氫氯酸(HCl)引入到磊晶製程而控制生長選擇性以防止SiGe薄膜形成於非矽表面(未顯示)。添加入通道層18之Ge的濃度為從大約20%至大約35%之範圍，而較佳為大約23%Ge。然後本方法以如顯示於第1至3圖或第1至4圖者及參考該等圖所說明者而繼續。According to another embodiment (which is particularly effective when the device 10 is fabricated as a PFET device), the channel layer 18 comprising the single crystal material is selectively epitaxially grown on the tantalum surface 21 prior to forming the gate insulating layer 22. A part of the structure shown in Fig. 5 is obtained. For a PFET device, the channel layer 18 can comprise any compressively stressed semiconductor material suitable for use as a PFET channel, such as germanium telluride (SiGe), germanium (Ge), or indium phosphide (InP). Jiawei includes SiGe. If the device 10 would be an NFET device, then the single crystal semiconductor material subjected to tensile stress can be selectively epitaxially grown. The compressively stressed SiGe layer can be epitaxially grown, for example, by reduction of these reactants under the addition of Ge to decane (SiH ₄ ) or dichloromethane (SiH ₂ Cl ₂ ). If desired, the growth selectivity can be controlled by introducing hydrochloric acid (HCl) into the epitaxial process to prevent the SiGe film from forming on the non-ruthenium surface (not shown). The concentration of Ge added to the channel layer 18 ranges from about 20% to about 35%, and preferably about 23% Ge. The method then continues as illustrated in Figures 1 through 3 or Figures 1 through 4 and as described with reference to the Figures.

又依照另一個實施例，在第1圖中所例示之形成閘極絕緣層22和高k閘極絕緣體24之後(不論具有或者不具有第5圖中所例示之通道層18)，如前面之說明，沉積額外之含金屬層以覆蓋高k閘極絕緣層24，如第6圖例示。能夠使用任何適當的金屬沉積製程(包含例如電漿氣相沉積(PVD)或者ALD)沉積這些含金屬層，而這些含金屬層可以由La或鑭合金、Al或鋁合金、Mg或鎂合金、譬如TiN成TiAlN之鈦基材料、譬如TaN、TaAlN、或Ta₂ C之鉭基材料、或WN等，或它們的組合來形成。此等含金屬層於PFET裝置會特別有用，其可調整性能參數，譬如設定用於裝置10之V_t 於傳導帶邊緣(conduction band edge)或接近傳導帶邊緣。舉例而言，參照第6圖，於一個範例實施例中，較佳包括TiN之含金屬層32被沉積成覆蓋在高k閘極絕緣層24上。可以使用PVD或ALD沉積含金屬層32，而該含金屬屬32具有從大約1.5nm至大約2.5nm的厚度，而較佳為大約2.0nm厚。然後本方法可以如上述顯示和說明者繼續。According to yet another embodiment, after forming the gate insulating layer 22 and the high-k gate insulator 24 as illustrated in FIG. 1 (with or without the channel layer 18 illustrated in FIG. 5), as in the foregoing It is noted that an additional metal containing layer is deposited to cover the high k gate insulating layer 24, as illustrated in FIG. These metal-containing layers can be deposited using any suitable metal deposition process, including, for example, plasma vapor deposition (PVD) or ALD, and these metal-containing layers can be made of La or tantalum alloys, Al or aluminum alloys, Mg or magnesium alloys, For example, TiN is formed into a titanium-based material of TiAlN, a tantalum material such as TaN, TaAlN, or Ta ₂ C, or WN or the like, or a combination thereof. These metal-containing layer may be particularly useful in the PFET device, which can adjust the performance parameters, such as setting means 10 for the V _{t of} the conduction band edge (conduction band edge) at or near the conduction band edge. For example, referring to FIG. 6, in an exemplary embodiment, a metal containing layer 32, preferably including TiN, is deposited overlying the high-k gate insulating layer 24. The metal containing layer 32 may be deposited using PVD or ALD, and the metal containing genus 32 has a thickness of from about 1.5 nm to about 2.5 nm, and preferably about 2.0 nm. The method can then continue as shown and described above.

依照另一個實施例，額外的含金屬層36和/或40可以依序地沉積以覆蓋含金屬層32，如第6圖中所示。含金屬層36和40亦可以包括上文所揭示之用於形成含金屬層32的金屬之任何其中一個或其組合，並且較佳地分別包括Al和TiN。於一個實施例中，含金屬層36具有從大約0.1nm至大約0.8nm範圍的厚度，而較佳為大約0.8nm厚。含金屬層40具有從大約1.0nm至大約2.5nm範圍的厚度，而較佳為大約1.5nm厚。含金屬層32、36和/或40可以單獨或結合使用，以設定用於PFET裝置之V_t 至所希望之位準。In accordance with another embodiment, additional metal containing layers 36 and/or 40 may be sequentially deposited to cover the metal containing layer 32, as shown in FIG. Metal-containing layers 36 and 40 may also include any one or combination of the metals disclosed above for forming metal-containing layer 32, and preferably include Al and TiN, respectively. In one embodiment, the metal containing layer 36 has a thickness ranging from about 0.1 nm to about 0.8 nm, and preferably about 0.8 nm thick. Metal-containing layer 40 has a thickness ranging from about 1.0 nm to about 2.5 nm, and preferably about 1.5 nm thick. Metal-containing layers 32, 36 and / or 40 may be used alone or in combination, it is used to set the level of _t V PFET device to the desired.

在形成含金屬層32、36和/或40後，本方法繼續形成含金屬閘極電極層48、矽蓋層52、矽化物形成用金屬蓋層56(如果需要)、含矽閘極電極層60、和硬遮罩層64，如前面的圖示和說明。能夠將硬遮罩層64圖案化為硬遮罩，並於之後使用來蝕刻這些各層連同通道層18、閘極絕緣層22、和高k閘極絕緣層24。於該等蝕刻製程和去除硬遮罩層64後，便形成閘極堆疊95，該閘極堆疊95包含PFET通道72、閘極絕緣體74和高k閘極絕緣體76、視需要選用之含金屬層78、80、和82、含金屬閘極電極86、經摻雜之矽蓋88、視需要選用之矽化物形成用金屬蓋90、和矽閘極電極92，如第7圖所示。After forming the metal-containing layers 32, 36 and/or 40, the method continues to form the metal-containing gate electrode layer 48, the cap layer 52, the metallization layer 56 for telluride formation (if necessary), and the germanium-containing gate electrode layer. 60, and hard mask layer 64, as shown and described above. The hard mask layer 64 can be patterned into a hard mask and used thereafter to etch the layers together with the channel layer 18, the gate insulating layer 22, and the high-k gate insulating layer 24. After the etching process and removal of the hard mask layer 64, a gate stack 95 is formed. The gate stack 95 includes a PFET channel 72, a gate insulator 74, and a high-k gate insulator 76, optionally including a metal-containing layer. 78, 80, and 82, a metal-containing gate electrode 86, a doped crucible cover 88, a metallization forming metal cover 90, and a germanium gate electrode 92, as desired, as shown in FIG.

依照又另一個實施例，當將裝置10製造為NFET裝置時，執行上述說明和圖示之方法步驟，惟於形成高k閘極絕緣層24後接著沉積金屬氧化物閘極蓋層44，如第8圖所示。金屬氧化物閘極蓋層44可以使用來將用於NFET裝置之V_t 設定於傳導帶邊緣或接近傳導帶邊緣，並且可以包括包含下述者之金屬氧化物和/或金屬氮氧化物之任何其中一種或其組合：La、氧化鑭(LaO_x )和氮氧化鑭(LaO_x N_y )、氧化鉿(HfO_x )和氮氧化鉿(HfO_x N_y )、氧化鋯(ZrO_x )和氮氧化鋯(ZrO_x N_y )、氧化鎂(MgO_x )和氮氧化鎂(MgO_x N_y )、氧化鋁(AlO_x )和氮氧化鋁(AlO_x N_y )、氧化鈦(TiO_x )和氮氧化鈦(TiO_x N_y )、氧化鉭(TaO_x )和氮氧化鉭(TaO_x N_y )、和氧化釔(YO_x )和氮氧化釔(YO_x N_y )，其中x和y為大於0之數，而較佳為La。可以使用任何適合的沉積技術，譬如像是PVD製程(例如，蒸發或濺鍍)、CVD、PECVD、LPCVD、ALD，來沉積金屬氧化物閘極蓋層44，而較佳為藉由ALD形成。層44亦可以使用適合用於此種沉積之化學化合物形成為自身組合或經自身組合之單層(self-assembled monolayer,SAM)。此種化合物一般包括經適當地功能化為用於黏著性吸附或者接合至基板表面之分子位置之分子結構，但是缺少形成超過單層厚度之薄膜之傾向。可以使用例如自旋塗覆或浸泡製程而從適當的溶劑進行澆鑄而沉積SAM化合物。金屬氧化物閘極蓋層44之厚度為從大約0.1nm至大約0.8nm範圍，而較佳為大約0.4nm厚。In accordance with yet another embodiment, when the device 10 is fabricated as an NFET device, the method steps described above and illustrated are performed, except that the high-k gate insulating layer 24 is formed followed by deposition of a metal oxide gate cap layer 44, such as Figure 8 shows. Gate metal oxide layer 44 can be used for V NFET device of _t is set to the conduction band edge at or near the conduction band edge, and may include those containing any of the following metal oxides and / or metal oxides of nitrogen One or a combination thereof: La, lanthanum oxide (LaO _x ) and lanthanum oxynitride (LaO _x N _y ), lanthanum oxide (HfO _x ) and lanthanum oxynitride (HfO _x N _y ), zirconia (ZrO _x ) and nitrogen Zirconia (ZrO _x N _y ), magnesium oxide (MgO _x ) and magnesium oxynitride (MgO _x N _y ), alumina (AlO _x ) and aluminum oxynitride (AlO _x N _y ), titanium oxide (TiO _x ) and Titanium oxide (TiO _x N _y ), lanthanum oxide (TaO _x ), and lanthanum oxynitride (TaO _x N _y ), and yttrium oxide (YO _x ) and yttrium oxynitride (YO _x N _y ), where x and y are More than 0, and preferably La. The metal oxide gate cap layer 44 can be deposited using any suitable deposition technique, such as a PVD process (e.g., evaporation or sputtering), CVD, PECVD, LPCVD, ALD, and is preferably formed by ALD. Layer 44 can also be formed into a self-assembled monolayer (SAM) by itself or by a combination of chemical compounds suitable for such deposition. Such compounds generally include molecular structures that are suitably functionalized for adhesive adsorption or bonding to molecular sites on the surface of the substrate, but lack the tendency to form films that exceed the thickness of a single layer. The SAM compound can be deposited by casting from a suitable solvent using, for example, a spin coating or soaking process. The metal oxide gate cap layer 44 has a thickness ranging from about 0.1 nm to about 0.8 nm, and preferably about 0.4 nm thick.

在形成金屬氧化物閘極蓋層44後，本方法依照上述說明和圖示之任何實施例繼續進行。可以圖案化硬遮罩層64並且予以使用為蝕刻遮罩以去除包含閘極絕緣層22、高k閘極絕緣層24、和金屬氧化物閘極蓋層44之該等層之一部分。在這些蝕刻和硬遮罩層64之去除後，形成閘極堆疊98，該閘極堆疊98包含閘極絕緣體74和高k閘極絕緣體76、金屬氧化物閘極蓋層84、含金屬閘極電極86、經摻雜之矽蓋88、視需要選用之矽化物形成用金屬蓋90、和矽閘極電極92，如第9圖所示。After forming the metal oxide gate cap layer 44, the method continues in accordance with any of the above description and illustrated embodiments. The hard mask layer 64 can be patterned and used as an etch mask to remove portions of the layers including the gate insulating layer 22, the high-k gate insulating layer 24, and the metal oxide gate cap layer 44. After the etch and hard mask layer 64 is removed, a gate stack 98 is formed. The gate stack 98 includes a gate insulator 74 and a high-k gate insulator 76, a metal oxide gate cap layer 84, and a metal-containing gate. The electrode 86, the doped lid 88, the optional metallization forming metal lid 90, and the tantalum gate electrode 92 are shown in Fig. 9.

在形成閘極堆疊70(第3圖)、95(第7圖)、或98任一者後，裝置10可以經受額外的製程，該額外製程可涉及暴露至升高的溫度，譬如像是那些通常用來活化源極和汲極摻雜劑或反應性地將矽閘極電極92以及後續所沉積的金屬層轉變成為金屬矽化物閘極電極接觸點者。在閘極堆疊中使用有經摻雜之矽蓋88但沒有矽化物形成用金屬蓋90的情形中，則二個可能的結果之其中之一可能會發生。第一個可能的結果為，若矽閘極電極92其自身完全轉變成為矽化物，則經摻雜之矽蓋88也許會轉變成經摻雜之金屬矽化物。第二個可能的結果為，若矽閘極電極92未完全轉變成為矽化物，譬如像是若矽閘極電極92對於此種完全的轉變而言太厚，則經摻雜之矽蓋88可以保持為在含金屬閘極電極86與矽閘極電極92之間之未反應、導電的、過渡的摻雜矽層。於此情形中可能發生之第三個結果是矽化物形成用金屬蓋90被包含於閘極堆疊之情況。於此情況，涉及充分暴露於時間和溫度(譬如，像是大約400℃或者較高者達大於約5秒)之後續的熱處理將引致矽化物形成用金屬蓋90與鄰接之經摻雜之矽蓋88反應以形成包括該矽化物形成用金屬之經摻雜之矽化物的層。矽化物形成用金屬之一部分亦可以與來自鄰接之矽閘極電極92之多晶矽反應，以形成金屬矽化物。若來自蓋88之摻雜矽存在有以化學計量計超過矽化物形成用金屬之量，則摻雜矽之一部分可以保持未被反應，或者於轉變矽閘極電極92成為金屬矽化物閘極接觸點之製程過程中可以被轉變成經摻雜之金屬矽化物區。插置於含金屬閘極電極86與矽閘極電極92之間之包括摻雜矽或者較佳地包括經摻雜之金屬矽化物之層業經實驗發現可降低閘極堆疊之AC阻抗，並且由此提升裝置之整體AC性能。After forming either gate stack 70 (Fig. 3), 95 (Fig. 7), or 98, device 10 may be subjected to an additional process that may involve exposure to elevated temperatures, such as those Typically used to activate the source and drain dopants or reactively convert the germanium gate electrode 92 and the subsequently deposited metal layer into a metal telluride gate electrode contact. In the case where a doped lid 88 is used in the gate stack but without the metallization 90 for the telluride formation, one of two possible outcomes may occur. The first possible result is that if the gate electrode 92 itself completely transforms into a germanide, the doped cap 88 may be converted to a doped metal telluride. A second possible result is that if the gate electrode 92 is not completely converted to a germanide, such as if the gate electrode 92 is too thick for such a complete transition, the doped cap 88 can The unreacted, electrically conductive, transitional doped germanium layer is maintained between the metal-containing gate electrode 86 and the germanium gate electrode 92. A third result that may occur in this case is the case where the telluride forming metal cover 90 is included in the gate stack. In this case, a subsequent heat treatment involving sufficient exposure to time and temperature (e.g., about 400 ° C or higher for more than about 5 seconds) will result in a telluride forming metal cap 90 and adjacent doped germanium. The lid 88 reacts to form a layer comprising the doped telluride of the telluride forming metal. A portion of the metal for telluride formation may also react with the polysilicon from the adjacent gate electrode 92 to form a metal halide. If the doping enthalpy from the cap 88 is present in stoichiometric excess of the amount of metal for telluride formation, one portion of the doped germanium may remain unreacted, or the transition gate electrode 92 may become a metal telluride gate contact. The process of the dot can be converted into a doped metal halide region. Inserting a layer comprising a doped germanium or preferably a doped metal germanide between the metal-containing gate electrode 86 and the germanium gate electrode 92 has been experimentally found to reduce the AC impedance of the gate stack and is The overall AC performance of this lifting device.

第10至22圖依照本發明範例實施例示意地顯示具有包含經摻雜之矽蓋層之P通道MOS(PMOS)和N通道MOS(NMOS)電晶體之半導體裝置100之一部分之剖面圖和用來形成此種半導體裝置之方法。雖然顯示了一個NMOS和一個PMOS之部分之製造，但是應該了解到描述於第10至22圖之本方法能夠用來製造任何數目之此種電晶體。如前面之方法，於製造MOS組件之各種步驟已為眾所熟知，因此為了簡便起見，許多習知的步驟將僅簡短提及或者將被省略。10 through 22 are schematic cross-sectional views showing a portion of a semiconductor device 100 having a P-channel MOS (PMOS) and an N-channel MOS (NMOS) transistor including a doped cap layer, and used in accordance with an exemplary embodiment of the present invention. A method of forming such a semiconductor device. Although the fabrication of a portion of an NMOS and a PMOS is shown, it should be understood that the method described in Figures 10 through 22 can be used to fabricate any number of such transistors. As in the previous methods, various steps in the manufacture of MOS components are well known, and thus many conventional steps will be briefly mentioned or will be omitted for the sake of brevity.

參照第10圖，依照範例實施例，本方法一開始先提供半導體基板110。半導體基板110相似於上述之半導體基板14，但是另外包括隔離區域118，該隔離區域118延伸穿過薄矽層16至絕緣層12。隔離區域118較佳由已熟知的淺溝槽隔離(STI)技術形成，其中溝槽被蝕刻入薄矽層16，且該等溝槽被譬如沉積二氧化矽之介電材料所填滿，並且藉由化學機械平坦化(CMP)去除過量的二氧化矽。隔離區域118用來電性隔離NFET區域180和PFET區域200，而用於NFET和PFET電晶體之閘極堆疊係接著分別形成在該NFET區域180和PFET區域200上。例如，藉由在PFET區域200中形成N形井區域和在NFET區域180中形成P形井區域，而將雜質摻雜於矽基板110之至少表面區域108，以分別製造PFET和NFET電晶體。Referring to Fig. 10, in accordance with an exemplary embodiment, the method initially provides a semiconductor substrate 110. The semiconductor substrate 110 is similar to the semiconductor substrate 14 described above, but additionally includes an isolation region 118 that extends through the thin layer 16 to the insulating layer 12. The isolation regions 118 are preferably formed by well-known shallow trench isolation (STI) techniques in which trenches are etched into the thin germanium layer 16, and the trenches are filled with a dielectric material such as germanium dioxide deposited, and Excess cerium oxide is removed by chemical mechanical planarization (CMP). The isolation region 118 is used to electrically isolate the NFET region 180 and the PFET region 200, and the gate stacks for the NFET and PFET transistors are then formed on the NFET region 180 and the PFET region 200, respectively. For example, impurities are doped to at least surface region 108 of germanium substrate 110 by forming N-well regions in PFET region 200 and forming P-well regions in NFET region 180 to fabricate PFET and NFET transistors, respectively.

其次，形成硬遮罩層122以覆蓋NFET和PFET區域180和200，如第11圖中所示。硬遮罩層122可以包括熱生長SiO₂ ，或者取而代之，可以包括經沉積之SiO_x 、Si₃ N₄ 、或SiON、或者於後續磊晶生長製程過程中適合用來提供遮罩保護之另一種材料。當使用沉積製程時，可以例如藉由CVD、LPCVD或PECVD覆蓋性地沉積硬遮罩層122。硬遮罩層122較宜為熱生長SiO₂ 形成在薄矽層16之表面，如所示，並且具有從大約7nm至大約15nm範圍之厚度，而較佳為大約8nm厚。Second, a hard mask layer 122 is formed to cover the NFET and PFET regions 180 and 200, as shown in FIG. The hard mask layer 122 may comprise thermally grown SiO ₂ or, alternatively, may comprise deposited SiO _x , Si ₃ N ₄ , or SiON, or another suitable for providing mask protection during subsequent epitaxial growth processes material. When a deposition process is used, the hard mask layer 122 can be overlaid, for example, by CVD, LPCVD, or PECVD. The hard mask layer 122 is preferably formed of thermally grown SiO ₂ on the surface of the thin layer 16, as shown, and has a thickness ranging from about 7 nm to about 15 nm, and preferably about 8 nm thick.

然後使用適合的光學微影術和RIE製程序列從PFET區域200去除硬遮罩層122，如第12圖中所示。所使用之RIE製程化學作用係依於所選擇用於硬遮罩層122之材料而定，並且可以為根據例如CHF₃ 、CF₄ 或SF₆ 者，以用於氧化矽/二氧化矽、或者氮化矽。然後將包括單晶半導體材料之PFET通道層134磊晶生長於PFET區域200中之薄矽層16之矽表面130，如第13圖中所示。選擇性地實施磊晶製程至矽表面而使得不會發生於非矽表面(譬如硬遮罩層122)之生長。PFET通道層134可以包括前面說明過之用於通道層18之任何受壓縮應力之半導體材料和組成範圍，並且可以使用相同的磊晶製程來形成。較佳的情況是，PFET通道層134包括具有大約23%Ge之組成之SiGe。然後使用RIE製程相對於PFET通道層134選擇性去除硬遮罩層122。The hard mask layer 122 is then removed from the PFET region 200 using a suitable optical lithography and RIE program sequence, as shown in FIG. The RIE process chemistry used depends on the material selected for the hard mask layer 122, and may be for yttria/yttria according to, for example, CHF ₃ , CF ₄ or SF ₆ , or Tantalum nitride. A PFET channel layer 134 comprising a single crystal semiconductor material is then epitaxially grown on the tantalum surface 130 of the thin germanium layer 16 in the PFET region 200, as shown in FIG. The epitaxial process is selectively performed to the crucible surface such that growth does not occur on non-defective surfaces such as hard mask layer 122. The PFET channel layer 134 can include any of the compressive stress semiconductor materials and composition ranges described above for the channel layer 18 and can be formed using the same epitaxial process. Preferably, the PFET channel layer 134 comprises SiGe having a composition of approximately 23% Ge. The hard mask layer 122 is then selectively removed relative to the PFET channel layer 134 using an RIE process.

其次，如第14圖中所示，將閘極絕緣層138覆蓋性地沉積以覆蓋半導體裝置100，包含於NFET區域180中之薄矽層16和於PFET區域200中之PFET通道層134。閘極絕緣層138包括沉積絕緣材料，譬如SiO_x 、Si₃ N₄ 、或SiON，而較佳的是SiON。可以例如藉由CVD、LPCVD、或PECVD製程施行沉積。閘極絕緣層138具有大約0.8nm至大約1.2nm之厚度，而較佳為大約0.8nm厚。Next, as shown in FIG. 14, a gate insulating layer 138 is overlaid to cover the semiconductor device 100, the thin germanium layer 16 included in the NFET region 180, and the PFET channel layer 134 in the PFET region 200. The gate insulating layer 138 includes a deposition insulating material such as SiO _x , Si ₃ N ₄ , or SiON, and preferably SiON. The deposition can be performed, for example, by a CVD, LPCVD, or PECVD process. The gate insulating layer 138 has a thickness of about 0.8 nm to about 1.2 nm, and is preferably about 0.8 nm thick.

仍參照第14圖，在形成閘極絕緣層138後，將高k閘極絕緣層140覆蓋性地沉積以覆蓋NFET和PFET區域180和200。較佳為，由經沉積之高k絕緣材料(譬如鉿之氧化物，包含HfSi_x O_y 、HfO₂ 、HfO_x N_y 、和HfSi_x O_y Nz(此處x、y、z分別大於0)、ZnO₂ 等，而較佳為HfO₂ )形成高k閘極絕緣層140。可以例如藉由CVD、LPCVD、PECVD、PVD、或ALD沉積高k閘極絕緣層140。選擇用於高k閘極絕緣層140之材料具有大於大約7.0之介電常數，而較佳至少大約12.0。高k閘極絕緣層140具有從大約1nm至大約10nm之厚度，而較佳為大約1.7nm厚。Still referring to FIG. 14, after forming the gate insulating layer 138, a high-k gate insulating layer 140 is overlaid to cover the NFET and PFET regions 180 and 200. Preferably, the deposited high-k insulating material (such as an oxide of lanthanum, including HfSi _x O _y , HfO ₂ , HfO _x N _y , and HfSi _x O _y Nz (where x, y, and z are respectively greater than 0) ), ZnO ₂ or the like, and preferably HfO ₂ ) forms a high-k gate insulating layer 140. The high-k gate insulating layer 140 can be deposited, for example, by CVD, LPCVD, PECVD, PVD, or ALD. The material selected for the high-k gate insulating layer 140 has a dielectric constant greater than about 7.0, and preferably at least about 12.0. The high-k gate insulating layer 140 has a thickness of from about 1 nm to about 10 nm, and is preferably about 1.7 nm thick.

其次，於各種範例實施例中，額外的含金屬層經沉積而覆蓋高k閘極絕緣層140，並且用來建立於PFET區域200中待製造之PFET裝置之V_t 。此等層可以後續地從NFET區域180去除，如下文中將作進一步之說明。參照第14圖，於一個實施例中，含金屬層142被覆蓋性地沉積以覆蓋高k閘極絕緣層140於NFET和PFET區域180和200兩者。可以使用任何適當的金屬沉積製程(包含PVD或ALD)沉積含金屬層142，並且該含金屬層142具有從大約1.5nm至大約2.5nm範圍之厚度，而較佳為大約2.0nm厚。含金屬層142可以由La或鑭合金、Al或鋁合金、Mg或鎂合金、譬如TiN或TiAlN之鈦基材料、譬如TaN、TaAlN、或Ta₂ C之鉭基材料、或WN等，或者它們的組合形成，而較佳為由TiN形成。Secondly, the coverage of high-k gate insulating layer 140 in various examples of additional metal-containing layers were deposited embodiment, and is used to establish the V _t PFET device 200 to be manufactured in the PFET region. These layers can be subsequently removed from the NFET region 180 as will be further explained below. Referring to FIG. 14, in one embodiment, metal containing layer 142 is overlaid to cover high k gate insulating layer 140 in both NFET and PFET regions 180 and 200. The metal containing layer 142 can be deposited using any suitable metal deposition process (including PVD or ALD), and the metal containing layer 142 has a thickness ranging from about 1.5 nm to about 2.5 nm, and preferably about 2.0 nm thick. The metal-containing layer 142 may be made of La or a tantalum alloy, Al or an aluminum alloy, Mg or a magnesium alloy, a titanium-based material such as TiN or TiAlN, a tantalum material such as TaN, TaAlN, or Ta ₂ C, or WN, or the like. The combination is formed, and is preferably formed of TiN.

依照其他的實施例，含金屬閘極層146和/或150係後續地被覆蓋性地沉積以覆蓋含金屬閘極層142於NFET和PFET區域180和200兩者。含金屬閘極層146和150可以包括上文中參照含金屬閘極層142所說明過之任何的材料，並可由上文中參照含金屬閘極層142所說明過之任何製程所沉積。含金屬層146較佳為鋁，並且具有從大約0.1nm至大約0.8nm範圍之厚度，而較佳為大約0.8nm厚。含金屬閘極層150較佳為TiN，具有從大約1nm至大約2.5nm範圍之厚度，而較佳為大約1.5nm厚。In accordance with other embodiments, the metal-containing gate layer 146 and/or 150 is subsequently overlaid to cover the metal-containing gate layer 142 in both the NFET and PFET regions 180 and 200. Metal-containing gate layers 146 and 150 may comprise any of the materials described above with reference to metal-containing gate layer 142 and may be deposited by any of the processes described above with reference to metal-containing gate layer 142. The metal containing layer 146 is preferably aluminum and has a thickness ranging from about 0.1 nm to about 0.8 nm, and preferably about 0.8 nm thick. The metal-containing gate layer 150 is preferably TiN having a thickness ranging from about 1 nm to about 2.5 nm, and preferably about 1.5 nm thick.

然後使用適當的圖案化製程分別將所使用之任何含金屬層142、146和150從NFET區域180去除。此製程較佳包含形成硬遮罩154，如第15圖所示，該形成製程使用先前針對硬遮罩層說明過之適當的沉積、光學微影術、和乾蝕刻製程順序。接著，使用硬遮罩154作為蝕刻遮罩，將含金屬層142、146、和150從NFET區域180去除，如第16圖中所示。選擇性地實施蝕刻製程以便不會腐蝕於NFET區域180中之高k閘極絕緣層140。所使用之蝕刻化學作用將部分地依據在含金屬層142、146、和150中待蝕刻之材料組成而定，並且也許根據例如用於TiN之Cl₂ /HBr化學作用、用於TaN之Cl₂ /CF₄ 化學作用、或用於WN之SF₆ /CH₂ F₂ 化學作用。在此蝕刻後，可以使用適當的濕蝕刻或乾蝕刻製程去除硬遮罩層154，其中，該蝕刻製程不會從PFET區域200腐蝕掉含金屬層142、146、和/或150(如果有使用)，或從NFET區域180腐蝕掉高k閘極絕緣層140。Any metal containing layers 142, 146, and 150 used are then removed from the NFET region 180, respectively, using a suitable patterning process. The process preferably includes forming a hard mask 154, as shown in Fig. 15, which uses the appropriate deposition, optical lithography, and dry etch process sequences previously described for the hard mask layer. Next, using the hard mask 154 as an etch mask, the metal containing layers 142, 146, and 150 are removed from the NFET region 180, as shown in FIG. The etch process is selectively performed so as not to erode the high-k gate insulating layer 140 in the NFET region 180. The etch chemistry used will be based in part 142, 146, and 150 of the metal-containing material to be etched layers may be, for example, and may be based TiN chemistry of ₂ HBr Cl /, for the TaN Cl ₂ /CF ₄ chemistry, or SF ₆ /CH ₂ F ₂ chemistry for WN. After this etch, the hard mask layer 154 can be removed using a suitable wet or dry etch process that does not etch away the metal containing layers 142, 146, and/or 150 from the PFET region 200 (if used) The high-k gate insulating layer 140 is etched away from the NFET region 180.

在該去除硬遮罩層154後，本方法接著覆蓋性地沉積金屬氧化物閘極蓋層162以覆蓋NFET和PFET區域180和200，如第17圖中所示。如上文參照金屬氧化物閘極蓋層44所揭示，金屬氧化物閘極蓋層162可以使用來設定用於待形成於NFET區域180中之NFET裝置之V_t 。金屬氧化物閘極蓋層162可以包括下述金屬氧化物和/或金屬氮氧化物之任何其中一種或其組合，包含La、LaO_x 、和LaO_x N_y 、HfO_x 和HfO_x N_y 、ZrO_x 和ZrO_x N_y 、(MgO_x )和MgO_x N_y 、AlO_x 和AlO_x N_y 、TiO_x 和TiO_x N_y 、TaO_x 和TaO_x N_y 、YO_x 和YO_x N_y ，其中x和y為大於0之數，而較佳是La。可以使用任何適合的沉積技術沉積金屬氧化物閘極蓋層162，且該金屬氧化物閘極蓋層162之厚度範圍係如前面參照金屬氧化物閘極蓋層44之說明者。After the hard mask layer 154 is removed, the method then overlays a metal oxide gate cap layer 162 to cover the NFET and PFET regions 180 and 200, as shown in FIG. As described above with reference to metal gate oxide layer 44 disclosed, a metal oxide gate cap layer 162 may be used to set V _t NFET device to be formed in the region 180 of the NFET. The metal oxide gate cap layer 162 may include any one or a combination of the following metal oxides and/or metal oxynitrides, including La, LaO _x , and LaO _x N _y , HfO _{x ,} and HfO _x N _y , ZrO _x and ZrO _x N _y , (MgO _x ) and MgO _x N _y , AlO _x and AlO _x N _y , TiO _x and TiO _x N _y , TaO _x and TaO _x N _y , YO _x and YO _x N _y , Wherein x and y are numbers greater than 0, and preferably La. The metal oxide gate cap layer 162 can be deposited using any suitable deposition technique, and the thickness of the metal oxide gate cap layer 162 is as previously described with reference to the metal oxide gate cap layer 44.

接著，形成含金屬閘極層166以覆蓋金屬閘極蓋層162。含金屬閘極層166可以由La或鑭合金、Al或鋁合金、Mg或鎂合金、譬如TiN或TiAlN之鈦基材料、譬如TaN、TaAlN或Ta₂ C之鉭基材料、WN等形成，而較佳的是TiN。可以使用PVD或CVD製程實施含金屬閘極層166之沉積。含金屬閘極層166較佳具有從大約2.5nm至大約7nm之厚度，而較佳為大約3.5nm厚。Next, a metal-containing gate layer 166 is formed to cover the metal gate cap layer 162. The metal-containing gate layer 166 may be formed of a La or tantalum alloy, Al or an aluminum alloy, a Mg or a magnesium alloy, a titanium-based material such as TiN or TiAlN, a tantalum material such as TaN, TaAlN or Ta ₂ C, WN or the like, and Preferred is TiN. The deposition of the metal containing gate layer 166 can be performed using a PVD or CVD process. Metal-containing gate layer 166 preferably has a thickness of from about 2.5 nm to about 7 nm, and is preferably about 3.5 nm thick.

在沉積含金屬閘極層166後，將半導體裝置100維持於真空下(若使用於層166之沉積)或者於另一種型式之實質無氧環境中以避免原生氧化物形成於含金屬閘極層166之表面168上。接著，使用例如LPCVD製程而將包含摻雜矽之經摻雜之矽蓋層170覆蓋性地沉積以覆蓋NFET和PFET區域180和200中之含金屬閘極層166。經摻雜之矽蓋層170包括與於沉積製程過程中於原位加入於薄膜中之雜質摻雜劑混合之矽。此種摻雜劑元素可以包括譬如硼(B)之P型元素，或者包括譬如磷(P)、砷(As)、或銻(Sb)之N型元素。於一個實施例中，經摻雜之矽蓋層170具有從大約5nm至大約10nm範圍之厚度，而較佳為大約8nm厚。於另一個實施例中，經摻雜之矽蓋層170具有從大約1.0×10¹⁹ at/cm³ 至大約1.0×10²⁰ at/cm³ 的摻雜濃度。After depositing the metal-containing gate layer 166, the semiconductor device 100 is maintained under vacuum (if used for deposition of layer 166) or in another type of substantially oxygen-free environment to avoid formation of native oxides in the metal-containing gate layer. On surface 168 of 166. Next, a doped cap layer 170 comprising doped germanium is overlaid to cover the metal-containing gate layer 166 in the NFET and PFET regions 180 and 200 using, for example, an LPCVD process. The doped cap layer 170 includes a crucible that is mixed with an impurity dopant that is added to the film in situ during the deposition process. Such a dopant element may include a P-type element such as boron (B) or an N-type element such as phosphorus (P), arsenic (As), or antimony (Sb). In one embodiment, the doped cap layer 170 has a thickness ranging from about 5 nm to about 10 nm, and preferably about 8 nm thick. In another embodiment, the doped cap layer 170 has a doping concentration of from about 1.0 x 10 ¹⁹ at/cm ³ to about 1.0 x 10 ²⁰ at/cm ³ .

接著形成含矽閘極電極層178以覆蓋經摻雜之矽蓋層170，如第18圖中所示。含矽閘極電極層178可以包括非晶矽或較佳之多晶矽，並且可以使用前面說明用於含矽閘極電極層60之製程和摻雜劑元素來沉積和進行摻雜植入。A germanium-containing gate electrode layer 178 is then formed to cover the doped cap layer 170, as shown in FIG. The germanium-containing gate electrode layer 178 may comprise amorphous germanium or, preferably, polycrystalline germanium, and may be deposited and doped implanted using the processes and dopant elements previously described for the germanium-containing gate electrode layer 60.

在沉積含矽閘極電極層178後，可依於對裝置100所希望之應用和所使用之整體製程，而形成額外的層。這些層包含被覆蓋性地沉積之硬遮罩層182以覆蓋含矽閘極電極層178，使用適當的光學微影術和乾蝕刻順序而圖案化該硬遮罩層182，以形成硬遮罩186和190而分別覆蓋於NFET和PFET區域180和200，如第19圖中所示。硬遮罩186和190被各使用為蝕刻遮罩，以去除覆蓋區域180和200之層之部分，以分別形成閘極堆疊204和208，如第20圖中所示。當此種蝕刻和去除(包含去除硬遮罩186和190)完成時，閘極堆疊204包含NFET閘極絕緣體222、NFET高k閘極絕緣體226、NFET金屬氧化物閘極蓋230、NFET含金屬閘極電極234、NFET摻雜矽蓋238、和NFET矽閘極電極250。閘極堆疊208包含PFET通道254、PFET閘極絕緣體258、PFET高k閘極絕緣體262、視需要選擇使用之PFET含金屬層266、270、和274、PFET金屬氧化物閘極蓋278、PFET含金屬閘極電極282、PFET摻雜矽蓋286、和PFET矽閘極電極294。After depositing the germanium-containing gate electrode layer 178, additional layers may be formed depending on the desired application of the device 100 and the overall process used. The layers include a blanket deposited hard mask layer 182 to cover the germanium-containing gate electrode layer 178, which is patterned using appropriate optical lithography and dry etch sequences to form a hard mask. 186 and 190 cover the NFET and PFET regions 180 and 200, respectively, as shown in FIG. Hard masks 186 and 190 are each used as an etch mask to remove portions of the layers of cover regions 180 and 200 to form gate stacks 204 and 208, respectively, as shown in FIG. When such etching and removal (including removal of the hard masks 186 and 190) is completed, the gate stack 204 includes an NFET gate insulator 222, an NFET high-k gate insulator 226, an NFET metal oxide gate cap 230, and a NFET metal-containing Gate electrode 234, NFET doped cap 238, and NFET gate electrode 250. Gate stack 208 includes PFET channel 254, PFET gate insulator 258, PFET high-k gate insulator 262, PFET metal-containing layers 266, 270, and 274, optionally used, PFET metal oxide gate cap 278, PFET included Metal gate electrode 282, PFET doped cap 286, and PFET gate electrode 294.

於另一個實施例中，在將含矽閘極電極層178形成於區域180和200兩者之前，先沉積矽化物形成用金屬蓋層174以覆蓋摻雜矽蓋層170，如第21圖中所示。矽化物形成用金屬蓋層174可以包括上述參照矽化物形成用金屬蓋層56所說明之任何的金屬或該等金屬之任何組合。於另一個實施例中，矽化物形成用金屬蓋層174包括Ni並且包含大約5至15原子百分比之Pt，而較佳包含大約5至10原子百分比之Pt。沉積矽化物形成用金屬蓋層174至從大約4nm至大約12nm之厚度，而較佳為大約5nm至10nm之間的厚度。在形成矽化物形成用金屬蓋層174後，執行前面所述和顯示於第18和19圖中之製程步驟，包含形成含矽閘極電極層178、硬遮罩層182、和硬遮罩186和190。然後將這些硬遮罩使用為蝕刻遮罩，用來分別形成閘極堆疊210和220而覆蓋區域180和200，如第22圖中所示。In another embodiment, a germanium formation metal cap layer 174 is deposited to cover the doped cap layer 170 prior to forming the germanium-containing gate electrode layer 178 in both regions 180 and 200, as in FIG. Shown. The metallization layer 174 for telluride formation may include any of the metals described above with reference to the metallization layer 56 for telluride formation or any combination of such metals. In another embodiment, the metallization layer 174 for telluride formation comprises Ni and comprises from about 5 to 15 atomic percent Pt, and preferably from about 5 to 10 atomic percent Pt. The metallization layer 174 for depositing the telluride is deposited to a thickness of from about 4 nm to about 12 nm, and preferably between about 5 nm and 10 nm. After forming the metallization layer 174 for telluride formation, the process steps described above and shown in FIGS. 18 and 19 are performed, including forming a germanium-containing gate electrode layer 178, a hard mask layer 182, and a hard mask 186. And 190. These hard masks are then used as etch masks to form gate stacks 210 and 220, respectively, to cover regions 180 and 200, as shown in FIG.

在此蝕刻和去除硬遮罩186和190後，閘極堆疊210包含NFET閘極絕緣體222、NFET高k閘極絕緣體226、NFET金屬氧化物閘極蓋230、NFET含金屬閘極電極234、NFET摻雜矽蓋238、NFET矽化物形成用金屬蓋242、和NFET矽閘極電極250。閘極堆疊220包含PFET通道254、PFET閘極絕緣體258、PFET高k閘極絕緣體262、視需要選擇使用之PFET含金屬層266、270、和274、PFET金屬氧化物閘極蓋278、PFET含金屬閘極電極282、PFET摻雜矽蓋286、PFET矽化物形成用金屬蓋290、和PFET矽閘極電極294。After etching and removing the hard masks 186 and 190, the gate stack 210 includes an NFET gate insulator 222, an NFET high-k gate insulator 226, an NFET metal oxide gate cap 230, an NFET metal-containing gate electrode 234, and an NFET. A doped cap 238, an NFET telluride forming metal cap 242, and an NFET gate electrode 250 are provided. Gate stack 220 includes PFET channel 254, PFET gate insulator 258, PFET high-k gate insulator 262, PFET metal-containing layers 266, 270, and 274, optionally used, PFET metal oxide gate cap 278, PFET included A metal gate electrode 282, a PFET doped cap 286, a PFET telluride forming metal cap 290, and a PFET gate electrode 294.

如前述關於裝置10之上下文的說明中，於後續的製程期間，裝置100也許將經歷熱處理，其涉及升高的溫度經過預先特定的時間間隔。這些製程通常將包含進行加熱以反應性地分別結合後續沉積金屬層(未顯示)與NFET和PFET矽閘極電極250和294，以形成用於閘極堆疊之相關聯之金屬矽化物閘極電極接觸點。若未使用譬如由第20圖中之閘極堆疊204、208所示之NFET矽化物形成用金屬蓋，則二種可能結果之其中一種可能會發生。NFET摻雜之矽蓋238和PFET摻雜矽蓋286可能與後續形成的金屬層反應以形成經摻雜之金屬矽化物層。若覆蓋之矽閘極電極250和294被完全反應地轉變成矽化物，則此情況也許會發生。若矽閘極電極未全部被轉變，譬如像是若這些電極太厚，則NFET摻雜矽蓋238和PFET摻雜矽蓋286也許在它們的各自的閘極堆疊維持為未經反應之導電性摻雜矽層。若於閘極堆疊210和220中包含矽化物形成用金屬蓋242和290，譬如第22圖中所示，則第三種結果可能發生。於此情況，當後續的熱處理包含暴露於溫度超過大約400℃經過大約5秒鐘或更久，則NFET摻雜矽蓋238和PFET摻雜矽蓋286將分別與矽化物形成用金屬蓋242、290反應以形成關聯之金屬矽化物。若來自這些蓋層之矽以化學計量計存在有超過來自鄰接之矽化物形成用金屬蓋層之金屬物種，則摻雜矽蓋之一部分也許會保持為未反應之摻雜矽。或者是，如此過量之矽於將矽閘極電極250和294轉變為金屬矽化物閘極接觸點之製程過程中也許會被消耗和轉變成經摻雜之金屬矽化物區。以化學計量計超過來自各個摻雜矽蓋之矽的來自矽化物形成用金屬蓋242和290之金屬物種，則很可能將與來自矽閘極電極250和294之矽反應並且轉變成金屬矽化物。包括分別***置於含金屬閘極電極234和282與矽閘極電極250和294之間之摻雜矽或者較佳之摻雜金屬矽化物之層業經實驗發現可降低閘極堆疊之AC阻抗。As described above with respect to the context of device 10, during subsequent processing, device 100 may undergo a heat treatment that involves elevated temperatures through a predetermined time interval. These processes will typically involve heating to reactively combine subsequent deposited metal layers (not shown) with NFET and PFET gate electrodes 250 and 294, respectively, to form associated metal telluride gate electrodes for gate stacking. Contact point. If a metal cap for NFET telluride formation, such as shown by gate stacks 204, 208 in Figure 20, is not used, one of two possible outcomes may occur. The NFET doped cap 238 and the PFET doped cap 286 may react with the subsequently formed metal layer to form a doped metal telluride layer. This may occur if the covered gate electrodes 250 and 294 are completely converted into germanium. If the gate electrodes are not all converted, such as if the electrodes are too thick, the NFET-doped cap 238 and the PFET-doped cap 286 may remain unreacted in their respective gate stacks. Doped with a layer of germanium. If the metallization forming metal caps 242 and 290 are included in the gate stacks 210 and 220, as shown in Fig. 22, a third result may occur. In this case, when the subsequent heat treatment comprises exposure to a temperature exceeding about 400 ° C for about 5 seconds or more, the NFET-doped cap 238 and the PFET doped cap 286 will be respectively associated with the telluride-forming metal cap 242, 290 reacts to form an associated metal halide. If the ruthenium from these cap layers is present in stoichiometry over a metal species from a neighboring ruthenium-forming metal cap layer, then a portion of the doped ruthenium cap may remain unreacted doped yttrium. Alternatively, such an excess may be consumed and converted into a doped metal halide region during the process of converting the gate electrodes 250 and 294 into metal halide gate contacts. The metal species from the telluride-forming metal caps 242 and 290 from the respective doped lids are stoichiometrically measured, and it is likely to react with the tantalum gate electrodes 250 and 294 and convert to metal halides. . Layers comprising doped germanium or preferably doped metal telluride interposed between metal-containing gate electrodes 234 and 282 and germanium gate electrodes 250 and 294, respectively, have been found to reduce the AC impedance of the gate stack.

因此，本文中說明之實施例提供新穎的方法用來製造半導體裝置，該半導體裝置具有經摻雜之含矽蓋層插置於電晶體閘極堆疊之金屬與多晶矽閘極電極層之間。摻雜矽層可以單獨使用或者與插置於摻雜矽蓋層與多晶矽閘極層之間之矽化物形成用金屬蓋層結合使用。當於後續的製程過程中被充分加熱時，摻雜矽層可以保持未反應，或者可以藉由與矽化物形成用金屬蓋層(如果有使用)反應、或者藉由與用來形成源極/汲極/閘極矽化物接觸點之後續形成之金屬層反應之任何一種情況，而後續地形成經摻雜之金屬矽化物。所導致的經摻雜之矽化物或者經摻雜之金屬矽化物蓋層係橋接金屬與多晶矽閘極層之間之介面，有效地增加此區域之導電率並且減少咸信為造成不希望之高閘極阻抗之原因之介面缺陷。藉由減少或者消除此種介面異常，能夠更有效地使用具有其固有的性能優點之金屬閘極材料，而結合多晶矽閘極以提供進一步之性能改善。這些優點包含相容的加入高k介電閘極絕緣體、連同它們固有的優越絕緣性質於閘極堆疊中。因此，可以結合使用這些方法製造CMOS裝置上之PFET和NFET電晶體，或者製造個別的PFET和NFET裝置，並且能夠整合至習知的製造順序中以提供改善之裝置性能。Accordingly, the embodiments described herein provide a novel method for fabricating a semiconductor device having a doped capping layer interposed between a metal and polysilicon gate electrode layer of a transistor gate stack. The doped germanium layer may be used alone or in combination with a metal cap layer for telluride formation interposed between the doped cap layer and the polysilicon gate layer. The doped germanium layer may remain unreacted during subsequent processing, or may be reacted with a metal cap layer (if used) for telluride formation, or by forming a source/ Any of the subsequent metal layer reactions formed by the drain/gate germanium contact points, followed by formation of the doped metal germanide. The resulting doped telluride or doped metal germanide capping layer bridges the interface between the metal and the polysilicon gate layer, effectively increasing the conductivity of the region and reducing the saltiness to cause undesirable heights Interface defects due to gate impedance. By reducing or eliminating such interface anomalies, metal gate materials having their inherent performance advantages can be used more efficiently, combined with polysilicon gates to provide further performance improvements. These advantages include compatible addition of high-k dielectric gate insulators, along with their inherent superior insulating properties in the gate stack. Thus, PFET and NFET transistors on CMOS devices can be fabricated in conjunction with these methods, or individual PFET and NFET devices can be fabricated and integrated into conventional fabrication sequences to provide improved device performance.

雖然於本發明之上述詳細說明中呈現了至少一個實施範例，但是應該了解到存在有許多之變化。亦應該了解到實施範例或諸實施範例僅是作實例用，而並不欲限制本發明之範圍、應用、或架構於任何方式。而是，以上之詳細說明將供提熟悉此項技術者施行本發明之實施範例之方便的路途指引，將了解到在例示之實施範例中所說明之功能和元件的配置可以作各種之改變而仍不脫離本發明提出於所附申請專利範圍中及其合法均等之範圍。While at least one embodiment has been presented in the foregoing Detailed Description of the invention, it should be understood that there are many variations. It should be understood that the examples or embodiments are merely illustrative and are not intended to limit the scope, application, or architecture of the invention. Rather, the above detailed description is to be construed as a part of the description of the preferred embodiments of the invention. The scope of the invention is intended to be within the scope of the appended claims.

10、100．．．半導體MOS電晶體裝置(半導體裝置)10,100. . . Semiconductor MOS transistor device (semiconductor device)

11．．．載體晶圓11. . . Carrier wafer

12．．．絕緣層12. . . Insulation

14、110．．．半導體基板(矽基板)14, 110. . . Semiconductor substrate

16．．．薄矽層16. . . Thin layer

18、134．．．通道層18, 134. . . Channel layer

21．．．矽表面twenty one. . .矽 surface

22、138．．．閘極絕緣層22,138. . . Gate insulation

24、140．．．高k閘極絕緣層(高k介電層)24, 140. . . High-k gate insulating layer (high-k dielectric layer)

32、36、40．．．含金屬層32, 36, 40. . . Metal containing layer

44、162．．．金屬氧化物閘極蓋層44, 162. . . Metal oxide gate cap

48、142、146、150、166．．．含金屬閘極電極層(含金屬閘極層)48, 142, 146, 150, 166. . . Metal-containing gate electrode layer (including metal gate layer)

50．．．外表面50. . . The outer surface

52、170．．．含矽蓋層(摻雜之矽蓋層)52, 170. . . Cover layer (doped cap layer)

56、174、242、290．．．矽化物形成用金屬蓋層56, 174, 242, 290. . . Metal cap layer for telluride formation

60、178．．．含矽閘極電極層(含矽閘極層)60, 178. . .矽-gate electrode layer (including 矽 gate layer)

64、122、182．．．硬遮罩層64, 122, 182. . . Hard mask layer

68、154、186、190．．．硬遮罩68, 154, 186, 190. . . Hard mask

70、95、98、204、208、210、220．．．閘極堆疊70, 95, 98, 204, 208, 210, 220. . . Gate stack

72．．．PFET72. . . PFET

74．．．閘極絕緣體74. . . Gate insulator

76．．．高k閘極絕緣體76. . . High-k gate insulator

78、80、82．．．含金屬層78, 80, 82. . . Metal containing layer

84、162．．．金屬氧化物閘極蓋層84, 162. . . Metal oxide gate cap

86．．．含金屬閘極電極86. . . Metal gate electrode

88．．．摻雜之矽蓋88. . . Doped lid

90．．．矽化物形成用金屬蓋90. . . Metal cover for telluride formation

92．．．矽閘極電極92. . .矽 gate electrode

108．．．表面區域108. . . Surface area

118．．．隔離區域118. . . Isolated area

130．．．矽表面130. . .矽 surface

180．．．NFET區域180. . . NFET region

200．．．PFET區域200. . . PFET area

222．．．NFET閘極絕緣體222. . . NFET gate insulator

226．．．NFET高k閘極絕緣體226. . . NFET high-k gate insulator

230．．．NFET金屬氧化物閘極蓋230. . . NFET metal oxide gate cap

234．．．NFET含金屬閘極電極234. . . NFET metal gate electrode

238．．．NFET摻雜之矽蓋238. . . NFET doped cover

242．．．NFET矽化物形成用金屬蓋242. . . Metal cover for NFET telluride formation

250．．．NFET矽閘極電極250. . . NFET gate electrode

254．．．PFET通道254. . . PFET channel

258．．．PFET閘極絕緣體258. . . PFET gate insulator

262．．．PFET高k閘極絕緣體262. . . PFET high-k gate insulator

266、270、274．．．PFET含金屬層266, 270, 274. . . PFET with metal layer

278．．．PFET金屬氧化物閘極蓋278. . . PFET metal oxide gate cap

282．．．PFET含金屬閘極電極282. . . PFET with metal gate electrode

286．．．PFET摻雜之矽蓋286. . . PFET doped cover

290．．．PFET矽化物形成用金屬蓋290. . . PFET telluride forming metal cover

294．．．PFET矽閘極電極294. . . PFET gate electrode

上文中結合下列之圖式而說明本發明，其中相同之元件符號表示相同之元件，且其中：The invention is described above in conjunction with the following drawings in which like reference numerals represent the

第1至9圖示意地顯示依照本發明之範例實施例具有經摻雜之含矽蓋層的半導體裝置之部分之剖面圖和用來製造此種半導體裝置方法；以及1 through 9 are schematic views showing a cross-sectional view of a portion of a doped capping-containing semiconductor device and a method for fabricating such a semiconductor device in accordance with an exemplary embodiment of the present invention;

第10至22圖示意地顯示依照另一個範例實施例經摻雜之含矽蓋層的半導體裝置之部分之剖面圖和用來製造此種半導體裝置之方法。10 through 22 are schematic views showing a cross-sectional view of a portion of a doped capping-containing semiconductor device in accordance with another exemplary embodiment and a method for fabricating such a semiconductor device.

11．．．載體晶圓11. . . Carrier wafer

12．．．絕緣層12. . . Insulation

14．．．半導體基板(矽基板)14. . . Semiconductor substrate

16．．．薄矽層16. . . Thin layer

74．．．閘極絕緣體74. . . Gate insulator

76．．．高k閘極絕緣體76. . . High-k gate insulator

84．．．金屬氧化物閘極蓋層84. . . Metal oxide gate cap

86．．．含金屬閘極電極86. . . Metal gate electrode

88．．．摻雜之矽蓋88. . . Doped lid

92．．．矽閘極電極92. . .矽 gate electrode

98．．．閘極堆疊98. . . Gate stack

Claims

一種用來形成半導體裝置(10、100)之方法，其中，該半導體裝置包括半導體基板(14、110)，該方法包括下列步驟：形成高k介電層(24、140)以覆蓋該半導體基板；形成含金屬閘極層(48、166)以覆蓋該高k介電層；形成經摻雜之含矽蓋層(52、170)以覆蓋該含金屬閘極層；沉積含矽閘極層(60、178)以覆蓋該經摻雜之含矽蓋層；以及形成用金屬蓋層(56、174)於該經摻雜之含矽蓋層(52、170)與該含矽閘極層(60、178)之間。 A method for forming a semiconductor device (10, 100), wherein the semiconductor device comprises a semiconductor substrate (14, 110), the method comprising the steps of: forming a high-k dielectric layer (24, 140) to cover the semiconductor substrate Forming a metal-containing gate layer (48, 166) to cover the high-k dielectric layer; forming a doped capping layer (52, 170) to cover the metal-containing gate layer; depositing a germanium-containing gate layer (60, 178) to cover the doped capping layer; and forming a metal cap layer (56, 174) on the doped capping layer (52, 170) and the germanium containing gate layer Between (60, 178).

如申請專利範圍第1項之方法，其中，形成矽化物形成用金屬蓋層(56、174)之該步驟包括：形成包括選擇自由Ni、Pt、Co、Ti、和它們的組合所組成之群組中之金屬之矽化物形成用金屬蓋層。 The method of claim 1, wherein the step of forming a metal cap layer (56, 174) for forming a telluride comprises: forming a group comprising a selective free Ni, Pt, Co, Ti, and a combination thereof The metal telluride of the metal in the group is formed with a metal cap layer.

如申請專利範圍第2項之方法，其中，形成矽化物形成用金屬蓋層(56、174)之該步驟包括：形成包括NiPt之矽化物形成用金屬蓋層。 The method of claim 2, wherein the step of forming a metal cap layer (56, 174) for forming a telluride includes forming a metal cap layer for forming a telluride comprising NiPt.

如申請專利範圍第3項之方法，其中，形成包括NiPt之矽化物形成用金屬蓋層(56、174)之該步驟包括：形成具有從大約5原子百分比(atomic %)至大約15原子百分比之Pt濃度的矽化物形成用金屬蓋層。 The method of claim 3, wherein the step of forming a metal cap layer (56, 174) for forming a telluride comprising NiPt comprises: forming from about 5 atomic percent to about 15 atomic percent The telluride for Pt concentration forms a metal cap layer.

如申請專利範圍第1項之方法，復包括下列步驟：在形成高k介電層(24、140)之該步驟之前，先形成閘極絕緣層(22、138)以覆蓋該半導體基板(14、110)；以及在該閘極絕緣層與該半導體基板之間形成通道層(18、134)，該通道層包括由受壓縮應力之單晶層和受拉張應力之單晶層所組成之群組中之其中一個。 For example, the method of applying for the first item of the patent scope includes the following steps: Before the step of forming the high-k dielectric layer (24, 140), a gate insulating layer (22, 138) is formed to cover the semiconductor substrate (14, 110); and the gate insulating layer and the semiconductor substrate A channel layer (18, 134) is formed between the channel layer comprising one of a group consisting of a single layer of compressively stressed and a single layer of tensile stress.

如申請專利範圍第1項之方法，其中，形成經摻雜之含矽蓋層(52、170)之該步驟包括：形成於原位經摻雜之含矽蓋層。 The method of claim 1, wherein the step of forming the doped cap layer (52, 170) comprises: forming a doped cap layer in situ.

如申請專利範圍第1項之方法，其中，形成經摻雜之含矽蓋層(52、170)之該步驟包括：形成包括選擇自由B、As、P、和Sb所組成之群組中之摻雜元素之經摻雜之含矽蓋層。 The method of claim 1, wherein the step of forming the doped capping layer (52, 170) comprises: forming a group comprising the selected free B, As, P, and Sb A doped cap layer comprising a doped element.

如申請專利範圍第1項之方法，其中，形成經摻雜之含矽蓋層(52、170)之該步驟包括：形成包括具有從大約1.0×10¹⁹ 原子/cm³ 至大約1.0×10²⁰ 原子/cm³ 之濃度之摻雜元素之含矽蓋層。The method of claim 1, wherein the step of forming the doped capping layer (52, 170) comprises: forming comprising from about 1.0 x 10 ¹⁹ atoms/cm ³ to about 1.0 x 10 ²⁰ A niobium-containing capping layer of doping elements at a concentration of atoms/cm ³ .

如申請專利範圍第1項之方法，復包括形成***置於該高k介電層(24、140)與該含金屬閘極層(48、166)之間之金屬氧化物閘極蓋層(44、162)的步驟。 The method of claim 1, further comprising forming a metal oxide gate cap layer interposed between the high-k dielectric layer (24, 140) and the metal-containing gate layer (48, 166) (44, 162) steps.