TWI476896B - 多晶片模組及其製造方法 - Google Patents
多晶片模組及其製造方法 Download PDFInfo
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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Description
本發明係有關一種多晶片模組及其製造方法,特別是指一種將高壓元件晶片與低壓控制晶片固定於同一晶片座之多晶片模組及其製造方法。
第1圖顯示一種典型的電源供應電路,其中,多晶片模組10中的低壓控制晶片14,根據反馳式(flyback)的回授訊號FB,以及電流感測訊號CS,操作高壓元件晶片12中的功率開關,以將輸入電壓Vin轉換為輸出電壓Vout。
請參閱第2A圖,顯示多晶片模組10一種先前技術的安排方式。如圖所示,多晶片模組10包含高壓元件晶片12與低壓控制晶片14。其中,高壓元件晶片12固定於專用的晶片座11上;且低壓控制晶片14固定於另一個專用的晶片座13上。一般而言,高壓元件與低壓元件的製程不同,分別製造的成本較同時製造於同一基板上來得低,因此分別製造成為高壓元件晶片12與低壓控制晶片14是很普遍的方式;此外,高壓元件若為垂直式的元件,則其基板表面具有電位,因此,高壓元件晶片12與低壓控制晶片14不宜同時固定於同一晶片座上,以免相互影響,甚至造成短路,其具體實施方式,如第2A圖所示,將高壓元件晶片12與低壓控制晶片14固定於不同的晶片座11與13上,並將其封裝於同一模組中。這種先前技術的優點在於:整合高壓元件晶片12與低壓控制晶片14於單一封裝之內,並避免晶片訊號相互的干擾影響。
第2B圖顯示第2A圖中,AA切線的剖面圖。如圖所示,分開的晶片座11與晶片座13上,分別固定高壓元件晶片12與低壓控制晶片14,且其晶片間,利用金屬導線15相互耦接,以傳送訊號。這種先前技術的缺點是:晶片固定於單一專屬晶片座,因此每一晶片座的面積相對於共用晶片座的安排方式小,如此一來,其散熱的效率相對較差。此外,低壓控制晶片14中的溫度感測器(未示出)無法感測高壓元件晶片12(或感測準確度較差)的溫度,以於溫度過高時啟動過溫保護(over temperature protection,OTP)。上述先前技術例如可見於美國專利申請案第2007/0200537號。
第3A-3C圖顯示另一種多晶片模組20安排方式的先前技術。相較於前述先前技術,此先前技術係將高壓元件與低壓元件整合於單一(monolithic)晶片22中。如第3A圖所示,晶片座21將單一晶片22固定於其上,如此一來,晶片座21相較於前述之先前技術中,分開的晶片座11與13,本先前技術的散熱面積較大,具有較佳的散熱效果。第3B圖分別以簡圖顯示單一晶片22的上視圖,如圖所示,高壓元件221與低壓元件222整合於單一晶片22中。第3C圖顯示第2A圖中,AA切線的剖面圖。但這種先前技術的缺點在於,高壓元件需要與低壓元件同時於同一基板上製造,其製造成本較高;此外,高壓元件與低壓元件於同一基板上,容易產生訊號相互影響的雜訊問題,例如串擾(crosstalk)等問題。
有鑑於此,本發明即針對上述先前技術之不足,提出一種將高壓元件晶片與低壓控制晶片固定於同一晶片座之多晶片模組及其製造方法,可改善晶片散熱問題,並且不需要增加製造成本。
本發明目的之一在提供一種多晶片模組。
本發明另一目的在提供一種多晶片模組製造方法。
為達上述之目的,就其中一觀點言,本發明提供了一種多晶片模組,包含:一高壓元件晶片,其具有至少一功率開關;一低壓控制晶片,其藉由金屬導線與該高壓元件晶片耦接;單一晶片座,用以將該高壓元件晶片與該低壓控制晶片固定於其上;以及複數引腳,藉由該晶片座之一延伸部或金屬導線與該單一晶片座耦接。
在其中一種實施型態中,其中該高壓元件晶片宜包括:一橫向(lateral)金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)功率開關;以及一橫向空乏型啟動開關。
所述多晶片模組,其中該高壓元件晶片可更包含一熱二極體用以感測溫度。
在另一種實施型態中,其中該橫向空乏型啟動開關宜具有一橫向空乏型MOSFET或一橫向空乏型接面場效電晶體(junction field effect transistor,JFET)。
在另一種實施型態中,其中該功率開關具有一第一電流流入端、一第一控制端、以及一第一電流流出端,藉由該第一控制端的操作,控制一開關電流流入該第一電流流入端,並自該第一電流流出端流出;該高壓元件晶片更包括一取樣電晶體,用以取樣該開關電流,其包含:一第二電流流入端,包含於該第一電流流入端;一第二控制端,包含於該第一控制端;以及一第二電流流出端,與該第一電流流出端流出隔絕,並產生一與該開關電流具有一比例之取樣電流。
就另一觀點,本發明也提供了一種多晶片模組製造方法,包含:提供一高壓元件晶片,其具有至少一功率開關;藉由金屬導線將該高壓元件晶片耦接至一低壓控制晶片;將該高壓元件晶片與該低壓控制晶片固定於單一晶片座;以及藉由該晶片座之一延伸部或金屬導線將該單一晶片座耦接至複數引腳。
底下藉由具體實施例詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
請參閱第4A與第4B圖,顯示本發明第一個實施例,多晶片模組30中包含具有至少一功率開關之高壓元件晶片32、低壓控制晶片34、單一晶片座31與複數引腳37。如第4A圖所示,低壓控制晶片34其藉由金屬導線35與高壓元件晶片32耦接。並且,高壓元件晶片32與低壓控制晶片34皆固定於單一晶片座31上,如第4B圖所示之第4A圖中CC剖線之剖視圖。此外,複數引腳37藉由晶片座31之延伸部39或金屬導線35與單一晶片座31上之高壓元件晶片32與低壓控制晶片34耦接。
為使高壓元件晶片32與低壓控制晶片34可固定於單一晶片座31上,且為避免如先前技術所述之垂直式高壓元件的基板表面與低壓控制晶片之基板表面具有不同的電位;本實施例之高壓元件晶片32可以但不限於包括:橫向金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)功率開關;以及/或橫向空乏型啟動開關。由於橫向高壓元件與垂直式高壓元件不同,其基板表面與低壓控制晶片之基板表面具有相同電位(接地),因此可以固定於同一晶片座31上。
其中,高壓元件晶片32中,可以但不限於包括如熱二極體(thermal diode),可用以感測溫度,進而對高壓元件加以控制,以進一步避免晶片過熱。
此外,上述橫向空乏型啟動開關例如但不限於為橫向空乏型MOSFET或橫向空乏型接面場效電晶體(junction field effect transistor,JFET),其用以操作於電路啟動程序。
第5A-5C圖顯示本發明第二個實施例。如第5A圖所示,多晶片模組40中包含高壓元件晶片42與低壓控制晶片44。在本實施例中,高壓元件晶片42例如包含功率開關S1與取樣電晶體S2,取樣電晶體S2係用以感測功率開關S1之電流。取樣電晶體S2的電流流入端耦接於功率開關S1之電流流入端。取樣電晶體S2的控制端與功率開關S1之控制端,皆耦接於低壓控制晶片44的控制接腳Gate。取樣電晶體S2的電流流出端與電阻R之一端耦接,電阻R之另一端則耦接於地。(在NMOS的情況下,電流流入端為汲極、控制端為閘極、電流流出端為源極;在PMOS或雙載子接面電晶體時則為對應的端子,此為相同技術領域中之具有通常知識者所熟知。)藉由此種取樣方式,可減少感測功率開關電流的功率損失,並提升效率,改善取樣的精確度。此外,請參照第5B圖,顯示藉由取樣電晶體S2感測功率開關S1電流,以達成過電流保護(over current protection,OCP)的機制,可以進一步省略低壓控制晶片44的電流感測CS接腳。如第5B圖所示,將取樣電晶體S2源極耦接至一比較器電路,與一設定值比較,並產生過電流保護訊號OCP,即可達成過電流保護機制,進而省略低壓控制晶片44的電流感測CS接腳,以提高整合性,並降低製造成本。
第5C圖顯示取樣電晶體S2與功率開關S1的上視圖。如第5C圖所示,功率開關S1包含汲極Drain、漂移區、閘極Gate、以及源極Source1。在實際的做法中,可視為將源極Source1分割出一小段以作為取樣電晶體S2之源極Source2,而汲極Drain、漂移區、與閘極Gate則與功率開關S1共用,也就是說,功率開關S1的汲極Drain(電流流入端)與閘極Gate(控制端)也分別作為或包含取樣電晶體S2的汲極Drain(電流流入端)與閘極Gate(控制端),而取樣電晶體S2的源極Source2(電流流出端)與功率開關S1的源極Source1(電流流出端)隔絕,但取樣電晶體S2與功率開關S1整合成單一元件,以節約元件面積及簡化元件製作程序。如此,可根據源極Source2與源極Source1的尺寸比例,與感測到的源極Source2電壓或電流訊號,即可推導出功率開關S1的開關電流,以作為電流感測訊號CS或直接用以進行過電流保護機制。
以上已針對較佳實施例來說明本發明,唯以上所述者,僅係為使熟悉本技術者易於了解本發明的內容而已,並非用來限定本發明之權利範圍。在本發明之相同精神下,熟悉本技術者可以思及各種等效變化。例如,功率開關S1可為PMOS或NMOS電晶體;在所示各實施例電路中,可***不影響訊號主要意義的元件,如其他開關等;又例如比較器或誤差放大器的輸入端正負可以互換,僅需對應修正電路的訊號處理方式即可;再例如本發明之多晶片模組可以應用於各種電源供應電路,例如功率因子校正(PFC)電路、返馳式功率因子校正電路、或半橋電路等,並非限於如各圖所示之返馳式電路。凡此種種,皆可根據本發明的教示類推而得,因此,本發明的範圍應涵蓋上述及其他所有等效變化。
10,20,30,40‧‧‧多晶片模組
11,13,15,21,31‧‧‧晶片座
12,16,32,42‧‧‧高壓元件晶片
14,34,44‧‧‧低壓控制晶片
15,35‧‧‧金屬導線
22‧‧‧單一晶片
221‧‧‧高壓元件
222‧‧‧低壓元件
37‧‧‧引腳
39‧‧‧延伸部
CS‧‧‧電流感測訊號
Drain‧‧‧汲極
Drift Region‧‧‧漂移區
FB‧‧‧回授訊號
Gate‧‧‧閘極
R‧‧‧電阻
S1‧‧‧功率開關
S2‧‧‧取樣電晶體
Source 1,Source 2‧‧‧源極
Vin‧‧‧輸入電壓
Vout‧‧‧輸出電壓
第1圖顯示一種典型的電源供應電路。
第2A-2B圖顯示多晶片模組10一種先前技術的安排方式。
第3A-3C圖顯示另一種多晶片模組20安排方式的先前技術。
第4A-4B圖顯示本發明第一個實施例。
第5A-5C圖顯示本發明第二個實施例。
30...多晶片模組
31...晶片座
32...高壓元件晶片
34...低壓控制晶片
35...金屬導線
37...引腳
39...延伸部
Claims (8)
- 一種多晶片模組,包含:一高壓元件晶片,其具有至少一功率開關、以及用以感測溫度之一熱二極體;一低壓控制晶片,其藉由金屬導線與該高壓元件晶片耦接;單一晶片座,用以將該高壓元件晶片與該低壓控制晶片固定於其上;以及複數引腳,藉由該晶片座之一延伸部或金屬導線與該單一晶片座耦接。
- 如申請專利範圍第1項所述之多晶片模組,其中該高壓元件晶片包括:一橫向(lateral)金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)功率開關;以及一橫向空乏型啟動開關。
- 如申請專利範圍第2項所述之多晶片模組,其中該橫向空乏型啟動開關具有一橫向空乏型MOSFET或一橫向空乏型接面場效電晶體(junction field effect transistor,JFET)。
- 如申請專利範圍第1項所述之多晶片模組,其中該功率開關具有一第一電流流入端、一第一控制端、以及一第一電流流出端,藉由該第一控制端的操作,控制一開關電流流入該第一電流流入端,並自該第一電流流出端流出;該高壓元件晶片更包括一取樣電晶體,用以取樣該開關電流,其包含:該第一電流流入端;該第一控制端;以及一第二電流流出端,與該第一電流流出端流出隔絕,並產生一與該開關電流具有一比例之取樣電流,其中該取樣電晶體 與功率開關整合成單一元件。
- 一種多晶片模組製造方法,包含:提供一高壓元件晶片,其具有至少一功率開關、以及用以感測溫度之一熱二極體;藉由金屬導線將該高壓元件晶片耦接至一低壓控制晶片;將該高壓元件晶片與該低壓控制晶片固定於單一晶片座;以及藉由該晶片座之一延伸部或金屬導線將該單一晶片座耦接至複數引腳。
- 如申請專利範圍第5項所述之多晶片模組製造方法,其中該高壓元件晶片包括:一橫向(lateral)金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)功率開關;以及一橫向空乏型啟動開關。
- 如申請專利範圍第6項所述之多晶片模組製造方法,其中該橫向空乏型啟動開關具有一橫向空乏型MOSFET或一橫向空乏型接面場效電晶體(junction field effect transistor,JFET)。
- 如申請專利範圍第5項所述之多晶片模組製造方法,其中該功率開關具有一第一電流流入端、一第一控制端、以及一第一電流流出端,藉由該第一控制端的操作,控制一開關電流流入該第一電流流入端,並自該第一電流流出端流出;該高壓元件晶片更包括一取樣電晶體,用以取樣該開關電流,其包含:該第一電流流入端;該第一控制端;以及一第二電流流出端,與該第一電流流出端流出隔絕,並產生一與該開關電流具有一比例之取樣電流,其中該取樣電晶體 與功率開關整合成單一元件。
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US6756689B2 (en) * | 1999-09-13 | 2004-06-29 | Fairchild Korea Semiconductor, Ltd. | Power device having multi-chip package structure |
US20080304305A1 (en) * | 2007-06-11 | 2008-12-11 | Alpha & Omega Semiconductor, Ltd. | Boost converter with integrated high power discrete fet and low voltage controller |
TW200905853A (en) * | 2007-07-31 | 2009-02-01 | Alpha & Amp Omega Semiconductor Ltd | A multi-die DC-DC buck power converter with efficient packaging |
US20110063025A1 (en) * | 2008-02-13 | 2011-03-17 | Masliah Denis A | High Breakdown Voltage Double-Gate Semiconductor Device |
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US6756689B2 (en) * | 1999-09-13 | 2004-06-29 | Fairchild Korea Semiconductor, Ltd. | Power device having multi-chip package structure |
US20080304305A1 (en) * | 2007-06-11 | 2008-12-11 | Alpha & Omega Semiconductor, Ltd. | Boost converter with integrated high power discrete fet and low voltage controller |
TW200905853A (en) * | 2007-07-31 | 2009-02-01 | Alpha & Amp Omega Semiconductor Ltd | A multi-die DC-DC buck power converter with efficient packaging |
US20110063025A1 (en) * | 2008-02-13 | 2011-03-17 | Masliah Denis A | High Breakdown Voltage Double-Gate Semiconductor Device |
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