TWI471948B - 氧化物薄膜電晶體製程方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims description 33
- 239000010409 thin film Substances 0.000 title claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 112
- 229910044991 metal oxide Inorganic materials 0.000 claims description 57
- 150000004706 metal oxides Chemical class 0.000 claims description 57
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 193
- 239000010408 film Substances 0.000 description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 239000001257 hydrogen Substances 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 238000004380 ashing Methods 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052793 cadmium Inorganic materials 0.000 description 2
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks
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Description
本發明係關於一種電晶體製造方法,特別是有關於一種氧化物薄膜電晶體之製造方法。
近年來,平面顯示器的發展越來越迅速,已經逐漸取代傳統的陰極射線管顯示器。現今的平面顯示器主要有下列幾種:有機發光二極體顯示器(Organic Light-Emitting Diodes Display,OLED)、電漿顯示器(Plasma Display Panel,PDP)、液晶顯示器(Liquid Crystal Display,LCD)、以及場發射顯示器(Field Emission Display,FED)等。其中控制這些平面顯示器中每個畫素之開啟與關閉的薄膜電晶體(Thin Film Transistor,TFT),即為這些平面顯示器中相當關鍵性的元件之一。
第1圖繪示習知金屬氧化物薄膜電晶體結構的剖面示意圖。如第1圖所示,習知金屬氧化物薄膜電晶體結構10包含一基板101、一閘極102設置於基板101上、一半導體絕緣層103設置於基板101與閘極102上、一金屬氧化物層104設置於半導體絕緣層103上、一源極105與一汲極106分別設置於金屬氧化物層104上,且源極105與汲極106係經由蝕刻一金屬層所構成。然而,習知金屬氧化物薄膜電晶體10在進行源極105與汲極106的蝕刻製程時,位於源極105與汲極106下方之金屬氧化物層104常會因受到金屬蝕刻液之侵蝕而造成斷線之情形。
因此,如何有效避免金屬氧化物層在源極與汲極蝕刻時,不受蝕刻液侵蝕或其他後續製程之破壞,以提升氧化物薄膜電晶體的品質與製程良率即成為追求之目標。
有鑑於此,本發明提供一種氧化物薄膜電晶體製程方法,藉由一灰階光罩在金屬氧化物層上保留光阻層,來保護金屬氧化物層不會遭到蝕刻液以及氫摻雜之破壞,進而提升氧化物薄膜電晶體的品質與製程良率。
本發明之一態樣係提供一種製作氧化物薄膜電晶體之方法,包含:提供一基板;形成一閘極於基板上;形成一半導體絕緣層於閘極上;形成一金屬氧化物層於半導體絕緣層上;形成一第一圖案化光阻層於金屬氧化物層上,例如,利用一灰階光罩形成此第一圖案化光阻層;接著,第一圖案化光阻層作為罩幕來蝕刻金屬氧化物層形成一圖案化金屬氧化物層;移除部份第一圖案化光阻層來形成一第二圖案化光阻層;形成一金屬層於半導體絕緣層、圖案化金屬氧化物層以及第二圖案化光阻層上;形成一第三圖案化光阻層於金屬層上;以此第三圖案化光阻層罩幕,對金屬層進行蝕刻以形成一源極區與一汲極區,並暴露出第二圖案化光阻層;以及移除第三圖案化光阻層以及部份此第二圖案化光阻層來形成一第四圖案化光阻層。
在一實施例中,製作氧化物薄膜電晶體之方法更包括:形成一接觸洞層於金屬層以及第四圖案化光阻層上,並於源極區和汲極區形成歐姆接觸。
在一實施例中,第一圖案化光阻層具有一第一厚度以及一第二厚度,其中第一厚度大於此第二厚度。且金屬氧化物層對應此第一厚度之位置作為一通道區,金屬氧化物層對應此第二厚度之位置作為源極區與汲極區。
在一實施例中,移除部份第一圖案化光阻層來形成一第二圖案化光阻層,更包括將此第一圖案化光阻移除第二厚度,來形成一具有一第三厚度之第二圖案化光阻層,其中第三厚度大於第二厚度,金屬氧化物層對應此第三厚度之位置作為此通道區。其中,第一厚度,第二厚度以及第三厚度間具有3:1:2之厚度比值。
在一實施例中,第四圖案化光阻層具有一第四厚度,金屬氧化物層對應此第四厚度之位置作為通道區。
在一實施例中,使用一濕式蝕刻法對此金屬層進行蝕刻。
依此,本發明利用一灰階光罩在金屬氧化物層上形成不同厚度之光阻層,藉以保護金屬氧化物層於進行金屬層之濕式蝕刻製程時,不會遭到蝕刻液之侵蝕,以及沉積接觸洞層時,不會遭到氫摻雜之破壞,進而提升氧化物薄膜電晶體的品質與製程良率。
以下為本發明較佳具體實施例以所附圖示加以詳細說明,下列之說明及圖示使用相同之參考數字以表示相同或類似元件,並且在重複描述相同或類似元件時則予省略。
請先參考第13圖,第13圖繪示本發明之一較佳實施
例的氧化物薄膜電晶體結構之剖面示意圖。如第13圖所示,本實施例之氧化物薄膜電晶體結構20包含一基板200;一閘極201設置於基板200上;一半導體絕緣層202設置於基板200與閘極201上;一金屬氧化物層208設置於半導體絕緣層202上;一光阻層2074、一源極區2091和一汲極區2092設置於金屬氧化物層208上,且位於光阻層2074之兩側,金屬氧化物層208中對應光阻層2074之位置作為通道區,其中源極區2091和汲極區2092係由金屬層209所構成;一接觸洞層212設置於金屬層209以及光阻層2074上,並露出源極區2091和汲極區2092,接觸洞層212是做為保護層用,一般是使用化學氣相沉積法沉積一層氮化矽(SiNx)層;一透明金屬層213設置於接觸洞層212上,可藉由一微影蝕刻製程來形成顯示器之畫素電極。在本實施例中,金屬氧化物層208係為例如一氧化銦鎵鋅層(Indium Gallium Zinc Oxide,IGZO),但不以此為限。舉例而言,金屬氧化物層208亦可為其他包含銦、鋅、錫、鎵、鉛、鍺、鎘或上述元素組合之氧化物,例如氧化銦鋅、氧化鋅錫,但不以此為限。
請參考第2圖至第13圖,第2圖至第13圖繪示本發明之一較佳實施例之金屬氧化物薄膜電晶體之製作方法示意圖。如第2圖所示,首先,提供一基板200。隨後,於基板200上形成一金屬層,再利用例如一微影蝕刻製程,但不以此為限,對該金屬層進行蝕刻而構成一閘極201。
接著,如第3圖所示,形成一半導體絕緣層202於閘極201與基板200上。然後,形成一金屬氧化物層203於
半導體絕緣層202上。在一實施例中,金屬氧化物層203係利用真空濺鍍製程於半導體絕緣層202上沉積一氧化銦鎵鋅層,但不以此為限。舉例而言,金屬氧化物層203亦可為其他包含銦、鋅、錫、鎵、鉛、鍺、鎘或上述元素組合之氧化物,例如氧化銦鋅、氧化鋅錫,但不以此為限。此外,在本實施例中,金屬氧化物層203係利用一真空鍍膜製程而沉積於半導體絕緣層202上,但不以此為限,例如亦可使用一溶液成膜製程成膜於半導體絕緣層202上,或是利用其它製程加以形成。
之後,如第4圖所示,在金屬氧化物層203上形成一光阻層204,在本實施例中,光阻層204是由樹脂、感光劑及溶劑組成。接著,利用一光源206以及一灰階光罩(Gray Level Mask)205對光阻層204進行一曝光製程。在本實施例中,灰階光罩205是放置在光源206與光阻層204之間,且本實施例光源206,例如為是均勻之紫外線光源(ultraviolet ray,UV ray)。其中,灰階光罩205是利用光罩上各個區域穿透率的不同,使得曝光時,對光阻層204之曝光程度有所不同,因此經過顯影後光阻層204表面就會產生高低起伏的變化。在本實施例中,為了避免後續進行源極區與汲極區蝕刻製程時,位於下方作為通道區之金屬氧化物層亦受到金屬蝕刻液之侵蝕,因此對應通道區之光阻層204與對應源極區與汲極區之光阻層204,於顯影後要具有不同之厚度,藉以保護通道區。因此,本案之灰階光罩205具有三個穿透率不同的光罩區域2051,2052和2053,在一實施例中,光罩區域2053之穿透率最佳,光罩
區域2052次之,光罩區域2051最低,因此,於顯影後,當對應光罩區域2053處之光阻層204完全移除後,對應光罩區域2051和光罩區域2052之光阻層會保留於金屬氧化物層203上,且會具有不同之厚度,而形成如第5圖所示之第一圖案化光阻層207。由於光罩區域2052之穿透率高於光罩區域2053,因此顯影後之第一圖案化光阻層207將具有兩不同厚度,第一厚度H1和第二厚度H2,其中對應通道區之光阻層2071具有第一厚度H1,對應源極區與汲極區之光阻層2072具有第二厚度H2,第一厚度H1為第二厚度H2之三倍。也就是說,光阻層2071厚度與光阻層2072厚度之比值約為3:1,亦即第一厚度H1和第二厚度H2之比值約為3:1。
接著,如第6圖所示,以第一圖案化光阻層207為罩幕對金屬氧化物層203進行蝕刻,以形成圖案化金屬氧化物層208。接著,如第7圖所示,在蝕刻結束後進行第一圖案化光阻層207之灰化製程,直到移除光阻層2072,暴露出部分圖案化金屬氧化物層208之表面,在一實施例中,由於光阻層2071厚度為光阻層2072厚度之三倍,因此於灰化製程移除光阻層2072後,仍然保有未被灰化之光阻層作為第二圖案化光阻層2073,其中,第二圖案化光阻層2073具有一第三厚度H3,第三厚度H3約為原本光阻層2071厚度之2/3,因此光阻層2071厚度與光阻層2072厚度和第二圖案化光阻層2073厚度之比值約為3:1:2,亦即第一厚度H1、第二厚度H2和第三厚度H3之比值約為3:1:2。
隨後,如第8圖所示,形成一金屬層209於圖案化金屬氧化物層208、第二圖案化光阻層2073和半導體絕緣層202上。接著,形成一光阻層210於金屬層209之上,在一實施例中,光阻層210之厚度小於第二圖案化光阻層2073。其中,在本實施例中,構成閘極201之金屬層與金屬層209可分別為一單一金屬層,例如鋁、鉬、鈦、鉻、銅、上述金屬之合金或其化合物,或一複合金屬層,例如包含鋁、鉬、鈦、鉻、銅、上述金屬之合金或其化合物中至少兩者之複合金屬。
接著,如第9圖所示,對光阻層210進行曝光,再對曝光後之光阻層210進行顯影,來形成第三圖案化光阻層211,來定義出源極區2091、汲極區2092與通道區2093。接著,如第10圖所示,以第三圖案化光阻層211為罩幕對金屬層209進行蝕刻,例如,利用一濕式蝕刻製程移去除未被該第三圖案化光阻層211覆蓋之部份金屬層209,以於金屬層209處定義出源極區2091,汲極區2092和通道區2093之位置。其中第二圖案化光阻層2073作為濕式蝕刻製程時對作為通道區2093之金屬氧化物層208之保護用。接著,如第11圖所示,進行第三圖案化光阻層211之灰化製程,此時部分之第二圖案化光阻層2073亦會被移除,但因為光阻層210之厚度小於第二圖案化光阻層2073,亦即第三圖案化光阻層211之厚度小於第二圖案化光阻層2073,因此於光阻灰化製程結束後,仍然保有未被灰化之光阻層而形成第四圖案化光阻層2074,其中第四圖案化光阻層2074具有一第四厚度H4,在一實施例中,第
四圖案化光阻層2074之厚度約為原本第二圖案化光阻層2073厚度之一半,亦即第四厚度H4約為第三厚度H3之一半。因此,光阻層2071、第二圖案化光阻層2073和第四圖案化光阻層2074之厚度比值為3:2:1,亦即第一厚度H1、第三厚度H3和第四厚度H4之比值約為3:2:1。在另一實施例中,亦可採用不同顯影速度之光阻液來分別形成光阻層210和第二圖案化光阻層2073,則此時,則不限制光阻層210之厚度要小於第二圖案化光阻層2073。
接著,如第12圖所示,於光阻層2074以及金屬層209上形成一接觸洞(contact hole,CH)層212以及進行源極區2091和汲極區2092之歐姆接觸(ohmic contact)2095和2096製作,其中接觸洞層是做為保護層用,一般是使用化學氣相沉積法沉積一層氮化矽(SiNx)層作為接觸洞層212,由於在進行接觸洞層212以及歐姆接觸製作之過程中會牽涉到氫摻雜(H-doping),藉由光阻層2074覆蓋於作為通道區2074之金屬氧化物層208之上,可避免此部分之金屬氧化物層208因為氫摻雜而轉變為導體,而破壞電晶體之電性。接著,如第13圖所示,圖案化此接觸洞層212以露出源極區2091和汲極區2092區域,並沉積一作為畫素電極和導電電極之透明金屬層213,此金屬層之材料,例如為氧化鋅摻雜銦(Indium Zinc Oxide,IZO)或銦錫氧化物(Indium Tin Oxide,ITO)之透明導電薄膜。最後,可圖案化金屬層213來完成後續之導線連接結構和畫素電極之製作。
綜合上述所言,本發明利用一灰階光罩在金屬氧化物
層上形成厚度不一之光阻層,其中作為通道區之金屬氧化物層上具有最厚之光阻層,藉以於其後進行金屬層濕式蝕刻製程時作為保護層,以避免通道區之金屬氧化物層被蝕刻而造成斷線問題;以及於金屬氧化物層上沉積接觸洞層時作為停止層,避免沉積過程中所使用之氫摻雜造成通道區之金屬氧化物層轉變為導體,進而提升氧化物薄膜電晶體的品質與製程良率。雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧金屬氧化物薄膜電晶體結構
101‧‧‧基板
102‧‧‧閘極
103‧‧‧半導體絕緣層
104‧‧‧金屬氧化物層
105‧‧‧源極
106‧‧‧汲極
20‧‧‧氧化物薄膜電晶體結構
200‧‧‧基板
201‧‧‧閘極
202‧‧‧半導體絕緣層
203、208‧‧‧金屬氧化物層
204、210、2071、2072‧‧‧光阻層
207‧‧‧第一圖案化光阻層
2073‧‧‧第二圖案化光阻層
211‧‧‧第三圖案化光阻層
2074‧‧‧第四圖案化光阻層
205‧‧‧灰階光罩
2051,2052、2053‧‧‧光罩區域
206‧‧‧光源
209‧‧‧金屬層
2091‧‧‧源極區
2092‧‧‧汲極區
2093‧‧‧通道區
2095、2096‧‧‧歐姆接觸
212‧‧‧接觸洞層
213‧‧‧透明金屬層
H1‧‧‧第一厚度
H2‧‧‧第二厚度
H3‧‧‧第三厚度
H4‧‧‧第四厚度
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:第1圖繪示習知金屬氧化物薄膜電晶體結構的剖面示意圖。
第2圖至第13圖繪示本發明之一較佳實施例之金屬氧化物薄膜電晶體之製作方法示意圖。
20‧‧‧氧化物薄膜電晶體結構
200‧‧‧基板
201‧‧‧閘極
202‧‧‧半導體絕緣層
208‧‧‧金屬氧化物層
2074‧‧‧第四圖案化光阻層
209‧‧‧金屬層
2091‧‧‧源極區
2092‧‧‧汲極區
2095、2096‧‧‧歐姆接觸
212‧‧‧接觸洞層
213‧‧‧透明金屬層
Claims (9)
- 一種製作氧化物薄膜電晶體之方法,包含:提供一基板;形成一閘極於該基板上;形成一半導體絕緣層於該閘極上;形成一金屬氧化物層於該半導體絕緣層上;形成一第一圖案化光阻層於該金屬氧化物層上,其中係利用一灰階光罩形成該第一圖案化光阻層;利用該第一圖案化光阻層為罩幕蝕刻該金屬氧化物層來形成一圖案化金屬氧化物層;移除部份該第一圖案化光阻層來形成一第二圖案化光阻層;形成一金屬層於該半導體絕緣層、該圖案化金屬氧化物層以及該第二圖案化光阻層上;形成一第三圖案化光阻層於該金屬層上;以該第三圖案化光阻層罩幕,對該金屬層進行蝕刻以形成一源極區與一汲極區,並暴露出該第二圖案化光阻層;以及移除該第三圖案化光阻層以及部份該第二圖案化光阻層來形成一第四圖案化光阻層。
- 如申請範圍第1項所述之製作氧化物薄膜電晶體之 方法,更包括:形成一接觸洞層於該金屬層以及該第四圖案化光阻層上,以及於該源極區和該汲極區形成一歐姆接觸。
- 如申請範圍第1項所述之製作氧化物薄膜電晶體之方法,其中該第一圖案化光阻層具有一第一厚度以及一第二厚度,其中該第一厚度大於該第二厚度。
- 如申請範圍第3項所述之製作氧化物薄膜電晶體之方法,其中該金屬氧化物層對應該第一厚度之位置作為一通道區,該金屬氧化物層對應該第二厚度之位置作為該源極區與該汲極區。
- 如申請範圍第3項所述之製作氧化物薄膜電晶體之方法,其中移除部份該第一圖案化光阻層來形成該第二圖案化光阻層,更包括將該第一圖案化光阻移除該第二厚度,來形成一具有一第三厚度之該第二圖案化光阻層,其中該第三厚度大於該第二厚度,該金屬氧化物層對應該第三厚度之位置作為一通道區。
- 如申請範圍第5項所述之製作氧化物薄膜電晶體之方法,其中該第一厚度、該第二厚度以及該第三厚度間具有3:1:2之厚度比值。
- 如申請範圍第6項所述之製作氧化物薄膜電晶體之方法,其中該第四圖案化光阻層具有一第四厚度,該金屬氧化物層對應該第四厚度之位置作為該通道區。
- 如申請範圍第7項所述之製作氧化物薄膜電晶體之方法,其中該第一厚度、該第三厚度和該第四厚度之比值約為3:2:1。
- 如申請範圍第1項所述之製作氧化物薄膜電晶體之方法,其中對該金屬層進行蝕刻是使用一濕式蝕刻法對該金屬層進行蝕刻。
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