TWI470328B - Display panel - Google Patents
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Description
本發明是有關於一種顯示裝置，特別是有關於一種顯示面板。The present invention relates to a display device, and more particularly to a display panel.
隨著顯示技術的發展，顯示面板已廣泛應用在各種不同的領域，諸如手機、平板電腦或數位相機等各式電子產品。With the development of display technology, display panels have been widely used in various fields, such as mobile phones, tablets or digital cameras.
在傳統做法中，顯示面板上具有一掃描驅動晶片及一資料驅動晶片，分別配置在主動區的兩側，且分別佈線進入主動區以提供訊號給彼此垂直正交的掃描線與資料線。但這樣的作法使得主動區之周圍必須有足夠的空間配置掃描、資料驅動晶片及佈線。在當今的電子產品逐漸朝向輕薄短小的趨勢之下，傳統做法對於實現一窄邊框的顯示面板而言殊為不利。In the conventional method, the display panel has a scan driving chip and a data driving chip respectively disposed on both sides of the active area, and respectively wired into the active area to provide signals to the scan lines and data lines orthogonal to each other. However, such an approach requires sufficient space around the active area to be configured for scanning, data-driven wafers, and wiring. Under the trend that today's electronic products are gradually becoming lighter and shorter, the conventional practice is disadvantageous for realizing a narrow-frame display panel.
是以，為了追求顯示面板更廣泛的應用，以上問題有必要提出解決方法。Therefore, in order to pursue a wider application of the display panel, it is necessary to propose a solution to the above problems.
本發明之一態樣是在提供一種顯示面板。依據本發明之一實施例，顯示面板包括基板、複數條第一訊號線、複數條第二訊號線、複數個畫素單元、複數條傳遞線以及驅動晶片。基板具有一主動區包含複數個畫素區塊。第一 訊號線平行配置於基板上。第二訊號線平行配置於該基板上，與第一訊號線彼此交錯以界定畫素區塊，且第二訊號線的數量大於第一訊號線的數量。畫素單元，分別配置於畫素區塊內，並分別與第一、第二訊號線連接。傳遞線平行配置於該基板上，分別與該些第二訊號線連接，橫越該主動區的相對兩側，並平行於該些第一訊號線。驅動晶片包括第一腳位第二腳位以及驅動電路。第一腳位連接第一訊號線。連結傳遞線。驅動電路用以分別產生第一訊號以及第二訊號給第一腳位以及第二腳位。其中第一腳位與第二腳位交互且平均配置，使與其連接的第一訊號線和傳遞線不彼此重疊，且使傳遞線平均配置在基板上。One aspect of the present invention is to provide a display panel. According to an embodiment of the invention, the display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of transfer lines, and a driving wafer. The substrate has an active area including a plurality of pixel blocks. the first The signal lines are arranged in parallel on the substrate. The second signal lines are arranged in parallel on the substrate, and the first signal lines are interlaced with each other to define a pixel block, and the number of the second signal lines is greater than the number of the first signal lines. The pixel units are respectively disposed in the pixel block and are respectively connected to the first and second signal lines. The transmission lines are arranged in parallel on the substrate, and are respectively connected to the second signal lines, and traverse the opposite sides of the active area and parallel to the first signal lines. The driving chip includes a first pin second pin and a driving circuit. The first pin is connected to the first signal line. Link the transfer line. The driving circuit is configured to generate the first signal and the second signal to the first pin and the second pin, respectively. The first pin and the second pin interact and are evenly arranged such that the first signal line and the transfer line connected thereto do not overlap each other, and the transfer line is evenly disposed on the substrate.
依據本發明之一實施例，顯示面板更包括複數條偽傳遞線。偽傳遞線平均配置於基板上，與傳遞線平行並橫越主動區的相對兩側，其中傳遞線區分為第一傳遞線以及第二傳遞線，畫素區塊中每一者其上所通過的該些第一傳遞線數量均相同，且畫素區塊的每一者被第二傳遞線之一者通過或被偽傳遞線之一者通過。According to an embodiment of the invention, the display panel further includes a plurality of pseudo transfer lines. The pseudo transfer lines are evenly disposed on the substrate, parallel to the transfer line and traversing opposite sides of the active area, wherein the transfer line is divided into a first transfer line and a second transfer line, and each of the pixel blocks passes thereon The number of the first transfer lines is the same, and each of the pixel blocks is passed by one of the second transfer lines or passed by one of the pseudo transfer lines.
依據本發明之一實施例，顯示面板更包括共電極以及控制電路。共電極配置於基板上且位於主動區周圍，用以連接偽傳遞線。控制電路連接共電極與驅動晶片，用以提供共電極一關閉電位，並驅動驅動晶片。According to an embodiment of the invention, the display panel further includes a common electrode and a control circuit. The common electrode is disposed on the substrate and located around the active region for connecting the dummy transfer line. The control circuit connects the common electrode and the driving wafer to provide a common electrode-off potential and drive the driving wafer.
依據本發明之一實施例，其中偽傳遞線、第一傳遞線、第二傳遞線以及第一訊號線在基板上的正投影皆不重疊。According to an embodiment of the invention, the front projections of the dummy transmission line, the first transmission line, the second transmission line and the first signal line on the substrate do not overlap.
依據本發明之一實施例，其中位於偽傳遞線中的相鄰兩條間且未被偽傳遞線通過的畫素區塊定義為複數個中央 區域，每個中央區域中的畫素區塊數量彼此相同。According to an embodiment of the present invention, a pixel block located between adjacent two of the pseudo transfer lines and not passed by the pseudo transfer line is defined as a plurality of central blocks Area, the number of pixel blocks in each central area is the same as each other.
依據本發明之一實施例，位於偽傳遞線中最接近於第一邊界的偽傳遞線和第一邊界之間且未被偽傳遞線通過的畫素區塊定義為一第一邊界區域。位於偽傳遞線中最接近於第二邊界的偽傳遞線和第二邊界之間且未被偽傳遞線通過的畫素區塊定義為第二邊界區域。其中第一、第二邊界為主動區的相對兩邊界，第一邊界區域和第二邊界區域的畫素區塊數量相同。According to an embodiment of the present invention, a pixel block located between the pseudo transfer line closest to the first boundary and the first boundary in the pseudo transfer line and not passed by the dummy transfer line is defined as a first boundary region. A pixel block located between the pseudo transfer line closest to the second boundary and the second boundary in the pseudo transfer line and not passed by the pseudo transfer line is defined as the second boundary area. The first and second boundaries are opposite boundaries of the active area, and the number of pixel blocks of the first boundary area and the second boundary area are the same.
依據本發明之一實施例，其中位於偽傳遞線中最接近於第一邊界的偽傳遞線和第一邊界之間且未被偽傳遞線通過的畫素區塊定義為第一邊界區域。位於偽傳遞線中最接近於第二邊界的偽傳遞線和第二邊界之間且未被偽傳遞線通過的畫素區塊定義為第二邊界區域。其中第一、第二邊界為主動區的相對兩邊界。第一邊界區域和每一個中央區域的畫素區塊數量均相同，和第二邊界區域的畫素區塊數量不同。According to an embodiment of the present invention, a pixel block located between the pseudo transfer line closest to the first boundary and the first boundary in the pseudo transfer line and not passed by the dummy transfer line is defined as the first boundary region. A pixel block located between the pseudo transfer line closest to the second boundary and the second boundary in the pseudo transfer line and not passed by the pseudo transfer line is defined as the second boundary area. The first and second boundaries are the opposite boundaries of the active area. The number of pixel blocks in the first boundary region and each of the central regions is the same, and the number of pixel blocks in the second boundary region is different.
依據本發明之一實施例，其中位於第二傳遞線中的相鄰兩條間且未被第二傳遞線通過的畫素區塊定義為複數個中央區域，每個中央區域中的畫素區塊數量彼此相同。According to an embodiment of the present invention, a pixel block located between adjacent two of the second transfer lines and not passed by the second transfer line is defined as a plurality of central regions, each of which is a pixel region The number of blocks is the same as each other.
依據本發明之一實施例，位於第二傳遞線中最接近於第一邊界的第二傳遞線和第一邊界之間且未被第二傳遞線通過的畫素區塊定義為第一邊界區域。位於第二傳遞線中最接近於一第二邊界的第二傳遞線和第二邊界之間且未被第二傳遞線通過的畫素區塊定義為第二邊界區域。其中第一、第二邊界為主動區的相對兩邊界。第一邊界區域和第 二邊界區域的畫素區塊數量相同。According to an embodiment of the present invention, a pixel block located between the second transfer line closest to the first boundary and the first boundary in the second transfer line and not passed by the second transfer line is defined as the first boundary region . A pixel block located between the second transfer line and the second boundary closest to a second boundary in the second transfer line and not passed by the second transfer line is defined as a second boundary region. The first and second boundaries are the opposite boundaries of the active area. First boundary area and The number of pixel blocks in the two boundary regions is the same.
依據本發明之一實施例，位於第二傳遞線中最接近於第一邊界的第二傳遞線和第一邊界之間且未被第二傳遞線通過的畫素區塊定義為第一邊界區域。位於第二傳遞線中最接近於第二邊界的第二傳遞線和第二邊界之間且未被第二傳遞線通過的畫素區塊定義為第二邊界區域。其中第一、第二邊界為主動區的相對兩邊界。第一邊界區域和每一個中央區域的畫素區塊數量均相同，和第二邊界區域的畫素區塊數量不同。According to an embodiment of the present invention, a pixel block located between the second transfer line closest to the first boundary and the first boundary in the second transfer line and not passed by the second transfer line is defined as the first boundary region . A pixel block located between the second transfer line closest to the second boundary and the second boundary in the second transfer line and not passed by the second transfer line is defined as the second boundary region. The first and second boundaries are the opposite boundaries of the active area. The number of pixel blocks in the first boundary region and each of the central regions is the same, and the number of pixel blocks in the second boundary region is different.
是以，藉由應用上述實施例，可使得實現一窄邊框的顯示面板。其中利用傳遞線傳遞第二訊號可取代傳統做法以縮小邊框。利用交互且平均地配置驅動晶片的腳位，可使第一訊號線和傳遞線彼此皆無重疊，而可避免產生線路間的雜散電容及避免電容耦合效應。另外也可透過配置上的設計，使偽傳遞線、第一傳遞線、以及第二傳遞線以及第一訊號線在基板上的正投影皆不重疊，而避免傳遞線間的寄生電容。除此之外，更可透過偽傳遞線與第二傳遞線的平均配置，使顯示面板的畫面負載平均，而提高畫面的品質。Therefore, by applying the above embodiment, it is possible to realize a display panel having a narrow bezel. The use of a transfer line to transmit a second signal can replace the traditional approach to narrow the border. By alternately and evenly arranging the pins of the driving chip, the first signal line and the transmission line can be made to overlap each other, and stray capacitance between the lines can be avoided and the capacitive coupling effect can be avoided. In addition, through the configuration, the pseudo transfer line, the first transfer line, and the second transfer line and the front projection of the first signal line on the substrate are not overlapped, and the parasitic capacitance between the lines is avoided. In addition, the average configuration of the pseudo transfer line and the second transfer line can increase the picture load on the display panel to improve the picture quality.
以下將以圖式及詳細敘述清楚說明本揭示內容之精神，任何所屬技術領域中具有通常知識者在瞭解本揭示內容之較佳實施例後，當可由本揭示內容所教示之技術，加以改變及修飾，其並不脫離本揭示內容之精神與範圍。The spirit and scope of the present disclosure will be apparent from the following description of the preferred embodiments of the present disclosure. Modifications do not depart from the spirit and scope of the disclosure.
第1圖為依據本發明一實施例中顯示面板100所繪的示意圖。顯示面板100包括基板110、複數條第一訊號線120、複數條第二訊號線122、複數個畫素單元130、複數條傳遞線140、142以及驅動晶片150。值得注意的是，上述第一訊號線120、第二訊號線122可分別為資料線和掃描線，當第一訊號線120為資料線時，第二訊號線122則為掃描線，反之亦然。FIG. 1 is a schematic view of a display panel 100 according to an embodiment of the invention. The display panel 100 includes a substrate 110, a plurality of first signal lines 120, a plurality of second signal lines 122, a plurality of pixel units 130, a plurality of transfer lines 140, 142, and a driving wafer 150. It should be noted that the first signal line 120 and the second signal line 122 are respectively a data line and a scan line. When the first signal line 120 is a data line, the second signal line 122 is a scan line, and vice versa. .
在結構上，基板110具有一主動區112包含複數個畫素區塊114。第一訊號線120平行配置於基板110上。第二訊號線122平行配置於基板110上，與第一訊號線120彼此交錯以界定畫素區塊114，且第二訊號線122的數量大於第一訊號線120的數量。畫素單元130分別配置於畫素區塊114內，並分別與第一、第二訊號線120、122連接。畫素單元130可包括開關(可為薄膜電晶體)、儲存電容與畫素電極，當開關被掃描線導通時，儲存電容可被資料線上的資料電位充電，且在開關關閉後繼續提供資料電位給畫素電極。傳遞線140、142平行配置於基板110上，橫越該主動區112的相對兩側，並平行於該些第一訊號線120。驅動晶片150包括第一腳位152、第二腳位154以及驅動電路156。第一腳位152連接第一訊號線120。第二腳位154連接傳遞線140、142。驅動電路156用以分別產生第一訊號以及第二訊號給第一腳位152以及第二腳位154。其中第一腳位152與第二腳位154交互且平均配置，使與其連接的第一訊號線120和傳遞線140、142皆不彼此交叉重疊，且使傳遞線140、142平均配置在基板110上。值得 注意的是，傳遞線140、142可以穿孔或連接栓塞方式與第二訊號線122連接。此外，此處的第一、第二訊號可分別為資料訊號和掃描訊號，其可用不同電位來表示。舉例而言，資料訊號可為-15V、0V、+15V，其可分別代表三個不同程度的灰階，而掃描訊號可為-20V和+22V，其可分別控制一排畫素單元130的開關(未繪示)導通或斷路。Structurally, substrate 110 has an active region 112 that includes a plurality of pixel blocks 114. The first signal lines 120 are arranged in parallel on the substrate 110. The second signal lines 122 are disposed on the substrate 110 in parallel, and the first signal lines 120 are interleaved with each other to define the pixel block 114, and the number of the second signal lines 122 is greater than the number of the first signal lines 120. The pixel units 130 are respectively disposed in the pixel block 114 and are respectively connected to the first and second signal lines 120 and 122. The pixel unit 130 may include a switch (which may be a thin film transistor), a storage capacitor and a pixel electrode. When the switch is turned on by the scan line, the storage capacitor may be charged by the data potential on the data line, and the data potential is continuously supplied after the switch is turned off. Give the pixel electrode. The transmission lines 140 and 142 are disposed on the substrate 110 in parallel, and traverse the opposite sides of the active region 112 and parallel to the first signal lines 120. The driver wafer 150 includes a first pin 152, a second pin 154, and a drive circuit 156. The first pin 152 is connected to the first signal line 120. The second leg 154 connects the transfer lines 140, 142. The driving circuit 156 is configured to generate the first signal and the second signal to the first pin 152 and the second pin 154, respectively. The first pin 152 and the second pin 154 are alternately arranged, and the first signal line 120 and the transmission lines 140 and 142 connected thereto are not overlapped with each other, and the transfer lines 140 and 142 are evenly disposed on the substrate 110. on. worth it It is noted that the transfer lines 140, 142 may be connected to the second signal line 122 by means of a perforation or a connection plug. In addition, the first and second signals herein may be data signals and scanning signals, respectively, which may be represented by different potentials. For example, the data signals can be -15V, 0V, +15V, which can represent three different levels of gray scale, respectively, and the scan signals can be -20V and +22V, which can respectively control a row of pixel units 130. The switch (not shown) is turned on or off.
在本實施例中，驅動晶片150可為一個可調整式驅動晶片，其可以透過以驅動電路156給予一特定腳位不同訊號的方式，決定此特定腳位作為第一腳位152或第二腳位154。舉例而言，當驅動晶片150透過驅動電路156給予一特定腳位-20V或+22V的掃描訊號時，此特定腳位即可為掃描腳位而連接掃描線。換句話說，驅動晶片150可用驅動電路156給予任何一個腳位不同電位，使此腳位能視硬體實際需要而連接掃描線或資料線。舉例而言，可給予五種不同電位，也就是-15V、0V、+15V、-20V、+22V。下表為說明驅動晶片150腳位配置的進一步例示。In this embodiment, the driving chip 150 can be an adjustable driving chip, and the specific pin can be determined as the first pin 152 or the second pin by the driving circuit 156 giving a specific signal to a specific pin. Bit 154. For example, when the driving chip 150 is given a scan signal of a specific pin -20V or +22V through the driving circuit 156, the specific pin can be connected to the scan line for the scan pin. In other words, the driving chip 150 can be given a different potential to any of the pins by the driving circuit 156, so that the pin can be connected to the scan line or the data line according to the actual needs of the hardware. For example, five different potentials can be given, namely -15V, 0V, +15V, -20V, +22V. The following table is a further illustration of the configuration of the driver chip 150 pin.
在上表中，G可代表掃描腳位，S可代表資料腳位。若顯示面板100之比例為10x8時，腳位1可為掃描腳位、腳位2可為資料腳位，以此類推。In the above table, G can represent the scan pin, and S can represent the data pin. If the ratio of the display panel 100 is 10x8, the pin 1 can be the scan pin, the pin 2 can be the data pin, and so on.
是以，利用驅動晶片150可視實際需要而決定特定腳位為資料腳位或掃描腳位的特性，可讓第一腳位152與第二腳位154交互且平均配置，而使第一訊號線120、傳遞線140、142皆不彼此交叉重疊，且使傳遞線140、142平均配置在基板110上。Therefore, by using the driving chip 150 to determine the specific pin position as the data pin or the scan pin according to actual needs, the first pin 152 and the second pin 154 can be alternately and evenly configured, and the first signal line is configured. 120. The transfer lines 140, 142 do not overlap each other, and the transfer lines 140, 142 are evenly disposed on the substrate 110.
藉由上述傳遞線140、142的配置可縮小顯示面板100的邊框，而藉由驅動晶片150的腳位配置，一方面可使傳遞線140、142皆不彼此交叉重疊，而避免產生雜散電容以及電容耦合效應，而另一方面可使傳遞線140、142皆平均配置在基板110上，以避免主動區112負載不平衡，而導致的亮暗不均問題。The layout of the transmission lines 140 and 142 can reduce the frame of the display panel 100. By driving the pin configuration of the wafer 150, the transfer lines 140 and 142 can be overlapped with each other to avoid stray capacitance. As well as the capacitive coupling effect, on the other hand, the transfer lines 140, 142 can be evenly disposed on the substrate 110 to avoid the imbalance of the active region 112, resulting in uneven brightness and darkness.
然而儘管傳遞線140、142的平均配置，仍會使得不同畫素區塊114上所通過的傳遞線數量140、142不同，而導致主動區112負載不平衡。是以，在其它實施例中更可以透過設置偽傳遞線160的方式解決此問題。However, despite the average configuration of the transfer lines 140, 142, the number of transfer lines 140, 142 passing through the different pixel blocks 114 will be different, resulting in an unbalanced load on the active area 112. Therefore, in other embodiments, the problem can be solved by setting the pseudo transfer line 160.
在本發明的一實施例中，顯示面板100更包括複數條偽傳遞線160。偽傳遞線160平行且平均地配置於基板110上，與傳遞線140，142平行並橫越主動區112的相對兩側。在本實施例中，傳遞線140、142可進一步區分為第一傳遞線140以及第二傳遞線142，而每一個畫素區塊114中所通過的第一傳遞線140數量均相同，且每一個畫素區塊114被一條第二傳遞線142通過或被一條偽傳遞線160通過。換句話說，第一傳遞線140以相同數量配置於每一行畫素區塊114上，而第二傳遞線142的數量不足以配置在每一行畫素區塊114，是以在沒有配置第二傳遞線142的畫素 區塊114上，可配置偽傳遞線160，以避免主動區112負載不平衡導致的畫面亮度不均。In an embodiment of the invention, the display panel 100 further includes a plurality of pseudo transfer lines 160. The dummy transfer lines 160 are disposed in parallel and evenly on the substrate 110, parallel to the transfer lines 140, 142 and traversing opposite sides of the active region 112. In this embodiment, the transfer lines 140, 142 can be further divided into a first transfer line 140 and a second transfer line 142, and the number of the first transfer lines 140 passing through each of the pixel blocks 114 is the same, and each A pixel block 114 is passed by a second transfer line 142 or by a pseudo transfer line 160. In other words, the first transfer lines 140 are arranged in the same number on each row of pixel blocks 114, and the number of second transfer lines 142 is insufficient to be arranged in each row of pixel blocks 114, so that no second configuration is provided. The pixel of the transfer line 142 On the block 114, the dummy transfer line 160 can be configured to avoid uneven brightness of the picture caused by the load imbalance of the active area 112.
在本發明的一實施例中，顯示面板100更包括共電極170以及控制電路180。共電極170配置於基板110上且位於主動區112周圍，用以連接所有偽傳遞線160。控制電路180連接共電極170與驅動晶片150，用以提供共電極170一關閉電位，並驅動驅動晶片150。值得注意的是，控制電路180可以硬體電路或軟體，或部份硬體部份軟體以實現。另外，關閉電位可為掃描訊號中使畫素單元130的開關斷路的電位，舉例而言，可為-20V。In an embodiment of the invention, the display panel 100 further includes a common electrode 170 and a control circuit 180. The common electrode 170 is disposed on the substrate 110 and located around the active region 112 for connecting all the dummy transmission lines 160. The control circuit 180 connects the common electrode 170 and the driving wafer 150 to provide a common potential of the common electrode 170 and drive the driving wafer 150. It should be noted that the control circuit 180 can be implemented by a hardware circuit or a software body, or a part of a hardware part. In addition, the turn-off potential may be the potential of the scan signal to open the switch of the pixel unit 130, for example, -20V.
透過上述給予所有偽傳遞線160關閉電位的做法，可使偽傳遞線160形同被給予關閉電位的第一、第二傳遞線140、142，而能顯示面板100負衡平衡且畫面亮度平均。另外透過使所有偽傳遞線160連接到共電極170的配置，可節省驅動晶片150的腳位，而可降低驅動晶片150的成本及複雜度。By turning off the potentials of all the pseudo transfer lines 160 as described above, the pseudo transfer lines 160 can be given the first and second transfer lines 140, 142 that are turned off, and the display panel 100 can be balanced and the screen brightness is averaged. In addition, by configuring all of the dummy transfer lines 160 to be connected to the common electrode 170, the pins of the drive wafer 150 can be saved, and the cost and complexity of driving the wafers 150 can be reduced.
第2圖為依據本發明一實施例中第1圖之顯示面板沿線段2-2的剖面示意圖。其中偽傳遞線160在基板110上的正投影P1、第一傳遞線140在基板110上的正投影P2、第二傳遞線142在基板110上的正投影P3以及第一訊號線120在基板110上的正投影P4皆不重疊。如此設置可避免產生寄生電容以及電容耦合效應。值得注意的是，第2圖僅為例示，第一訊號線120、第一傳遞線140、第二傳遞線142以及偽傳遞線160可視實際需求配置於不同的電路層，並不以第2圖所繪為限。2 is a cross-sectional view of the display panel of FIG. 1 along line 2-2 in accordance with an embodiment of the present invention. The orthographic projection P1 of the pseudo transmission line 160 on the substrate 110, the orthographic projection P2 of the first transmission line 140 on the substrate 110, the orthographic projection P3 of the second transmission line 142 on the substrate 110, and the first signal line 120 are on the substrate 110. The orthographic projections P4 on the top do not overlap. This setting avoids parasitic capacitance and capacitive coupling effects. It should be noted that the second diagram is only an example. The first signal line 120, the first transmission line 140, the second transmission line 142, and the pseudo transmission line 160 may be disposed on different circuit layers according to actual requirements, and are not shown in FIG. It is drawn as a limit.
在本發明的實施例中，由於第二傳遞線142會傳送第二訊號，而偽傳遞線160不會，是以為避免主動區112負載不平衡而導致畫面不均，需使第二傳遞線142及偽傳遞線160平均配置於主動區112上。而為使平均配置的精神能進一步被了解，以下藉由第3圖至第6圖所表示的不同實施例以具體說明之。In the embodiment of the present invention, since the second transmission line 142 transmits the second signal, and the pseudo transmission line 160 does not, in order to avoid the image unevenness caused by the load imbalance of the active area 112, the second transmission line 142 is required. The dummy transfer lines 160 are evenly disposed on the active area 112. In order to further understand the spirit of the average configuration, the following description will be specifically made by the different embodiments shown in FIGS. 3 to 6.
第3圖為依據本發明一實施例中平均配置第二傳遞線142與偽傳遞線160的示意圖。如第3圖所示，主動區112由15x9的畫素區塊114以矩陣方式組合而成。主動區112具有第一邊界320與第二邊界330，且第一、第二邊界320、330彼此相對，並平行於偽傳遞線160。在本實施例中，對應到畫素區塊114的行數，是以第一傳遞線140共九條，連接部份第二訊號線122，而第二傳遞線142連結剩下第二訊號線122，共需六條。偽傳遞線160可配置於第2、第5、第8行畫素區塊114上，而相對地第二傳遞線142可配置於第1、第3、第4、第6、第7、第9行畫素區塊114上。如此地平均配置第二傳遞線142與偽傳遞線160，即可避免主動區112負載不平衡。FIG. 3 is a schematic diagram showing the second transfer line 142 and the dummy transfer line 160 being evenly arranged in accordance with an embodiment of the present invention. As shown in FIG. 3, the active area 112 is formed by a matrix combination of 15x9 pixel blocks 114. The active region 112 has a first boundary 320 and a second boundary 330, and the first and second boundaries 320, 330 are opposite each other and parallel to the dummy transfer line 160. In this embodiment, the number of rows corresponding to the pixel block 114 is nine lines of the first transmission line 140, and the second signal line 122 is connected, and the second transmission line 142 is connected to the second signal line. 122, a total of six. The pseudo transmission line 160 can be disposed on the second, fifth, and eighth rows of the pixel block 114, and the second transmission line 142 can be disposed on the first, third, fourth, sixth, seventh, and 9 rows of pixels on block 114. By arranging the second transfer line 142 and the dummy transfer line 160 on average, the load imbalance of the active region 112 can be avoided.
若定義位於相鄰兩條偽傳遞線160間且未被偽傳遞線160通過的畫素區塊114為中央區域310。則如此地平均配置第二傳遞線142與偽傳遞線160可使每個中央區域310中的畫素區塊114數量彼此相同。在本實施例中，每個中央區域310中的畫素區塊114均為三十個。使中央區域310中的畫素區塊114數量彼此相同，其功用在於避免主動區112的每個中央區域310負載不平衡，否則亮暗不均的情 況將極為明顯。If the pixel block 114 located between the adjacent two pseudo transfer lines 160 and not passed by the pseudo transfer line 160 is defined as the central area 310. Then, arranging the second transfer line 142 and the dummy transfer line 160 on average so that the number of the pixel blocks 114 in each of the central regions 310 is identical to each other. In this embodiment, the pixel blocks 114 in each central region 310 are thirty. The number of pixel blocks 114 in the central area 310 is made equal to each other, and the function thereof is to prevent the load imbalance of each central area 310 of the active area 112, otherwise the brightness and darkness are uneven. The situation will be extremely obvious.
若定義位於最接近於第一邊界320的偽傳遞線160和第一邊界320之間且未被偽傳遞線160通過的畫素區塊114為第一邊界區域322，且定義位於最接近於第二邊界330的偽傳遞線160和第二邊界330之間且未被偽傳遞線160通過的畫素區塊114為第二邊界區域332。則如此地平均配置第二傳遞線142與偽傳遞線160，可使第一邊界區域322和第二邊界區域332中的畫素區塊114數量彼此相同。在本實施例中，第一、第二邊界區域322、332中的畫素區塊114均為十五個。應注意到，雖然第一、第二邊界區域322、332與中央區域310的畫素區塊114數量不同，但由於邊界區域322、332的亮暗不均不易為人眼察覺，是以不易造成明顯的影響。另外，值得注意的是，在其它實施當中第一、第二邊界區域322、332與中央區域310的畫素區塊114數量也可為相同。If the pixel block 114 that is located between the pseudo transfer line 160 and the first boundary 320 that is closest to the first boundary 320 and is not passed by the dummy transfer line 160 is defined as the first boundary region 322, and the definition is located closest to the first The pixel block 114 between the pseudo transfer line 160 and the second boundary 330 of the second boundary 330 and not passed by the pseudo transfer line 160 is the second boundary area 332. Then, the second transfer line 142 and the dummy transfer line 160 are evenly arranged in such a manner that the number of the pixel blocks 114 in the first boundary region 322 and the second boundary region 332 can be identical to each other. In this embodiment, the pixel blocks 114 in the first and second boundary regions 322 and 332 are all fifteen. It should be noted that although the number of the pixel blocks 114 of the first and second boundary regions 322, 332 and the central region 310 is different, since the unevenness of the boundary regions 322, 332 is not easily perceived by the human eye, it is not easy to cause Obvious influence. In addition, it is noted that in other implementations, the number of pixel blocks 114 of the first and second boundary regions 322, 332 and the central region 310 may also be the same.
第4圖為依據本發明一實施例中平均配置第二傳遞線142與偽傳遞線160的示意圖。本實施例和前一實施例同為以15x9的畫素區塊114組成主動區112，故相同之處在此不贅述。主動區112具有第一邊界420與第二邊界430。本實施例中偽傳遞線160可配置於第3、第6、第9行畫素區塊114上，而相對地第二傳遞線142可配置於第1、第2、第4、第5、第7、第8行畫素區塊114上。4 is a schematic diagram showing the second transfer line 142 and the dummy transfer line 160 being evenly arranged in accordance with an embodiment of the present invention. The embodiment and the previous embodiment are the same as the active area 112 of the 15x9 pixel block 114, so the same points are not described herein. The active region 112 has a first boundary 420 and a second boundary 430. In this embodiment, the dummy transmission line 160 can be disposed on the third, sixth, and ninth rows of the pixel block 114, and the second transmission line 142 can be disposed on the first, second, fourth, and fifth sides. The 7th and 8th rows are on the pixel block 114.
若定義位於相鄰兩條偽傳遞線160間且未被偽傳遞線160通過的畫素區塊114為中央區域410，則在本實施例中每個中央區域410中的畫素區塊114均為三十個。If the pixel block 114 located between the adjacent two pseudo transfer lines 160 and not passed by the pseudo transfer line 160 is defined as the central area 410, the pixel blocks 114 in each central area 410 in this embodiment are all It is thirty.
若定義位於最接近於第一邊界420的偽傳遞線160和第一邊界420之間且未被偽傳遞線160通過的畫素區塊114為第一邊界區域422，且定義位於最接近於第二邊界430的偽傳遞線160和第二邊界430之間且未被偽傳遞線160通過的畫素區塊114為第二邊界區域432，則第一邊界區域422中的的畫素區塊114為三十個，第二邊界區域432的畫素區塊114為零個。值得注意的是，雖然在本實施例中第一邊界區域422和每一個中央區域410的畫素區塊數量均相同，而和第二邊界區域432的畫素區塊數量不同，但由於邊界區域432的亮暗不均不易為人眼察覺，是以不易造成明顯的影響。If the pixel block 114 that is located between the pseudo transfer line 160 and the first boundary 420 that is closest to the first boundary 420 and is not passed by the dummy transfer line 160 is defined as the first boundary region 422, and the definition is located closest to the first The pixel block 114 between the pseudo transfer line 160 and the second boundary 430 of the two boundary 430 and not passed by the pseudo transfer line 160 is the second boundary area 432, and the pixel block 114 in the first boundary area 422 For thirty, the pixel block 114 of the second boundary region 432 is zero. It should be noted that although the number of pixel blocks of the first boundary area 422 and each of the central areas 410 is the same in the present embodiment, and the number of pixel blocks of the second boundary area 432 is different, the boundary area is different. The unevenness of light and darkness of 432 is not easy to be perceived by the human eye, so it is not easy to cause obvious influence.
上述第3圖及第4圖中所示的實施例，為根據偽傳遞線160的配置劃分主動區112，而以下第5、第6圖中所示的實施例，將根據第二傳遞線142的配置劃分主動區112。The embodiments shown in the third and fourth figures described above divide the active area 112 according to the configuration of the dummy transfer line 160, and the embodiments shown in the fifth and sixth figures below will be based on the second transfer line 142. The configuration divides the active area 112.
第5圖為依據本發明一實施例中平均配置第二傳遞線142與偽傳遞線160的示意圖。如第5圖所示，主動區112由12x9的畫素區塊114以矩陣方式組合而成。主動區112具有第一邊界520與第二邊界530，且第一、第二邊界520、530彼此相對，並平行於偽傳遞線160。在本實施例中，對應到畫素區塊114的行數，是以第一傳遞線140共九條，連接部份第二訊號線122，而第二傳遞線142連結剩下第二訊號線122，共需三條。第二傳遞線142可配置於第2、第5、第8行畫素區塊114上，而相對地偽傳遞線160可配置於第1、第3、第4、第6、第7、第9行畫素區塊114上。如此地平均配置第二傳遞線142與偽傳遞線160，即 可避免主動區112負載不平衡。FIG. 5 is a schematic diagram showing the second transfer line 142 and the dummy transfer line 160 being evenly arranged in accordance with an embodiment of the present invention. As shown in FIG. 5, the active area 112 is formed by a combination of 12x9 pixel blocks 114 in a matrix. The active region 112 has a first boundary 520 and a second boundary 530, and the first and second boundaries 520, 530 are opposite each other and parallel to the dummy transfer line 160. In this embodiment, the number of rows corresponding to the pixel block 114 is nine lines of the first transmission line 140, and the second signal line 122 is connected, and the second transmission line 142 is connected to the second signal line. 122, a total of three. The second transfer line 142 can be disposed on the second, fifth, and eighth rows of the pixel block 114, and the opposite pseudo transfer line 160 can be disposed on the first, third, fourth, sixth, seventh, and 9 rows of pixels on block 114. The second transfer line 142 and the pseudo transfer line 160 are evenly arranged in such a manner that Active zone 112 load imbalance can be avoided.
若定義位於相鄰兩條第二傳遞線142間且未被第二傳遞線142通過的畫素區塊114為中央區域510。則每個中央區域510中的畫素區塊114數量彼此相同。在本實施例中，每個中央區域510中的畫素區塊114均為二十四個。使中央區域510中的畫素區塊114數量彼此相同，其功用在於避免主動區112的每個中央區域510負載不平衡，否則亮暗不均的情況將極為明顯。If the pixel block 114 located between the adjacent two second transfer lines 142 and not passed by the second transfer line 142 is defined as the central region 510. Then the number of pixel blocks 114 in each central region 510 is the same as each other. In the present embodiment, the pixel blocks 114 in each of the central regions 510 are twenty-four. The number of pixel blocks 114 in the central region 510 is made equal to each other, and its function is to prevent the load imbalance of each central region 510 of the active region 112, otherwise the situation of uneven brightness and darkness will be extremely obvious.
若定義位於最接近於第一邊界520的第二傳遞線142和第一邊界520之間且未被第二傳遞線142通過的畫素區塊114為第一邊界區域522，且定義位於最接近於第二邊界530的第二傳遞線142和第二邊界530之間且未被偽傳遞線160通過的畫素區塊114為第二邊界區域532。則如此配置，可使第一邊界區域522和第二邊界區域532中的畫素區塊114數量彼此相同。在本實施例中，第一、第二邊界區域522、532中的畫素區塊114均為十五個。應注意到，雖然第一、第二邊界區域522、532與中央區域510的畫素區塊114數量不同，但由於邊界區域522、532的亮暗不均不易為人眼察覺，是以不易造成明顯的影響。另外，值得注意的是，在其它實施當中第一、第二邊界區域522、532與中央區域510的畫素區塊114數量也可為相同。If the pixel block 114 defined between the second transfer line 142 and the first boundary 520 that is closest to the first boundary 520 and is not passed by the second transfer line 142 is defined as the first boundary region 522, and the definition is located closest to The pixel block 114 between the second transfer line 142 and the second boundary 530 of the second boundary 530 and not passed by the dummy transfer line 160 is the second boundary region 532. So configured, the number of pixel blocks 114 in the first boundary region 522 and the second boundary region 532 can be made identical to each other. In this embodiment, the pixel blocks 114 in the first and second boundary regions 522 and 532 are all fifteen. It should be noted that although the number of the pixel blocks 114 of the first and second boundary regions 522, 532 and the central region 510 is different, since the unevenness of the brightness of the boundary regions 522, 532 is not easily perceived by the human eye, it is not easy to cause Obvious influence. Additionally, it is worth noting that in other implementations the number of pixel blocks 114 of the first and second boundary regions 522, 532 and the central region 510 may also be the same.
第6圖為依據本發明一實施例中平均配置第二傳遞線142與偽傳遞線160的示意圖。本實施例和前一實施例同為以12x9的畫素區塊114組成主動區112，故相同之處在此不贅述。主動區112具有第一邊界620與第二邊界630。 本實施例中第二傳遞線142可配置於第3、第6、第9行畫素區塊114上，而相對地偽傳遞線160可配置於第1、第2、第4、第5、第7、第8行畫素區塊114上。FIG. 6 is a schematic diagram of the average arrangement of the second transfer line 142 and the dummy transfer line 160 in accordance with an embodiment of the present invention. The embodiment and the previous embodiment are the same as the active area 112 formed by the 12x9 pixel block 114, so the same points are not described herein. Active region 112 has a first boundary 620 and a second boundary 630. In this embodiment, the second transmission line 142 can be disposed on the third, sixth, and ninth rows of the pixel block 114, and the opposite pseudo transmission line 160 can be disposed on the first, second, fourth, and fifth, The 7th and 8th rows are on the pixel block 114.
若定義位於相鄰兩條第二傳遞線142間且未被偽傳遞線160通過的畫素區塊114為中央區域610，則在本實施例中每個中央區域610中的畫素區塊114均為二十四個。If the pixel block 114 located between the adjacent two second transfer lines 142 and not passed by the pseudo transfer line 160 is defined as the central region 610, the pixel block 114 in each central region 610 in this embodiment is used. All are twenty-four.
若定義位於最接近於第一邊界620的第二傳遞線142和第一邊界620之間且未被第二傳遞線142通過的畫素區塊114為第一邊界區域622，且定義位於最接近於第二邊界630的第二傳遞線142和第二邊界630之間且未被第二傳遞線142通過的畫素區塊114為第二邊界區域632，則第一邊界區域622中的的畫素區塊114為二十四個，第二邊界區域632的畫素區塊114為零個。值得注意的是，雖然在本實施例中第一邊界區域622和每一個中央區域610的畫素區塊114數量均相同，而和第二邊界區域632的畫素區塊114數量不同，但由於邊界區域632的亮暗不均不易為人眼察覺，是以不易造成明顯的影響。If the pixel block 114 defined between the second transfer line 142 and the first boundary 620 that is closest to the first boundary 620 and is not passed by the second transfer line 142 is defined as the first boundary region 622, and the definition is located closest to The pixel block 114 between the second transfer line 142 and the second boundary 630 of the second boundary 630 and not passed by the second transfer line 142 is the second boundary area 632, and the picture in the first boundary area 622 The prime block 114 is twenty-four, and the second boundary region 632 has zero pixel blocks 114. It should be noted that although the number of the pixel blocks 114 of the first boundary region 622 and each of the central regions 610 is the same in the present embodiment, and the number of the pixel blocks 114 of the second boundary region 632 is different, The unevenness of the brightness and darkness of the boundary area 632 is not easily perceived by the human eye, and is not easily caused to have a significant influence.
從上述第3、第4、第5、第6圖中所示的實施例應可明瞭，平均配置偽傳遞線160和第二傳遞線142的精神在於，使被偽傳遞線160或第二傳遞線142界定出的中央區域310、410、510、610的畫素區塊114數量均相同，而當畫素區塊114無法被傳遞線160和第二傳遞線142平均通過時，就使無法被傳遞線160和第二傳遞線142平均通過的畫素區塊114位於主動區112之邊界區域322、332、422、432、522、532、622、632中，如此主動區112縱有亮暗 不均之現象亦不易為人眼察覺。當須注意的是，以上所述的第3、第4、第5、第6圖中之實施例，僅在於述明平均配置偽傳遞線160和第二傳遞線142的精神，而非用以限制本發明。另外，同樣值得注意的是以上所述第一邊界320、420、520、620和第二邊界330、430、530、630僅為主動區112與偽傳遞線160平行之相對兩邊，並不限於第3、第4、第5、第6圖中所繪。It should be understood from the embodiments shown in the above third, fourth, fifth, and sixth figures that the spirit of arranging the pseudo transfer line 160 and the second transfer line 142 on average is to make the pseudo transfer line 160 or the second pass The number of pixel blocks 114 of the central regions 310, 410, 510, 610 defined by the line 142 are all the same, and when the pixel block 114 cannot be uniformly passed by the transfer line 160 and the second transfer line 142, it cannot be The pixel blocks 114 passing through the transfer line 160 and the second transfer line 142 are located in the boundary regions 322, 332, 422, 432, 522, 532, 622, 632 of the active region 112, such that the active region 112 is bright and dark. The phenomenon of unevenness is also not easy to detect by the human eye. It should be noted that the embodiments in the third, fourth, fifth, and sixth figures described above are merely illustrative of the spirit of the average configuration of the pseudo transfer line 160 and the second transfer line 142, rather than Limit the invention. In addition, it is also worth noting that the first boundary 320, 420, 520, 620 and the second boundary 330, 430, 530, 630 are only opposite sides of the active region 112 and the pseudo transmission line 160, and are not limited to the first 3. Drawings in Figures 4, 5, and 6.
綜上所述，應用本發明之實施例，可透過第一、第二傳遞線傳遞第二訊號，取代傳統的周圍配線做法，以縮小顯示面板的邊框。然而加入傳遞線，一方面會使線路交叉重疊，而產生雜散電容，另一方面將會導致主動區負載不平衡。因此，使驅動晶片第一、第二腳位交互且平均配置，可避免雜散電容產生的電容耦合效應，且可使第二傳遞線平均配置在主動區上。而後另外加入偽傳遞線，並且使偽傳遞線和第二傳遞線平均分配在主動區上，可避免主動區負載不平衡導致畫面亮度不均。此外，透過使線路在基板上的正投影不重疊，寄生電容產生可被避免。In summary, the embodiment of the present invention can transmit the second signal through the first and second transmission lines instead of the traditional surrounding wiring to reduce the frame of the display panel. However, adding a transfer line, on the one hand, causes the lines to overlap, resulting in stray capacitance, and on the other hand, the active area load imbalance. Therefore, the first and second pins of the driving chip are alternately and evenly arranged, the capacitive coupling effect generated by the stray capacitance can be avoided, and the second transfer line can be evenly arranged on the active region. Then, a pseudo transfer line is additionally added, and the pseudo transfer line and the second transfer line are evenly distributed on the active area, which can avoid unevenness of the screen brightness caused by the imbalance of the active area load. Furthermore, by making the orthographic projections of the lines on the substrate not overlap, parasitic capacitance generation can be avoided.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and retouched without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.
100‧‧‧顯示面板100‧‧‧ display panel
110‧‧‧基板110‧‧‧Substrate
112‧‧‧主動區112‧‧‧active area
114‧‧‧畫素區塊114‧‧‧ pixel block
120‧‧‧第一訊號線120‧‧‧First signal line
122‧‧‧第二訊號線122‧‧‧Second signal line
130‧‧‧畫素單元130‧‧‧ pixel unit
140‧‧‧第一傳遞線140‧‧‧First transfer line
142‧‧‧第二傳遞線142‧‧‧second transfer line
150‧‧‧驅動晶片150‧‧‧Drive chip
152‧‧‧第一腳位152‧‧‧First position
154‧‧‧第二腳位154‧‧‧second foot
156‧‧‧驅動電路156‧‧‧ drive circuit
160‧‧‧偽傳遞線160‧‧‧Pseudo-transmission line
170‧‧‧共電極170‧‧‧Common electrode
180‧‧‧控制電路180‧‧‧Control circuit
310‧‧‧中央區域310‧‧‧Central area
320‧‧‧第一邊界320‧‧‧ first border
322‧‧‧第一邊界區域322‧‧‧First border area
330‧‧‧第二邊界330‧‧‧ second border
332‧‧‧第二邊界區域332‧‧‧Second boundary area
410‧‧‧中央區域410‧‧‧Central area
420‧‧‧第一邊界420‧‧‧ first border
422‧‧‧第一邊界區域422‧‧‧First border area
430‧‧‧第二邊界430‧‧‧ second border
432‧‧‧第二邊界區域432‧‧‧Second boundary area
510‧‧‧中央區域510‧‧‧Central Area
520‧‧‧第一邊界520‧‧‧ first border
522‧‧‧第一邊界區域522‧‧‧First border area
530‧‧‧第二邊界530‧‧‧ second border
532‧‧‧第二邊界區域532‧‧‧Second boundary area
610‧‧‧中央區域610‧‧‧Central Area
620‧‧‧第一邊界620‧‧‧ first border
622‧‧‧第一邊界區域622‧‧‧First border area
630‧‧‧第二邊界630‧‧‧ second border
632‧‧‧第二邊界區域632‧‧‧Second boundary area
P1-P4‧‧‧正投影P1-P4‧‧‧ orthographic projection
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下： 第1圖為依據本發明一實施例中顯示面板所繪的示意圖。The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. 1 is a schematic view of a display panel according to an embodiment of the invention.
第2圖為依據本發明一實施例中第1圖之顯示面板沿線段2-2的剖面示意圖。2 is a cross-sectional view of the display panel of FIG. 1 along line 2-2 in accordance with an embodiment of the present invention.
第3圖為依據本發明一實施例中平均配置第二傳遞線與偽傳遞線的示意圖。FIG. 3 is a schematic diagram of arranging the second transfer line and the pseudo transfer line on average according to an embodiment of the invention.
第4圖為依據本發明一實施例中平均配置第二傳遞線與偽傳遞線的示意圖。4 is a schematic diagram of arranging an average of a second transfer line and a pseudo transfer line in accordance with an embodiment of the present invention.
第5圖為依據本發明一實施例中平均配置第二傳遞線與偽傳遞線的示意圖。FIG. 5 is a schematic diagram showing an average arrangement of a second transfer line and a pseudo transfer line in accordance with an embodiment of the present invention.
第6圖為依據本發明一實施例中平均配置第二傳遞線與偽傳遞線的示意圖。Figure 6 is a schematic diagram showing the arrangement of the second transfer line and the pseudo transfer line on average in accordance with an embodiment of the present invention.
100‧‧‧顯示面板100‧‧‧ display panel
110‧‧‧基板110‧‧‧Substrate
112‧‧‧主動區112‧‧‧active area
114‧‧‧畫素區塊114‧‧‧ pixel block
120‧‧‧第一訊號線120‧‧‧First signal line
122‧‧‧第二訊號線122‧‧‧Second signal line
130‧‧‧畫素單元130‧‧‧ pixel unit
140‧‧‧第一傳遞線140‧‧‧First transfer line
142‧‧‧第二傳遞線142‧‧‧second transfer line
150‧‧‧驅動晶片150‧‧‧Drive chip
152‧‧‧第一腳位152‧‧‧First position
154‧‧‧第二腳位154‧‧‧second foot
156‧‧‧驅動電路156‧‧‧ drive circuit
160‧‧‧偽傳遞線160‧‧‧Pseudo-transmission line
170‧‧‧共電極170‧‧‧Common electrode
180‧‧‧控制電路180‧‧‧Control circuit
Claims (10)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210380711.7A CN103208248B (en) | 2012-01-17 | 2012-10-09 | Display panel |
| US13/733,897 US9247615B2 (en) | 2012-01-17 | 2013-01-04 | Display panel |
| US14/967,384 US9780123B2 (en) | 2012-01-17 | 2015-12-14 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261587643P | 2012-01-17 | 2012-01-17 |
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| TW201331688A TW201331688A (en) | 2013-08-01 |
| TWI470328B true TWI470328B (en) | 2015-01-21 |
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| TW101123897A TWI470328B (en) | 2012-01-17 | 2012-07-03 | Display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI714322B (en) * | 2019-02-27 | 2020-12-21 | 友達光電股份有限公司 | Pixel array substrate and driving method thereof |
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| CN111009185B (en) * | 2018-10-08 | 2021-10-12 | 元太科技工业股份有限公司 | Pixel array |
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| CN1719602A (en) * | 2004-07-07 | 2006-01-11 | 恩益禧电子股份有限公司 | Driving device and display |
| TWM371907U (en) * | 2009-08-05 | 2010-01-01 | Wintek Corp | Pixel array and vertical alignment liquid crystal display panel |
| TW201113613A (en) * | 2009-10-05 | 2011-04-16 | Au Optronics Corp | Active device array substrate and display panel thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1719602A (en) * | 2004-07-07 | 2006-01-11 | 恩益禧电子股份有限公司 | Driving device and display |
| TWM371907U (en) * | 2009-08-05 | 2010-01-01 | Wintek Corp | Pixel array and vertical alignment liquid crystal display panel |
| TW201113613A (en) * | 2009-10-05 | 2011-04-16 | Au Optronics Corp | Active device array substrate and display panel thereof |
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| TWI714322B (en) * | 2019-02-27 | 2020-12-21 | 友達光電股份有限公司 | Pixel array substrate and driving method thereof |
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