TWI469507B - Gm-regulated operational amplifier - Google Patents
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Description
本發明係有關於一種轉導校準運算放大器，特別係有關於一種具轉導校準之全差動轉導運算放大器。
The present invention relates to a transconductance calibration operational amplifier, and more particularly to a fully differential transconductance operational amplifier with transconductance calibration.
習知運算轉導放大器200如第2圖所示，其係包含一第一差動對201、一電性連接該第一差動對之電阻202、一電性連接該電阻202之第二差動對203、一電性連接該第一差動對200之第三差動對204，該第一差動對201係具有一第一電晶體205，其係電性連接該電阻202，該第一差動對201及該第二差動對203分別從一第一電壓輸入端206及一第二電壓輸入端207接收一第一輸入電壓及一第二輸入電壓，該電阻202之兩端係形成一電壓差，該電壓差係轉換為一轉換電流，此時，若該第一輸入電壓與該第二輸入電壓不同，則該轉換電流係被分流至該第一差動對201之該第一電晶體205，使得輸出電流成分係包含一偏壓電流，為了使得輸出電流成分中不含該偏壓電流，利用該第三差動對204來對輸出電流進行修正，使得輸出電流的成分僅由該第一輸入電壓、該第二輸入電壓及該電阻202控制，由於習知技術並未對其轉導值飄移進行補償，因此無法應用於增益需維持定值之電路。
As shown in FIG. 2, the conventional operational transconductance amplifier 200 includes a first differential pair 201, a resistor 202 electrically connected to the first differential pair, and a second difference electrically connected to the resistor 202. The movable pair 203 is electrically connected to the third differential pair 204 of the first differential pair 200. The first differential pair 201 has a first transistor 205 electrically connected to the resistor 202. A differential pair 201 and the second differential pair 203 receive a first input voltage and a second input voltage from a first voltage input terminal 206 and a second voltage input terminal 207, respectively. Forming a voltage difference, the voltage difference is converted into a conversion current. At this time, if the first input voltage is different from the second input voltage, the converted current is shunted to the first differential pair 201 A transistor 205 is configured such that the output current component includes a bias current. In order to prevent the bias current from being included in the output current component, the third differential pair 204 is used to correct the output current so that the output current component is only Controlled by the first input voltage, the second input voltage, and the resistor 202, Since the prior art does not compensate for the drift of the transconductance value, it cannot be applied to a circuit whose gain needs to maintain a constant value.
本發明之主要目的係在於提供一種轉導校準運算放大器，其係包含一轉導校準電路及一輸入放大器，其中該轉導校準電路係具有一第一差動對及一電性連接該第一差動對之電流鏡，該第一差動對係具有一第一電晶體及一第二電晶體，該第一電晶體係具有一第一源極端，該第二電晶體係具有一第二源極端，該第一電晶體之該第一源極端及該第二電晶體之該第二源極端係共接至一第一節點，該電流鏡係具有一第三電晶體及一第四電晶體，該第三電晶體係具有一第三閘極端及一第三汲極端，該第四電晶體係具有一第四閘極端、一第四汲極端及一第四源極端，該第三電晶體之該第三閘極端、該第三電晶體之該第三汲極端及該第四電晶體之該第四閘極端係電性連接至該第一節點，該輸入放大器係具有一第二差動對、一第五電晶體及一第六電晶體，該第五電晶體係具有一第五汲極端，該第六電晶體係具有一第六汲極端，該第五電晶體之該第五汲極端係電性連接該第四電晶體之該第四源極端，該第六電晶體之該第六汲極端、該第四電晶體之該第四汲極端及該第二差動對係共接至一第二節點。本發明係藉由該轉導校準電路為該輸入放大器之半複製電路(half-replica)，當該第二節點因製程飄移而產生一電壓變化時，由於複製電路的特性，該轉導校準電路之該第一節點係同時產生一電壓變化，最後經由該電流鏡與該第一節點之電性連接關係，使得該第五電晶體之該第五汲極端與該第二節點產生相同的電壓變化，使得該輸入放大器之轉導(gm)係可維持一恆定值，因此，該轉導校準運算放大器係可應用於增益需為定值之電路。
The main purpose of the present invention is to provide a transconductance calibration operational amplifier comprising a transconductance calibration circuit and an input amplifier, wherein the transconductance calibration circuit has a first differential pair and an electrical connection. a differential pair current mirror, the first differential pair has a first transistor and a second transistor, the first transistor system has a first source terminal, and the second transistor system has a second The first source terminal of the first transistor and the second source terminal of the second transistor are connected to a first node. The current mirror has a third transistor and a fourth electrode. a third electro-optic system having a third gate terminal and a third gate terminal, the fourth transistor system having a fourth gate terminal, a fourth gate terminal, and a fourth source terminal, the third electrode The third gate terminal of the crystal, the third drain terminal of the third transistor, and the fourth gate terminal of the fourth transistor are electrically connected to the first node, and the input amplifier has a second difference Moving pair, a fifth transistor and a sixth transistor, the fifth transistor Having a fifth 汲 extreme, the sixth enamel system has a sixth 汲 extreme, the fifth 汲 extreme of the fifth transistor is electrically connected to the fourth source terminal of the fourth transistor, the first The sixth terminal of the sixth transistor, the fourth terminal of the fourth transistor, and the second differential pair are connected to a second node. According to the present invention, the transduction calibration circuit is a half-replica of the input amplifier. When the second node generates a voltage change due to process drift, the transduction calibration circuit is due to the characteristics of the replica circuit. The first node generates a voltage change at the same time, and finally the electrical connection between the current node and the first node is such that the fifth terminal of the fifth transistor generates the same voltage change as the second node. The transconductance (gm) of the input amplifier can be maintained at a constant value. Therefore, the transconductance calibration operational amplifier can be applied to a circuit whose gain needs to be constant.
請參閱第1圖，其係本發明之一較佳實施例，一種轉導校準運算放大器100係包含一轉導校準電路110及一輸出放大電路120，其中該轉導校準電路110係具有一第一差動對111、電性連接該第一差動對111之一電流鏡114及一電流源S，該轉導校準電路110係用以補償該輸入放大器120之轉導值，該第一差動對111係具有一第一電晶體112及一第二電晶體113，該第一電晶體112係具有一第一閘極端112a、一第一汲極端112及一第一源極端112c，該第二電晶體113係具有一第二閘極端113a、一第二汲極端113b及一第二源極端113c，該第一源極端112c及該第二源極端113c係共接至一第一節點N1，該第一電流鏡114係具有一第三電晶體115及一第四電晶體116，該第三電晶體115係具有一第三閘極端115a、一第三汲極端115b及一第三源極端115c，該第四電晶體116係具有一第四閘極端116a、一第四汲極端116b及一第四源極端116c，該第三閘極端115a、該第三汲極端115b及該第四閘極端116a係電性連接該第一節點N1，在本實施例中，該電流源S係可為一電晶體，該電流源S係具有一第十一閘極端S1、一第十一汲極端S2及一第十一源極端S3，該第十一汲極端S2係電性連接該第一節點N1，該輸入放大器120係具有一第二差動對121、一第五電晶體124及一第六電晶體125，該第五電晶體124係具有一第五閘極端124a、一第五汲極端124b及一第五源極端124c，該第五汲極端124b係電性連接該第四電晶體116之該第四源極端116c，該第六電晶體125係具有一第六閘極端125a、一第六汲極端125b及一第六源極端125c，該第六汲極端125b係電性連接該第四電晶體116之該第四汲極端116b，該第六閘極端125a係電性連接該電流源S之該第十一閘極端S1，該第二差動對121係具有一第七電晶體122及一第八電晶體123，該第七電晶體122係具有一第七閘極端122a、一第七汲極端122b及一第七源極端122c，該第八電晶體123係具有一第八閘極端123a、一第八汲極端123b及一第八源極端123c，該第七源極端122c、該第八源極端123c及該第六電晶體125之該第六汲極端125c係共接至一第二節點N2。
請再參閱第1圖，在本實施例中，該輸入放大器120係另具有一第三差動對126，該第三差動對126係具有一第九電晶體127及一第十電晶體128，該第九電晶體127係具有一第九閘極端127a、一第九汲極端127b及一第九源極端127c，該第十電晶體128係具有一第十閘極端128a、一第十汲極端128b及一第十源極端128c，該第九源極端127c、該第十源極端128c及該第五電晶體124之該第五汲極端124b係共接至一第三節點N3，該第七電晶體122之該第七閘極端122a係電性連接該第一電晶體112之該第一閘極端112a及該第九電晶體127之該第九閘極端127a，該第八電晶體123之該第八閘極端123a係電性連接該第二電晶體113之該第二閘極端113a及該第十電晶體128之該第十閘極端128a，在本實施例中，該轉導校準電路110之該第一差動對111係為該輸入放大器120之該第二差動對121之半複製電路，此外，該轉導校準電路110係另具有一第四差動對117，其係為該輸入放大器120之該第三差動對126之半複製電路，該第四差動對117係具有一第十二電晶體118及一第十三電晶體119，該第十二電晶體118係具有一第十二閘極端118a、一第十二汲極端118b及一第十二源極端118c，該第十三電晶體119係具有一第十三閘極端119a、一第十三汲極端119b及一第十三源極端119c，該第十二閘極端118a、該第十三閘極端119a、該第十二汲極端118b、該第十三汲極端119b、該第一汲極端112b及該第二汲極端113b係共接至一第二節點N4，該電流源S係為該輸入放大器120之該第五電晶體124及該第六電晶體125之半複製電路，該轉導校準運算放大器係另具有一增益放大電路130，其係電性連接該輸入放大器120，該輸入放大器120係接收一差動電壓，將其放大並轉換為電流，以供該增益放大電路130使用，該增益放大電路130將該輸入放大器120提供之電流進行放大並轉換為電壓輸出。
請參閱第1圖，本發明之電路作動係敘述如下，輸入一差動電壓至該輸入放大器120之該第二差動對121及該第三差動對126，該轉導校準電路110之該第一差動對111係接收相同之差動電壓，因製程飄移或是輸入電壓飄移，使得該輸入放大器120之該第六電晶體125之該第六汲極端125b產生電壓變化時，該轉導校準電路110之該電流源S之該第十一汲極端S2係也產生相同之電壓變化，而該第四電晶體116之該第四閘極端116a及該第十一汲極端S2之電性連接關係，使得該第四閘極端116a係產生相同電壓變化，該電流鏡114係維持一固定電流，該第四電晶體116之該第四源極端116c及該第四電晶體116之該第四閘極端116a之電壓差係維持不變，使得該第四源極端116c也產生相同電壓變化，而由於該第四源極端116c及該第五電晶體124之該第五汲極端124b之電性連接關係，使得該第五汲極端124b係產生相同電壓變化，最後，該第五汲極端124b及該第六汲極端125b係具有相同之電壓變化，不論是製程飄移或是輸入電壓飄移，該輸入放大器120之轉導(gm)皆可為一恆定值，該輸入放大器120經由轉導校準後將該差動電壓放大並轉換成電流訊號送至該增益放大電路130，該增益放大電路130再將該電流訊號放大並轉換成電壓輸出。
本發明係藉由該轉導校準電路110為該輸入放大器120之半複製電路(half-replica)，當該第二節點N2因製程飄移而產生一電壓變化時，由於複製電路的特性，該轉導校準電路110之該第一節點N1係同時產生一電壓變化，最後經由該電流鏡114與該第一節點N1之電性連接關係，使得該第五電晶體124之該第五汲極端124b的該第三節點N3與該第二節點N2係產生相同的電壓變化，使得該輸入放大器120之轉導(gm)係可維持一恆定值，因此，該轉導校準運算放大器100係可應用於增益需為定值之電路。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
1 is a preferred embodiment of the present invention. A transconductance calibration operational amplifier 100 includes a transconductance calibration circuit 110 and an output amplification circuit 120. The transduction calibration circuit 110 has a first a differential pair 111 electrically connected to the current mirror 114 and a current source S of the first differential pair 111, the transconductance calibration circuit 110 is configured to compensate the transconductance value of the input amplifier 120, the first difference The movable pair 111 has a first transistor 112 and a second transistor 113. The first transistor 112 has a first gate terminal 112a, a first threshold 112 and a first source 112c. The second transistor 113 has a second gate 113a, a second gate 113b and a second source 113c. The first source 112c and the second source 113c are connected to a first node N1. The first current mirror 114 has a third transistor 115 and a fourth transistor 116. The third transistor 115 has a third gate 115a, a third terminal 115b and a third source 115c. The fourth transistor 116 has a fourth gate terminal 116a, a fourth gate terminal 116b, and a first The fourth source terminal 116c, the third gate terminal 115a, the third gate electrode 115b and the fourth gate electrode 116a are electrically connected to the first node N1. In this embodiment, the current source S can be a battery. a crystal, the current source S has an eleventh gate terminal S1, an eleventh gate terminal S2, and an eleventh source terminal S3. The eleventh pole extreme S2 is electrically connected to the first node N1. The input amplifier 120 has a second differential pair 121, a fifth transistor 124 and a sixth transistor 125. The fifth transistor 124 has a fifth gate terminal 124a, a fifth threshold electrode 124b and a The fifth source terminal 124c is electrically connected to the fourth source terminal 116c of the fourth transistor 116. The sixth transistor 125 has a sixth gate terminal 125a and a sixth terminal. 125b and a sixth source terminal 125c, the sixth electrode terminal 125b is electrically connected to the fourth electrode terminal 116b of the fourth transistor 116, and the sixth gate electrode 125a is electrically connected to the current source S. An eleven gate extreme S1, the second differential pair 121 has a seventh transistor 122 and an eighth transistor 123, the seventh transistor The 122 series has a seventh gate terminal 122a, a seventh gate terminal 122b and a seventh source terminal 122c. The eighth transistor 123 has an eighth gate terminal 123a, an eighth terminal electrode 123b and an eighth source. The fourth source terminal 122c, the eighth source terminal 123c, and the sixth threshold electrode 125c of the sixth transistor 125 are connected to a second node N2.
Referring to FIG. 1 again, in the embodiment, the input amplifier 120 further has a third differential pair 126, and the third differential pair 126 has a ninth transistor 127 and a tenth transistor 128. The ninth transistor 127 has a ninth gate terminal 127a, a ninth gate terminal 127b and a ninth source terminal 127c. The tenth transistor 128 has a tenth gate terminal 128a and a tenth 汲 terminal. 128b and a tenth source terminal 128c, the ninth source terminal 127c, the tenth source terminal 128c and the fifth electrode terminal 124b of the fifth transistor 124 are connected to a third node N3, the seventh battery The seventh gate terminal 122a of the crystal 122 is electrically connected to the first gate terminal 112a of the first transistor 112 and the ninth gate terminal 127a of the ninth transistor 127. The eighth gate terminal 123a is electrically connected to the second gate electrode 113a of the second transistor 113 and the tenth gate terminal 128a of the tenth transistor 128. In the embodiment, the transduction calibration circuit 110 The first differential pair 111 is a half-copy circuit of the second differential pair 121 of the input amplifier 120, and further, the transduction calibration The circuit 110 further has a fourth differential pair 117, which is a half replica circuit of the third differential pair 126 of the input amplifier 120. The fourth differential pair 117 has a twelfth transistor 118 and a thirteenth transistor 119 having a twelfth gate terminal 118a, a twelfth gate terminal 118b and a twelfth source terminal 118c, the thirteenth transistor 119 having a thirteenth gate terminal 119a, a thirteenth 汲 terminal 119b and a thirteenth source terminal 119c, the twelfth gate terminal 118a, the thirteenth gate terminal 119a, the twelfth ridge terminal 118b, the first The thirteenth extreme 119b, the first 汲 extreme 112b and the second 汲 extreme 113b are connected to a second node N4, the current source S being the fifth transistor 124 of the input amplifier 120 and the sixth a half-copy circuit of the transistor 125, the transconductance calibration operational amplifier further has a gain amplifying circuit 130 electrically connected to the input amplifier 120, the input amplifier 120 receives a differential voltage, amplifies and converts it into a current for use by the gain amplifying circuit 130, the gain amplifying circuit 130 Provided the current amplifier 120 amplifies and converts a voltage output.
Referring to FIG. 1 , the circuit actuation system of the present invention is described as follows. A differential voltage is input to the second differential pair 121 and the third differential pair 126 of the input amplifier 120. The transduction calibration circuit 110 The first differential pair 111 receives the same differential voltage, and the transducing occurs when the sixth 汲 terminal 125b of the sixth transistor 125 of the input amplifier 120 generates a voltage change due to process drift or input voltage drift. The eleventh pole S2 of the current source S of the calibration circuit 110 also generates the same voltage change, and the fourth gate terminal 116a of the fourth transistor 116 and the eleventh pole end S2 are electrically connected. The relationship is such that the fourth gate terminal 116a generates the same voltage change, the current mirror 114 maintains a fixed current, and the fourth source terminal 116c of the fourth transistor 116 and the fourth gate of the fourth transistor 116 The voltage difference of the terminal 116a is maintained, so that the fourth source terminal 116c also generates the same voltage change, and the electrical connection relationship between the fourth source terminal 116c and the fifth electrode terminal 124b of the fifth transistor 124 is To make the fifth 汲 extreme 124b The same voltage change occurs. Finally, the fifth 汲 terminal 124b and the sixth 汲 terminal 125b have the same voltage change. Whether the process drifts or the input voltage drifts, the transduction (gm) of the input amplifier 120 can be A constant value, the input amplifier 120 is amplified by the transconductance and converted into a current signal and sent to the gain amplifying circuit 130. The gain amplifying circuit 130 then amplifies and converts the current signal into a voltage output.
The present invention is a half-replica of the input amplifier 120 by the transconductance calibration circuit 110. When the second node N2 generates a voltage change due to process drift, the turn is due to the characteristics of the replica circuit. The first node N1 of the calibration circuit 110 simultaneously generates a voltage change, and finally electrically connected to the first node N1 via the current mirror 114, so that the fifth electrode terminal 124b of the fifth transistor 124 The third node N3 and the second node N2 generate the same voltage change, so that the transconductance (gm) of the input amplifier 120 can maintain a constant value. Therefore, the transconductance calibration operational amplifier 100 can be applied to the gain. A circuit that requires a constant value.
The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .
100．．．轉導校準運算放大器100. . . Transducing calibration operational amplifier
110．．．轉導校準電路110. . . Transduction calibration circuit
111．．．第一差動對111. . . First differential pair
112．．．第一電晶體112. . . First transistor
112a．．．第一閘極端112a. . . First gate extreme
112b．．．第一汲極端112b. . . First extreme
112c．．．第一源極端112c. . . First source extreme
113．．．第二電晶體113. . . Second transistor
113a．．．第二閘極端113a. . . Second gate extreme
113b．．．第二汲極端113b. . . Second extreme
113c．．．第二源極端113c. . . Second source extreme
114．．．電流鏡114. . . Current mirror
115．．．第三電晶體115. . . Third transistor
115a．．．第三閘極端115a. . . Third gate extreme
115b．．．第三汲極端115b. . . Third extreme
115c．．．第三源極端115c. . . Third source extreme
116．．．第四電晶體116. . . Fourth transistor
116a．．．第四閘極端116a. . . Fourth gate extreme
116b．．．第四汲極端116b. . . Fourth extreme
116c．．．第四源極端116c. . . Fourth source extreme
117．．．第四差動對117. . . Fourth differential pair
118．．．第十二電晶體118. . . Twelfth transistor
118a．．．第十二閘極端118a. . . Twelfth gate extreme
118b．．．第十二汲極端118b. . . Twelfth 汲 extreme
118c．．．第十二源極端118c. . . Twelfth source extreme
119．．．第十三電晶體119. . . Thirteenth transistor
119a．．．第十三閘極端119a. . . Thirteenth gate extreme
119b．．．第十三汲極端119b. . . Thirteenth Extreme
119c．．．第十三源極端119c. . . Thirteen source extreme
120．．．輸入放大器120. . . Input amplifier
121．．．第二差動對121. . . Second differential pair
122．．．第七電晶體122. . . Seventh transistor
122a．．．第七閘極端122a. . . Seventh gate extreme
122b．．．第七汲極端122b. . . Seventh 汲 extreme
122c．．．第七源極端122c. . . Seventh source extreme
123．．．第八電晶體123. . . Eighth transistor
123a．．．第八閘極端123a. . . Eighth gate extreme
123b．．．第八汲極端123b. . . Eighth extreme
123c．．．第八源極端123c. . . Eighth source extreme
124．．．第五電晶體124. . . Fifth transistor
124a．．．第五閘極端124a. . . Fifth gate extreme
124b．．．第五汲極端124b. . . Fifth extreme
124c．．．第五源極端124c. . . Fifth source extreme
125．．．第六電晶體125. . . Sixth transistor
125a．．．第六閘極端125a. . . Sixth gate extreme
125b．．．第六汲極端125b. . . Sixth extreme
125c．．．第六源極端125c. . . Sixth source extreme
126．．．第三差動對126. . . Third differential pair
127．．．第九電晶體127. . . Ninth transistor
127a．．．第九閘極端127a. . . Ninth gate extreme
127b．．．第九汲極端127b. . . Ninth extreme
127c．．．第九源極端127c. . . Ninth source extreme
128．．．第十電晶體128. . . Tenth transistor
128a．．．第十閘極端128a. . . Tenth gate extreme
128b．．．第十汲極端128b. . . Tenth extreme
128c．．．第十源極端128c. . . Tenth source extreme
130．．．增益放大電路130. . . Gain amplification circuit
S．．．電流源S. . . Battery
S1．．．第十一閘極端S1. . . Eleventh gate extreme
S2．．．第十一汲極端S2. . . Eleventh extreme
S3．．．第十一源極端S3. . . Eleventh source extreme
N1．．．第一節點N1. . . First node
N2．．．第二節點N2. . . Second node
N3．．．第三節點N3. . . Third node
N4．．．第四節點N4. . . Fourth node
200．．．運算轉導放大器200. . . Operational transconductance amplifier
201．．．第一差動對201. . . First differential pair
202．．．電阻202. . . resistance
203．．．第二差動對203. . . Second differential pair
204．．．第三差動對204. . . Third differential pair
205．．．第一電晶體205. . . First transistor
206．．．第一電壓輸入端206. . . First voltage input
207．．．第二電壓輸入端207. . . Second voltage input
第1圖：依據本發明之一較佳實施例，一種轉導校準運算放大器之電路圖。
第2圖：習知轉導運算放大器之電路圖。
Figure 1 is a circuit diagram of a transconductance calibration operational amplifier in accordance with a preferred embodiment of the present invention.
Figure 2: Circuit diagram of a conventional transducing operational amplifier.
100．．．轉導校準運算放大器100. . . Transducing calibration operational amplifier
110．．．轉導校準電路110. . . Transduction calibration circuit
111．．．第一差動對111. . . First differential pair
112．．．第一電晶體112. . . First transistor
112a．．．第一閘極端112a. . . First gate extreme
112b．．．第一汲極端112b. . . First extreme
112c．．．第一源極端112c. . . First source extreme
113．．．第二電晶體113. . . Second transistor
113a．．．第二閘極端113a. . . Second gate extreme
113b．．．第二汲極端113b. . . Second extreme
113c．．．第二源極端113c. . . Second source extreme
114．．．電流鏡114. . . Current mirror
115．．．第三電晶體115. . . Third transistor
115a．．．第三閘極端115a. . . Third gate extreme
115b．．．第三汲極端115b. . . Third extreme
115c．．．第三源極端115c. . . Third source extreme
116．．．第四電晶體116. . . Fourth transistor
116a．．．第四閘極端116a. . . Fourth gate extreme
116b．．．第四汲極端116b. . . Fourth extreme
116c．．．第四源極端116c. . . Fourth source extreme
117．．．第四差動對117. . . Fourth differential pair
118．．．第十二電晶體118. . . Twelfth transistor
118a．．．第十二閘極端118a. . . Twelfth gate extreme
118b．．．第十二汲極端118b. . . Twelfth 汲 extreme
118c．．．第十二源極端118c. . . Twelfth source extreme
119．．．第十三電晶體119. . . Thirteenth transistor
119a．．．第十三閘極端119a. . . Thirteenth gate extreme
119b．．．第十三汲極端119b. . . Thirteenth Extreme
119c．．．第十三源極端119c. . . Thirteen source extreme
120．．．輸入放大器120. . . Input amplifier
121．．．第二差動對121. . . Second differential pair
122．．．第七電晶體122. . . Seventh transistor
122a．．．第七閘極端122a. . . Seventh gate extreme
122b．．．第七汲極端122b. . . Seventh 汲 extreme
122c．．．第七源極端122c. . . Seventh source extreme
123．．．第八電晶體123. . . Eighth transistor
123a．．．第八閘極端123a. . . Eighth gate extreme
123b．．．第八汲極端123b. . . Eighth extreme
123c．．．第八源極端123c. . . Eighth source extreme
124．．．第五電晶體124. . . Fifth transistor
124a．．．第五閘極端124a. . . Fifth gate extreme
124b．．．第五汲極端124b. . . Fifth extreme
124c．．．第五源極端124c. . . Fifth source extreme
125．．．第六電晶體125. . . Sixth transistor
125a．．．第六閘極端125a. . . Sixth gate extreme
125b．．．第六汲極端125b. . . Sixth extreme
125c．．．第六源極端125c. . . Sixth source extreme
126．．．第三差動對126. . . Third differential pair
127．．．第九電晶體127. . . Ninth transistor
127a．．．第九閘極端127a. . . Ninth gate extreme
127b．．．第九汲極端127b. . . Ninth extreme
127c．．．第九源極端127c. . . Ninth source extreme
128．．．第十電晶體128. . . Tenth transistor
128a．．．第十閘極端128a. . . Tenth gate extreme
128b．．．第十汲極端128b. . . Tenth extreme
128c．．．第十源極端128c. . . Tenth source extreme
130．．．增益放大電路130. . . Gain amplification circuit
S．．．電流源S. . . Battery
S1．．．第十一閘極端S1. . . Eleventh gate extreme
S2．．．第十一汲極端S2. . . Eleventh extreme
S3．．．第十一源極端S3. . . Eleventh source extreme
N1．．．第一節點N1. . . First node
N2．．．第二節點N2. . . Second node
N3．．．第三節點N3. . . Third node
N4．．．第四節點N4. . . Fourth node
Claims (8)
一轉導校準電路，其係具有一第一差動對、一電性連接該第一差動對之電流鏡，該第一差動對係具有一第一電晶體及一第二電晶體，該第一電晶體係具有一第一閘極端、一第一汲極端及一第一源極端，該第二電晶體係具有一第二閘極端、一第二汲極端及一第二源極端，該第一電晶體之該第一源極端及該第二電晶體之該第二源極端係共接至一第一節點，該電流鏡係具有一第三電晶體及一第四電晶體，該第三電晶體係具有一第三閘極端及一第三汲極端，該第四電晶體係具有一第四閘極端、一第四源極端及一第四汲極端，該第三電晶體之該第三閘極端、該第三電晶體之該第三汲極端及該第四電晶體之該第四閘極端係電性連接該第一節點；以及
一輸入放大器，其係具有一第二差動對、一第五電晶體及一第六電晶體，該第五電晶體係具有一第五汲極端，該第六電晶體係具有一第六汲極端及一第六閘極端，該第五電晶體之該第五汲極端係電性連接該第四電晶體之該第四源極端，該第六電晶體之該第六汲極端、該第四電晶體之該第四汲極端及該第二差動對係共接至一第二節點。A transconductance calibration operational amplifier, the system comprising:
a transconductance calibration circuit having a first differential pair and a current mirror electrically connected to the first differential pair, the first differential pair having a first transistor and a second transistor, The first electro-optic system has a first gate terminal, a first gate terminal and a first source terminal, and the second transistor system has a second gate terminal, a second gate terminal and a second source terminal. The first source terminal of the first transistor and the second source terminal of the second transistor are connected to a first node. The current mirror has a third transistor and a fourth transistor. The third electro-crystalline system has a third gate terminal and a third gate terminal, and the fourth transistor system has a fourth gate terminal, a fourth source terminal and a fourth terminal electrode, and the third transistor has the third transistor a third gate terminal, the third drain terminal of the third transistor, and the fourth gate terminal of the fourth transistor are electrically connected to the first node; and an input amplifier having a second differential a fifth transistor and a sixth transistor, the fifth transistor system having a fifth terminal, the first The electro-crystal system has a sixth 汲 extreme and a sixth thyristor, and the fifth 汲 extreme of the fifth transistor is electrically connected to the fourth source terminal of the fourth transistor, the sixth transistor The sixth antenna terminal, the fourth antenna terminal of the fourth transistor, and the second differential pair are connected to a second node.
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5631607A (en) * | 1995-09-06 | 1997-05-20 | Philips Electronics North America Corporation | Compact GM-control for CMOS rail-to-rail input stages by regulating the sum of the gate-source voltages constant |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5631607A (en) * | 1995-09-06 | 1997-05-20 | Philips Electronics North America Corporation | Compact GM-control for CMOS rail-to-rail input stages by regulating the sum of the gate-source voltages constant |
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