TWI467764B - Vertical transistor structure and method of manufacturing same - Google Patents
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Description
本發明係有關一種半導體結構，尤指一種垂直式電晶體之結構及其製作方法。The present invention relates to a semiconductor structure, and more particularly to a structure of a vertical transistor and a method of fabricating the same.
隨著半導體製程技術的不斷精進，一方面大幅縮小了電子元件的尺寸，另一方面亦大幅縮減了電子元件之製造成本。而歷年所使用之半導體製程技術僅限制於基板上以蝕刻、離子佈值、佈線等方式形成平面式的半導體結構，而最小晶片之尺寸已能達到6F2的大小。但目前此類技術隨著最小線寬(Feature Size)之發展速度漸趨於平緩而無法顯著的縮小半導體於晶圓上所佔用的面積。於是，垂直式(或稱為立體式)的半導體製程技術漸趨發展，其係利用將半導體垂直成長於晶圓上的方式減少電晶體於晶圓表面上所佔用的面積，而更進一步的將晶片尺寸縮小到4F2。With the continuous improvement of semiconductor process technology, on the one hand, the size of electronic components has been greatly reduced, and on the other hand, the manufacturing cost of electronic components has been greatly reduced. The semiconductor process technology used in the past years is limited to the formation of planar semiconductor structures by etching, ion cloth values, wiring, etc. on the substrate, and the minimum wafer size can reach 6F2. However, at present, such technologies are gradually becoming flatter with the development of the minimum feature size, and the area occupied by the semiconductor on the wafer cannot be significantly reduced. Thus, vertical (or three-dimensional) semiconductor process technology is gradually evolving, which reduces the area occupied by the transistor on the wafer surface by vertically growing the semiconductor on the wafer, and further The chip size is reduced to 4F2.
而如美國專利公告第7326611號之「DRAM arrays,vertical transistor structures and methods of forming transistor structure and DRAM Array」，以及美國專利公開第20050190617號之「Folded bit line DRAM with vertical ultra thin body transistors」，其分別揭露了垂直式的柱狀電晶體(Vertical Pillar Transistor)架構、製作方法及過程，請配合參閱「圖1」所示，其係為垂直式動態隨機存取記憶體之立體結構示意圖，其於柱狀體1(Pillar)旁形成閘極2(gate material)以控制作為電晶體使用的柱狀體1之導通與否，而閘極2之形成通常是以蝕刻金屬線而形成兩相互不接觸並貼附該柱狀體的閘極2，並將設置於該柱狀體1兩側的閘極2利用導線3連接，而可同時對該柱狀體1進行電壓控制，使作為電晶體使用的該柱狀體1隨著該閘極2之控制進行導通或截止，藉此對設置於該柱狀體1上的電容4進行資料儲存或讀取。但隨著最小線寬已經降到40奈米(nm)以下的現今技術中，金屬線之厚度以及金屬線之間的間距皆必須縮小以符合最小線寬之尺寸，尤其是金屬線之間的間距，由原本在65奈米製程中有45nm的間距，縮減到15nm，僅為原本的三分之一，因而其蝕刻位置的確定，以及蝕刻時間的長短等，皆受到了極大的挑戰。因此，如何有效於最小線寬漸縮的現代製程以及未來製程中進行閘極2製作，便成為現今半導體廠所亟欲解決之問題。And "Folded bit line DRAM with vertical ultra thin body transistors" of US Patent Publication No. 20070190617, respectively, The vertical columnar transistor structure, fabrication method and process are disclosed. Please refer to the schematic diagram of FIG. 1 , which is a schematic diagram of a vertical dynamic random access memory. A gate material is formed next to the Pillar 1 to control the conduction of the columnar body 1 used as a transistor, and the gate 2 is usually formed by etching metal lines to form two non-contacts. The gate 2 of the columnar body is attached, and the gates 2 provided on both sides of the columnar body 1 are connected by a wire 3, and the columnar body 1 can be simultaneously voltage-controlled for use as a transistor. The columnar body 1 is turned on or off as the gate electrode 2 is controlled, thereby storing or reading data on the capacitor 4 provided on the columnar body 1. However, with the current technology where the minimum line width has dropped below 40 nanometers (nm), the thickness of the metal lines and the spacing between the metal lines must be reduced to meet the minimum line width, especially between the metal lines. The spacing, which was originally reduced to 15nm by a 45nm pitch in the 65nm process, is only one-third of the original, so the determination of the etching position and the length of the etching time are all extremely challenging. Therefore, how to effectively manufacture the gate 2 in the modern process with the minimum line width and the future process is a problem that today's semiconductor factories are trying to solve.
本發明之主要目的，在於解決垂直式電晶體中之閘極因最小線寬漸縮而使得分離金屬線製程之蝕刻位置以及蝕刻時間控制不易的問題。The main object of the present invention is to solve the problem that the gate of the vertical transistor is tapered due to the minimum line width, so that the etching position of the separation metal line process and the etching time are not easily controlled.
為達上述目的，本發明提供一種垂直式電晶體之結構，包含有一基底、複數設置於該基底上並相互間隔一間距的柱狀體、一閘極線以及複數導電體。複數該柱狀體係沿一第一方向排列為一直線，該些柱狀體具有平行該第一方向的一主控制壁以及兩垂直該主控制壁的輔助控制壁。該閘極線沿該第一方向透過一第一絕緣層與該主控制壁連接並平行該基底，而複數該導電體則透過一第二絕緣層夾置於複數該柱狀體之輔助控制壁之間。To achieve the above object, the present invention provides a vertical transistor structure comprising a substrate, a plurality of columns disposed on the substrate and spaced apart from each other, a gate line, and a plurality of conductors. The plurality of columnar systems are arranged in a line along a first direction, the columns having a main control wall parallel to the first direction and two auxiliary control walls perpendicular to the main control wall. The gate line is connected to the main control wall in a first direction through a first insulating layer and parallel to the substrate, and the plurality of conductors are interposed between the auxiliary control walls of the plurality of columns through a second insulating layer. between.
除此之外，本發明更提供一種垂直式電晶體之製作方法，其包含有以下步驟：S1：於一基底上形成複數柱狀體，並使複數該柱狀體沿一第一方向排列為直線，該柱狀體具有一主控制壁以及兩垂直該主控制壁的輔助控制壁；S2：設置一蝕刻停止層以及一蝕刻區域於該柱狀體具有該主控制壁之一側，且使該蝕刻停止層相鄰於該柱狀體之主控制壁；S3：對該蝕刻區域進行蝕刻；S4：形成一隔離段於該蝕刻區域；S5：去除該蝕刻停止層之區域以形成一通道，並於該柱狀體具有該輔助控制壁之一側形成一凹槽；及S6：沉積一導電材質於該通道及該凹槽之表面，以形成一閘極線以及一導電體，並該閘極線與該通道之間具有一第一絕緣層，該導電體與該凹槽之間具有一第二絕緣層，使該導電體相鄰設置於該柱狀體之輔助控制壁，而部分該閘極線則相鄰設置於該柱狀體之主控制壁。In addition, the present invention further provides a method for fabricating a vertical transistor, comprising the steps of: forming a plurality of columns on a substrate, and arranging the plurality of columns in a first direction a straight line, the column body has a main control wall and two auxiliary control walls perpendicular to the main control wall; S2: an etch stop layer and an etched area are provided on the column body having one side of the main control wall, and The etch stop layer is adjacent to the main control wall of the column; S3: etching the etched region; S4: forming an isolation segment in the etched region; S5: removing the region of the etch stop layer to form a channel, And forming a groove on one side of the column body having the auxiliary control wall; and S6: depositing a conductive material on the surface of the channel and the groove to form a gate line and an electric conductor, and the gate a first insulating layer is disposed between the pole line and the channel, and a second insulating layer is disposed between the conductive body and the groove, so that the conductive body is adjacently disposed on the auxiliary control wall of the column body, and the portion is The gate line is adjacent to the column body The main control wall.
由上述說明可知，本發明僅於該柱狀體具有該主控制壁之一側形成該閘極線，並透過複數與該閘極線電性連接的導電體控制該柱狀體兩端之電性導通狀態，而解決習知技術必須對閘極進行蝕刻分離，但因蝕刻位置以及蝕刻時間控制困難造成蝕刻不均或蝕刻未完全分離的問題。As can be seen from the above description, the present invention only forms the gate line on one side of the columnar body having the main control wall, and controls the electricity at both ends of the column body through a plurality of electrical conductors electrically connected to the gate line. The state of conduction is improved, and the conventional technique must be etched and separated from the gate. However, the etching position and the etching time are difficult to control, resulting in uneven etching or incomplete etching.
有關本發明之詳細說明及技術內容，現就配合圖式說明如下：The detailed description and technical contents of the present invention will now be described as follows:
請參閱「圖2」所示：本發明係為一種垂直式電晶體之結構，需先說明的是，本發明係以垂直式動態存取記憶體為範例說明，說明電晶體之動作及結構。本發明可適用於垂直電晶體之結構，而不以動態隨機存取記憶體為限。本發明之垂直式電晶體之結構包含有一基底10、複數設置於該基底10的位元線11、複數設置於該基底10上並相互間隔一間距的柱狀體20、一設置於該柱狀體20表面的閘極線30以及一與該閘極線30連接的導電體40。複數該柱狀體20係沿一第一方向81排列為一直線，該些柱狀體20具有平行該第一方向81的一主控制壁21以及兩垂直該主控制壁21的輔助控制壁22，而該位元線11係以垂直該第一方向81並以離子佈植的方式於該基底10摻雜離子而形成於該基底10表面，且於本實施例中，該柱狀體20更排列形成陣列結構，以作為記憶體之資料存取。該閘極線30沿該第一方向81並平行該基底10而透過一第一絕緣層73與該主控制壁21連接。本發明僅利用設置於該主控制壁21的閘極進行電壓控制，換句話說，僅於該柱狀體20之主控制壁21設置閘極線30，而該柱狀體20遠離該主控制壁21之一側則不設置閘極。Please refer to FIG. 2: The present invention is a vertical type of transistor structure. It should be noted that the present invention is described by taking a vertical dynamic access memory as an example to illustrate the action and structure of the transistor. The present invention is applicable to the structure of a vertical transistor, and is not limited to a dynamic random access memory. The structure of the vertical type transistor of the present invention comprises a substrate 10, a plurality of bit lines 11 disposed on the substrate 10, a plurality of columnar bodies 20 disposed on the substrate 10 and spaced apart from each other, and a columnar body 20 disposed on the columnar shape. A gate line 30 on the surface of the body 20 and a conductor 40 connected to the gate line 30. The plurality of columnar bodies 20 are arranged in a line along a first direction 81. The columnar bodies 20 have a main control wall 21 parallel to the first direction 81 and two auxiliary control walls 22 perpendicular to the main control wall 21, The bit line 11 is formed on the surface of the substrate 10 by doping ions on the substrate 10 in a manner perpendicular to the first direction 81 and ion implantation. In the embodiment, the column 20 is further arranged. An array structure is formed to be accessed as data of the memory. The gate line 30 is connected to the main control wall 21 through the first insulating layer 73 along the first direction 81 and parallel to the substrate 10. The present invention uses only the gates provided on the main control wall 21 for voltage control. In other words, only the main control wall 21 of the columnar body 20 is provided with the gate line 30, and the columnar body 20 is remote from the main control. On one side of the wall 21, no gate is provided.
複數該導電體40透過一第二絕緣層74夾置於複數該柱狀體20之輔助控制壁22之間。該柱狀體20遠離該基底10之一端連接有一電容結構50，由此，該閘極線30電性連接該導電體40進而控制作為電晶體使用之該柱狀體20兩端(位元線11至該電容結構50)的電性導通與否，而進行電容結構50之電荷讀取或寫入。The plurality of electrical conductors 40 are interposed between the auxiliary control walls 22 of the plurality of columnar bodies 20 through a second insulating layer 74. The columnar body 20 is connected to a capacitor structure 50 at one end of the substrate 10. The gate line 30 is electrically connected to the conductor 40 to control both ends of the column body 20 used as a transistor (bit line). 11 or to the capacitor structure 50) is electrically turned on or off, and the charge reading or writing of the capacitor structure 50 is performed.
請配合參閱「圖3A」至「圖3E」所示，本發明亦揭露了垂直式電晶體之製作方法，該製作方法包含有以下步驟：S1：於一基底10上形成複數柱狀體20，並使複數該柱狀體20沿一第一方向81排列為直線，於本實施例中，複數該柱狀體20更以一垂直該第一方向81的一第二方向82排列形成陣列，而本發明形成該柱狀體20之方式可包含有以下步驟：S1A：對該基底10進行蝕刻以形成複數第一溝渠12，如「圖3A」所示，於該第一溝渠12內填充一氧化物121，該基底10於本實施例中為矽材質，而該氧化物121則可為二氧化矽(SiO2)。Referring to FIG. 3A to FIG. 3E, the present invention also discloses a method for fabricating a vertical transistor. The manufacturing method includes the following steps: S1: forming a plurality of columns 20 on a substrate 10, And the plurality of the columns 20 are arranged in a line along a first direction 81. In the embodiment, the plurality of columns 20 are further arranged in a second direction 82 perpendicular to the first direction 81 to form an array. The method for forming the columnar body 20 of the present invention may include the following steps: S1A: etching the substrate 10 to form a plurality of first trenches 12, as shown in FIG. 3A, filling the first trench 12 with oxidation The substrate 121 is made of ruthenium in this embodiment, and the oxide 121 may be ruthenium dioxide (SiO2).
S1B：蝕刻該氧化物121並進行線性沉積(liner deposition)，如「圖3B」所示，其係對該氧化物121進行乾蝕刻或濕蝕刻一段深度後，於蝕刻完成後的側壁進行氮化矽之線性沉積以形成一保護層23。S1B: etching the oxide 121 and performing a liner deposition process, as shown in FIG. 3B, which is performed by dry etching or wet etching the oxide 121 to a depth, and then nitriding the sidewall after the etching is completed. The tantalum is deposited linearly to form a protective layer 23.
S1C：於該基底10形成一位元線11，如「圖3C」所示，其係於該基底10對應該柱狀體20之位置進行摻雜，而形成該位元線11。S1C: A one-dimensional line 11 is formed on the substrate 10, as shown in FIG. 3C, which is doped to the position of the substrate 10 corresponding to the columnar body 20 to form the bit line 11.
S1D：形成一隔離層14於該第一溝渠12內對應該位元線11之位置並進行填補，如「圖3D」及「圖3E」所示，利用該隔離層14隔離該位元線11與外界之接觸可能，並進行一氮化矽層122以及氧化材質123之填充，而將該第一溝渠12填平。S1D: forming an isolation layer 14 corresponding to the location of the bit line 11 in the first trench 12, as shown in FIG. 3D and FIG. 3E, using the isolation layer 14 to isolate the bit line 11 Contact with the outside world may be performed, and a filling of the tantalum nitride layer 122 and the oxidized material 123 is performed, and the first trench 12 is filled.
S1E：垂直該第一溝渠12之方向形成複數第二溝渠15，完成複數該柱狀體20之形成，請配合參閱「圖4A」至「圖4C」所示，「圖4A」為本發明製程之上視位置示意圖，而「圖4B」及「圖4C」則分別為「圖4A」以A-A方向以及B-B方向的剖面示意圖，其中，A-A方向係為該第一方向81，B-B方向係為該第二方向82，完成步驟S1D後，沿該第一方向81進行蝕刻以形成複數第二溝渠15，以形成複數該柱狀體20，並準備進行閘極設置，而複數該柱狀體20具有一平行該第一方向81的主控制壁21以及兩平行該第二方向82的輔助控制壁22。S1E: a plurality of second trenches 15 are formed perpendicular to the direction of the first trench 12 to complete the formation of the plurality of columnar bodies 20. Please refer to "FIG. 4A" to "FIG. 4C", and FIG. 4A is a process of the present invention. FIG. 4B and FIG. 4C are schematic cross-sectional views of FIG. 4A in the AA direction and the BB direction, respectively, wherein the AA direction is the first direction 81, and the BB direction is the In the second direction 82, after the step S1D is completed, etching is performed along the first direction 81 to form a plurality of second trenches 15 to form a plurality of the columnar bodies 20, and the gate electrodes are prepared, and the plurality of the columnar bodies 20 have A main control wall 21 parallel to the first direction 81 and two auxiliary control walls 22 parallel to the second direction 82.
S2：設置一蝕刻停止層61以及一蝕刻區域62於該柱狀體20具有該主控制壁21之一側，且使該蝕刻停止層61相鄰於該柱狀體20之主控制壁21，請配合參閱「圖5A」至「圖5C」，「圖5B」為「圖5A」沿C-C之剖面示意圖，代表第一溝渠12所形成之非柱狀體20區域，而「圖5C」為「圖5A」沿D-D之剖面示意圖，代表柱狀體20所形成之區域。本發明於該柱狀體20的單側設置該蝕刻停止層61以定義出該蝕刻區域62(示於圖6A)，於本實施例中，該蝕刻停止層61之材質為氮化鈦(TiN)。S2: an etch stop layer 61 and an etched region 62 are disposed on the column body 20 having one side of the main control wall 21, and the etch stop layer 61 is adjacent to the main control wall 21 of the column body 20, Please refer to "FIG. 5A" to "FIG. 5C". "FIG. 5B" is a schematic cross-sectional view along the CC of "FIG. 5A", representing the non-columnar 20 region formed by the first trench 12, and "FIG. 5C" is " Figure 5A is a schematic cross-sectional view along DD, representing the area formed by the columnar body 20. In the present invention, the etch stop layer 61 is disposed on one side of the columnar body 20 to define the etched region 62 (shown in FIG. 6A). In the embodiment, the etch stop layer 61 is made of titanium nitride (TiN). ).
S3：進行該第二溝渠15之蝕刻，對該蝕刻區域62進行蝕刻，請配合參閱「圖6A」及「圖6B」所示，其係分別為「圖5B」以及「圖5C」之視角位置的後續製程示意圖，換句話說，「圖6A」係對應該第一溝渠12之非柱狀體區域的側向剖面，而「圖6B」則為對應柱狀體區域的側向剖面，本發明藉由非等向性蝕刻的方式蝕刻去除該蝕刻區域62的氧化材質123以及氮化矽層122。S3: etching the second trench 15 and etching the etched region 62. Please refer to FIG. 6A and FIG. 6B for the viewing angles of FIG. 5B and FIG. 5C, respectively. A schematic diagram of a subsequent process, in other words, "FIG. 6A" corresponds to a lateral section of the non-columnar region of the first trench 12, and "FIG. 6B" is a lateral cross-section of the corresponding columnar region, the present invention The oxidized material 123 and the tantalum nitride layer 122 of the etched region 62 are etched away by anisotropic etching.
S4：形成一隔離段63於該蝕刻區域62內，再請配合參閱「圖7A」及「圖7B」所示，同樣的，「圖7A」係對應非柱狀體區域的側向剖面，而「圖7B」則為對應柱狀體區域的側向剖面，以下圖式亦同。本發明於去除部分該氮化矽層122後，再次填充氧化材質123於該蝕刻區域62內，藉此形成一隔離段63，且於非柱狀體20區域內仍保留有部分的該氮化矽層122。S4: forming an isolation segment 63 in the etched region 62, and referring to "FIG. 7A" and "FIG. 7B", and similarly, "FIG. 7A" corresponds to a lateral cross-section of the non-columnar region. "Fig. 7B" is a lateral section corresponding to the columnar region, and the following figures are also the same. After removing a portion of the tantalum nitride layer 122, the present invention refills the oxidized material 123 in the etched region 62, thereby forming an isolation segment 63, and still retains a portion of the nitridation in the region of the non-columnar body 20.矽 layer 122.
S5：去除該蝕刻停止層61以及剩餘之氮化矽層122以形成一通道71以及一凹槽72，請配合參閱「圖8A」及「圖8B」所示，其係以濕蝕刻方式蝕刻依序去除該蝕刻停止層61以及該氮化矽層122，而形成該通道71以及該凹槽72，並留下該隔離段63以區隔不同區域的凹槽72，避免凹槽72相互連通。S5: removing the etch stop layer 61 and the remaining tantalum nitride layer 122 to form a channel 71 and a recess 72. Please refer to FIG. 8A and FIG. 8B for etching by wet etching. The etch stop layer 61 and the tantalum nitride layer 122 are sequentially removed to form the via 71 and the recess 72, and the isolation segment 63 is left to separate the recesses 72 of different regions to prevent the recesses 72 from communicating with each other.
S6：導電體40及閘極線30之設置，請再配合參閱「圖9A」，利用化學氣相沉積的方式沉積一導電材質於該通道71以及該凹槽72內，以分別形成該閘極線30以及該導電體40。需特別說明的是，於該通道71以及該凹槽72內形成該閘極線30以及該導電體40之前，係先形成一第一絕緣層73於該通道71表面，以及一第二絕緣層74於該凹槽72之表面，而使該閘極線30與該通道71之間具有一第一絕緣層73，該導電體40與該凹槽72之間具有一第二絕緣層74，避免設置該導電體40以及該閘極線30之後的漏電問題。於本實施例中，該導電體40是利用氣相沉積所形成，因而為中空結構。而於「圖9B」中，利用化學氣相沉積所形成之導電體40一併延伸而於該隔離段63之表面形成該閘極線30，且由於該隔離段63之設置，而使得部分該閘極線30僅透過該第二絕緣層74接觸於該柱狀體20之主控制壁21，而避免同時與相鄰的柱狀體20連接。並且，由於該隔離段63以及該凹槽72所形成之特殊形狀，而使該閘極線30形成於該導電體40之斜上方位置，亦即，該閘極線30與該基底10之距離大於該導電體40與該基底10之距離，若該閘極線30與該導電體40設置於同一水平，容易有誤導通或相互干擾的問題，造成訊號擷取不正確或不精準的問題，透過本發明將該導電體40及該閘極線30設置於不同一水平，而可避免該柱狀體20兩側同時因電壓造成之電場吸引離子誤使該柱狀體20形成電性導通通道71的問題。S6: the arrangement of the conductor 40 and the gate line 30, please refer to "FIG. 9A", and deposit a conductive material into the channel 71 and the groove 72 by chemical vapor deposition to form the gate respectively. Line 30 and the conductor 40. Specifically, before forming the gate line 30 and the conductor 40 in the channel 71 and the recess 72, a first insulating layer 73 is formed on the surface of the channel 71, and a second insulating layer is formed. 74 is disposed on the surface of the recess 72, and has a first insulating layer 73 between the gate line 30 and the channel 71. The second insulating layer 74 is disposed between the conductor 40 and the recess 72 to avoid The leakage problem after the conductor 40 and the gate line 30 are set. In the present embodiment, the conductor 40 is formed by vapor deposition and thus has a hollow structure. In FIG. 9B, the conductive body 40 formed by chemical vapor deposition is extended to form the gate line 30 on the surface of the isolation portion 63, and due to the arrangement of the isolation portion 63, the portion is The gate line 30 is in contact with the main control wall 21 of the columnar body 20 only through the second insulating layer 74, thereby avoiding simultaneous connection with the adjacent columnar body 20. Moreover, due to the special shape formed by the isolation segment 63 and the recess 72, the gate line 30 is formed at an obliquely upper position of the conductor 40, that is, the distance between the gate line 30 and the substrate 10. If the distance between the conductor 40 and the substrate 10 is greater than the distance between the gate electrode 30 and the conductor 40, the problem of mis-conduction or mutual interference may occur, resulting in incorrect or inaccurate signal extraction. The conductive body 40 and the gate line 30 are disposed at different levels through the present invention, so that the electric field attracting ions caused by the electric field caused by the voltage on both sides of the column body 20 can be prevented from causing the columnar body 20 to form an electrical conduction path. 71 problem.
S7：製備電容，於完成該閘極線30以及該導電體40之製作後，請配合參閱「圖2」所示，進行電容製程以形成電容結構50於該柱狀體20遠離該基底10之一端。S7: preparing a capacitor, after completing the fabrication of the gate line 30 and the conductor 40, please perform a capacitor process to form a capacitor structure 50 in the column 20 away from the substrate 10, as shown in FIG. 2 One end.
綜上所述，由於本發明僅於該柱狀體20具有該主控制壁21之一側形成該閘極線30，並透過複數與該閘極線30電性連接的導電體40控制該柱狀體20兩端之電性導通狀態，而解決習知技術必須對閘極進行蝕刻分離，因蝕刻位置以及蝕刻時間控制困難而造成蝕刻不均或蝕刻未完全分離的問題。除此之外，本發明將該閘極線30及該導電體40設置於不同高度，而避免誤導通或訊號干擾的問題。最後，本發明揭露一種製作該垂直式電晶體的方法，該方法係先形成該通道71以及該凹槽72，並利用氣相沉積的方式一體形成該閘極線30以及該導電體40，具有製作方便之特點。因此本發明極具進步性及符合申請發明專利之要件，爰依法提出申請，祈 鈞局早日賜准專利，實感德便。In summary, the present invention only forms the gate line 30 on the side of the column body 20 having the main control wall 21, and controls the column through a plurality of electrical conductors 40 electrically connected to the gate line 30. The electrical conduction state of the two ends of the body 20 solves the problem that the gate must be etched and separated by the prior art, and the etching position and the etching time are difficult to control, resulting in uneven etching or incomplete etching. In addition, the present invention sets the gate line 30 and the conductor 40 at different heights to avoid the problem of mis-conduction or signal interference. Finally, the present invention discloses a method for fabricating the vertical transistor. The method first forms the channel 71 and the recess 72, and integrally forms the gate line 30 and the conductor 40 by vapor deposition. Easy to make. Therefore, the present invention is highly progressive and conforms to the requirements of the invention patent application, and the application is filed according to law, and the praying office grants the patent as soon as possible.
以上已將本發明做一詳細說明，惟以上所述者，僅為本發明之一較佳實施例而已，當不能限定本發明實施之範圍。即凡依本發明申請範圍所作之均等變化與修飾等，皆應仍屬本發明之專利涵蓋範圍內。The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the present application should remain within the scope of the patent of the present invention.
1．．．柱狀體1. . . Columnar body
2．．．閘極2. . . Gate
3．．．導線3. . . wire
4．．．電容4. . . capacitance
10．．．基底10. . . Base
11．．．位元線11. . . Bit line
12．．．第一溝渠12. . . First ditches
121．．．氧化物121. . . Oxide
122．．．氮化矽層122. . . Tantalum nitride layer
123．．．氧化材質123. . . Oxidized material
14．．．隔離層14. . . Isolation layer
15．．．第二溝渠15. . . Second ditches
20．．．柱狀體20. . . Columnar body
21．．．主控制壁twenty one. . . Main control wall
22．．．輔助控制壁twenty two. . . Auxiliary control wall
23．．．保護層twenty three. . . The protective layer
30．．．閘極線30. . . Gate line
40．．．導電體40. . . Electrical conductor
50．．．電容結構50. . . Capacitor structure
61．．．蝕刻停止層61. . . Etch stop layer
62．．．蝕刻區域62. . . Etched area
63．．．隔離段63. . . Isolated segment
71．．．通道71. . . aisle
72．．．凹槽72. . . Groove
73．．．第一絕緣層73. . . First insulating layer
74．．．第二絕緣層74. . . Second insulating layer
81．．．第一方向81. . . First direction
82．．．第二方向82. . . Second direction
圖1，為習知技術之立體結構示意圖。FIG. 1 is a schematic perspective view of a conventional technique.
圖2，為本發明一較佳實施例之立體結構示意圖。2 is a schematic perspective view of a preferred embodiment of the present invention.
圖3A-3E，為本發明一較佳實施例之柱狀體製程流程示意圖。3A-3E are schematic views showing the flow of a column-shaped mechanism according to a preferred embodiment of the present invention.
圖4A-4C，為本發明一較佳實施例之柱狀體分割多面示意圖。4A-4C are schematic diagrams showing the multi-faceted division of a columnar body according to a preferred embodiment of the present invention.
圖5A-5C，為本發明一較佳實施例之蝕刻停止層設置多面示意圖。5A-5C are schematic diagrams showing the arrangement of an etch stop layer according to a preferred embodiment of the present invention.
圖6A-6B，為本發明一較佳實施例之蝕刻設置多面示意圖。6A-6B are schematic diagrams showing multiple aspects of an etching setup in accordance with a preferred embodiment of the present invention.
圖7A-7B，為本發明一較佳實施例之填充絕緣材質示意圖。7A-7B are schematic views of a filled insulating material according to a preferred embodiment of the present invention.
圖8A-8B，為本發明一較佳實施例之容置空間成形示意圖。8A-8B are schematic views showing the formation of an accommodation space according to a preferred embodiment of the present invention.
圖9A-9B，為本發明一較佳實施例之導電體成形示意圖。9A-9B are schematic views showing the formation of an electric conductor according to a preferred embodiment of the present invention.
10．．．基底10. . . Base
11．．．位元線11. . . Bit line
20．．．柱狀體20. . . Columnar body
21．．．主控制壁twenty one. . . Main control wall
22．．．輔助控制壁twenty two. . . Auxiliary control wall
30．．．閘極線30. . . Gate line
40．．．導電體40. . . Electrical conductor
50．．．電容結構50. . . Capacitor structure
73．．．第一絕緣層73. . . First insulating layer
74．．．第二絕緣層74. . . Second insulating layer
81．．．第一方向81. . . First direction
82．．．第二方向82. . . Second direction
Claims (12)
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI291218B (en) * | 2006-03-10 | 2007-12-11 | Promos Technologies Inc | Vertical-type surrounding gate semiconductor device |
| US7326611B2 (en) * | 2005-02-03 | 2008-02-05 | Micron Technology, Inc. | DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays |
| TW201017771A (en) * | 2008-10-29 | 2010-05-01 | Nanya Technology Corp | Vertical transistor and fabricating method thereof and vertical transistor array |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7326611B2 (en) * | 2005-02-03 | 2008-02-05 | Micron Technology, Inc. | DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays |
| TWI291218B (en) * | 2006-03-10 | 2007-12-11 | Promos Technologies Inc | Vertical-type surrounding gate semiconductor device |
| TW201017771A (en) * | 2008-10-29 | 2010-05-01 | Nanya Technology Corp | Vertical transistor and fabricating method thereof and vertical transistor array |
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