TWI467733B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI467733B
TWI467733B TW101117315A TW101117315A TWI467733B TW I467733 B TWI467733 B TW I467733B TW 101117315 A TW101117315 A TW 101117315A TW 101117315 A TW101117315 A TW 101117315A TW I467733 B TWI467733 B TW I467733B
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Taiwan
Prior art keywords
semiconductor
wire segment
semiconductor package
electrical connection
stacked
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TW101117315A
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English (en)
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TW201349438A (zh
Inventor
唐紹祖
蔡瀛洲
藍章益
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矽品精密工業股份有限公司
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Priority to TW101117315A priority Critical patent/TWI467733B/zh
Priority to CN2012101815937A priority patent/CN103426870A/zh
Publication of TW201349438A publication Critical patent/TW201349438A/zh
Application granted granted Critical
Publication of TWI467733B publication Critical patent/TWI467733B/zh

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Description

半導體封裝件及其製法
本發明係關於半導體封裝件，特別是關於一種藉由銲線接合達成細間距及微小化需求之半導體封裝件及其製法。
在現行覆晶技術中，如第1A圖所示，覆晶式半導體封裝件1係包括一具有複數覆晶銲墊100之封裝基板10與一具有複數電極墊110之晶片11，且該些電極墊110上會設置預銲錫材以結合該覆晶銲墊100，再回銲該預銲錫材以形成銲錫凸塊12，以提供該晶片11與該封裝基板10間的電性輸入/輸出(I/O)及機械性的連接；之後，再使用底膠(underfill)14耦合該晶片11與該封裝基板10，以確保該晶片11與該封裝基板10間之電性連接的完整性與可靠性。
一般製作該銲錫凸塊12的步驟，係先形成圖案化光阻(圖略)於該晶片11上以外露該電極墊110，再依序電鍍出銅柱與預銲錫材於該電極墊110上，接著移除該光阻，最後經回銲製程以形成銲錫凸塊12。因該銅柱於回銲製程中不會改變形狀，故能有效控制該銲錫凸塊12的高度與體積，以避免產生共面性(coplanarity)不良或橋接短路等現象，因而可達到覆晶結構對凸塊之細間距(Fine Pitch)的要求。
惟，製作該銲錫凸塊12時，需經圖案化製程與電鍍 製程，導致步驟繁多，製程時間冗長，因而不利於提高產能，且電鍍成本高，因而難以降低產品之成本。
再者，習知半導體封裝件1中，如第1A’圖所示，因該銲錫凸塊12之最小徑寬r為80μm，故該些覆晶銲墊100之徑寬R至少需為120μm，使各該銲錫凸塊12之間保持一定距離，以避免回銲時發生接點橋接現象而造成短路，但卻因此無法再縮小各該覆晶銲墊100之徑寬R與間距y，致使該封裝基板10之佈設面積無法縮減，且其佈線密度無法提高，以致於無法進一步微小化封裝件，且難以再提升電性功能。
另一方面，隨著電子產品輕薄短小及系統整合的趨勢，使得半導體封裝件之空間運用更加重要，而為了提高單一半導體封裝件之性能以符合電子產品輕薄短小之需求，係藉由將至少兩晶片組合在單一半導體封裝件中，以縮減電子產品整體電路結構體積，並提昇電性功能，例如，使系統運作速度之限制最小化，且減少晶片間連接線路之長度而降低訊號延遲及存取時間。
近年來，係使用堆疊方法增加晶片之數量以節省基板使用空間，如第20090068790號美國專利或如第1B圖所示之半導體封裝件1’，各晶片11’係利用重佈線路層(Redistribution layer,RDL)之製程於該電極墊110’上形成複數向外延伸凸出有複數導電體13，再將各該晶片11’垂直堆疊於一具有複數電性連接墊100’之基板10’上，接著利用脈沖方法塗佈複數導電膠粒12’以電性連接該導 電體13與該電性連接墊100’。之後，再進行封裝製程(圖略)。
惟，習知具堆疊晶片11’之半導體封裝件1’中，該導電膠粒12’係為膠材，其與金屬材(如該導電體13或電性連接墊100’)之間的電性接合的可靠度並不佳。
再者，因該導電膠粒12’之寬度相當大，致使該基板10’上之各該電性連接墊100’的間距z需夠大(如第1B’圖所示，該間距z大於200um)，以避免各該導電膠粒12’相接觸而造成短路，故該基板10’需具有較大的承載面積以佈設該些電性連接墊100’，導致該基板10’仍需維持一定尺寸而難以再縮小，以致於無法進一步微小化封裝件。
因此，如何克服上述習知技術之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝件，係包括：一基板，係具有複數電性連接墊；至少一半導體元件，係具有相對之第一表面與第二表面及與該第一與第二表面相接之側面，該半導體元件以其第一表面置放於該基板上，且該第一表面上具有複數電極墊；以及銲線段，係具有相對之第一端與第二端，該銲線段以其第一端形成於該電極墊上，並朝該半導體元件側面向外之方向延伸，以令該銲線段之第二端結合該電性連接墊。
本發明復提供一種半導體封裝件之製法，係包括：提供至少一半導體元件，該半導體元件具有相對之第一表面與第二表面及與該第一與第二表面相接之側面，該第一表 面上具有複數電極墊；形成銲線段於該電極墊上，該銲線段具有相對之第一端與第二端，該銲線段以其第一端形成於該電極墊上，且該銲線段之第二端朝該半導體元件側面向外之方向延伸；以及使該半導體元件以其第一表面置放於一具有複數電性連接墊之基板上，且該電性連接墊結合該銲線段之第二端。
前述之半導體封裝件及其製法中，該銲線段之第二端具有金屬球部；或者，該電性連接墊上可具有導電凸塊。
前述之半導體封裝件及其製法中，該半導體元件係為複數時，各該半導體元件為相互堆疊，例如，階梯狀堆疊、垂直對齊堆疊、交錯堆疊、或部分垂直對齊堆疊而部分階梯狀堆疊；且該些半導體元件係相互電性連接，例如以該銲線段作電性連接或以該銲線段之第二端之導電層作電性連接。其中，該銲線段之第二端係進行化鍍製程或浸錫製程作電性連接。
前述之半導體封裝件及其製法中，復包括形成導電層於該電性連接墊上以包覆該銲線段之部分表面，且形成該導電層之方式係為化鍍製程或浸錫製程。
前述之半導體封裝件及其製法中，復包括形成絕緣材料於該電性連接墊上以包覆該銲線段之部分表面，且該絕緣材料復形成於該基板上。另外，形成該絕緣材料之方式係為點膠製程、填充底膠製程或模壓封裝製程。
由上可知，本發明之半導體封裝件及其製法中，因封裝製程中，打線技術是最簡易、快速、步驟少、成本低的電性連接方式，故藉由打線技術製作銲線段，以克服習知覆晶凸塊製程之步驟多、成本高、製程時間長等缺失，故 有利於提高產能。
再者，本發明藉由銲線段之線寬遠小於習知銲錫凸塊之徑寬與習知導電膠粒之寬度，故該些電性連接墊的間距可大幅縮減以滿足細間距之需求，使該基板不僅其尺寸可相對縮小，且仍可佈設足夠之電性連接墊，因而能達到微小化之需求。
又，相較於習知導電膠材，本發明之銲線段與電性連接墊之間或各該銲線段之間的電性接合之可靠度較佳。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“前”、“後”、“左”、“右”、“側面”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。例如，本發明中，第一表面之“第一”係指形成電極墊 之表面，而非限定所有半導體元件之第一表面皆為相同之用途。
請參閱第2A至2E圖，係為本發明之半導體封裝件2之第一實施例之製法之剖面示意圖。
如第2A圖所示，提供一半導體元件21，其具有相對之第一表面21a與第二表面21b及相鄰該第一與第二表面21a,21b之側面21c，該第一表面21a上具有複數電極墊210。於本實施例中，該半導體元件21可為晶片、晶圓或被動元件。
如第2B圖所示，形成一銲線段22於各該電極墊210上，且該銲線段22之一端端朝該半導體元件21之側面21c向外之方向延伸。
於本實施例中，該銲線段22之材質包含金、銀或銅材，且製作該銲線段22之方式係為打短線製程，其只需應用一般打線製程，例如：使用一般打線設備於拉出所需銲線長度後，再將銲線截斷即可；之後，可選擇性於該半導體元件21之表面上形成保護膜(圖略)。
再者，所述之銲線段22具有相對之第一端22a與第二端22b(末端)，第一端22a係結合於該電極墊210上，而第二端22b係為截斷端。
如第2C圖所示，將該半導體元件21以其第一表面21a置放於一具有複數電性連接墊200之基板20上，且該電性連接墊200結合該銲線段22之第二端22b。此外，可使用黏晶膜於該半導體元件21與基板20以加強其機械性的連 接。
於本實施例中，該電性連接墊200之材質包含銅或鋁，且可於該電性連接墊200上形成如鎳/金材之表面處理層(圖略)。
再者，雖然該半導體元件21以覆晶方式結合於該基板20上，但係藉由該銲線段22取代習知覆晶接合用之銲錫凸塊，而該銲線段22之徑寬係遠小於習知銲錫凸塊之徑寬，故該些電性連接墊200之結合面積可較小，例如設計為手指狀(finger)之打線墊，而無須設計成結合面積較大之覆晶銲墊，以利於提升佈線密度。
具體地，如第2C’圖所示，於打短線製程中之銲線段22之長度L約100um(含上下延伸部分)，該電性連接墊200之長度D(如90um)可小於習知覆晶銲墊之徑寬(120um)，而該電性連接墊200之寬度大於該銲線段22之線寬即可，故該些電性連接墊200所需之結合面積遠小於習知覆晶銲墊所需之結合面積。因此，該基板20不僅其尺寸可相對縮小，且仍可佈設足夠之電性連接墊200，故能有效縮小該基板20之尺寸，以達到微小化之需求。
又，各該電性連接墊200的間距x約20至30μm，且依該銲線段22之延伸方向變化(即前、後、左、右方向)，各該電性連接墊200的間距x大小可作調整，以滿足細間距之需求，而利於提升佈線密度及達到微小化之目的。
另外，可依需求，交錯排列該些電性連接墊200’，如第2C”圖所示，相鄰之兩電性連接墊200的間距約0μm， 而相間隔之兩電性連接墊200的間距x’約20至30μm，以滿足彈性佈線之需求，且更能提升佈線密度。例如，第2C”圖之各該銲線段22的間距t’小於第2C’圖之各該銲線段22的間距t，且即使各該銲線段22的間距t,t’如此小，各該銲線段22仍不會發生銲線橋接現象。
如第2D圖所示，形成一導電層23於該電性連接墊200上，以包覆該銲線段22之第二端22b，俾供加強該銲線段22與該電性連接墊200之間的連接力。然而，於其它實施例中，可不形成該導電層23。
於本實施例中，形成該導電層23之方式係為化鍍製程、電鍍製程、浸錫製程或點膠製程。
所述之化鍍製程係利用金屬氧化還原的化學反應，選擇性沈積一層金屬材於金屬表面。其中，該化鍍製程係使用化鍍液進行作業，而該化鍍液之種類繁多，例如，化銅鍍液係含硫酸銅(Copper Surfate)、甲醛(Formaldehyde)及甲醇(Methanol)；化鎳鍍液係含檸檬酸銨(Ammoniun Citrate)、NH4 Cl、六水合氯化鎳(Nickel Chloride Hexahydrate)、次磷酸鈉(Sodium Hypophosphite)、乙二胺四乙酸鹽(Ethylene Diamine Tetracetate)及氫氧化銨(Ammoniun Hydroxide)；化錫鍍液係含甲基磺酸錫(Tin(II)Methanesulphonate)、甲磺酸(Methanesulphonic Acid)及硫脲(Thiourea)；化銀鍍液係含丙醇(Propyl Alcohol)、鹽酸(Hydrochloric Acid)及氯化亞錫(Stannous Chloride)，但該化鍍液之種類並不限於上述。
所述之浸錫製程係利用金的散錫性，以於該銲線段22之第二端22b及該電性連接墊200上沾一層錫材。
所述之點膠製程係為最簡易的方式，即以如銀膠、銅膏之導電膠(圖未示)包覆該銲線段22之第二端22b，但須考量該導電膠之熱膨脹係數及電性之相關條件。
如第2E圖所示，進行模壓封裝製程，係形成絕緣材料24(即封裝膠體)於該基板20上，以包覆該半導體元件21與銲線段22(或該導電層23)。
於另一實施中，如第2E’圖所示，係利用填充底膠(underfill)製程形成絕緣材料24’於該電性連接墊200上，以包覆該銲線段22之第二端22b(或該導電層23)；於其它實施例中，亦可利用點膠製程形成絕緣材料。
再者，形成絕緣材料24,24’之方式繁多保，並不限於上述。
本發明之製法係利用打線製程之設備製作該銲線段22，因打線技術已相當成熟，故應用於打短線方式，可使製程簡易、快速，且因製程步驟少、成本低，而有利於提高產能(Unit Per Hour,UPH)，並能降低成本。
請參閱第3圖，係為本發明之半導體封裝件3之第二實施例之剖面示意圖。本實施例與第一實施例之差異僅在於該銲線段32之第二端32b復選擇性形成有金屬球部320，且該電性連接墊300上復選擇性具有導電凸塊301。
製作時，係於該些電性連接墊300上植設導電凸塊301，且將已設於該半導體元件21上之銲線段32之第二端 32b燒灼成一金屬球部320，再將每一銲線段32之金屬球部320接合該電性連接墊300之導電凸塊301。
於本實施例中，該半導體封裝件3係形成有該金屬球部320與導電凸塊301，而於其它實施例中，可令該半導體封裝件僅形成有金屬球部320或導電凸塊301之其中一者。
再者，可利用化鍍製程、浸錫製程或點膠製程將該金屬球部320與該導電凸塊301作結合，而有關化鍍製程、浸錫製程或點膠製程之相關技術可參考上述內容。
另外，有關該導電凸塊301之種類繁多，例如金屬植球、銅柱(Cu pillar)、銲錫材料(Solder bump)或柱形凸塊(Stud bump)等，並無特別限制。
請參閱第4、5、6及7圖，係揭示本發明半導體封裝件4,5,6,7之第三至六實施例，該些實施例與上述實施例之主要差異在於該半導體封裝件4,5,6,7包括有複數個半導體元件41,41’,51,61,61’,71，且各該半導體元件41,41’,51,61,61’,71係相互堆疊並以其銲線段42,42’,52,62,72進行電性連接。
如第4圖所示，該些半導體元件41,41’係階梯狀堆疊，並以該些銲線段42之金屬球部420作電性接合，且最底部之半導體元件41’之銲線段42(或金屬球部420)係電性連接該電性連接墊200(或導電凸塊301)。而上方之半導體元件41係以覆晶方式堆疊於下方之半導體元件41上，並使複數銲線段42彼此電性連接。
如第5圖所示，該些半導體元件51係垂直對齊堆疊。
如第6圖所示，部分該半導體元件61’係垂直對齊堆疊，而部分該半導體元件61係階梯狀堆疊。
如第7圖所示，該些半導體元件71係交錯堆疊，且該銲線段72(或金屬球部720)係電性連接該半導體元件71之線路(圖略)。
本發明之堆疊結構中，係利用該銲線段42,52,62,72之端部直接燒灼成金屬球部420,520,620,720，再以化鍍或浸錫電性接合相鄰之金屬球部420,520,620,720，故相較於習知技術中之導電膠粒，本發明之金屬球部420,520,620,720能提高電性接合的可靠度。
再者，該金屬球部420,520,620,720之徑寬係遠小於習知技術中之導電膠粒之寬度，因而無須擔憂前、後、左、右方之金屬球部420,520,620,720相接觸而造成短路之問題，故該些電性連接墊200的間距x可大幅縮減(如第2C’圖所示)，使該基板20不僅其尺寸可相對縮小，且仍可佈設足夠之電性連接墊200。因此，本發明能有效縮小該基板20之尺寸，因而突破微小化需求之瓶頸。
又，於第三至六實施例中，以第三實施例為例，如第4’圖所示，最底部之半導體元件41’並可於其它側邊形成銲線段42’，以電性連接該些電性連接墊400。
另外，各該銲線段42,42’,52,62,72可選擇性電性連接，而非所有該銲線段42,42’,52,62,72均需電性連接，且各該銲線段42,42’,52,62,72亦可以其它方式進行電性 連接，如化鍍接合或電鍍接合，亦即將上、下相鄰之銲線段42,42’,52,62,72之端部直接電性接合，而無需以該金屬球部420,520,620,720進行電性連接。
本發明之第一至第六實施例中，該基板20之製程可採用SMT(Surface-mount technology)製程或NSMD(none solder mask define)製程。
再者，該半導體元件具有相對之作用面與非作用面，且其電極墊可依需佈設於該作用面與非作用面上。例如：若以該半導體元件之作用面結合至另一半導體元件或基板上，則於該作用面上佈設電極墊；若以該半導體元件之非作用面結合至另一半導體元件或基板上，則於該非作用面上佈設電極墊。
又，有關該些半導體元件之堆疊方式與電性連接方式繁多，並不限於上述，例如，該銲線段之末端金屬以化鍍製程或浸錫製程進行電性連接。
本發明提供一種半導體封裝件2,2’,3，係包括：一基板20、設於該基板20上之一半導體元件21、以及形成於該半導體元件21上之銲線段22,32。
所述之基板20係具有複數電性連接墊200,300，且可依需求，令該電性連接墊300上具有導電凸塊301。
所述之半導體元件21係具有相對之第一表面21a與第二表面21b及相鄰該第一與第二表面21a,21b之側面21c，該半導體元件21以其第一表面21a置放於該基板20上，且該第一表面21a上具有複數電極墊210。
所述之銲線段22,32係設於該電極墊210上並向該半導體元件21之側面21c方向延伸，且其一端(即第一端22a)結合該電性連接墊200,300，並可依需求，令該銲線段32之一端(即第二端32b)具有金屬球部320。
所述之半導體封裝件2復包括一形成於該電性連接墊200上之導電層23，係用以包覆該銲線段22之部分表面。又包括形成於該電性連接墊200上之絕緣材料24,24’，係包覆該銲線段22。所述之絕緣材料24,24’復形成於該基板20上。
於半導體封裝件4,5,6,7之其它實施例中，該半導體元件41,41’,51,61,61’,71係為複數時，各該半導體元件41,41’,51,61,61’,71係為相互堆疊，例如，該些半導體元件41,41’係階梯狀堆疊；或者，該些半導體元件51係垂直對齊堆疊；或者，部分該半導體元件61’係垂直對齊堆疊，而部分該半導體元件61係階梯狀堆疊；或者，該些半導體元件71係交錯堆疊。
所述之各該半導體元件41,41’,51,61,61’,71並相互電性連接，例如，該些半導體元件41,41’,51,61,61’,71以其銲線段42,52,62,72作電性連接、或以該銲線段42,52,62,72之末端導電層(化鍍製程或浸錫製程形成之，圖略)作電性連接。
綜上所述，本發明之半導體封裝件及其製法，主要藉由打線製程製作銲線段，以令覆晶式封裝件或堆疊式封裝件之製程簡易與快速，且減少製程步驟及降低成本，並能 提高產能。
再者，藉由銲線段之線寬極小，以縮減該些電性連接墊的間距，使該基板之尺寸可相對縮小，因而該半導體封裝件能達到微小化之需求。
又，本發明之銲線段並非膠材，故其與金屬材之間的電性接合之可靠度較佳。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,1’,2,2’,3,4,5,6,7‧‧‧半導體封裝件
10,10’,20‧‧‧基板
100‧‧‧覆晶銲墊
100’,200,200’,300,400‧‧‧電性連接墊
11,11’‧‧‧晶片
110,110’,210‧‧‧電極墊
12‧‧‧銲錫凸塊
12’‧‧‧導電膠粒
13‧‧‧導電體
14‧‧‧底膠
21,31,41,41’,51,61,61’,71‧‧‧半導體元件
21a‧‧‧第一表面
21b‧‧‧第二表面
21c‧‧‧側面
22,32,42,42’,52,62,72‧‧‧銲線段
22a,32a‧‧‧第一端
22b,32b‧‧‧第二端
23‧‧‧導電層
24,24’‧‧‧絕緣材料
301‧‧‧導電凸塊
320,420,520,620,720‧‧‧金屬球部
L,D‧‧‧長度
R,r‧‧‧徑寬
x,x’,y,z,t,t’‧‧‧間距
第1A圖係為習知覆晶式半導體封裝件之剖面示意圖；其中，第1A’圖係為第1A圖省略晶片之局部上視示意圖；第1B圖係為習知具堆疊晶片之半導體封裝件之剖面示意圖；其中，第1B’圖係為第1B圖省略晶片之局部上視示意圖；第2A至2E圖係為本發明之半導體封裝件之第一實施例之製法之剖面示意圖；其中，第2C’圖係為第2C圖省略半導體元件之局部上視示意圖，第2C”圖係為第2C’圖之另一實施例，第2E’圖係為第2E圖之另一實施例；第3圖係為本發明之半導體封裝件之第二實施例之剖面示意圖；以及 第4至7圖係為本發明之半導體封裝件之第三至第六實施例之側視示意圖；其中，第4’圖係為第4圖之上視示意圖。
3‧‧‧半導體封裝件
20‧‧‧基板
300‧‧‧電性連接墊
301‧‧‧導電凸塊
31‧‧‧半導體元件
32‧‧‧銲線段
32a‧‧‧第一端
32b‧‧‧第二端
320‧‧‧金屬球部

Claims (17)

  1. 一種半導體封裝件，係包括：一基板，係具有複數電性連接墊；複數半導體元件，係相互堆疊，且各具有相對之第一表面與第二表面及與該第一與第二表面相接之側面，其中一方之該半導體元件以其第一表面置放於該基板上，且各該第一表面上具有複數電極墊；以及銲線段，係具有相對之第一端與第二端，該銲線段以其第一端形成於各該電極墊上，並朝該半導體元件側面向外之方向延伸，以令部分該銲線段之第二端結合該電性連接墊，其中，該些半導體元件係以該銲線段作電性連接。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該銲線段之第二端具有金屬球部。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該電性連接墊上具有導電凸塊。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該些半導體元件係以該銲線段之第二端之導電層作電性連接。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該些半導體元件係階梯狀堆疊、垂直對齊堆疊或交錯堆疊。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，部分該半導體元件係垂直對齊堆疊，而部分該半導體 元件係階梯狀堆疊。
  7. 如申請專利範圍第1項所述之半導體封裝件，復包括導電層，係形成於該電性連接墊上，以包覆該銲線段之部分表面。
  8. 如申請專利範圍第1項所述之半導體封裝件，復包括絕緣材料，係形成於該電性連接墊上，以包覆該銲線段之部分表面。
  9. 一種半導體封裝件之製法，係包括：提供複數相互堆疊之半導體元件，各該半導體元件具有相對之第一表面與第二表面及與該第一與第二表面相接之側面，該第一表面上具有複數電極墊；形成銲線段於該電極墊上，該銲線段具有相對之第一端與第二端，該銲線段以其第一端形成於該電極墊上，且該銲線段之第二端朝該半導體元件側面向外之方向延伸，又該些半導體元件係以該銲線段作電性連接；以及使其中一方之該半導體元件以其第一表面置放於一具有複數電性連接墊之基板上，且該電性連接墊結合該銲線段之第二端。
  10. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該銲線段之第二端具有金屬球部。
  11. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該些半導體元件之間係以該銲線段之第二端進行化鍍製程或浸錫製程作電性連接。
  12. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，該些半導體元件係階梯狀堆疊、垂直對齊堆疊或交錯堆疊。
  13. 如申請專利範圍第9項所述之半導體封裝件之製法，其中，部分該半導體元件係垂直對齊堆疊，而部分該半導體元件係階梯狀堆疊。
  14. 如申請專利範圍第9項所述之半導體封裝件之製法，復包括形成導電層於該電性連接墊上，以包覆該銲線段之部分表面。
  15. 如申請專利範圍第14項所述之半導體封裝件之製法，其中，形成該導電層之方式係為化鍍製程、電鍍製程或浸錫製程。
  16. 如申請專利範圍第9項所述之半導體封裝件之製法，復包括形成絕緣材料於該電性連接墊上，以包覆該銲線段之部分表面。
  17. 如申請專利範圍第16項所述之半導體封裝件之製法，其中，形成該絕緣材料之方式係為點膠製程、填充底膠製程或模壓封裝製程。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100140783A1 (en) * 2008-12-08 2010-06-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area Around the Device for Electrical Interconnection to Other Devices
US20100308443A1 (en) * 2009-06-08 2010-12-09 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Interconnect Structure with TSV Using Encapsulant for Structural Support
US20110108959A1 (en) * 2005-04-08 2011-05-12 Hembree David R Semiconductor Component Having Through Wire Interconnect With Compressed Bump

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005064362A (ja) * 2003-08-19 2005-03-10 Nec Electronics Corp 電子装置の製造方法及びその電子装置並びに半導体装置の製造方法
CN2805094Y (zh) * 2004-12-30 2006-08-09 威宇科技测试封装有限公司 一种无垫层的多芯片堆叠封装结构
CN1808702A (zh) * 2005-01-20 2006-07-26 矽品精密工业股份有限公司 半导体封装结构及其制法
JP2010021194A (ja) * 2008-07-08 2010-01-28 Toshiba Corp 積層型半導体装置、及び積層型半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110108959A1 (en) * 2005-04-08 2011-05-12 Hembree David R Semiconductor Component Having Through Wire Interconnect With Compressed Bump
US20100140783A1 (en) * 2008-12-08 2010-06-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area Around the Device for Electrical Interconnection to Other Devices
US20100308443A1 (en) * 2009-06-08 2010-12-09 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Interconnect Structure with TSV Using Encapsulant for Structural Support

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