TWI467694B - A bottom source power metal-oxide-semiconductor fiedld-effect transistor device and production methods - Google Patents
A bottom source power metal-oxide-semiconductor fiedld-effect transistor device and production methods Download PDFInfo
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本發明是有關於一種半導體元件結構及其製作方法，特別是關於一種底部具有源極的功率元件及其製作方法。元件及其製作方法。 The present invention relates to a semiconductor device structure and a method of fabricating the same, and more particularly to a power device having a source at the bottom and a method of fabricating the same. Components and how to make them.
垂直式功率金氧半場效電晶體(MOSFET)之晶片，於一般情況下，源極及閘極設置於晶片之正面，而將汲極設置於晶片之底部。在實際應用上，製造者往往期望功率金氧半場效電晶體之源極設置於晶片之底部，常見如利用堆疊晶片之封裝結構構成之直流電源轉換器。而在某些情況下，如將封裝體之晶片基座作為地極時，則必須使用底部具有源極之功率金氧化場效電晶體。 In a vertical power MOS field-effect transistor (MOSFET) wafer, in general, the source and gate are disposed on the front side of the wafer, and the drain is disposed on the bottom of the wafer. In practical applications, manufacturers often expect the source of the power MOS field-effect transistor to be placed at the bottom of the wafer, such as a DC power converter constructed using a package structure of stacked chips. In some cases, such as when the wafer base of the package is used as a ground electrode, it is necessary to use a power gold oxide field effect transistor having a source at the bottom.
請參閱第1圖，其係為一種習知底部具有源極的功率元件之示意圖。在元件之晶片100正面設置一閘極和一源極，其表面對應形成一閘極金屬層120和一源極金屬層110，源極金屬層110的表面更設置一源極軟焊層111。元件之晶片100背面設有一汲極，其表面具有一汲極金屬層130，且汲極金屬層130之表面亦設有一汲極 軟焊層131。元件之晶片100更設有一閘極引導體121，其一端與閘極金屬層120電性連接，另一端向上穿過元件之晶片100，延伸曝露於功率元件之頂面外，以形成可與外部元件連接之閘極區域。閘極引導體121之外部覆有氧化物，且其內部填充金屬，透過該氧化物，可將閘極引導體121與元件之晶片100絕緣隔離。元件之晶片100絕緣隔離。元件之晶片100絕緣隔離。元件之晶片100絕緣隔離。元件之晶片100絕緣隔離。元件之晶片100絕緣隔離。元件之晶片100絕緣隔離。元件之晶片100絕緣隔離。 Please refer to FIG. 1 , which is a schematic diagram of a conventional power element having a source at the bottom. A gate and a source are disposed on the front surface of the wafer 100 of the device, and a gate metal layer 120 and a source metal layer 110 are formed on the surface of the wafer 100, and a source solder layer 111 is further disposed on the surface of the source metal layer 110. The back surface of the wafer 100 of the device is provided with a drain having a drain metal layer 130 on the surface thereof and a drain electrode on the surface of the drain metal layer 130. Solder layer 131. The wafer 100 of the component further includes a gate guiding body 121, one end of which is electrically connected to the gate metal layer 120, and the other end of which extends upwardly through the wafer 100 of the component, and is extended and exposed outside the top surface of the power component to form an external The gate region where the components are connected. The gate of the gate guiding body 121 is covered with an oxide, and the inside thereof is filled with a metal. The oxide guiding body 121 can insulate the gate guiding body 121 from the wafer 100 of the element. The wafer 100 of the component is insulated and isolated. The wafer 100 of the component is insulated and isolated. The wafer 100 of the component is insulated and isolated. The wafer 100 of the component is insulated and isolated. The wafer 100 of the component is insulated and isolated. The wafer 100 of the component is insulated and isolated. The wafer 100 of the component is insulated and isolated.
同時，在功率元件之底部，源極金屬層110及源極軟焊層111與閘極金屬層120之間，設有一鈍化層140以彼此絕緣隔離，且閘極金屬層120完全包裹於鈍化層140中。在功率元件之頂部，汲極金屬層130及汲極軟焊層131，與閘極引導體121及其所形成之閘極區域之間，亦有鈍化層140加以絕緣隔離。源極軟焊層111之頂面，以及汲極軟焊層131之底面，各自曝露在功率元件之頂面及底面之外，形成可與外部元件電性連接之汲極區域和源極區域。意即，閘極區域和汲極區域位於功率元件之頂部；源極區域位於功率元件之底部。元件之底部。元件之底部。元件之底部。元件之底部。元件之底部。 Meanwhile, at the bottom of the power component, between the source metal layer 110 and the source solder layer 111 and the gate metal layer 120, a passivation layer 140 is provided to be insulated from each other, and the gate metal layer 120 is completely wrapped around the passivation layer. 140. On the top of the power device, the drain metal layer 130 and the gate solder layer 131 are insulated from the gate conductor 121 and the gate region formed by the passivation layer 140. The top surface of the source solder layer 111 and the bottom surface of the drain solder layer 131 are each exposed outside the top surface and the bottom surface of the power device to form a drain region and a source region electrically connectable to external components. That is, the gate region and the drain region are located at the top of the power device; the source region is located at the bottom of the power device. The bottom of the component. The bottom of the component. The bottom of the component. The bottom of the component. The bottom of the component.
請參閱第2圖，其係為另一種習知底部具有源極的功率元件之示意圖。如圖所示，晶片基板200正面具有一二氧化矽之起始層201，在起始層201上設有閘極220和源極210，且其表面分別設有一閘極金屬層221和一源極金屬層211。閘極220及閘極金屬層221與源極210及源極金屬層211之間，藉由一絕緣層240相互隔離。源極金屬層211上更設有一錫球212。在進行封裝時，利用一塑封體 250將曝露於絕緣層240外表面之閘極金屬層221，及源極金屬層211上錫球212之週邊部份包覆。將設有源極及閘極之表面朝下，以作為功率元件之底部時，錫球212之底面曝露於塑封體250之底面外，進而形成晶片可與外部元件連通之源極區域。元件之底部時，錫球212之底面曝露於塑封體250之底面外，進而形成晶片可與外部元件連通之源極區域。元件之底部時，錫球212之底面曝露於塑封體250之底面外，進而形成晶片可與外部元件連通之源極區域。 Please refer to FIG. 2, which is a schematic diagram of another conventional power element having a source at the bottom. As shown in the figure, the front surface of the wafer substrate 200 has a starting layer 201 of germanium dioxide, a gate 220 and a source 210 are disposed on the starting layer 201, and a gate metal layer 221 and a source are respectively disposed on the surface thereof. Polar metal layer 211. The gate 220 and the gate metal layer 221 are separated from the source 210 and the source metal layer 211 by an insulating layer 240. A solder ball 212 is further disposed on the source metal layer 211. Use a plastic seal when packaging 250 covers the gate metal layer 221 exposed on the outer surface of the insulating layer 240 and the peripheral portion of the solder ball 212 on the source metal layer 211. When the surface of the source and the gate is facing downward, as the bottom of the power component, the bottom surface of the solder ball 212 is exposed outside the bottom surface of the molding body 250, thereby forming a source region where the wafer can communicate with external components. At the bottom of the component, the bottom surface of the solder ball 212 is exposed outside the bottom surface of the molding body 250 to form a source region where the wafer can communicate with external components. At the bottom of the component, the bottom surface of the solder ball 212 is exposed outside the bottom surface of the molding body 250 to form a source region where the wafer can communicate with external components.
對應功率元件之頂部，在晶片基板200之背面設置一汲極金屬層230，以成為與外部元件連接之汲極區域。從功率元件之頂面向下對應閘極220之位置開設一孔槽260。該孔槽260依序貫穿汲極金屬層230、晶片基板200和二氧化矽起始層201，並使閘極220之頂面曝露於孔槽260之底面外，進而形成可與外部元件連接之閘極區域。在此結構中，汲極區域與於孔槽260中曝露之閘極區域，位於功率元件之頂部，而源極區域位於功率元件之底部。元件之底部。元件之底部。元件之底部。元件之底部。 On the top of the corresponding power device, a drain metal layer 230 is disposed on the back surface of the wafer substrate 200 to become a drain region connected to the external component. An aperture slot 260 is defined from the top of the power component facing the lower gate 220. The hole 260 sequentially penetrates the gate metal layer 230, the wafer substrate 200, and the ceria starting layer 201, and exposes the top surface of the gate 220 to the bottom surface of the hole 260, thereby forming a connection with an external component. Gate area. In this configuration, the drain region and the gate region exposed in the trench 260 are at the top of the power device and the source region is at the bottom of the power device. The bottom of the component. The bottom of the component. The bottom of the component. The bottom of the component.
有鑑於上述習知技藝之問題，本發明之其中一目的就是在提供一種底部具有源極的功率元件，可以使其源極曝露設置於具有源極的功率元件之底部，進而使曝露設置於具有源極的功率元件之頂部的汲極和閘極之間具有良好的絕緣保護，且可應用於厚度為超薄基板(substrate less)等級之晶片上，並有效減少光罩之使用，進而簡化製作流程。元件之頂部的汲極和閘極之間具有良好的絕緣保護，且可應用於厚度為超薄基板(substrate less)等 級之晶片上，並有效減少光罩之使用，進而簡化製作流程。元件之頂部的汲極和閘極之間具有良好的絕緣保護，且可應用於厚度為超薄基板(substrate less)等級之晶片上，並有效減少光罩之使用，進而簡化製作流程。 In view of the above-mentioned problems of the prior art, one of the objects of the present invention is to provide a power element having a source at the bottom, which can have its source exposed at the bottom of the power element having the source, thereby allowing the exposure to be set to have The source power element has good insulation protection between the drain and the gate at the top, and can be applied to a substrate having a thickness of a thin substrate, and the use of the photomask is effectively reduced, thereby simplifying the fabrication. Process. The bottom of the component has good insulation protection between the drain and the gate, and can be applied to a substrate with a thickness of less than a thin substrate. The level of the wafer, and effectively reduce the use of the mask, thereby simplifying the production process. The top of the component has good insulation protection between the drain and the gate, and can be applied to a substrate with a thickness of the substrate less, and the use of the mask is effectively reduced, thereby simplifying the manufacturing process.
根據本發明之一目的，提出一種底部具有源極的功率元件，其包含：一汲極、一閘極及一源極且其相互絕緣隔離，並可分別與外部元件電性連接。汲極、一閘極及一源極且其相互絕緣隔離，並可分別與外部元件電性連接。 According to an aspect of the present invention, a power device having a source at the bottom includes a drain, a gate, and a source and is insulated from each other and electrically connected to an external component. The drain, the gate and the source are insulated from each other and can be electrically connected to the external components.
其中，源極形成在一晶片的正面，晶片的正面朝下，使源極曝露設置於功率金氧半場效電晶體元件之底部。 Wherein, the source is formed on the front side of the wafer, and the front side of the wafer faces downward, so that the source is exposed at the bottom of the power MOS field device.
其中，汲極形成在晶片的背面，晶片的背面朝上，使汲極曝露設置於功率金氧半場效電晶體元件之頂部。 Wherein, the drain is formed on the back side of the wafer, and the back side of the wafer faces upward, so that the drain is exposed on top of the power MOS field device.
其中，閘極形成於晶片的正面，晶片的背面開設有一孔槽，其連通至閘極，孔槽側壁覆蓋有第二絕緣層，孔槽的底面為被第二絕緣層覆蓋，閘極的至少一部分從孔槽中曝露出來，進而使閘極曝露於功率金氧半場效電晶體元件之頂部。 Wherein, the gate is formed on the front surface of the wafer, and the back surface of the wafer defines a hole, which is connected to the gate, and the sidewall of the hole is covered with a second insulating layer, and the bottom surface of the hole is covered by the second insulating layer, and at least the gate is A portion is exposed from the aperture, thereby exposing the gate to the top of the power MOS field device.
其中，晶片包含基板，並在基板正面形成有絕緣的起始層，當晶片正面朝上時，在晶片的正面由下至上依序形成電性連接的源極、源極凸塊和源極金屬層。 Wherein, the wafer comprises a substrate, and an initial layer of insulation is formed on the front surface of the substrate. When the front side of the wafer faces upward, the source, the source bump and the source metal are electrically connected in sequence from the bottom to the top of the wafer. Floor.
其中，源極與閘極分別形成在晶片的起始層上。 Wherein the source and the gate are respectively formed on the starting layer of the wafer.
其中，在源極和閘極的外表面更設置第一絕緣層，並使源極的頂面上至少有一部分從第一絕緣層的表面曝露出來。 Wherein, the first insulating layer is further disposed on the outer surface of the source and the gate, and at least a portion of the top surface of the source is exposed from the surface of the first insulating layer.
其中，源極凸塊是透過電鍍形成的金屬塊，其連接在源極曝露的頂面上。 Wherein, the source bump is a metal block formed by electroplating, which is connected to the top surface of the source exposed.
其中，透過在晶片正面進行塑封形成有塑封體，其覆蓋在第一絕緣層及源極凸塊的外表面；並且，透過在晶片正面研磨，使源極凸塊的頂面，曝露在與之齊平的塑封體的頂面之外。 Wherein, a plastic sealing body is formed on the front surface of the wafer to cover the outer surface of the first insulating layer and the source bump; and the top surface of the source bump is exposed by being polished on the front surface of the wafer. Outside the top surface of the flushing plastic body.
其中，源極金屬層是在晶片正面透過金屬化形成的，其覆蓋在源極凸塊及塑封體的頂面；源極金屬層的頂面成為源極與外部元件電性連接的源極。 The source metal layer is formed by metallization on the front side of the wafer, and covers the top surface of the source bump and the molding body. The top surface of the source metal layer serves as a source for electrically connecting the source and the external component.
其中，晶片經由背面研磨，厚度減薄至超薄基板等級，較佳的厚度為小於2微米。 Among them, the wafer is polished by back surface, and the thickness is reduced to an ultra-thin substrate grade, and the thickness is preferably less than 2 micrometers.
其中，在晶片的背面朝上時，透過金屬化形成覆蓋在晶片基板背面的汲極金屬層，其頂面作為汲極與外部元件連接。 Wherein, when the back surface of the wafer faces upward, a gate metal layer covering the back surface of the wafer substrate is formed by metallization, and the top surface thereof is connected as a drain electrode to an external element.
其中，孔槽依次貫穿汲極金屬層、晶片的基板及起始層設置，覆蓋於孔槽側壁之第二絕緣層，延伸到汲極金屬層上環繞孔槽頂部開口一預定距離。 Wherein, the hole grooves are sequentially disposed through the base metal layer, the substrate of the wafer and the starting layer, and cover the second insulating layer on the sidewall of the hole, and extend to the bottom of the hole metal layer to open a predetermined distance around the top of the hole groove.
根據本發明之另一目的，提出一種底部具有源極的功率元件之製作方法，其包含下列步驟：元件之製作方法，其包含下列步驟：步驟1，使一晶片之一基板正面朝上，並於其正面上形成相互絕緣之一閘極和一源極；步驟2，形成一源極凸塊於源極上，並與源極電性連接；步驟3，對晶片之正面進行塑膠封裝，並形成一塑封體； 步驟4，研磨已進行塑膠封裝之晶片，並使源極凸塊之至少一部份表面曝露於塑封體之外；步驟5，使晶片之正面透過金屬化形成一源極金屬層，並使其覆蓋於源極凸塊曝露之表面，且與源極金屬層電性連接，進而使源極金屬層成為源極，並與外部元件連接；步驟6，使晶片之背面朝上，並加以研磨使晶片變薄；步驟7，使晶片背面透過金屬化形成一汲極金屬層，且汲極金屬層覆蓋於晶片之基板之背面；步驟8，於晶片之背面形成一孔槽，並連通至閘極；步驟9，對晶片背面進行絕緣保護；步驟10，去除晶片背面多於之絕緣材料，使汲極金屬層之至少一部份表面曝露於外，並成為可與外部元件連接之汲極，且使閘極之至少一部份表面曝露於孔槽之外，並成為可與外部元件連接之閘極。 According to another object of the present invention, a method for fabricating a power device having a source at the bottom thereof includes the following steps: a method of fabricating a device, comprising the steps of: step 1 of causing a substrate of a wafer to face up, and Forming a gate and a source insulated from each other on the front surface; forming a source bump on the source and electrically connecting the source; and step 3, plastically packaging the front surface of the wafer and forming a plastic seal; Step 4: grinding the wafer that has been plastically packaged, and exposing at least a portion of the surface of the source bump to the outside of the molding body; in step 5, the front side of the wafer is metallized to form a source metal layer, and Covering the exposed surface of the source bump and electrically connecting with the source metal layer, thereby making the source metal layer a source and connecting with the external component; and step 6, bringing the back side of the wafer upward and grinding The wafer is thinned; in step 7, the back surface of the wafer is metallized to form a drain metal layer, and the drain metal layer covers the back surface of the substrate of the wafer; in step 8, a hole is formed in the back surface of the wafer, and is connected to the gate Step 9: performing insulation protection on the back surface of the wafer; in step 10, removing more than the insulating material on the back side of the wafer, exposing at least a portion of the surface of the gate metal layer to the outside, and forming a drain which can be connected to the external component, and At least a portion of the surface of the gate is exposed outside the aperture and becomes a gate connectable to external components.
其中，步驟1中更包含下列步驟：使晶圓之基板之正面形成一絕緣起始層，且閘極及源極設置於絕緣起始層上；使閘極及源極之表面形成一第一絕緣層，並使源極之頂面至少一部份曝露於第一絕緣層之表面。 Wherein, the step 1 further comprises the steps of: forming an insulating starting layer on the front surface of the substrate of the wafer, and the gate and the source are disposed on the insulating starting layer; forming a surface of the gate and the source The insulating layer has at least a portion of the top surface of the source exposed to the surface of the first insulating layer.
其中，步驟2中更包含下列步驟：於源極曝露之頂面，透過電鍍形成金屬材質之源極凸塊，且透過 第一絕緣層將源極凸塊與閘極絕緣隔離。 Wherein, the step 2 further comprises the following steps: forming a source bump of the metal material by electroplating on the top surface of the source exposure, and transmitting The first insulating layer insulates the source bumps from the gates.
其中，步驟3中塑封體包覆第一絕緣層及源極凸塊之外表面，且源極凸塊頂面上覆蓋一定厚度之塑封體。 Wherein, in the step 3, the plastic sealing body covers the outer surfaces of the first insulating layer and the source bump, and the top surface of the source bump is covered with a certain thickness of the plastic sealing body.
其中，步驟4中更包含下列步驟：透過對晶片正面之研磨，使塑封體之頂面與源極凸塊之頂面齊平，並使源極凸塊之頂面曝露於外。 Wherein, in step 4, the method further comprises the steps of: grinding the front surface of the wafer, making the top surface of the molding body flush with the top surface of the source bump, and exposing the top surface of the source bump to the outside.
其中，步驟5中源極金屬層覆蓋於研磨後之塑封體頂面及源極凸塊曝露於外之頂面，且源極透過源極凸塊與源極金屬層電性連接，並藉由源極金屬層之頂面與外部元件電性連接。 Wherein, in step 5, the source metal layer covers the top surface of the molded plastic body and the source bump is exposed on the outer top surface, and the source is electrically connected to the source metal layer through the source bump, and The top surface of the source metal layer is electrically connected to the external component.
其中，步驟6中晶片之背面經研磨，其厚度減薄至超薄基板等級(substrate less)。 Wherein, in step 6, the back side of the wafer is ground, and the thickness thereof is reduced to an ultra-thin substrate less.
其中，步驟8中更包含下列步驟：透過雷射鑽孔法，貫穿晶片之基板及起始層，以形成連通至閘極背面之孔槽。 Wherein, the step 8 further comprises the steps of: through the laser drilling method, through the substrate of the wafer and the starting layer to form a hole connected to the back surface of the gate.
其中，步驟8中汲極金屬層之頂面更設有一第一遮罩板，且第一遮罩板上設有一通孔，該通孔設置在相對於第一遮罩板下方之閘極位置，並於通孔位置利用溼蝕刻法或乾蝕刻法，依序貫穿汲極金屬層、基板及起始層，以形成連通至閘極背面之孔槽。 Wherein, in the step 8, the top surface of the drain metal layer is further provided with a first mask plate, and the first mask plate is provided with a through hole, and the through hole is disposed at a gate position below the first mask plate. And using a wet etching method or a dry etching method to sequentially penetrate the gate metal layer, the substrate, and the starting layer at the via hole position to form a hole connected to the back surface of the gate.
其中，步驟9中晶片之背面具有一第二絕緣層，且第二絕緣層覆蓋於汲極金屬層之頂面與孔槽之側壁及底部。 Wherein, in step 9, the back surface of the wafer has a second insulating layer, and the second insulating layer covers the top surface of the drain metal layer and the sidewalls and the bottom of the hole.
其中，步驟10中第二絕緣層上更設有一第二遮罩板，經過蝕刻後 第二遮罩板所覆蓋之第二絕緣層被保留，其餘未被覆蓋之第二絕緣層則被去除，意即完成蝕刻後，孔槽之側壁與汲極金屬層上方環繞孔槽頂部開口之第二絕緣層被保留，汲極金屬層頂面之其餘未被第二絕緣層覆蓋之部份則成為汲極，且孔槽之底部未被第二絕緣層覆蓋，而使閘極背面之至少一部份曝露於孔槽底部之外，以成為與外部元件電性連接之閘極區域。 Wherein, in the step 10, the second insulating layer is further provided with a second mask plate, after etching The second insulating layer covered by the second mask is retained, and the remaining uncovered second insulating layer is removed, that is, after the etching is completed, the sidewalls of the trench and the top of the drain metal layer surround the top of the trench. The second insulating layer is retained, and the remaining portion of the top surface of the drain metal layer that is not covered by the second insulating layer becomes a drain, and the bottom of the hole is not covered by the second insulating layer, and at least the back surface of the gate is A portion is exposed outside the bottom of the slot to form a gate region that is electrically connected to the external component.
承上所述，依本發明之底部具有源極的功率元件及其製作方法，其可具有一或多個下述優點：元件及其製作方法，其可具有一或多個下述優點： In view of the above, a power component having a source at the bottom of the present invention and a method of fabricating the same can have one or more of the following advantages: an element and a method of fabricating the same, which can have one or more of the following advantages:
(1)此底部具有源極的功率元件及其製作方法，可應用於厚度為超薄基板等級(substrate less)之晶片。元件及其製作方法，可應用於厚度為超薄基板等級(substrate less)之晶片。 (1) The power element having a source at the bottom and a manufacturing method thereof can be applied to a wafer having a thickness of an ultra-thin substrate less. The component and the method of fabricating the same can be applied to a wafer having a thickness of an ultra-thin substrate less.
(2)此底部具有源極的功率元件及其製作方法，整個製作過程中僅使用兩個遮罩板，因而可簡化製作流程。元件及其製作方法，整個製作過程中僅使用兩個遮罩板，因而可簡化製作流程。 (2) The power element with the source at the bottom and the manufacturing method thereof, only two mask plates are used in the whole manufacturing process, thereby simplifying the production process. The components and their manufacturing methods use only two masks throughout the manufacturing process, which simplifies the production process.
(3)此底部具有源極的功率元件及其製作方法，使得汲極區域和曝露於孔槽中之的閘極區域位於功率元件之頂部，並使源極區域位於功率元件之底部，因而使得汲極區域及閘極區域之間，可藉由孔槽內之第二絕緣層以及閘極背面之起始層，對其作絕緣保護且可有效防止擊穿。元件之底部，因而使得汲極區域及閘極區域之間，可藉由孔槽內之第二絕緣層以及閘極背面之起始層，對其作絕緣保護且可有效防止擊穿。元件之底部，因而使得汲極區域及閘極區域之間，可藉由孔槽內之第二絕緣層以及閘極背面之起 始層，對其作絕緣保護且可有效防止擊穿。元件之底部，因而使得汲極區域及閘極區域之間，可藉由孔槽內之第二絕緣層以及閘極背面之起始層，對其作絕緣保護且可有效防止擊穿。 (3) a power element having a source at the bottom and a method of fabricating the same, such that the drain region and the gate region exposed in the hole are located at the top of the power device, and the source region is located at the bottom of the power device, thereby Between the drain region and the gate region, the second insulating layer in the hole and the starting layer on the back surface of the gate can be insulated and can effectively prevent breakdown. The bottom of the component, so that the drain region and the gate region can be insulated by the second insulating layer in the hole and the starting layer on the back surface of the gate, and the breakdown can be effectively prevented. The bottom of the component, so that between the drain region and the gate region, the second insulating layer in the hole and the back of the gate can be used The initial layer is insulated and protected against breakdown. The bottom of the component, so that the drain region and the gate region can be insulated by the second insulating layer in the hole and the starting layer on the back surface of the gate, and the breakdown can be effectively prevented.
100‧‧‧晶片 100‧‧‧ wafer
110‧‧‧源極金屬層 110‧‧‧ source metal layer
111‧‧‧源極軟焊層 111‧‧‧Source solder layer
120‧‧‧閘極金屬層 120‧‧‧ gate metal layer
121‧‧‧閘極引導體 121‧‧‧ gate guide
130‧‧‧汲極金屬層 130‧‧‧汲metal layer
131‧‧‧汲極軟焊層 131‧‧‧汲polar solder layer
140‧‧‧鈍化層 140‧‧‧ Passivation layer
200‧‧‧晶片基板 200‧‧‧ wafer substrate
201‧‧‧起始層 201‧‧‧ starting layer
210‧‧‧源極 210‧‧‧ source
211‧‧‧源極金屬層 211‧‧‧ source metal layer
212‧‧‧錫球 212‧‧‧ solder balls
220‧‧‧閘極 220‧‧‧ gate
221‧‧‧閘極金屬層 221‧‧‧ gate metal layer
230‧‧‧汲極金屬層 230‧‧‧汲metal layer
250‧‧‧塑封體 250‧‧‧plastic body
240‧‧‧絕緣層 240‧‧‧Insulation
260‧‧‧孔槽 260‧‧‧ hole slot
30‧‧‧基板 30‧‧‧Substrate
31‧‧‧起始層 31‧‧‧ starting layer
41‧‧‧源極 41‧‧‧ source
411‧‧‧源極凸塊 411‧‧‧ source bump
412‧‧‧源極金屬層 412‧‧‧ source metal layer
42‧‧‧閘極 42‧‧‧ gate
43‧‧‧汲極金屬層 43‧‧‧汲metal layer
51‧‧‧第一絕緣層 51‧‧‧First insulation
52‧‧‧第二絕緣層 52‧‧‧Second insulation
60‧‧‧塑封體 60‧‧‧plastic body
71‧‧‧第一掩模版 71‧‧‧First reticle
72‧‧‧第二遮罩板 72‧‧‧Second mask
80‧‧‧孔槽 80‧‧‧ hole slot
第1圖係為習知之底部具有源極的功率金氧半場效電晶體元件之結構示意圖。 Figure 1 is a schematic view showing the structure of a conventional power metal oxide half field effect transistor having a source at the bottom.
第2圖係為係為習知之另一底部具有源極的功率金氧半場效電晶體元件之結構示意圖。 Figure 2 is a schematic view showing the structure of a conventional power metal oxide half field effect transistor having a source at the bottom.
第3圖~第14圖係為本發明之係為習知之底部具有源極的功率金氧半場效電晶體元件之流程示意圖，其中，第14圖係為本發明之底部具有源極的功率金氧半場效電晶體元件之結構示意圖。 3 to 14 are flow diagrams of a power MOS field device having a source at the bottom of the present invention, wherein FIG. 14 is a power gold having a source at the bottom of the present invention. Schematic diagram of the structure of an oxygen half field effect transistor component.
為利 貴審查員瞭解本發明之技術特徵、內容與優點及其所能達成之功效，茲將本發明配合附圖，並以實施例之表達形式詳細說明如下，而其中所使用之圖式，其主旨僅為示意及輔助說明書之用，未必為本發明實施後之真實比例與精準配置，故不應就所附之圖式的比例與配置關係解讀、侷限本發明於實際實施上的權利範圍，合先敘明。 The technical features, contents, and advantages of the present invention, as well as the advantages thereof, can be understood by the present inventors, and the present invention will be described in detail with reference to the accompanying drawings. The subject matter is only for the purpose of illustration and description. It is not intended to be a true proportion and precise configuration after the implementation of the present invention. Therefore, the scope and configuration relationship of the attached drawings should not be interpreted or limited. First described.
以下將參照相關圖式，說明依本發明之底部具有源極的功率元件及其製作方法之實施例，為使便於理解，下述實施例中之相同元件係以相同之符號標示來說明。元件及其製作方法之實施例，為使便於理解，下述實施例中之相同元件係以相同之符號標示來說明。 The embodiments of the power elements having a source at the bottom and the method for fabricating the same according to the present invention will be described with reference to the related drawings. For the sake of understanding, the same components in the following embodiments are denoted by the same reference numerals. For the sake of understanding, the same components in the following embodiments are denoted by the same reference numerals.
請參閱第3圖至第14圖，其係為本發明之底部具有源極的功率元 件及其製作方法之示意圖。如圖所示，功率元件之頂部曝露設有可與外部元件電性連接之汲極與閘極，而底部設有源極。進一步地說，在晶片之基板30正面形成一絕緣的起始層31，起始層31向晶片基板30之邊緣延伸，並與晶片基板30之邊緣保有一段距離。起始層31上設有一閘極42和一源極41之電路圖案及一第一絕緣層51。第一絕緣層51覆蓋閘極42之整個外表面，且填充閘極42與源極41之間隙，並延伸覆蓋至源極41外表面之邊緣部份，進而使閘極42與源極41絕緣。閘極42和源極41各自向起始層31之邊緣延伸，並與其保有一段距離。第一絕緣層51所延伸之距離較閘極42與源極41所延伸之距離長。源極41未被第一絕緣層51覆蓋之外表面上設有一金屬製之源極凸塊411，且源極凸塊411高於第一絕緣層51。元件之頂部曝露設有可與外部元件電性連接之汲極與閘極，而底部設有源極。進一步地說，在晶片之基板30正面形成一絕緣的起始層31，起始層31向晶片基板30之邊緣延伸，並與晶片基板30之邊緣保有一段距離。起始層31上設有一閘極42和一源極41之電路圖案及一第一絕緣層51。第一絕緣層51覆蓋閘極42之整個外表面，且填充閘極42與源極41之間隙，並延伸覆蓋至源極41外表面之邊緣部份，進而使閘極42與源極41絕緣。閘極42和源極41各自向起始層31之邊緣延伸，並與其保有一段距離。第一絕緣層51所延伸之距離較閘極42與源極41所延伸之距離長。源極41未被第一絕緣層51覆蓋之外表面上設有一金屬製之源極凸塊411，且源極凸塊411高於第一絕緣層51。元件之頂部曝露設有可與外部元件電性連接之汲極與閘極，而底部設有源極。進一步地說，在晶片之基板30正面形成一絕緣的起始層31，起始層31向晶片基板30之邊緣延伸，並與晶片基板30之邊緣保有一段距離。起始層31上 設有一閘極42和一源極41之電路圖案及一第一絕緣層51。第一絕緣層51覆蓋閘極42之整個外表面，且填充閘極42與源極41之間隙，並延伸覆蓋至源極41外表面之邊緣部份，進而使閘極42與源極41絕緣。閘極42和源極41各自向起始層31之邊緣延伸，並與其保有一段距離。第一絕緣層51所延伸之距離較閘極42與源極41所延伸之距離長。源極41未被第一絕緣層51覆蓋之外表面上設有一金屬製之源極凸塊411，且源極凸塊411高於第一絕緣層51。 Please refer to FIG. 3 to FIG. 14 , which are power elements having a source at the bottom of the present invention. Schematic diagram of the piece and its making method. As shown, the top of the power component is exposed with a drain and a gate electrically connected to the external component, and the bottom is provided with a source. Further, an insulating starting layer 31 is formed on the front surface of the substrate 30 of the wafer, and the starting layer 31 extends toward the edge of the wafer substrate 30 and maintains a distance from the edge of the wafer substrate 30. The starting layer 31 is provided with a circuit pattern of a gate 42 and a source 41 and a first insulating layer 51. The first insulating layer 51 covers the entire outer surface of the gate 42 and fills the gap between the gate 42 and the source 41, and extends to cover the edge portion of the outer surface of the source 41, thereby insulating the gate 42 from the source 41. . The gate 42 and the source 41 each extend toward the edge of the starting layer 31 and are kept at a distance therefrom. The first insulating layer 51 extends a distance longer than the distance over which the gate 42 and the source 41 extend. The source 41 is not covered by the first insulating layer 51, and a metal source bump 411 is disposed on the surface, and the source bump 411 is higher than the first insulating layer 51. The top of the component is exposed with a drain and a gate electrically connected to the external component, and the bottom is provided with a source. Further, an insulating starting layer 31 is formed on the front surface of the substrate 30 of the wafer, and the starting layer 31 extends toward the edge of the wafer substrate 30 and maintains a distance from the edge of the wafer substrate 30. The starting layer 31 is provided with a circuit pattern of a gate 42 and a source 41 and a first insulating layer 51. The first insulating layer 51 covers the entire outer surface of the gate 42 and fills the gap between the gate 42 and the source 41, and extends to cover the edge portion of the outer surface of the source 41, thereby insulating the gate 42 from the source 41. . The gate 42 and the source 41 each extend toward the edge of the starting layer 31 and are kept at a distance therefrom. The first insulating layer 51 extends a distance longer than the distance over which the gate 42 and the source 41 extend. The source 41 is not covered by the first insulating layer 51, and a metal source bump 411 is disposed on the surface, and the source bump 411 is higher than the first insulating layer 51. The top of the component is exposed with a drain and a gate electrically connected to the external component, and the bottom is provided with a source. Further, an insulating starting layer 31 is formed on the front surface of the substrate 30 of the wafer, and the starting layer 31 extends toward the edge of the wafer substrate 30 and maintains a distance from the edge of the wafer substrate 30. On the starting layer 31 A circuit pattern of a gate 42 and a source 41 and a first insulating layer 51 are provided. The first insulating layer 51 covers the entire outer surface of the gate 42 and fills the gap between the gate 42 and the source 41, and extends to cover the edge portion of the outer surface of the source 41, thereby insulating the gate 42 from the source 41. . The gate 42 and the source 41 each extend toward the edge of the starting layer 31 and are kept at a distance therefrom. The first insulating layer 51 extends a distance longer than the distance over which the gate 42 and the source 41 extend. The source 41 is not covered by the first insulating layer 51, and a metal source bump 411 is disposed on the surface, and the source bump 411 is higher than the first insulating layer 51.
對晶片正面進行塑膠封裝，即在第一絕緣層51之整個外表面，以及源極凸塊411週邊未被第一絕緣層51包覆之部份，形成一塑封體60。透過研磨塑封體60之頂面，使源極凸塊411之頂面曝露於與之齊平的研磨後之塑封體60之頂面外。覆蓋一層金屬於源極凸塊411之頂面和塑封體60之頂面，以形成一源極金屬層412，並透過源極凸塊411連通源極41，進而成為晶片可與外部元件連接之源極41。源極金屬層412可以延伸覆蓋至晶片基板30之邊緣。使晶片之正面朝下，進而使得源極位於功率元件之底部。元件之底部。 The package body 60 is formed by plastically encapsulating the front surface of the wafer, that is, the entire outer surface of the first insulating layer 51, and the portion of the source bump 411 not covered by the first insulating layer 51. The top surface of the source bump 411 is exposed to the top surface of the ground molded body 60 which is flush with it by polishing the top surface of the molding body 60. Covering a layer of metal on the top surface of the source bump 411 and the top surface of the molding body 60 to form a source metal layer 412 and connecting the source electrode 41 through the source bump 411, thereby forming the wafer to be connected to external components. Source 41. The source metal layer 412 may extend to cover the edge of the wafer substrate 30. The face of the wafer is facing down so that the source is at the bottom of the power component. The bottom of the component.
請參閱第8圖至第14圖，其係為本發明之底部具有源極的功率元件及其製作方法之示意圖。如圖所示，將晶片之基板30背面朝上，透過研磨使該晶片厚度減薄至超薄基板等級(substrate less)，例如10微米或更薄。在一個具體實施方式中，該晶片減薄至4微米；在另外一個具體實施方式中，該晶片減薄至2微米。一汲極金屬層43覆蓋在晶片之基板30的整個背面上，以形成可與外部元件連接的汲極。由功率金氧半場效電晶體元件之頂面，向下貫穿汲極金屬層43、晶片之基板30及起始層31，以形成連通至閘極 42背面之一孔槽80。一第二絕緣層52覆蓋孔槽80之側壁，且覆蓋汲極金屬層43上環繞孔槽80頂部開口一預定距離內之部份。第二絕緣層52沿孔槽80之側壁延伸至孔槽80之底部並與起始層31連結，孔槽80之底面未被第二絕緣層52覆蓋，使得閘極42背面之其中一部份可曝露於外，以成為晶片可與外部元件連接之閘極區域。簡而言之，汲極和孔槽80中曝露之閘極42位於功率金氧半場效電晶體元件之頂部；源極41位於功率金氧半場效電晶體元件之底部。汲極及閘極42之間係，藉由孔槽80內之第二絕緣層52以及閘極42背面之起始層31絕緣保護，以有效防止擊穿。晶片之基板30及起始層31，以形成連通至閘極42背面之一孔槽80。一第二絕緣層52覆蓋孔槽80之側壁，且覆蓋汲極金屬層43上環繞孔槽80頂部開口一預定距離內之部份。第二絕緣層52沿孔槽80之側壁延伸至孔槽80之底部並與起始層31連結，孔槽80之底面未被第二絕緣層52覆蓋，使得閘極42背面之其中一部份可曝露於外，以成為晶片可與外部元件連接之閘極區域。簡而言之，汲極和孔槽80中曝露之閘極42位於功率金氧半場效電晶體元件之頂部；源極41位於功率金氧半場效電晶體元件之底部。汲極及閘極42之間係，藉由孔槽80內之第二絕緣層52以及閘極42背面之起始層31絕緣保護，以有效防止擊穿。 Please refer to FIG. 8 to FIG. 14 , which are schematic diagrams of a power element having a source at the bottom of the present invention and a manufacturing method thereof. As shown, the back side of the substrate 30 of the wafer is facing upward, and the thickness of the wafer is thinned to an ultra-thin substrate less, for example, 10 microns or less. In one embodiment, the wafer is thinned to 4 microns; in another embodiment, the wafer is thinned to 2 microns. A drain metal layer 43 overlies the entire back surface of the substrate 30 of the wafer to form a drain that can be connected to external components. From the top surface of the power MOS field device, through the drain metal layer 43, the substrate 30 of the wafer, and the starting layer 31 to form a connection to the gate 42 one of the back slots 80. A second insulating layer 52 covers the sidewalls of the trench 80 and covers a portion of the drain metal layer 43 that surrounds the top opening of the trench 80 by a predetermined distance. The second insulating layer 52 extends along the sidewall of the slot 80 to the bottom of the slot 80 and is coupled to the starting layer 31. The bottom surface of the slot 80 is not covered by the second insulating layer 52, so that a part of the back surface of the gate 42 It can be exposed to the outside as a gate region where the wafer can be connected to external components. Briefly, the exposed gate 42 in the drain and slot 80 is located on top of the power MOS field device; the source 41 is located at the bottom of the power MOS field device. The drain electrode and the gate 42 are insulated by the second insulating layer 52 in the hole 80 and the starting layer 31 on the back surface of the gate 42 to effectively prevent breakdown. The substrate 30 of the wafer and the starting layer 31 are formed to communicate with one of the apertures 80 in the back surface of the gate 42. A second insulating layer 52 covers the sidewalls of the trench 80 and covers a portion of the drain metal layer 43 that surrounds the top opening of the trench 80 by a predetermined distance. The second insulating layer 52 extends along the sidewall of the slot 80 to the bottom of the slot 80 and is coupled to the starting layer 31. The bottom surface of the slot 80 is not covered by the second insulating layer 52, so that a part of the back surface of the gate 42 It can be exposed to the outside as a gate region where the wafer can be connected to external components. Briefly, the exposed gate 42 in the drain and slot 80 is located on top of the power MOS field device; the source 41 is located at the bottom of the power MOS field device. The drain electrode and the gate 42 are insulated by the second insulating layer 52 in the hole 80 and the starting layer 31 on the back surface of the gate 42 to effectively prevent breakdown.
請參閱第3圖至第14圖，其係為本發明之功率金氧半場效電晶體元件之製作流程圖。 Please refer to FIG. 3 to FIG. 14 , which are flowcharts for fabricating the power metal oxide half field effect transistor component of the present invention.
步驟1，在晶片正面形成相互絕緣之閘極42及源極41。進一步說，如第3圖所示，使一晶片之正面朝上，在晶片之基板30上形成一絕緣之起始層31，且將一閘極42及一源極41設置於起始層31上 ，並藉由起始層31絕緣隔離以防止擊穿。於閘極42及源極41之外表面形成一第一絕緣層51，意即第一絕緣層51覆蓋閘極42之週邊與整個頂面，及源極41之週邊和頂面之邊緣部份，且源極41曝露於第一絕緣層51頂面之中間部份。 In step 1, a gate 42 and a source 41 which are insulated from each other are formed on the front surface of the wafer. Further, as shown in FIG. 3, a front side of a wafer is faced upward, an insulating starting layer 31 is formed on the substrate 30 of the wafer, and a gate 42 and a source 41 are disposed on the starting layer 31. on And insulated by the starting layer 31 to prevent breakdown. A first insulating layer 51 is formed on the outer surface of the gate 42 and the source 41, that is, the first insulating layer 51 covers the periphery of the gate 42 and the entire top surface, and the peripheral portion of the source 41 and the edge portion of the top surface And the source 41 is exposed to the middle portion of the top surface of the first insulating layer 51.
步驟2，透過電鍍作業，於源極41未被第一絕緣層51覆蓋之表面形成一金屬的源極凸塊411。如第4圖所示，將源極凸塊411設置於源極41頂面曝露之中間部份，且源極凸塊411之頂面高於第一絕緣層51之頂面，並藉由第一絕緣層51將源極凸塊411與閘極42相互絕緣隔離。 In step 2, a metal source bump 411 is formed on the surface of the source 41 not covered by the first insulating layer 51 through a plating operation. As shown in FIG. 4, the source bump 411 is disposed at an intermediate portion of the top surface of the source 41, and the top surface of the source bump 411 is higher than the top surface of the first insulating layer 51, and An insulating layer 51 insulates the source bumps 411 from the gates 42 from each other.
步驟3，對晶片正面進行塑膠封裝，如第5圖所示，在第一絕緣層51及源極凸塊411之外表面，設有足夠厚度之塑膠封裝材料，以形成一塑封體60。意即，塑封體60覆蓋第一絕緣層51之整個頂面及週邊、源極凸塊411之整個頂面及源極凸塊411週邊未被第一絕緣層51包覆之部份。 In step 3, the front side of the wafer is plastically packaged. As shown in FIG. 5, a plastic encapsulating material having a sufficient thickness is provided on the outer surface of the first insulating layer 51 and the source bump 411 to form a molding body 60. That is, the molding body 60 covers the entire top surface and the periphery of the first insulating layer 51, the entire top surface of the source bump 411, and the portion of the source bump 411 that is not covered by the first insulating layer 51.
步驟4，對塑膠封裝後之晶片正面加以研磨。如第6圖所示，對塑封體60之頂面進行研磨，直到塑封體60之頂面與源極凸塊411的之頂面齊平，並且使源極凸塊411之頂面曝露於外。 In step 4, the front surface of the plastic packaged wafer is ground. As shown in FIG. 6, the top surface of the molding body 60 is ground until the top surface of the molding body 60 is flush with the top surface of the source bump 411, and the top surface of the source bump 411 is exposed. .
步驟5，對晶片正面金屬化。如第7圖所示，將一金屬覆蓋於源極凸塊411之頂面及研磨後之塑封體60頂面上，以形成一源極金屬層412。源極金屬層412透過源極凸塊411連通源極41，進而成為晶片可與外部元件連接之閘極區域。 In step 5, the front side of the wafer is metallized. As shown in FIG. 7, a metal is coated on the top surface of the source bump 411 and the top surface of the polished molding body 60 to form a source metal layer 412. The source metal layer 412 is connected to the source 41 through the source bump 411, and further becomes a gate region where the wafer can be connected to an external component.
步驟6，對晶片背面進行研磨。如第8圖所示，使晶片之基板30背面朝上，透過研磨將晶片之基板30減薄至超薄等級(substrate less)，例如10微米或更薄；在一個具體實施方式中，晶片基板30減薄至4微米；在另外一個具體實施方式中，晶片基板30減薄至2微米。又，此時晶片之正面朝下，故經過上述步驟1~6所形成之源極區域，即位於功率金氧半場效電晶體元件之底部。 In step 6, the back side of the wafer is ground. As shown in FIG. 8, the back surface of the substrate 30 of the wafer is turned upward, and the substrate 30 of the wafer is thinned to an ultra-thin grade by polishing. Less, for example, 10 microns or less; in one embodiment, the wafer substrate 30 is thinned to 4 microns; in another embodiment, the wafer substrate 30 is thinned to 2 microns. Moreover, at this time, the front side of the wafer faces downward, so that the source region formed through the above steps 1 to 6 is located at the bottom of the power MOS field device.
步驟7，對晶片背面金屬化。如第9圖所示，覆蓋一金屬於基板30之整個背面，以形成一汲極金屬層43。 In step 7, the back side of the wafer is metallized. As shown in FIG. 9, a metal is covered on the entire back surface of the substrate 30 to form a drain metal layer 43.
步驟8，使晶片背面形成連通至閘極42之一孔槽80。如第11圖所示，孔槽80從功率金氧半場效電晶體元件之頂面依序向下貫穿，汲極金屬層43、晶片之基板30及起始層31，直到閘極42背面之至少一部份曝露於孔槽80之底部。如第10圖所示，可在步驟7之後，先在汲極金屬層43之頂面上設置一第一遮罩板71，第一遮罩板71對應下方之閘極42位置設有一通孔，並透過濕蝕刻法或乾蝕刻法，於通孔之位置形成孔槽80。若透過雷射鑽孔法，則不需要使用上述之第一遮罩板71及其相關步驟，即可以直接形成如第11圖所示之孔槽80結構。 In step 8, the back surface of the wafer is formed to communicate with one of the apertures 80 of the gate 42. As shown in FIG. 11, the holes 80 are sequentially penetrated downward from the top surface of the power MOS field device, and the gate metal layer 43, the substrate 30 of the wafer, and the starting layer 31 are up to the back of the gate 42. At least a portion is exposed to the bottom of the aperture 80. As shown in FIG. 10, after step 7, a first mask 71 is disposed on the top surface of the gate metal layer 43. The first mask 71 is provided with a through hole corresponding to the lower gate 42. The hole 80 is formed at the position of the through hole by a wet etching method or a dry etching method. If the laser drilling method is used, it is not necessary to use the first mask 71 described above and its associated steps, that is, the structure of the slot 80 as shown in Fig. 11 can be directly formed.
步驟9，對整個晶片之背面進行絕緣保護。如第12圖所示，一第二絕緣層52覆蓋於汲極金屬層43之頂面和孔槽80之側壁及底部。 In step 9, the back side of the entire wafer is insulated. As shown in FIG. 12, a second insulating layer 52 covers the top surface of the gate metal layer 43 and the sidewalls and bottom of the trench 80.
步驟10，去除多餘之絕緣材料，以使汲極和閘極42曝露於外。如第13圖及第14圖所示，對應於孔槽80位置之第二絕緣層52上設有一第二遮罩板72，透過蝕刻或類似工法，以保留被第二遮罩板72所覆蓋之第二絕緣層52，而去除其他位置之絕緣材料。意即，孔槽80的側壁以及在汲極金屬層43上方環繞孔槽80頂部開口一預定距離內設置之第二絕緣層52被保留，而汲極金屬層43頂面的其他 位置和孔槽80底部皆未被第二絕緣層52覆蓋。因而，汲極金屬層43頂面上未被第二絕緣層52覆蓋之部份，成為晶片可與外部元件連接之汲極，且閘極42背面之其中一部份曝露於外，以形成晶片與外部元件連接之閘極區域。 In step 10, excess insulating material is removed to expose the drain and gate 42 to the outside. As shown in FIGS. 13 and 14, a second mask 72 is disposed on the second insulating layer 52 corresponding to the position of the slot 80, and is covered by the second mask 72 by etching or the like. The second insulating layer 52 removes the insulating material at other locations. That is, the sidewall of the hole 80 and the second insulating layer 52 disposed within a predetermined distance around the top opening of the hole 80 in the gate metal layer 43 are retained, and the other side of the top surface of the gate metal layer 43 Both the position and the bottom of the slot 80 are not covered by the second insulating layer 52. Therefore, the portion of the top surface of the gate metal layer 43 that is not covered by the second insulating layer 52 becomes a drain that the wafer can be connected to the external component, and a portion of the back surface of the gate 42 is exposed to form a wafer. A gate region that is connected to an external component.
綜上所述，本發明所提出之底部具有源極之功率金氧半場效電晶體元件，其晶片厚度在超薄基板等級(substrateless)，且整個製作過程中僅使用兩個遮罩板，如用雷射鑽孔法形成孔槽，則整個製作過程中僅需一個遮罩板，並使汲極和曝露於孔槽中之閘極42位於功率金氧半場效電晶體元件之頂部，且源極位於該功率金氧半場效電晶體元件之底部。汲極及閘極42之間隙，藉由孔槽80內之第二絕緣層52以及閘極42背面之起始層31進行絕緣保護，可有效防止擊穿。 In summary, the present invention has a source of power metal oxide half field effect transistor element at the bottom, the wafer thickness is substrateless, and only two masks are used in the whole manufacturing process, such as By forming the hole by laser drilling, only one mask is needed in the whole manufacturing process, and the gate and the gate 42 exposed in the hole are located on the top of the power MOS field device, and the source The pole is located at the bottom of the power MOS field device. The gap between the drain and the gate 42 is insulated by the second insulating layer 52 in the hole 80 and the starting layer 31 on the back surface of the gate 42 to effectively prevent breakdown.
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。 The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.
30‧‧‧基板 30‧‧‧Substrate
31‧‧‧起始層 31‧‧‧ starting layer
41‧‧‧源極 41‧‧‧ source
411‧‧‧源極凸塊 411‧‧‧ source bump
412‧‧‧源極金屬層 412‧‧‧ source metal layer
42‧‧‧閘極 42‧‧‧ gate
43‧‧‧汲極金屬層 43‧‧‧汲metal layer
51‧‧‧第一絕緣層 51‧‧‧First insulation
52‧‧‧第二絕緣層 52‧‧‧Second insulation
60‧‧‧塑封體 60‧‧‧plastic body
80‧‧‧孔槽 80‧‧‧ hole slot
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20070040255A1 (en) * | 2005-08-16 | 2007-02-22 | Yasuo Osone | Semiconductor device |
| US20080012119A1 (en) * | 2006-07-17 | 2008-01-17 | Infineon Technologies Ag | Semiconductor component and method for producing the same |
| US20090224313A1 (en) * | 2008-03-04 | 2009-09-10 | Burke Hugo R G | Semiconductor device having a gate contact on one surface electrically connected to a gate bus on an opposing surface |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20070040255A1 (en) * | 2005-08-16 | 2007-02-22 | Yasuo Osone | Semiconductor device |
| US20080012119A1 (en) * | 2006-07-17 | 2008-01-17 | Infineon Technologies Ag | Semiconductor component and method for producing the same |
| US20090224313A1 (en) * | 2008-03-04 | 2009-09-10 | Burke Hugo R G | Semiconductor device having a gate contact on one surface electrically connected to a gate bus on an opposing surface |
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