TWI466242B - 具有護桿的半導體封裝體結構 - Google Patents

具有護桿的半導體封裝體結構 Download PDF

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TWI466242B
TWI466242B TW98100097A TW98100097A TWI466242B TW I466242 B TWI466242 B TW I466242B TW 98100097 A TW98100097 A TW 98100097A TW 98100097 A TW98100097 A TW 98100097A TW I466242 B TWI466242 B TW I466242B
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package structure
semiconductor package
disposed
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TW201027678A (en
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Jen Chung Chen
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Nanya Technology Corp
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Priority to DE200910013782 priority patent/DE102009013782A1/de
Priority to JP2009065626A priority patent/JP5005718B2/ja
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Description

具有護桿的半導體封裝體結構
本發明係有關於一種半導體封裝體結構(semiconductor package structure)，特別是有關於一種具有護桿的半導體封裝體結構。
隨著電腦系統應用越來越廣泛，其所面臨的應用環境也越來越嚴苛，同時晶片與記憶體也必須面臨嚴格的測試，以符合並達到未來的需求。其中，信賴度測試(reliability test)中的高低溫循環測試主要是用來評估晶片封裝體在高低溫循環過程中，由於封裝體結構中不同材料的熱膨脹係數不同，導致溫度變化時的往復拉伸及收縮應力，對於封裝體結構中的錫球因疲勞導致破裂等負面影響的程度。
請參閱第1圖，其繪示的是封裝體在高低溫循環測試過程中的翹曲度對應溫度的曲線圖。如第1圖所示，在高低溫循環測試過程中，封裝體於低溫區及高溫區呈現的是不同的翹曲變形現象。在低溫區時，封裝體的側面類似一哭臉圖案，此時，錫球承受一壓縮應力(compressive stress)。當由低溫區過渡到高溫區時，封裝體的周圍會略往上翹，使其側面形同一笑臉圖案，此時，錫球承受一拉伸應力(tensile stress)。當封裝體的錫球反覆受到不同的應力拉扯，錫球就有可能無法牢固的固定在印刷電路板上的接觸墊上，進而造成封裝體與印刷電路板之間的電性連結失效。
由此可知，目前該技術領域需要一種有效的技術方案，用以解決在前述高低溫循環測試過程中封裝體的翹曲變形現象，及其對封裝體與印刷電路板之間的電性連結所產生的破壞，藉以提昇產品的可信賴度。
本發明之主要目的在提供一種改良之半導體封裝體結構，以解決先前技藝中封裝體與印刷電路板之間的電性連結的信賴度不足之缺點。
根據本發明一較佳實施例，本發明提供一種半導體封裝體結構，包含有一載板；一晶片或多個晶片，設置在該載板的一上表面；一模封材料，包覆住該載板的上表面及該晶片；複數個錫球，設於該載板的一下表面；以及一護桿，設於該載板的該下表面，其中該護桿由一熱固性高分子材料所構成。
根據本發明另一較佳實施例，本發明提供一種記憶體模組結構，包含有一印刷電路板；複數個設於該印刷電路板上的記憶體晶片封裝體；一散熱器，覆蓋在各該記憶體晶片封裝體上，且該散熱器透過塗佈在各該記憶體晶片封裝體上的散熱膏，構成熱接觸；其中，各該記憶體晶片封裝體包含有：一載板；一晶片或多個晶片，設置在該載板的一上表面；一模封材料，包覆住該載板的上表面及該晶片；複數個錫球，設於該載板的一下表面；以及一護桿，設於該載板的該下表面，其中該護桿由一熱固性高分子材料所構成。
為了使　貴審查委員能更進一步了解本發明之特徵及技術內容，請參閱以下有關本發明之詳細說明與附圖。然而所附圖式僅供參考與輔助說明用，並非用來對本發明加以限制者。
請參閱第2圖及第3圖，其中，第2圖為依據本發明一較佳實施例所繪示的半導體封裝體結構，當其處在一相對低溫區時的剖面示意圖，第3圖繪示的是本發明半導體封裝體結構，當其處在一相對高溫區時的剖面示意圖。如第2圖所示，本發明半導體封裝體結構1包含有一載板10，在載板10的上表面10a設有一IC晶片20，其與載板10透過金線22構成電性連接，而載板10的上表面10a以及IC晶片20則是被模封材料30包覆住。在載板10的下表面10b設有複數個錫球40，分別與一印刷電路板100的連接墊102連結，如此使載板10與印刷電路板100構成電性連接。本發明之主要特徵在於載板10的下表面10b的周圍設有一護桿50，其由一熱固性(thermosetting)高分子材料所構成的，例如，日立(Hitachi)公司供應的CEL-1802-HF19-GZ、CEL-1802-HF19-GB、CEL-1802-HF19-GC、CEL-1802-HF19-GF、CEL-1802-HF19-GJ、CEL-1802-HF19-HA等。根據本發明之較佳實施例，護桿50與模封材料30是由相同的高分子材料所構成的，較佳為日立公司供應的CEL-1802-HF19-GF、CEL-1802-HF19-GJ、CEL-1802-HF19-HA。
如第2圖所示，根據本發明較佳實施例，當本發明半導體封裝體結構1處在一相對低溫區時，例如，25℃至125℃之間，半導體封裝體結構1的翹曲變形現象將因為有護桿50抵住印刷電路板100，因而獲得足夠的支撐力，使得半導體封裝體結構1在低溫下不致變形，這也使得錫球不會在低溫時受到壓縮應力的破壞。如第3圖所示，當本發明半導體封裝體結構1處在一相對高溫區時，例如，125℃至280℃之間，半導體封裝體結構1的周圍則會略往上翹，使得封裝體結構1的側面如同一笑臉圖案，但由於載板10的下表面10b的周圍設有護桿50，由於其為熱固性高分子材料所構成，為一相對較剛性的結構，故可以抵銷部分半導體封裝體結構1的周圍的上翹力道，並降低錫球在高溫時所承受的拉伸應力。
另外，本發明之另一技術特徵在於採用特定的模封材料30，使得半導體封裝體結構1在高低溫循環測試過程中均保持類似哭臉圖案的變形態樣，而不會出現類似笑臉圖案的變形態樣。請參閱第4圖，其繪示的是本發明半導體封裝體結構1採用不同模封材料30下的翹曲度對應溫度的曲線圖。如第4圖所示，曲線(a)-(f)分別採用的是不同二氧化矽填充物比例的熱固性高分子成分，例如，曲線(a)-(f)可分別對應於日立(Hitachi)公司供應的CEL-1802-HF19-GZ(二氧化矽填充物比例：70%)、CEL-1802-HF19-GB(二氧化矽填充物比例：72%)、CEL-1802-HF19-GC(二氧化矽填充物比例：73%)、CEL-1802-HF19-GF(二氧化矽填充物比例：76%)、CEL-1802-HF19-GJ(二氧化矽填充物比例：79%)、CEL-1802-HF19-HA(二氧化矽填充物比例：81%)。根據本發明之較佳實施例，為了使半導體封裝體結構1在高低溫循環測試過程中均保持類似哭臉圖案的變形態樣，模封材料30採用的是曲線(d)-(f)所對應的CEL-1802-HF19-GF(二氧化矽填充物比例：76%)、CEL-1802-HF19-GJ(二氧化矽填充物比例：79%)、CEL-1802-HF19-HA(二氧化矽填充物比例：81%)三種日立(Hitachi)公司供應的熱固性高分子材料。
請參閱第5圖及第6圖，其分別繪示的是本發明半導體封裝體結構1的護桿50在載板10的下表面10b的配置圖。本發明半導體封裝體結構1的護桿50可配置在載板10的下表面10b的周邊，如第5圖所示。或者，本發明半導體封裝體結構1的護桿50可配置在載板10的下表面10b的相對的兩個側邊上，如第6圖所示。本發明之另一優點在於，由於護桿50為熱固性高分子材料所構成，為一相對較剛性的結構，故可以提升半導體封裝體結構1通過邊緣破裂(edge break)測試之能力。
請參閱第7圖，其為依據本發明另一較佳實施例所繪示的一種記憶體模組結構的剖面示意圖。如第7圖所示，本發明另提供一種記憶體模組結構2，其包含一印刷電路板100，複數個設於印刷電路板100上的記憶體晶片封裝體1a、1b、1c、1d，以及一散熱器70，覆蓋在記憶體晶片封裝體1a、1b、1c、1d上面，且散熱器70透過塗佈在記憶體晶片封裝體1a、1b、1c、1d上表面的散熱膏72，構成熱接觸。
依據本發明此另一較佳實施例，各個記憶體晶片封裝體1a、1b、1c、1d的構造與第2圖中的半導體封裝體結構1相同，包含一載板10，在載板10的上表面10a設有一IC晶片20，其與載板10透過金線22構成電性連接，而載板10的上表面10a以及IC晶片20則是被模封材料30包覆住。在載板10的下表面10b設有複數個錫球40，與印刷電路板100上的連接墊102連結，如此使載板10與印刷電路板100構成電性連接。載板10的下表面10b的周圍設有一護桿50，其由一熱固性高分子材料所構成。根據本發明，護桿50與模封材料30是由相同的高分子材料所構成的。
由於記憶體晶片封裝體1a、1b、1c、1d均有護桿50，因此可以使得記憶體晶片封裝體1a、1b、1c、1d上表面控制在同一平面上，而不會受到錫球本身大小不同所產生的不共面波動的影響，因此，可以確保散熱器70能夠確實接觸到各個記憶體晶片封裝體1a、1b、1c、1d上表面。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1．．．半導體封裝體結構
1a．．．記憶體晶片封裝體
1b．．．記憶體晶片封裝體
1c．．．記憶體晶片封裝體
1d．．．記憶體晶片封裝體
2．．．記憶體模組結構
10．．．載板
10a．．．上表面
10b．．．下表面
20．．．IC晶片
22．．．金線
30．．．模封材料
40．．．錫球
50．．．護桿
70．．．散熱器
72．．．散熱膏
100．．．印刷電路板
102．．．連接墊
第1圖繪示的是封裝體在高低溫循環測試過程中的翹曲度對應溫度的曲線圖。
第2圖為依據本發明一較佳實施例所繪示的封裝體結構處在一相對低溫區時的剖面示意圖。
第3圖繪示的是本發明封裝體結構處處在一相對高溫區時的剖面示意圖。
第4圖繪示的是本發明封裝體結構採用不同模封材料下的翹曲度對應溫度的曲線圖。
第5圖及第6圖分別繪示的是本發明封裝體結構的護桿在載板的下表面的配置圖。
第7圖為依據本發明另一較佳實施例所繪示的一種記憶體模組結構的剖面示意圖。
1．．．半導體封裝體結構
10．．．載板
10a．．．上表面
10b．．．下表面
20．．．IC晶片
22．．．金線
30．．．模封材料
40．．．錫球
50．．．護桿
100．．．印刷電路板
102．．．連接墊

Claims (9)

  1. 一種半導體封裝體結構，包含有：一載板；一晶片，設置在該載板的一上表面；一模封材料，包覆住該載板的上表面及該晶片；複數個錫球，設於該載板的一下表面；以及一護桿，設於該載板的該下表面，其中該模封材料與該護桿是由一相同的熱固性高分子材料所構成，使得整個信賴度測試的高低溫循環過程中該半導體封裝體結構的周圍只會向下翹曲。
  2. 如申請專利範圍第1項所述之半導體封裝體結構，其中該護桿設置於該載板的該下表面的周邊。
  3. 如申請專利範圍第1項所述之半導體封裝體結構，其中該熱固性高分子材料選自日立(Hitachi)公司供應的CEL-1802-HF19-GZ、CEL-1802-HF19-GB、CEL-1802-HF19-GC、CEL-1802-HF19-GF、CEL-1802-HF19-GJ、CEL-1802-HF19-HA。
  4. 如申請專利範圍第1項所述之半導體封裝體結構，其中該晶片透過金線與該載板構成電性連接。
  5. 一種記憶體模組結構，包含有： 一印刷電路板；複數個設於該印刷電路板上的記憶體晶片封裝體；一散熱器，覆蓋在各該記憶體晶片封裝體上，且該散熱器透過塗佈在各該記憶體晶片封裝體上的散熱膏，構成熱接觸；其中，各該記憶體晶片封裝體包含有：一載板；一晶片，設置在該載板的一上表面；一模封材料，包覆住該載板的上表面及該晶片；複數個錫球，設於該載板的一下表面；以及一護桿，設於該載板的該下表面，其中該模封材料與該護桿是由一相同的熱固性高分子材料所構成，使得整個信賴度測試的高低溫循環過程中該半導體封裝體結構的周圍只會向下翹曲。
  6. 如申請專利範圍第5項所述之半導體封裝體結構，其中該護桿設置於該載板的該下表面的周邊。
  7. 如申請專利範圍第5項所述之半導體封裝體結構，其中該熱固性高分子材料選自日立(Hitachi)公司供應的CEL-1802-HF19-GZ、CEL-1802-HF19-GB、CEL-1802-HF19-GC、CEL-1802-HF19-GF、CEL-1802-HF19-GJ、CEL-1802-HF19-HA。
  8. 如申請專利範圍第5項所述之半導體封裝體結構，其中該晶片透過金線與該載板構成電性連接。
  9. 如申請專利範圍第5項所述之半導體封裝體結構，其中該複數個錫球，與該印刷電路板上的連接墊連結。
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DE200910013782 DE102009013782A1 (de) 2009-01-05 2009-03-18 Halbleiterverpackungsaufbau mit Schutzleiste
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