TWI466233B - Multilayer connection structure and making method - Google Patents
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Description
本發明是有關於一種高密度積體電路裝置，且特別是有關於一種多層次三維堆疊式積體電路裝置。The present invention relates to a high density integrated circuit device, and more particularly to a multi-level three-dimensional stacked integrated circuit device.
在高密度記憶體裝置之製造中，一積體電路其每單位面積之資料量為一關鍵因素。於是當記憶體裝置之臨界尺寸已逼近蝕刻技述的限制時，記憶體單元之多層堆疊技術被提出，以達到更大的儲存密度及更低的位元成本。In the manufacture of high-density memory devices, the amount of data per unit area of an integrated circuit is a key factor. Thus, when the critical dimension of the memory device has approached the limitations of the etching technique, a multi-layer stacking technique of memory cells has been proposed to achieve greater storage density and lower bit cost.
隨著所有多層次三維堆疊式裝置中不同組件的尺寸下降，由於各絕緣層之厚度降低，與崩潰電壓及電流洩漏有關的問題開始出現。針對這些問題，舉例而言，可增加位於一互連區域內通過不同接點層之電性絕緣環繞栓塞或其他電導體的厚度。然而這樣的做法會減少栓塞的截面積，因而導致其電阻上升。又或者可以維持栓塞的截面積，但卻會增加栓塞間的距離，並因此降低裝置密度。類似的問題也出現在位於該互連區域內並通過部分或全數接點層之接地層間栓塞或其他層間栓塞。藉由最小化層間栓塞的截面積，可達到有效的空間利用，但卻必須做出限制層間栓塞及各接點層之導電層間接觸面積的犧牲。而增加層間栓塞的截面積會導致裝置密度的降低。As the size of the various components in all multi-level three-dimensional stacked devices decreases, problems associated with breakdown voltages and current leakage begin to occur due to the reduced thickness of the various insulating layers. In response to these problems, for example, the thickness of the plug or other electrical conductor surrounding the plug through a different contact layer in an interconnected region can be increased. However, such an approach reduces the cross-sectional area of the plug, thereby causing its resistance to rise. Alternatively, the cross-sectional area of the plug can be maintained, but it will increase the distance between the plugs and thus reduce the density of the device. A similar problem arises between ground-level plugs or other inter-layer plugs located in the interconnected area and through partial or full contact layers. Effective space utilization can be achieved by minimizing the cross-sectional area of the interlaminar plugs, but the sacrifice of the interlaminar plug and the contact area between the conductive layers of each contact layer must be made. Increasing the cross-sectional area of the interlaminar plug results in a decrease in device density.
本發明係有關於一種多層次三維堆疊式積體電路裝置。The present invention relates to a multi-level three-dimensional stacked integrated circuit device.
一實施例係有關一種積體電路裝置，包括：由數個接點層所構成之一堆疊，且每一接點層皆包括一導電層及一絕緣層；環繞一電導體之一介電質襯，係位於該堆疊之通過部份堆疊的一開口中，且電導體透過介電質襯與各接點層之導電層電性絕緣；以及導電層凹陷部，係該導電層相對於其相鄰之絕緣層顯得凹陷的部分。某些實施例中，還包括位於該堆疊上之一電性絕緣層；以及通過電性絕緣層之一電導體外延部，該電導體外延部並與電導體電性接觸。在某些實施例中，介電質襯包括一外延部，該介電質襯外延部延伸進入相鄰之絕緣層間。在某些實施例中，該外延部通常為環形。An embodiment relates to an integrated circuit device comprising: a stack of a plurality of contact layers, each of the contact layers including a conductive layer and an insulating layer; and a dielectric surrounding one of the electrical conductors The lining is located in an opening of the stacking portion of the stack, and the electrical conductor is electrically insulated from the conductive layer of each of the contact layers through the dielectric lining; and the depressed portion of the conductive layer is opposite to the phase of the conductive layer The adjacent insulating layer appears to be a concave portion. In some embodiments, an electrically insulating layer on the stack is further included; and an electrical conductor extension is formed by one of the electrically insulating layers, the electrical conductor is extended and electrically in electrical contact with the electrical conductor. In some embodiments, the dielectric liner includes an extension that extends between adjacent insulating layers. In some embodiments, the extension is generally annular.
另一實施例係有關一種三維堆疊式積體電路裝置，包括：至少由第一接點層、第二接點層、第三接點層及第四接點層所構成之一堆疊，其中每一接點層皆包括一導電層及一絕緣層；第一電導體、第二電導體、第三電導體及第四電導體，係位於通過部份該堆疊的接觸開口中，該第一、第二、第三及第四電導體係分別延伸並電性接觸至第一、第二、第三及第四接點層；一介電質襯，係環繞第二、第三及第四電導體，以使第二電導體與第一接點層電性隔離，第三電導體與第一、第二接點層電性隔離，第四電導體與第一、第二及第三接點層電性隔離；以及導電層凹陷部，係導電層於鄰接接觸開口處相對於其相鄰絕緣層顯得凹陷的部分。部分介電質襯延伸至前述之相鄰絕緣層間，以建立電性絕緣之介電質襯外延部，並提供加強對置之導電層及電導體間的電性絕緣。Another embodiment relates to a three-dimensional stacked integrated circuit device, comprising: at least one of a first contact layer, a second contact layer, a third contact layer, and a fourth contact layer, wherein each Each of the contact layers includes a conductive layer and an insulating layer; the first electrical conductor, the second electrical conductor, the third electrical conductor, and the fourth electrical conductor are located in the contact opening through the portion of the stack, the first The second, third and fourth conductance systems respectively extend and electrically contact the first, second, third and fourth contact layers; a dielectric liner surrounds the second, third and fourth electrical conductors The second electrical conductor is electrically isolated from the first contact layer, the third electrical conductor is electrically isolated from the first and second contact layers, and the fourth electrical conductor is coupled to the first, second, and third contact layers. Electrically isolating; and a recess of the conductive layer is a portion of the conductive layer that is recessed relative to its adjacent insulating layer adjacent the contact opening. A portion of the dielectric liner extends between the adjacent insulating layers to form an electrically insulating dielectric liner extension and provides electrical insulation between the opposing conductive layer and the electrical conductor.
又一實施例係有關在一積體電路裝置建立電導體的一種方法，該積體電路裝置包括由複數個接點層構成之一堆疊，其中每一接點層皆包括一導電層及一絕緣層。該方法包括：形成通過部份該堆疊之一接觸開口，由此建立一暴露的導電層邊緣及絕緣層邊緣；於暴露的導電層邊緣建立導電層之一凹陷部，以建立一凹陷的導電層邊緣；於接觸開口中形成一介電質襯，藉此覆蓋該些絕緣層邊緣及該凹陷的導電層邊緣，且形成介電質襯之電性絕緣材料於該凹陷部內沉積，介電質襯建立一加襯接觸開口；使用一導電材料，於該加襯接觸開口建立一電導體，凹陷部內之電性絕緣材料使該電導體與該凹陷的導電層邊緣電性隔離，由此提供加強電導體及環繞該電導體之導電層間的電性絕緣；以及電性連接電導體及其下之導電層。在某些實施例中，形成介電質襯包括以電性絕緣材料至少實質填充該凹陷部。某些實施例更包括在介電質襯形成前，氧化該凹陷的導電層邊緣。Yet another embodiment relates to a method of establishing an electrical conductor in an integrated circuit device, the integrated circuit device comprising a stack of a plurality of contact layers, wherein each contact layer comprises a conductive layer and an insulation Floor. The method includes forming a contact opening through a portion of the stack, thereby establishing an exposed conductive layer edge and an insulating layer edge; forming a recess of one of the conductive layers at the edge of the exposed conductive layer to establish a recessed conductive layer a dielectric lining is formed in the contact opening, thereby covering the edge of the insulating layer and the edge of the conductive layer of the recess, and an electrical insulating material forming a dielectric lining is deposited in the recess, the dielectric lining Establishing a lining contact opening; using an electrically conductive material to establish an electrical conductor in the lining contact opening, the electrically insulating material in the recess electrically isolating the electrical conductor from the edge of the recessed conductive layer, thereby providing enhanced electrical power Electrically insulating between the conductor and the conductive layer surrounding the electrical conductor; and electrically connecting the electrical conductor and the conductive layer thereunder. In some embodiments, forming the dielectric liner includes at least substantially filling the recess with an electrically insulating material. Some embodiments further include oxidizing the recessed conductive layer edges prior to formation of the dielectric liner.
再一實施例係有關在一三維堆疊式積體電路裝置建立電導體的一種方法，該三維堆疊式積體電路裝置包括至少由第一接點層、第二接點層、第三接點層及第四接點層構成之一堆疊，其中每一接點層皆包括一導電層及一絕緣層。該方法包括：形成通過部份該堆疊之接觸開口，由此建立暴露的導電層邊緣及絕緣層邊緣；於該些接觸開口之兩相鄰絕緣層間、在該些暴露的導電層邊緣建立導電層之凹陷部，以建立凹陷的導電層邊緣；於該些接觸開口中形成介電質襯，該些介電質襯覆蓋該些絕緣層邊緣及該些凹陷的導電層邊緣，且形成介電質襯之電性絕緣材料於該些凹陷部內沉積，介電質襯定義加襯接觸開口；使用一導電材料，於該些加襯接觸開口建立第一電導體、第二電導體、第三電導體及第四電導體，該些凹陷部內之電性絕緣材料使第二電導體與第一接點層之導電層電性隔離，使第三電導體與第一及第二接點層之導電層電性隔離，且使第四電導體與第一、第二及第三接點層之導電層電性隔離，藉此提供加強該些電導體及環繞該些電導體之導電層間的電性絕緣，第一、第二、第三及第四電導體係分別延伸並電性連接至第一、第二、第三及第四接點層之導電層。Still another embodiment relates to a method for establishing an electrical conductor in a three-dimensional stacked integrated circuit device, the three-dimensional stacked integrated circuit device including at least a first contact layer, a second contact layer, and a third contact layer And forming a stack of the fourth contact layer, wherein each of the contact layers comprises a conductive layer and an insulating layer. The method includes: forming a contact opening through a portion of the stack, thereby establishing an exposed conductive layer edge and an insulating layer edge; establishing a conductive layer between the adjacent conductive layers of the contact openings at the edges of the exposed conductive layers a recessed portion to establish a recessed conductive layer edge; forming a dielectric liner in the contact openings, the dielectric liner covering the edges of the insulating layer and the recessed conductive layer edges, and forming a dielectric a lining electrical insulating material is deposited in the recesses, the dielectric lining defines a lining contact opening; and a conductive material is used to establish a first electrical conductor, a second electrical conductor, and a third electrical conductor at the lining contact openings And a fourth electrical conductor, the electrically insulating material in the recesses electrically isolates the second electrical conductor from the conductive layer of the first contact layer, and the conductive layer of the third electrical conductor and the first and second contact layers Electrically isolating, and electrically isolating the fourth electrical conductor from the conductive layers of the first, second, and third contact layers, thereby providing electrical insulation between the conductive conductors and the conductive layers surrounding the electrical conductors ,First second, Three and fourth conductivity extending system and electrically connected to the first, second, third, and fourth conductive layers of the contact layer.
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式，作詳細說明如下：In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings
第1圖係描繪三維堆疊式積體電路裝置10之一剖面圖，一互連區域(interconnect region)17包含至少由第一、第二、第三及第四接點層(contact levels)18構成之一堆疊(stack)11。一積體電路裝置通常具有遠多於四層之接點層。各接點層18皆包含一導電層34及一絕緣層36，包含於該第一、第二、第三及第四接點層18.1、18.2、18.3及18.4之導電層分別為34.1、34.2、34.3及34.4，而絕緣層分別為36.1、36.2、36.3及36.4。對於下述之其他多種元件，也以類似方式訂定其於圖式中之指定參考符號。1 is a cross-sectional view of a three-dimensional stacked integrated circuit device 10, an interconnect region 17 including at least first, second, third, and fourth contact levels 18. One of the stacks 11 is stacked. An integrated circuit device typically has a contact layer that is much more than four layers. Each of the contact layers 18 includes a conductive layer 34 and an insulating layer 36. The conductive layers included in the first, second, third, and fourth contact layers 18.1, 18.2, 18.3, and 18.4 are respectively 34.1 and 34.2. 34.3 and 34.4, and the insulating layers are 36.1, 36.2, 36.3 and 36.4, respectively. For the various other elements described below, the specified reference symbols in the drawings are also set in a similar manner.
一層間栓塞(interlevel plug)55延伸通過部分之堆疊11，並電性連接至各導電層34。該層間栓塞55有時也被稱為層間導體(interlevel conductor)，可為或可不為一接地栓塞。鄰接層間栓塞55之部分絕緣層36，相對於與其相鄰之導電層34顯得凹陷，以形成如第12圖所示之環形凹陷部37。層間栓塞55之環形部分50(該部分通常為環形)延伸至上述的環形凹陷部37，以進入其上與其下之接點層18間並與該些接點層18電性接觸。此一型態提供加強層間栓塞55及導電層34間之電性接觸。An interlevel plug 55 extends through the portion of the stack 11 and is electrically connected to each of the conductive layers 34. The interlayer plug 55 is sometimes also referred to as an interlevel conductor and may or may not be a ground plug. A portion of the insulating layer 36 adjacent the interlaminar plug 55 is recessed relative to the conductive layer 34 adjacent thereto to form an annular recess 37 as shown in FIG. The annular portion 50 of the interlayer plug 55 (which is generally annular) extends to the annular recess 37 described above to enter and be in electrical contact with the contact layer 18 therebelow. This type provides enhanced electrical contact between the interlayer plug 55 and the conductive layer 34.
堆疊11也包含第一栓塞、第二栓塞、第三栓塞及第四栓塞54.1、54.2、54.3及54.4。該些栓塞54有時也被稱為電導體或層間導體，係分別與第一、第二、第三及第四導電層34.1、34.2、34.3及34.4電性接觸。而介電側壁間隔層(dielectric sidewall spacers)61使第二、第三及第四栓塞54.2、54.3及54.4之側壁與第一、第二及第三導電層34.1、34.2及34.3電性隔離。該介電側壁間隔層61亦被稱為介電質襯。鄰接第二、第三及第四栓塞54.2、54.3及54.4之部分導電層34，相對於與其相鄰之絕緣層36顯得凹陷，以形成如第7圖所示之環形凹陷部39。介電側壁間隔層61之環形部分(通常為環形)延伸進入與其相鄰之絕緣層36間。此一型態於上述之栓塞54及環繞之導電層34建立一更遠的距離，因而提供加強該導電層34及具導電性之栓塞54間的電性絕緣。The stack 11 also includes a first plug, a second plug, a third plug, and fourth plugs 54.1, 54.2, 54.3, and 54.4. The plugs 54 are sometimes also referred to as electrical conductors or interlayer conductors that are in electrical contact with the first, second, third, and fourth conductive layers 34. 1 , 34.2, 34.3, and 34.4, respectively. The dielectric sidewall spacers 61 electrically isolate the sidewalls of the second, third, and fourth plugs 54.2, 54.3, and 54.4 from the first, second, and third conductive layers 34. 1, 34.2, and 34.3. The dielectric sidewall spacers 61 are also referred to as dielectric liners. A portion of the conductive layer 34 adjacent to the second, third, and fourth plugs 54.2, 54.3, and 54.4 is recessed relative to the adjacent insulating layer 36 to form an annular recess 39 as shown in FIG. The annular portion (usually annular) of the dielectric sidewall spacer 61 extends between the insulating layer 36 adjacent thereto. This type establishes a greater distance between the plug 54 and the surrounding conductive layer 34, thereby providing electrical insulation between the conductive layer 34 and the conductive plug 54.
一介電層25位於堆疊11之下，一氧化層29係位於介電層25與一基板19之間。介電層25之材料通常為氮化矽(SiN)，氧化層29之材料通常為二氧化矽(SiO2 )，而基板19通常為矽基板。一氧化層30與一間隙層32位於該堆疊11之上。氧化層30之材料通常為二氧化矽，而間隙層32之材料通常為氮化矽。層間介電質52係位於間隙層32之上，且其成份通常為氧化物，例如二氧化矽。栓塞外延部(plug extension)51.1-51.4係通過層間介電質52及間隙層32以分別接觸栓塞54.1-54.4。一層間栓塞外延部(interlevel plug extension)56通過層間介電質52及間隙層32以接觸層間栓塞55。A dielectric layer 25 is disposed under the stack 11, and an oxide layer 29 is disposed between the dielectric layer 25 and a substrate 19. The material of the dielectric layer 25 is typically tantalum nitride (SiN), the material of the oxide layer 29 is typically hafnium oxide (SiO 2 ), and the substrate 19 is typically a tantalum substrate. An oxide layer 30 and a gap layer 32 are located above the stack 11. The material of the oxide layer 30 is typically hafnium oxide, and the material of the interstitial layer 32 is typically tantalum nitride. The interlayer dielectric 52 is located over the gap layer 32 and is typically composed of an oxide such as hafnium oxide. Plug extensions 51.1-51.4 pass through interlayer dielectric 52 and gap layer 32 to contact plugs 54.1-54.4, respectively. An interlevel plug extension 56 passes through the interlayer dielectric 52 and the gap layer 32 to contact the interlayer plug 55.
底部橫向尺寸58(通常被稱為直徑58)，係小於沉積於環形凹陷部39(繪示於第8圖)之間隙層材料62(繪示於第9圖)的相關橫向尺寸60(通常被稱為直徑60)。由於當一接觸並未對齊時，沉積於環形凹陷部39之間隙層材料62可幫助停止接觸窗蝕刻，因此這樣的尺寸關係有利於製程窗口。The bottom lateral dimension 58 (commonly referred to as diameter 58) is less than the relative lateral dimension 60 of the gap layer material 62 (shown in Figure 9) deposited in the annular recess 39 (shown in Figure 8) (usually Called diameter 60). Since the gap layer material 62 deposited on the annular recess 39 can help stop the contact window etch when a contact is not aligned, such a dimensional relationship facilitates the process window.
第2-13圖係描繪一三維堆疊式積體電路裝置10之第一實施例的結構以及其製作方法。第2圖係一三維堆疊式積體電路裝置10之互連區域17的剖面簡圖，描繪由交互的導電層34及絕緣層36構成之一堆疊11。各導電層34及與之相鄰之一絕緣層36共同建立一接點層18。氧化層30係位於最上層導電層34.1之上。氧化層30具有一層間栓塞開口44及一系列栓塞開口46，且通常係使用一光阻光罩並配合蝕刻技術來形成該層間栓塞開口44及栓塞開口46。層間栓塞開口44與該些栓塞開口46係安置以容納下述之一層間栓塞55及一系列具導電性之栓塞54。實務上，互連區域17通常具有多於一個之層間栓塞55，且互連區域17中之每一導電層18皆至少有一栓塞54。2-13 are diagrams showing the structure of a first embodiment of a three-dimensional stacked integrated circuit device 10 and a method of fabricating the same. 2 is a schematic cross-sectional view of an interconnect region 17 of a three-dimensional stacked integrated circuit device 10 depicting a stack 11 of alternating conductive layers 34 and insulating layers 36. Each of the conductive layers 34 and an adjacent one of the insulating layers 36 establish a contact layer 18. The oxide layer 30 is located above the uppermost conductive layer 34.1. The oxide layer 30 has an interposed plug opening 44 and a series of plug openings 46, and is typically formed using a photoresist mask and etching techniques to form the interlaminar plug opening 44 and the plug opening 46. Interlayer plug openings 44 are disposed with the plug openings 46 to accommodate one of the interlaminar plugs 55 and a series of electrically conductive plugs 54. In practice, interconnect region 17 typically has more than one interlaminar plug 55, and each of conductive layers 18 in interconnect region 17 has at least one plug 54.
第3圖繪示對於第2圖之結構，進行等向性沉積間隙層32的結果。該間隙層32之材料通常為氮化矽。第4圖繪示於第3圖之結構建立一第一光阻光罩42，該第一光阻光罩42係在第二栓塞開口46.2及第四栓塞開口46.4處具有光罩開口43。第一光阻光罩42形成後，第一導電層34.1係於第二及第四栓塞開口46.2及46.4處被蝕刻通過。Fig. 3 is a view showing the result of performing the isotropic deposition of the gap layer 32 for the structure of Fig. 2. The material of the gap layer 32 is typically tantalum nitride. FIG. 4 illustrates the structure of FIG. 3 to create a first photoresist mask 42 having a mask opening 43 at the second plug opening 46.2 and the fourth plug opening 46.4. After the first photoresist mask 42 is formed, the first conductive layer 34. 1 is etched through the second and fourth plug openings 46.2 and 46.4.
在第5圖中，係藉由一第二光阻光罩48之建立來調整第4圖之結構，第二光阻光罩48係在第三栓塞開口46.3及第四栓塞開口46.4處具有光罩開口49。於該第三及第四栓塞開口46.3及46.4處，皆有兩層導電層34被蝕刻。特別是在第三栓塞開口46.3處為第一及第二導電層34.1及34.2被蝕刻，而在第四栓塞開口46.4處為第二及第三導電層34.2及34.3被蝕刻。第6圖描繪將第5圖結構中之第二光阻光罩48移除的結果。In Fig. 5, the structure of Fig. 4 is adjusted by the establishment of a second photoresist mask 48 having light at the third plug opening 46.3 and the fourth plug opening 46.4. Cover opening 49. At the third and fourth plug openings 46.3 and 46.4, two conductive layers 34 are etched. In particular, the first and second conductive layers 34. 1 and 34.2 are etched at the third plug opening 46.3, while the second and third conductive layers 34. 2 and 34.3 are etched at the fourth plug opening 46.4. Figure 6 depicts the result of removing the second photoresist mask 48 in the structure of Figure 5.
第7圖繪示對於第二、第三及第四栓塞開口46.2、46.3及46.4進行側壁蝕刻的結果，係對於不同接點層18其暴露於外的導電層34進行蝕刻。側壁蝕刻有時也被稱為多重回拉(poly pull back)，於上下兩絕緣層36間形成環形凹陷部39(通常為環形，有時也被稱為凹陷部)。如下所述，該些環形凹陷部39將被電性絕緣材料填充，以於栓塞54與環繞該些栓塞54之導電層34間形成較厚之絕緣材料，該些栓塞54係將建立於栓塞開口46內。請參照第7圖，凹陷量係栓塞開口46處被蝕刻凹入之導電層34的導電層表面63與絕緣層36的絕緣層表面65間之水平距離，該凹陷量最好大於10奈米以達較佳之絕緣效果。FIG. 7 illustrates the results of sidewall etching for the second, third, and fourth plug openings 46.2, 46.3, and 46.4, which are etched for the different contact layers 18 that are exposed to the outer conductive layer 34. Sidewall etching, sometimes referred to as poly pull back, forms an annular recess 39 (typically a ring, sometimes referred to as a recess) between the upper and lower insulating layers 36. As described below, the annular recesses 39 will be filled with an electrically insulating material to form a thicker insulating material between the plugs 54 and the conductive layers 34 surrounding the plugs 54. The plugs 54 will be built into the plug openings. Within 46. Referring to FIG. 7, the recessed amount is a horizontal distance between the conductive layer surface 63 of the conductive layer 34 and the insulating layer surface 65 of the insulating layer 36 where the recessed opening 46 is etched, and the recessed amount is preferably greater than 10 nm. Achieve better insulation.
第8圖繪示移除第二、第三及第四栓塞開口46.2、46.3及46.4處覆蓋第二、第三及第四導電層38.2、38.3及38.4之部分第一、第二及第三絕緣層36.1、36.2及36.3的結果。由於絕緣層36之材料通常為氧化物，此一移除步驟有時也被稱為氧化物穿透(oxide breakthrough)。Figure 8 illustrates the removal of portions of the second, third and fourth plug openings 46.2, 46.3 and 46.4 covering the second, third and fourth conductive layers 38.2, 38.3 and 38.4 of the first, second and third insulation Results of layers 36.1, 36.2 and 36.3. Since the material of the insulating layer 36 is typically an oxide, this removal step is sometimes referred to as oxide breakthrough.
在第9圖中，不導電之間隙層材料62沉積於第8圖之結構並填充該些環形凹陷部39，該些間隙層材料62通常為氮化矽。間隙層材料62並為栓塞開口46加襯以形成介電側壁間隔層61。In Fig. 9, a non-conductive gap layer material 62 is deposited in the structure of Fig. 8 and fills the annular recesses 39, which are typically tantalum nitride. The gap layer material 62 is lined with the plug opening 46 to form a dielectric sidewall spacer layer 61.
第9圖所示之結構中，位於層間栓塞開口44及各栓塞開口46底部之間隙層材料62於後續步驟被移除，如第10圖所示。由於間隙層材料62之組成通常為氮化矽，此一移除步驟有時也被稱為氮化矽穿透。移除步驟使得以下部分之導電層暴露於外：層間栓塞開口44及第一栓塞開口46.1處之第一導電層34.1、第二栓塞開口46.2處之第二導電層34.2、第三栓塞開口46.3處之第三導電層34.3及第四栓塞開口46.4處之第四導電層34.4。In the configuration shown in Fig. 9, the gap layer material 62 at the bottom of the interlayer plug opening 44 and the respective plug openings 46 is removed in a subsequent step, as shown in Fig. 10. Since the composition of the gap layer material 62 is typically tantalum nitride, this removal step is sometimes referred to as tantalum nitride penetration. The removing step exposes the conductive portion of the following portion: the inter-layer plug opening 44 and the first conductive layer 34. 1 at the first plug opening 46. 1 , the second conductive layer 34.2 at the second plug opening 46.2, and the third plug opening 46.3. The third conductive layer 34.3 and the fourth conductive layer 34.4 at the fourth plug opening 46.4.
第11圖繪示一第三光阻光罩66於第10圖之結構成形後的結果，第三光阻光罩66覆蓋該些栓塞開口46而於層間栓塞開口44處提供一光罩開口67。第三光阻光罩66成形後，即於層間栓塞開口44處蝕刻通過接點層18.1-18.3，直到接觸第四導電層34.4時停止。11 is a result of forming a structure of the third photoresist mask 66 in FIG. 10, the third photoresist mask 66 covering the plug openings 46 and providing a mask opening 67 at the interlayer plug opening 44. . After the third photoresist mask 66 is formed, it is etched through the contact layer 18.1-18.3 at the interlayer plug opening 44 until it stops when it contacts the fourth conductive layer 34.4.
在第12圖中繪示一氧化物凹陷部蝕刻步驟，此一實施例中之氧化物係絕緣層36。第12圖顯示對於第11圖之結構，蝕刻層間栓塞開口44處暴露於外之第一、第二及第三絕緣層36.1-36.3。此一蝕刻行為提供層間栓塞開口44環形凹陷部37(通常為環形)，該環形凹陷部37係於其上與其下之導電層34間建立之凹陷部。隨後並移除第三光阻光罩66。An oxide recess etching step, the oxide-based insulating layer 36 in this embodiment, is shown in FIG. Fig. 12 shows the first, second and third insulating layers 36.1-36.3 exposed to the outside of the plug opening 44 at the etch interlayer for the structure of Fig. 11. This etching action provides an inter-layer plug opening 44 annular recess 37 (typically annular) that is recessed between the conductive layer 34 and the underlying conductive layer 34. The third photoresist mask 66 is then removed.
第13圖繪示對於第12圖中，將通常為多晶矽之導電材料填充於層間栓塞開口44後，形成一層間栓塞55之結構，該層間栓塞55係與各導電層34.1-34.4電性接觸。環形凹陷部37之存在使得層間栓塞55具有環形部分50，該環形部分50延伸至其上與其下之導電層34間並與該些導電層34電性接觸。層間栓塞55與導電層34間之電性接觸表面遠大於僅在第11圖所示之一般圓柱形層間栓塞開口44中沉積該層間栓塞所能形成之電性接觸表面。因此具有環形部分50之層間栓塞55與導電層34間之電性接觸較強。FIG. 13 is a view showing a structure in which a conductive plug of a polycrystalline germanium is filled in the interlayer plug opening 44 to form an inter-plug 55, which is in electrical contact with each of the conductive layers 34.1-34.4. The presence of the annular recess 37 causes the interlayer plug 55 to have an annular portion 50 that extends between and is in electrical contact with the conductive layer 34 therebelow. The electrical contact surface between the interlayer plug 55 and the conductive layer 34 is much larger than the electrical contact surface that can be formed by depositing the interlayer plug only in the general cylindrical interlayer plug opening 44 shown in FIG. Therefore, the electrical contact between the interlayer plug 55 having the annular portion 50 and the conductive layer 34 is strong.
第13圖並繪示栓塞54.1-54.4於栓塞開口46.1-46.4內之成形。第一、第二、第三及第四栓塞54.1-54.4分別電性連接至第一、第二、第三及第四導電層34.1-34.4。沉積導電材料後，即進行化學機械拋光以建立第13圖所示之上表面64。隨後再沉積層間介電質52，並於層間介電質52內建立對齊層間栓塞55及栓塞54.1-54.4之穿孔。具導電性之層間栓塞外延部56及栓塞外延部51.1-51.4於穿孔內形成，以建立第1圖所示之結構。Figure 13 and shows the formation of the plugs 54.1-54.4 in the plug openings 46.1-46.4. The first, second, third, and fourth plugs 54.1-54.4 are electrically connected to the first, second, third, and fourth conductive layers 34.1-34.4, respectively. After depositing the conductive material, chemical mechanical polishing is performed to establish the upper surface 64 shown in FIG. The interlayer dielectric 52 is then deposited and inter-layer plugs 55 and vias 54.1-54.4 are formed in the interlayer dielectric 52. Conductive interlaminar plug extensions 56 and plug extensions 51.1-51.4 are formed in the perforations to create the structure shown in FIG.
第14-17圖描繪一三維堆疊式積體電路裝置10之第二實施例的結構以及其製作方法。第14圖繪示類似於第9圖所示之一結構，但該些栓塞開口46.2-46.4僅蝕刻通過部分之第一、第二及第三絕緣層36.1-36.3，而非如前述之完全蝕刻通過絕緣層36.1-36.3以形成如第8圖所示之第二、第三及第四栓塞開口46.2-46.4。第一、第二及第三絕緣層36.1-36.3仍覆蓋第二、第三及第四導電層34.2-34.4。隨後以類似於第9圖相關討論之方式，沉積電性絕緣之間隙層材料62，該些間隙層材料62通常為氮化矽。Figures 14-17 depict the structure of a second embodiment of a three-dimensional stacked integrated circuit device 10 and a method of fabricating the same. Figure 14 is a view similar to the structure shown in Figure 9, but the plug openings 46.2-46.4 only etch through portions of the first, second and third insulating layers 36.1-36.3 instead of being completely etched as described above The second, third and fourth plug openings 46.2-46.4 as shown in Fig. 8 are formed by insulating layers 36.1-36.3. The first, second and third insulating layers 36.1-36.3 still cover the second, third and fourth conductive layers 34.2-34.4. Electrically insulating gap layer material 62 is then deposited in a manner similar to that discussed in relation to Figure 9, which is typically tantalum nitride.
第14圖結構中之層間栓塞開口44及各栓塞開口46底部之間隙層材料62，於第15圖中被蝕刻通過。第15圖並繪示蝕刻通過部分該第二、第三及第四導電層34.2-34.4的結果。此一蝕刻步驟有時也被稱為氮化矽/氧化物穿透。The interlayer plug opening 44 in the structure of Fig. 14 and the gap layer material 62 at the bottom of each plug opening 46 are etched through in Fig. 15. Figure 15 also shows the results of etching through portions of the second, third and fourth conductive layers 34.2-34.4. This etching step is sometimes referred to as tantalum nitride/oxide penetration.
第16圖繪示對於第15圖之結構，以類似於第11圖之方式沉積一第三光阻光罩66。第17圖繪示對於第16圖之結構，蝕刻層間栓塞開口44處暴露於外的絕緣層36.1-36.4。此一蝕刻步驟係以類似於第12圖之方式，在上下兩導電層間形成環形凹陷部37。第12圖及第17圖所示之二實施例皆需一氧化物凹陷步驟以建立環形凹陷部37，氧化物凹陷步驟又稱為氧化物回拉步驟。一般而言，可使用氫氟酸緩衝液(BOE/HF)以達此目的。該二實施例之差異在於：第17圖中，於氧化物回拉步驟進行時，非目標區域係由第三光阻光罩66加以保護；而在第12圖所示之實施例中並無第三光阻光罩66，氧化物回拉步驟進行時，對於非目標區域的保護係由氮化矽間隙層32提供。由於在第12圖及第17圖之實施例中，對於側壁之保護皆由間隙層32提供；此二實施例於保護上的差異不應太多。然而第16圖中，氮化矽間隙層32下存在有一些暴露於外的氧化物，因此相較於第12圖之實施例，第17圖之實施例於氧化物回拉步驟進行時具有較多的保護。第二實施例其餘的步驟係對應於第12圖及第13圖之相關討論。Fig. 16 is a view showing the structure of Fig. 15 in which a third photoresist mask 66 is deposited in a manner similar to that of Fig. 11. Fig. 17 is a view showing the structure of Fig. 16 for etching the insulating layer 36.1-36.4 exposed at the opening 44 of the interlayer. This etching step forms an annular depressed portion 37 between the upper and lower conductive layers in a manner similar to that of Fig. 12. Both of the embodiments shown in Figures 12 and 17 require an oxide recess step to create an annular recess 37, which is also referred to as an oxide pullback step. In general, hydrofluoric acid buffer (BOE/HF) can be used for this purpose. The difference between the two embodiments is that, in FIG. 17, the non-target area is protected by the third photoresist mask 66 during the oxide pullback step; and in the embodiment shown in FIG. The third photoresist mask 66 is provided with a barrier layer 32 for the non-target region when the oxide pullback step is performed. Since in the embodiments of Figures 12 and 17, the protection for the side walls is provided by the gap layer 32; the difference in protection between the two embodiments should not be too much. However, in Fig. 16, there are some exposed oxides under the tantalum nitride gap layer 32. Therefore, compared with the embodiment of Fig. 12, the embodiment of Fig. 17 has a comparison in the oxide pullback step. More protection. The remaining steps of the second embodiment correspond to the related discussion of Figures 12 and 13.
第18-20圖繪示一三維堆疊式積體電路裝置10之第三實施例的結構以及其製作方法。第18圖繪示類似於第7圖所示結構之結構，但氧化第一、第二及第三多晶矽導電層34.1-34.3之凹陷部，以建立氧化部分74。當導電層34之組成為多晶矽時，此一氧化步驟有時也被稱為多晶矽氧化(poly oxidation)。建立環形凹陷部39並因此使第二栓塞開口46.2與第一導電層34.1電性絕緣，第三栓塞開口46.3與第一及第二導電層34.1及34.2電性絕緣，而第四栓塞開口46.4與第一、第二及第三導電層34.1-34.3電性絕緣。18-18 illustrate the structure of a third embodiment of a three-dimensional stacked integrated circuit device 10 and a method of fabricating the same. Fig. 18 is a view similar to the structure of the structure shown in Fig. 7, but oxidizing the depressed portions of the first, second and third polysilicon conductive layers 34.1-34.3 to establish the oxidized portion 74. When the composition of the conductive layer 34 is polycrystalline germanium, this oxidation step is sometimes referred to as polyoxidation. An annular recess 39 is formed and thus the second plug opening 46.2 is electrically insulated from the first conductive layer 34.1, the third plug opening 46.3 is electrically insulated from the first and second conductive layers 34. 1 and 34.2, and the fourth plug opening 46.4 is The first, second and third conductive layers 34.1-34.3 are electrically insulated.
在第19圖中，第18圖之結構於該第二、第三及第四栓塞開口46.2-46.4之底部蝕刻通過第一、第二及第三絕緣層36.1-36.3，以暴露第二、第三及第四導電層34.2-34.4。此一步驟有時也被稱為氧化物穿透。In FIG. 19, the structure of FIG. 18 is etched through the first, second and third insulating layers 36.1-36.3 at the bottom of the second, third and fourth plug openings 46.2-46.4 to expose the second, Three and fourth conductive layers 34.2-34.4. This step is sometimes referred to as oxide breakthrough.
第20圖繪示對於第19圖之結構，以一電性絕緣之介電側壁間隔層61為栓塞開口46加襯，該介電側壁間隔層61並填充栓塞開口46處位於上下兩絕緣層36間之環形凹陷部39。介電側壁間隔層61之組成通常為氮化矽。第三實施例其餘的步驟係對應於第12圖及第13圖之相關討論。Figure 20 is a view showing the structure of Fig. 19, in which an electrically insulating dielectric sidewall spacer 61 is used to line the plug opening 46. The dielectric sidewall spacer 61 is filled with the plug opening 46 at the upper and lower insulating layers 36. An annular recess 39 therebetween. The composition of the dielectric sidewall spacers 61 is typically tantalum nitride. The remaining steps of the third embodiment correspond to the related discussion of Figures 12 and 13.
在某些實施例中，由於回拉拓僕學(pullback topology)，可能在層間栓塞55中有如第1圖中以虛線繪示之多個孔洞70被建立。孔洞70的存在可作為層間栓塞55已被建立之一項指標，如同本發明所教示之藉由蝕刻絕緣層36而建立該層間栓塞55。In some embodiments, a plurality of holes 70, as shown in phantom in Figure 1, may be created in the interlaminar plug 55 due to the pullback topology. The presence of the voids 70 can serve as an indicator that the interlayer plugs 55 have been established, and the interlayer plugs 55 are created by etching the insulating layer 36 as taught by the present invention.
任何，以及所有於以上內容中提到之專利、專利申請和印刷出版物係以參考文獻之形式附於本說明書。Any and all patents, patent applications, and printed publications mentioned in the above are hereby incorporated by reference.
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
10．．．三維堆疊式積體電路裝置10. . . Three-dimensional stacked integrated circuit device
11．．．堆疊11. . . Stacking
17．．．互連區域17. . . Interconnected area
18.1、18.2、18.3、18.4．．．接點層18.1, 18.2, 18.3, 18.4. . . Contact layer
19．．．基板19. . . Substrate
25．．．介電層25. . . Dielectric layer
29．．．氧化層29. . . Oxide layer
30．．．氧化層30. . . Oxide layer
32．．．間隙層32. . . Gap layer
34.1、34.2、34.3、34.4．．．導電層34.1, 34.2, 34.3, 34.4. . . Conductive layer
36.1、36.2、36.3、36.4．．．絕緣層36.1, 36.2, 36.3, 36.4. . . Insulation
37．．．環形凹陷部37. . . Annular depression
39．．．環形凹陷部39. . . Annular depression
42．．．第一光阻光罩42. . . First photoresist mask
43．．．光罩開口43. . . Mask opening
44．．．層間栓塞開口44. . . Interlaminar embolic opening
46、46.1、46.2、46.3、46.4．．．栓塞開口46, 46.1, 46.2, 46.3, 46.4. . . Plug opening
48．．．第二光阻光罩48. . . Second photoresist mask
49．．．光罩開口49. . . Mask opening
50．．．環形部分50. . . Ring part
51.1、51.2、51.3、51.4．．．栓塞外延部51.1, 51.2, 51.3, 51.4. . . Plug extension
52．．．層間介電質52. . . Interlayer dielectric
54.1、54.2、54.3、54.4．．．栓塞54.1, 54.2, 54.3, 54.4. . . embolism
55．．．層間栓塞55. . . Interlaminar embolization
56．．．層間栓塞外延部56. . . Interlayer embedding extension
58．．．底部橫向尺寸58. . . Bottom lateral dimension
60．．．相關橫向尺寸60. . . Related lateral dimensions
61．．．介電側壁間隔層61. . . Dielectric sidewall spacer
62．．．間隙層材料62. . . Gap layer material
63‧‧‧導電層表面63‧‧‧ Conductive layer surface
64‧‧‧上表面64‧‧‧ upper surface
65‧‧‧絕緣層表面65‧‧‧Insulation surface
66‧‧‧第三光阻光罩66‧‧‧ Third photoresist mask
67‧‧‧光罩開口67‧‧‧Mask opening
70‧‧‧孔洞70‧‧‧ holes
74‧‧‧氧化部分74‧‧‧Oxidized part
第1圖係一三維堆疊式積體電路裝置之一實例的剖面圖，該三維堆疊式積體電路裝置係根據本發明而描繪，並於一互連區域包含一堆疊。1 is a cross-sectional view showing an example of a three-dimensional stacked integrated circuit device, which is depicted in accordance with the present invention and includes a stack in an interconnected region.
第2圖係一三維堆疊式積體電路裝置之互連區域的剖面簡圖，描繪由交互的導電層及絕緣層構成之一堆疊。Figure 2 is a schematic cross-sectional view of an interconnected region of a three-dimensional stacked integrated circuit device depicting a stack of alternating conductive and insulating layers.
第3圖繪示對於第2圖之結構進行間隙層之沉積。Figure 3 illustrates the deposition of the gap layer for the structure of Figure 2.
第4圖繪示對於第3圖之結構，建立具有光罩開口之一第一光阻光罩，並於該些開口處蝕刻通過第一導電層。4 is a view showing the structure of FIG. 3, establishing a first photoresist mask having a mask opening, and etching through the first conductive layer at the openings.
第5圖繪示對於第4圖之結構，建立具有光罩開口之一第二光阻光罩，並於該些開口處蝕刻通過兩層導電層。Figure 5 illustrates the construction of the structure of Figure 4, the creation of a second photoresist mask having a reticle opening, and etching through the two conductive layers at the openings.
第6圖描繪將第5圖結構中之第二光阻光罩移除。Figure 6 depicts the removal of the second photoresist mask in the structure of Figure 5.
第7圖繪示對於不同接點層其暴露於外的導電層進行側壁蝕刻，於上下兩絕緣層間建立凹陷部。FIG. 7 illustrates sidewall etching of the conductive layer exposed to the different contact layers, and a recess is formed between the upper and lower insulating layers.
第8圖繪示移除層間栓塞開口底部及第一栓塞開口底部該電性絕緣之間隙層，以及第二、第三及第四栓塞開口處覆蓋第二、第三及第四導電層之絕緣層材料。Figure 8 is a view showing the gap between the bottom of the interlayer plug opening and the bottom of the first plug opening, and the second, third and fourth plug openings covering the second, third and fourth conductive layers. Layer material.
第9圖繪示對於第8圖之結構，使不導電之間隙層材料沉積填充該些凹陷部並為該些栓塞開口加襯。Figure 9 illustrates the structure of Figure 8 by depositing a non-conductive gap layer material to fill the recesses and lining the plug openings.
第10圖繪示將第9圖結構中各栓塞開口底部之間隙層材料移除。Figure 10 illustrates the removal of the gap layer material at the bottom of each plug opening in the structure of Figure 9.
第11圖繪示對於第10圖之結構，建立第三光阻光罩並進行蝕刻。Fig. 11 is a view showing the structure of Fig. 10, establishing a third photoresist mask and etching.
第12圖繪示對於第11圖之結構，蝕刻層間栓塞開口處暴露於外的絕緣層，以於該些絕緣層其上下兩導電層間建立凹陷部，並隨後移除該第三光阻光罩。12 is a view showing the structure of FIG. 11 , etching the insulating layer exposed at the opening between the interlayer plugs to form a recess between the upper and lower conductive layers of the insulating layer, and then removing the third photoresist mask .
第13圖繪示對於第12圖之結構，將導電材料填充於層間栓塞開口與栓塞開口，以建立一層間栓塞以及分別位於第一、第二、第三及第四栓塞開口之第一、第二、第三及第四栓塞，其中該層間栓塞與各導電層電性接觸，該第一、第二、第三及第四栓塞分別電性連接致第一、第二、第三及第四導電層。Figure 13 is a diagram showing the structure of Figure 12, filling a conductive material between the interlayer plug opening and the plug opening to establish an inter-layer plug and the first, second, third and fourth plug openings respectively. Second, third and fourth plugs, wherein the interlayer plug is in electrical contact with each conductive layer, and the first, second, third and fourth plugs are electrically connected to the first, second, third and fourth respectively Conductive layer.
第14-17圖描繪三維堆疊式積體電路裝置之第二實施例的結構以及其製作方法。Figures 14-17 depict the structure of a second embodiment of a three-dimensional stacked integrated circuit device and a method of fabricating the same.
第14圖繪示類似於第9圖所示之一結構，但並非如第8圖所示之蝕刻方式，栓塞開口係蝕刻通過部分之覆蓋第二、第三及第四導電層的絕緣層，隨後沉積不導電之間隙層材料。Figure 14 is a view similar to the structure shown in Figure 9, but not in the etching mode shown in Figure 8, the plug opening is etched through a portion of the insulating layer covering the second, third and fourth conductive layers, A non-conductive gap layer material is then deposited.
第15圖繪示對於第14圖之結構，蝕刻通過部分該第二、第三及第四導電層。Figure 15 is a view showing the structure of Figure 14 etched through portions of the second, third and fourth conductive layers.
第16圖繪示對於第15圖之結構，以類似於第11圖之方式沉積一第三光阻光罩。Fig. 16 is a view showing the structure of Fig. 15 in which a third photoresist mask is deposited in a manner similar to that of Fig. 11.
第17圖繪示對於第16圖之結構，蝕刻層間栓塞開口處暴露於外的絕緣層，以於其上下兩導電層間建立凹陷部。Fig. 17 is a view showing the structure of Fig. 16, etching the insulating layer exposed at the opening between the interlayer plugs to form a depressed portion between the upper and lower conductive layers.
第18-20圖描繪三維堆疊式積體電路裝置之第三實施例的結構以及其製作方法。Figures 18-20 depict the structure of a third embodiment of a three-dimensional stacked integrated circuit device and a method of fabricating the same.
第18圖繪示類似於第7圖所示結構之結構，但氧化該第一、第二及第三導電層之凹陷邊緣。Figure 18 is a view similar to the structure of the structure shown in Figure 7, but oxidizing the depressed edges of the first, second and third conductive layers.
第19圖繪示對於第18圖之結構，於第二、第三及第四栓塞開口之底部蝕刻通過第一、第二及第三絕緣層，以暴露第二、第三及第四導電層。Figure 19 is a view showing the structure of Figure 18, etched through the first, second and third insulating layers at the bottom of the second, third and fourth plug openings to expose the second, third and fourth conductive layers .
第20圖繪示對於第19圖之結構，以一電性絕緣間隙層為栓塞開口加襯，該電性絕緣間隙層並填充位於上下兩絕緣層間之導電層凹陷部。Figure 20 is a diagram showing the structure of Figure 19, in which an electrically insulating gap layer is used to line the plug opening, and the electrically insulating gap layer fills the recess of the conductive layer between the upper and lower insulating layers.
10．．．三維堆疊式積體電路裝置10. . . Three-dimensional stacked integrated circuit device
11．．．堆疊11. . . Stacking
17．．．互連區域17. . . Interconnected area
18.1、18.2、18.3、18.4．．．接點層18.1, 18.2, 18.3, 18.4. . . Contact layer
19．．．基板19. . . Substrate
25．．．介電層25. . . Dielectric layer
29．．．氧化層29. . . Oxide layer
30．．．氧化層30. . . Oxide layer
32．．．間隙層32. . . Gap layer
34.1、34.2、34.3、34.4．．．導電層34.1, 34.2, 34.3, 34.4. . . Conductive layer
36.1、36.2、36.3、36.4．．．絕緣層36.1, 36.2, 36.3, 36.4. . . Insulation
50．．．環形部分50. . . Ring part
51.1、51.2、51.3、51.4．．．栓塞外延部51.1, 51.2, 51.3, 51.4. . . Plug extension
52．．．層間介電質52. . . Interlayer dielectric
54.1、54.2、54.3、54.4．．．栓塞54.1, 54.2, 54.3, 54.4. . . embolism
55．．．層間栓塞55. . . Interlaminar embolization
56．．．層間栓塞外延部56. . . Interlayer embedding extension
58．．．底部橫向尺寸58. . . Bottom lateral dimension
60．．．相關橫向尺寸60. . . Related lateral dimensions
61．．．介電側壁間隔層61. . . Dielectric sidewall spacer
62．．．間隙層材料62. . . Gap layer material
70．．．孔洞70. . . Hole
Claims (22)
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| US20010009805A1 (en) * | 2000-01-21 | 2001-07-26 | Samsung Electronics Co., Ltd. | Borderless contact structure and method of forming the same |
| US20080284006A1 (en) * | 2007-05-16 | 2008-11-20 | Samsung Electronics Co., Ltd. | Semiconductor devices including interlayer conductive contacts and methods of forming the same |
| US20090001437A1 (en) * | 2007-06-27 | 2009-01-01 | Samsung Electronics Co., Ltd. | Integrated Circuit Devices Including Recessed Conductive Layers and Related Methods |
| US20100044778A1 (en) * | 2008-08-21 | 2010-02-25 | Kwang-Soo Seol | Non-volatile memory device and method of manufacturing same |
| US20100155810A1 (en) * | 2008-12-24 | 2010-06-24 | Samsung Electronics Co., Ltd. | Multi-layer nonvolatile memory devices having vertical charge storage regions |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20010009805A1 (en) * | 2000-01-21 | 2001-07-26 | Samsung Electronics Co., Ltd. | Borderless contact structure and method of forming the same |
| US20080284006A1 (en) * | 2007-05-16 | 2008-11-20 | Samsung Electronics Co., Ltd. | Semiconductor devices including interlayer conductive contacts and methods of forming the same |
| US20090001437A1 (en) * | 2007-06-27 | 2009-01-01 | Samsung Electronics Co., Ltd. | Integrated Circuit Devices Including Recessed Conductive Layers and Related Methods |
| US20100044778A1 (en) * | 2008-08-21 | 2010-02-25 | Kwang-Soo Seol | Non-volatile memory device and method of manufacturing same |
| US20100155810A1 (en) * | 2008-12-24 | 2010-06-24 | Samsung Electronics Co., Ltd. | Multi-layer nonvolatile memory devices having vertical charge storage regions |
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