TWI464883B - 形成具深溝式電荷補償區域之半導體裝置之方法 - Google Patents

形成具深溝式電荷補償區域之半導體裝置之方法 Download PDF

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TWI464883B
TWI464883B TW101132234A TW101132234A TWI464883B TW I464883 B TWI464883 B TW I464883B TW 101132234 A TW101132234 A TW 101132234A TW 101132234 A TW101132234 A TW 101132234A TW I464883 B TWI464883 B TW I464883B
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Gary H Loechelt
Peter J Zdebel
Gordon M Grivna
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Semiconductor Components Ind
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Description

形成具深溝式電荷補償區域之半導體裝置之方法
本發明一般有關半導體裝置，尤其有關功率切換裝置及其製造方法。
金氧半導體場效電晶體(MOSFET)為常見的功率切換裝置類型。MOSFET裝置包括：源極區域、汲極區域、在源極區域及汲極區域之間延伸的通道區域、及鄰接通道區域提供的閘極結構。閘極結構包括布置鄰接通道區域且和通道區域以介電薄層隔開的導電閘極層。
當MOSFET裝置在開啟狀態中，會對閘極結構施加電壓以在源極區域及汲極區域之間形成傳導通道區域，讓電流流動通過裝置。在關閉狀態中，對閘極結構所施加的任何電壓將低到使傳導通道無法形成，因而無法形成電流。在關閉狀態期間，裝置必須支援源極區域及汲極區域之間的高壓。
有兩個主要參數駕馭今日的高壓功率開關市場：崩潰電壓(BVdss)與開啟狀態電阻(Rdson)。對於特定應用而言，需要使用最小崩潰電壓，而實際上，設計者通常能夠達成BVdss規格的要求。然而，這通常會犧牲Rdson。對高壓功率切換裝置的製造者及使用者而言，此效能上的權衡是主要的設計挑戰。
近來，為了改進Rdson及BVdss間的權衡，超接合裝置漸 獲重視。在習用的n通道超接合裝置中，多個高濃度摻雜之擴散的n型及p型區域取代一個輕微摻雜的n型磊晶區域。在開啟狀態中，電流流動通過高濃度摻雜的n型區域，因而降低Rdson。在關閉狀態或閉鎖狀態中，高濃度摻雜的n型及p型區域彼此耗盡或彼此補償以提供高BVdss。雖然超接合裝置的前景看好，但在製造時仍有重大挑戰。
目前高壓功率切換產品的另一個問題是其通常需要大量輸入(如，閘極或控制電極)電荷，以從一個狀態切換至另一個狀態。除了別的以外，此需求對於周邊控制電路造成額外負擔。
因此，需要高壓功率切換裝置結構及其製造方法，以提供較低的Rdson、高BVdss並減少輸入電荷。
為了便於瞭解，圖式中的元件未必按比例繪製，及所有不同圖式中視需要使用相同的元件。儘管下文說明n通道裝置，但本發明亦有關藉由顛倒所述薄層及區域之導電率類型來形成的p通道裝置。
此外，本發明的裝置可執行蜂巢式設計(其中本體區域為複數個蜂巢式區域)或單一本體設計(其中本體區域由按通常為蛇形圖案之伸長圖案形成的單一區域組成)。然而，為便於瞭解，在整個說明中皆將本發明之裝置說明為蜂巢式設計。應明白，本發明希望既包括蜂巢式設計又包括單一的基本設計。
圖1顯示根據本發明之絕緣閘極場效電晶體(IGFET)、MOSFET、超接合裝置、或切換裝置或單元10的局部放大橫截面圖。舉例而言，裝置10係屬於在半導體晶片中整合邏輯組件及/或其他組件作為功率積體電路之部分的許多此類裝置。或者，裝置10屬於整合一起以形成離散電晶體裝置的許多此類裝置。
裝置10包括半導體材料11的區域，該區域包含如具有範圍介於約0.001至約0.005 ohm-cm之電阻率的n型矽基板12並可以砷進行摻雜。在所示的具體實施例中，基板12提供汲極接觸。半導體層14係形成於基板12中或形成於其上，且根據本發明為輕微摻雜的n型或p型或含有極少量的雜質(即，為本質半導體層)。在示範性具體實施例中，半導體層14係使用習用的磊晶生長技術來形成。在適於750伏特裝置的示範性具體實施例中，半導體層14為摻雜物濃度約1.0x1013 atoms/cm3 至約5.0x1013 atoms/cm3 的p型，具有等級約40微米的厚度。半導體層14的厚度隨著裝置10的所需BVdss額定值而增加或減少。應明白，半導體材料11的本體或其部分可使用其他材料，包括矽-鍺、矽-鍺-碳、摻雜碳的矽、或其類似物。
裝置10亦包括形成於半導體材料11之區域之上表面或主表面18中或與其鄰接的n型區域或毯狀層17。N型區域17提供裝置10低電阻電流路徑，其詳細說明如下。在示範性具體實施例中，n型區域17具有最大濃度等級約6.0x1016 atoms/cm3 及深度約0.4微米。視情況，p型區域或毯狀層19 係形成於主表面18之中或與其鄰接，且在n型區域17之下或與其鄰接。P型區域19對n型區域17及半導體層14間的pn接合面提供較佳控制，且在完全耗盡條件下提供n型區域17電荷補償。在示範性具體實施例中，p型區域19具有表面濃度約5.0x1015 atoms/cm3 及深度約0.8微米。
根據本發明，裝置10進一步包括填充溝渠、半導體材料填充溝渠、磊晶填充區域或溝渠、電荷補償溝渠區域、深溝式電荷補償區域、電荷補償填充溝渠或電荷補償區域22。電荷補償填充溝渠22包括複數個層或多個半導體材料層，其包括相反導電率類型的層，其較佳是以本質或緩衝半導體層來隔開。除了別的以外，本質層作用可防止混合相反導電率類型的層(即，兩個電荷層)，因這在開啟狀態中，對裝置10的傳導效率有不利的影響。
在示範性具體實施例中，填充溝渠22包括使用磊晶生長技術形成之多個層或堆疊的半導體材料層。例如，填充溝渠22包括形成於鄰接半導體材料11之本體之溝渠壁面或表面上、或其上方、或和其鄰接的n型層23。本質半導體或緩衝層24係形成於n型層23上、或其上方、或和其鄰接，p型層26係形成於本質半導體層24上、或其上方、或和其鄰接，及本質半導體或緩衝層27係形成於p型層26上、或其上方、或和其鄰接。除了別的以外，本質層24作用可防止混合薄層23及26，其如先前所述，改良裝置10的傳導效率。除了別的以外，本質層27作用可填充其餘溝渠。對於n通道裝置及根據本發明，n型層23在裝置10處於開啟狀態 時提供通道至汲極的主要垂直低電阻電流路徑。當裝置10處於關閉狀態時，根據本發明，n型層23及p型層26彼此補償，以提供增加的BVdss特性。應明白，可使用附加的n型層及p型層，且較佳是以附加的本質層或緩衝層隔開。
舉例而言，n型層23及p型層26各具有摻雜物濃度等級約2.0x1016 至約4.0x1016 atoms/cm3 及各具有厚度約0.1微米至約0.3微米。在示範性具體實施例中，本質半導體或緩衝層24及27為未摻雜或極輕微摻雜的p型，其摻雜物濃度低於約2.0x1014 atoms/cm3 ，及各具有厚度約0.5微米至約1.0微米。調整本質層27的厚度以如填充溝渠的剩餘部分。
在填充溝渠22間及在其附近或和其鄰接，本體或摻雜區域31係形成於半導體層14中，並自主表面18延伸。在示範性具體實施例中，本體區域31包含p型導電率，具有適於形成操作為裝置10之傳導通道45之反向層的摻雜物濃度，其說明如下。本體區域31自主表面18延伸至深度約1.0至約5.0微米。n型源極區域33係於本體區域31內或其中形成，且自主表面18延伸至深度約0.2微米至約0.5微米。p型本體接觸或接觸區域36亦形成於本體區域31中，並提供較低接觸電阻至主表面18的本體區域31。此外，接觸區域36可降低源極區域33下之本體區域31的薄片電阻，以抑制寄生雙極效應。
第一介電層41係形成於主表面18的部分之上或與其鄰接。在示範性具體實施例中，介電層41包含具有厚度約0.1微米至約0.2微米的熱氧化層。第二介電層42係形成於 介電層41之上。在示範性具體實施例中，第二介電層42包含氮化矽，具有厚度約0.1微米。
閘極介電層43係形於主表面18鄰接本體區域31的其他部分之上或與其鄰接。在示範性具體實施例中，閘極介電層43包含氧化矽，具有厚度約0.05微米至約0.1微米。在替代性具體實施例中，閘極介電層43包含：氮化矽、五氧化鉭、二氧化鈦、鈦酸鍶鋇、或其組合(包括氧化矽之組合)、或其類似物。
根據本發明的一項具體實施例，摻雜的多晶半導體層、導電層、或接地平面層46係形成於介電層41及42之上，且透過形成於介電層41及42的開口47接觸p型層26。在示範性具體實施例中，導電層46包含多晶矽層，具有厚度約0.1微米，且具有n通道裝置的p型導電率。在進行熱處理時，導電層46的p型摻雜物擴散至填充溝渠22以形成p型摻雜區域52，因而強化p型層26的歐姆接觸。在替代性具體實施例中，導電層46包含非晶矽、金屬、矽化物、或其中包括多晶矽之組合的組合。如果導電層46使用金屬，則先透過開口47植入或沉積p型摻雜物以形成p型摻雜區域52，以強化p型層26層的歐姆接觸。導電層46較佳是直接或間接地連結或耦合至導電接觸或源極接觸層63，如圖1所示。
根據本發明，除了別的以外，導電層46可作為接地平面，以快速且有效地提供要自裝置清除或清除於裝置外之少數載子的路徑，以減少切換裝置10從一個狀態至另一個 狀態所需的輸入電荷及提高切換速度。另外，如下文詳細說明，另外使用導電層46作為根據本發明之邊緣終止結構的部分。
第三介電層48係形成於導電層46之上，及第四介電層51係形成於第三介電層48之上。在示範性具體實施例中，介電層48包含氮化矽(如，厚度約0.05微米)，及介電層51包含沉積氧化矽(如，厚度約0.7微米)。導電層53係形成於介電層51之上，且包含如n型多晶矽(如，厚度約0.3微米)。
導電間隔物閘極區域、垂直間隔物閘極區域、或間隔物定義閘極區域57係形成於閘極介電層43之上，並以介電質間隔物59而和導電層46隔離。導電間隔物閘極區域57連同閘極介電層43形成控制電極或閘極結構58。導電間隔物閘極區域57包含如n型多晶矽，厚度約0.8微米。在示範性具體實施例中，介電質間隔物59包含氮化矽，厚度約0.1微米。間隔物閘極區域57係耦合至導電層53以提供導電閘極結構，以在裝置10中控制通道45的形成及電流的傳導。在所示的具體實施例中，導電連接部分77將間隔物閘極區域57耦合至導電層53。導電連接部分77包含如n型多晶矽。間隔物閘極區域是指以在一表面上之沉積閘極材料形成的控制電極，以控制在另一垂直表面上形成的通道。至於裝置10，通道45係形成於視為水平表面的表面18。用以形成間隔物閘極區域57的控制電極薄膜係沿著和表面18垂直的垂直表面68沉積。
根據本發明的導電間隔物閘極區域57和習用的裝置相 比，提供最小的閘極至汲極重疊，藉此大幅減少閘極電荷。另外，在裝置10中，由高出主表面18上的導電層53提供閘極的電選路，藉此進一步減少閘極電荷。此外，除了別的以外，導電層46可作為***於閘極及汲極區域間的接地平面，以進一步減少閘極至汲極電容。本發明的這些特色可提高切換速度及減少輸入電荷需求。
第五介電層61係形成於裝置10的部分之上，且包含如具有厚度約0.05微米的氮化矽。層間介電(ILD)層62係形成於裝置10的部分之上，且包含如具有厚度約0.8微米的沉積氧化矽。在介電層中形成開口以提供源極接觸層63對裝置10的接觸。如圖所示，蝕刻主表面18的部分，致使源極接觸層63接觸源極區域33及本體區域36。在示範性具體實施例中，源極接觸層63包含鋁矽合金或其類似物。汲極接觸層66係形成於半導體材料11之區域的相對表面，且包含如可焊接的金屬結構，如鉭-鎳-銀、鉻-鎳-金、或其類似物。
裝置10的操作說明如下。假設源極終端63操作於零伏特的電位VS ，間隔物閘極區域57接收大於裝置10之傳導臨限值的控制電壓VG =5.0伏特，及汲極終端66操作於汲極電位VD =5.0伏特。VG 及VS 的值導致本體區域31在間隔物閘極區域57下反向，以形成使源極區域33電連接至層17的通道45。裝置電流IS 流自源極終端63並透過源極區域33、通道45、層17、n型層23選路至汲極終端66。因此，電流IS 垂直地流動通過n型層23，以產生低導通電阻。在一項具體 實施例中，IS =1.0安培。要將裝置10切換至關閉狀態，將小於裝置之傳導臨限值的控制電壓VG 施加於間隔物閘極57(如，VG <5.0伏特)。這將移除通道45，IS 不再流動通過裝置10，且導電層46將少數載子清除於裝置外。在關閉狀態中，n型層23及p型層26彼此補償為主要阻擋接合面散布的耗盡區域，以提高BVdss。在一項具體實施例中，在半導體層14為n型時，由本體區域31及半導體層14形成主要阻擋接合面。在另一項具體實施例中，在半導體層14為p型時，由半導體層14及基板12形成主要阻擋接合面。
現在參考圖2-7說明形成根據本發明之裝置10的程序。圖2顯示裝置10在初期製造階段的局部放大橫截面圖。在初期步驟，介電層40係形成於主表面18之上，及透過介電層40將選擇性p型區域19離子植入半導體層14。在示範性具體實施例中，以劑量約5.0x1011 atoms/cm2 及植入能量600 KeV植入硼以形成p型層19。接著，透過介電層40將n型層17離子植入半導體層14。在示範性具體實施例中，以劑量約2.0x1012 atoms/cm2 及植入能量600 KeV植入磷以形成n型層17。
然後，在主表面18之上形成及圖案化遮罩層71以形成開口72。然後，使用習用的技術蝕刻介電層40，以透過開口72曝露半導體材料11之本體的部分。舉例而言，開口72具有等級約3.0微米至約5.0微米的寬度74。接著，透過層17、19、及14蝕刻溝渠122。在示範性具體實施例中，溝渠122延伸至基板12的至少一部分。溝渠122的深度係由半 導體層14的厚度(為BVdss的函數)決定。在示範性具體實施例中，使用以氟或氯為主之化學物蝕刻的深反應性離子蝕刻(DRIE)形成溝渠122。DRIE蝕刻可使用若干技術，包括低溫、高密度電漿、或Bosch DRIE處理。在示範性具體實施例中，溝渠122具有實質上為垂直的側壁。在替代性具體實施例中，溝渠122具有溝渠在溝渠下表面的寬度小於寬度74的倒錐形輪廓。在使用習用的蝕刻技術形成溝渠122後移除遮罩層71。雖然說明溝渠122為複數，但應明白，溝渠122可以是單一連續溝渠或連接的溝渠矩陣(如圖10所示，其說明如下)。或者，溝渠122可以是複數個具有封閉末端及以半導體材料11之本體之部分隔開的個別溝渠。
圖3顯示裝置10在進一步處理階段的局部放大橫截面圖。此時，如形成填充溝渠22的第一階段，在溝渠122中形成、生長、或沉積半導體材料層。在示範性具體實施例中，使用半導體磊晶生長技術來填充溝渠122。
在第一步驟，在溝渠122的側壁上形成薄的熱氧化物，以移除因DRIE步驟所損壞的任何表面。然後，使用習用的各向同性蝕刻技術移除薄的熱氧化物。接著，如磊晶生長程序的第一步驟，將半導體材料11的本體置入磊晶生長反應器並進行預清洗。當填充層(如，層23、24、26、及27)的所選半導體材料是矽時，如SiHCl3 、SiH2 Cl2 、SiH4 或Si2 H6 的矽來源氣體適於形成這些層。在所示的具體實施例中，生長毯狀層(即，除了溝渠122之外，在主表面18 之上生長的這些層)。在替代性具體實施例中，使用選擇的磊晶生長技術以形成層23、24、26、及27，致使這些層不會在介電層40之上形成。
先沿著溝渠122的表面生長N型層23，以砷為合適的摻雜物來源。在示範性具體實施例中，n型層23具有摻雜物濃度等級約2.0x1016 至約4.0x1016 atoms/cm3 ，及厚度約0.1微米至約0.3微米。
接著，在n型層23之上生長本質或緩衝層24，其未經摻雜(除了通常在先前生長步驟後留在反應器隔室中之矽來源材料及/或殘餘摻雜物氣體中出現的這些微量雜質之外)，或為摻雜物濃度低於約2.0x1014 atoms/cm3 的輕微摻雜p型。層24具有厚度約0.5微米至約1.0微米。然後，在層24之上生長P型層26，以硼摻雜物來源為合適的摻雜物來源。在示範性具體實施例中，p型層26具有摻雜物濃度等級約2.0x1016 至約4.0x1016 atoms/cm3 ，及厚度約0.1微米至約0.3微米。然後，在p型層26之上生長本質或緩衝層27，其未經摻雜(除了通常在先前生長步驟後留在反應器隔室中之矽來源材料及/或殘餘摻雜物氣體中出現的這些微量雜質之外)，或為摻雜物濃度低於約2.0x1014 atoms/cm3 的輕微摻雜p型。層27具有厚度約0.5微米至約1.0微米。應明白，將根據溝渠122的寬度來調整層23、24、26、及27的厚度。在示範性具體實施例中，這些層的厚度將使所形成的磊晶層填滿溝渠122。當使用毯狀磊晶生長程序時，其後以化學機械拋光技術、回蝕技術、其組合、或其類似物 平坦化層27、26、24、及23。在平坦化程序中，將磊晶層27、26、24、及23向下或往回平坦化至主表面18，以形成填充溝渠22。在示範性具體實施例中，平坦化程序亦移除介電層40。可使用附加的蝕刻步驟，以進一步移除層40的任何殘餘介電材料。如果使用選擇的磊晶生長或選擇的回蝕技術，介電層40可留下並將取代層41，其說明如下。
圖4顯示裝置10在進一步處理後的局部放大橫截面圖。第一介電層41係形成於主表面18之上，且包含如氧化矽約0.1微米至約0.2微米厚。生長於攝氏750度的熱氧化物將為合適的熱氧化物。在選擇性步驟，使用濺鍍蝕刻步驟讓第一介電層41的上表面或曝露表面光滑。接著，第二介電層42係形成於介電質41之上，且包含如約0.1微米的氮化矽。然後，使用接觸微影蝕刻及蝕刻步驟以形成通過第二介電層42及第一介電層41的開口47。這將曝露主表面18在填充溝渠22之上的部分，如圖4所示。在示範性具體實施例中，開口47具有等級約0.5微米至約1.0微米的寬度49。
然後，導電層46係形成於第二介電層42之上，並透過開口47接觸或耦合至填充溝渠22。在示範性具體實施例中，導電層46包含約0.1微米的多晶矽，且為沉積摻雜或未摻雜。如果初始沉積導電層46時並未摻雜，則其後使用如離子植入技術摻雜導電層46。在此示範性具體實施例中，以硼摻雜導電層46，以提供p型層26的接觸。硼離子植入劑量約5.0x1015 至約1.0x1016 atoms/cm2 及植入能量約60 KeV將足以摻雜導電層26。在後續的熱處理步驟，導電層46的 摻雜物擴散至填充溝渠22以形成p型區域52。
接著，第三介電層48係形成於導電層46之上，及第四介電層51係形成於第三介電層48之上。第三介電層48包含如氮化矽(如，厚度約0.05微米)，及介電層51包含沉積氧化矽(如，厚度約0.7微米)。然後，導電層53係形成於第四介電層51之上，且包含如n型多晶矽(如，厚度約0.3微米)。介電層54係形成於導電層53之上，且包含如約0.15微米的氮化矽。
執行微影蝕刻及蝕刻步驟以蝕刻通過層54、53、51、48、46、及42的部分，以提供開口70。這亦形成基座堆疊結構56，其包含層42、46、48、51、53、及54的部分。在示範性具體實施例中，開口70具有等級約5.0微米至約8.0微米的寬度73。
圖5顯示裝置10在形成介電質間隔物59之附加處理步驟後的局部放大橫截面圖。在示範性具體實施例中，在基座堆疊結構56及第一介電層41之上沉積氮化矽薄膜。舉例而言，使用化學汽相沉積技術沉積約0.1微米厚的氮化矽薄膜。接著，使用習用的各向異性回蝕步驟移除氮化矽層在基座堆疊結構56及第一介電層41之上的部分，並留下氮化矽層在基座堆疊結構56之側壁或垂直表面68上的部分，以形成介電質間隔物59。
然後，使用氧化矽濕式蝕刻來移除介電層41在開口70內的部分。舉例而言，使用稀釋的氫氟酸(如，50：1)來蝕刻介電層41。在示範性具體實施例中，延長蝕刻時間(如，8 至15分鐘)以從介電質間隔物59下底切或移除介電層41的材料，以形成凹陷部分74。凹陷的介電層41依此方式確保在本體區域31中形成的通道45(如圖1所示)延伸至層17，以允許通道電流更有效地流動。在示範性具體實施例中，部分74在介電質間隔物59之下凹陷距離約0.1微米。然後，在開口70內的主表面18上生長熱氧化矽至厚度約0.08微米，以形成閘極介電層43。
圖6顯示裝置10在進一步處理後的局部放大橫截面圖。在裝置10之上沉積半導體材料的保形層至厚度約0.1微米至約0.15微米。然後，透過開口70及半導體材料的保形層將硼摻雜物引進主表面18，以提供本體區域31的p型摻雜物。在示範性具體實施例中，半導體材料的保形層包含未摻雜的多晶矽，及硼係透過未摻雜的多晶矽植入層17。離子植入劑量約1.0x1013 atoms/cm2 及植入能量約160 KeV適於650伏特裝置。在植入步驟後，使用清洗或蝕刻程序以清洗半導體材料之保形層的表面。
然後，在第一保形層之上沉積半導體材料的第二保形層，並蝕刻此二層以提供間隔物閘極57。在示範性具體實施例中，半導體材料的第二保形層包含約0.8微米的n型多晶矽，其係在沉積程序中進行摻雜或在其後使用離子植入或其他摻雜技術進行摻雜。在形成間隔物閘極57後，在間隔物閘極57的表面上加入附加之0.015微米的閘極介電質(如，氧化矽)並曝露閘極氧化物43的部分。
在示範性具體實施例中，蝕刻步驟曝露介電層54及介電 質間隔物59的上方部分。然後，蝕刻保護層54及介電質間隔物59的上方部分以移除保護層54，及在間隔物閘極57與導電層53之間移除介電質間隔物59的上方部分。
在進一步的步驟，沉積如多晶矽的導電材料，以提供連接導電部分77。連接導電部分77使間隔物閘極57耦合至或電連接至導電層53。然後，執行n型摻雜步驟以摻雜連接導電部分77及以提供源極區域33的摻雜物。在示範性具體實施例中，此摻雜步驟使用砷植入劑量3.0x1015 atoms/cm2 及植入能量80 KeV。
圖7顯示裝置10在進一步製造步驟後的局部放大橫截面圖。沉積第五介電層61，其包含如約0.05微米的氮化矽。然後，在第五介電層61之上沉積ILD層62。在示範性具體實施例中，ILD層62包含沉積氧化矽厚度約0.8微米。使用選擇性ILD錐形物蝕刻使ILD層62的部分62a成錐形，這有助於其後所形成層的階梯覆蓋率。
接著，使用習用的微影蝕刻及蝕刻步驟以形成接觸開口81，其將曝露主表面18的部分。然後，透過開口81，使用p型離子植入步驟形成接觸區域36。舉例而言，使用硼離子植入劑量3.0x1014 atoms/cm2 及植入能量80 KeV。然後，沉積及蝕刻等形間隔物層，以形成間隔物82。在示範性具體實施例中，沉積及蝕刻0.3微米的氮化矽層，以形成間隔物82。此時使用快速退火步驟以活化及擴散各種離子植入。例如，曝露裝置10於溫度約攝氏1030度約45秒。
然後，使用蝕刻步驟以移除主表面18的部分，以形成凹 陷部分84。這允許源極接觸層63接觸源極區域33及接觸區域36，以使這些區域一起短路。然後，移除間隔物82。在後續處理中，沉積及圖案化源極接觸層63。然後，視情況薄化基板12，及沉積汲極接觸層66，以提供圖1所示的結構。雖然在圖2-7中未顯示，但在所述製造階段中可使用微影蝕刻及蝕刻步驟，例如，在圖4-6中以曝露導電層46的部分，以提供源極接觸區域63耦合至導電層46的開口，如圖1所示。此外，應明白，在沉積源極接觸層63之前可形成其他導電層，如矽化物層。
圖8為描繪根據本發明及根據本文所述處理參數之裝置10之崩潰電壓(BVdss)特性的曲線圖。如圖8所示，裝置10呈現汲極及源極的標稱崩潰電壓約750伏特。另外，如圖8所示，裝置進一步呈現在崩潰之下的低洩漏。
圖9為描繪根據本發明及根據本文所述處理參數之裝置10之開啟狀態電阻(Rdson)特性的曲線圖。和習用之具相似BVdss的超接合裝置相比，裝置10呈現極佳的Rdson特性，其具有等級36 milli-ohm cm2 的典型Rdson值。
圖10顯示適於根據本發明之裝置10之單元結構300的局部放大橫截面圖。根據本發明的一項具體實施例，顯示單元結構300具有圍繞半導體層14之複數個多角形區域314的填充溝渠322，其中形成主動裝置或單元。應明白，多角形區域具有圓角，及應明白，包括圓形、方形、矩形、或其類似物的其他形狀為合適的形狀。蜂巢結構300的一個特色是其提供用於高封裝密度，以改良Rdson及電流載送 能力。根據本發明，填充溝渠322包括n型層23、本質層24與27、及p型層26。
圖11為裝置10之另一部分的局部放大橫截面圖，其顯示根據本發明的選擇性邊緣終止結構100。終止結構100的特色之一是其併入裝置10的基本組件，因而節省了處理成本。終止結構100包括導電接觸層或導電半導體層146，其係形成於主表面18之上且與其鄰接。在示範性具體實施例中，導電接觸半導體層146包含和導電層46相同的材料且係同時形成。例如，導電接觸半導體層146包含p型多晶矽。在熱處理後，p型摻雜物從導電接觸半導體層146擴散以形成p型摻雜層152，其反向摻雜n型層17及耦合至選擇性p型層19。圖11進一步顯示透過開口91而耦合至源極接觸層63的導電接觸半導體層146。
隔離溝渠103係形成於裝置10的周邊，且包含如以介電材料108填充的蝕刻溝渠106。視情況，先形成熱氧化層110以排列隔離溝渠103的側壁及/或下表面。
在替代性具體實施例中及如圖11所示，隔離溝渠103進一步包括和填充溝渠22同時形成的半導體材料層。舉例而言，半導體材料層包括：如參考圖1所述的n型層23、本質或緩衝層24、p型層26、及本質或緩衝層27。如果不使用半導體材料層，則在製造中和填充溝渠22分開形成溝渠106。
在示範性具體實施例中，介電材料108包含使用旋塗式玻璃(SOG)、BPSG、PSG、及/或TEOS沉積技術形成的氧 化矽。在形成氧化物後，使用回蝕或化學機械平坦化技術、其組合、或其類似物平坦化介電區域的上表面。在示範性具體實施例中，溝渠106具有寬度約30微米至約100微米，且係使用和形成參考圖2所述之溝渠122所用技術的類似技術來形成。溝渠106的側壁實質上為垂直、或為倒錐形，致使溝渠106之底部的寬度小於溝渠106之頂部的寬度。舉例而言，介電材料108及/或介電層110延伸至半導體層14下的深度或距離，如圖11所示。
在包括層23、24、26、27及隔離溝渠103的替代性具體實施例中，將n型區域109併入溝渠106下的基板12，以減少和晶粒分割相關聯的任何電流洩漏。
根據本發明，當半導體層14包含p型導電率時，BVdss的主要接合面為半導體層14及n型基板12所形成的pn接合面114。此特色可簡化邊緣終止結構100並可節省空間。例如，習用裝置需要距離約終止結構之磊晶層的厚度1至3X倍。在本發明中，此距離將減為約此厚度的1/2X倍。
在此具體實施例中，接合面114比在習用裝置中的接合面更平，因接合面從基板12耗盡，而非從本體區域31向下及橫跨耗盡。此外，由於導電接觸半導體層146係透過摻雜區域152及19而耦合至半導體層14，因此接合面114橫向延伸至裝置10的邊緣。依此方式，得以最佳化BVdss達成最佳化平面接合。除了別的以外，隔離溝渠103作用可鈍化接合面114。
圖12顯示根據本發明之替代性溝渠隔離203的局部放大 俯視圖。區域131代表裝置10用於參考圖11所述之終止結構的部分，及區域132代表裝置10用於圖1所述之主動結構的部分。當蝕刻隔離溝渠203時，該隔離溝渠包括所形成之複數個柱狀矩陣或形狀117。在示範性具體實施例中，鄰接列的形狀117為相對於彼此偏移，如圖12所示，致使形狀117彼此實質上為等距離。在示範性具體實施例中，柱狀物117相隔約5微米至約15微米。
舉例而言，形狀117為半導體材料11之本體之部分的柱狀物或區域。在示範性具體實施例中，形狀117包含：基板12、半導體層14、p型層19、n型層17、及介電層41，且具有寬度或直徑約0.8微米至約1.0微米。這如圖13清楚所示，圖13為沿著圖12之參考線13-13截取之隔離溝渠203之部分的放大橫截面圖。圖13顯示形成介電材料208前的隔離溝渠203。使用習用的微影蝕刻及蝕刻技術以形成溝渠206及形狀117。例如，使用以氟或氯為主之化學物的DRIE。
在形成溝渠206及形狀117後，形成介電層210，如圖14所示。舉例而言，介電層210包含熱生長的氧化矽。接著，沉積及平坦化介電層208。在示範性具體實施例中，介電層208包含旋塗式玻璃。根據本發明，形狀117在沉積介電層208時減少碟化效應，因而提供更平坦的表面、較佳鈍化、及更可靠的裝置。形狀117可為圓形、方形、矩形、多邊形、梯形、橢圓形、三角形、其組合、或其類似物。這些形狀可進一步包括圓角。
圖15顯示鄰接或複數個隔離溝渠203a及203b的局部放大橫截面圖，如兩個以劃分格柵或區域461隔開之裝置的部分所示。在此具體實施例中，半導體晶圓上的鄰接裝置10包括劃分格柵461，其包含半導體材料11的本體，而非在鄰接晶粒間為連續的介電材料208及210。這允許如切割機的晶粒分割裝置晶粒沿著中線463分割，以提供更強健的晶粒分割。
總之，已說明具有深溝式電荷補償的新型切換裝置結構，包括其製造方法。還有，也已說明適於本發明之裝置及其他半導體裝置的接地平面結構。此外，還說明適於本發明之裝置及其他半導體裝置的邊緣終止結構。
雖然本發明已參考其特定具體實施例加以說明及解說，但是不希望本發明限於該等解說性具體實施例。熟習此項技術者應明白，可進行修改與變更而不背離本發明之精神。因此，本發明係有意涵蓋符合隨附申請專利範圍之所有該等變更及修改。
10‧‧‧切換裝置
11‧‧‧半導體材料
12‧‧‧矽基板
14‧‧‧半導體層
17‧‧‧n型區域
18‧‧‧主表面
19‧‧‧P型區域
22‧‧‧電荷補償填充溝渠
23‧‧‧n型層
24、27‧‧‧本質層
26‧‧‧p型層
31‧‧‧本體區域
33‧‧‧源極區域
36‧‧‧接觸區域
40、208、210‧‧‧介電層
41‧‧‧第一介電層
42‧‧‧第二介電層
43‧‧‧閘極介電層
45‧‧‧傳導通道
46、53‧‧‧導電層
47、70、72、91‧‧‧開口
48‧‧‧第三介電層
49‧‧‧寬度
51‧‧‧第四介電層
52‧‧‧p型摻雜區域
54‧‧‧保護層
56‧‧‧基座堆疊結構
57‧‧‧導電間隔物閘極區域
58‧‧‧控制電極或閘極結構
59‧‧‧介電質間隔物
61‧‧‧第五介電層
62‧‧‧層間介電層
62a‧‧‧ILD層的部分
63‧‧‧源極接觸層
66‧‧‧汲極接觸層
68‧‧‧垂直表面
71‧‧‧遮罩層
74(圖2)‧‧‧寬度
74(圖5)、84‧‧‧凹陷部分
77‧‧‧導電連接部分
81‧‧‧接觸開口
82‧‧‧間隔物
100‧‧‧終止結構
103、203、203a、203b‧‧‧隔離溝渠
106‧‧‧蝕刻溝渠
108、208‧‧‧介電材料
114‧‧‧pn接合面
117‧‧‧柱狀物
122、206‧‧‧溝渠
131‧‧‧用於裝置終止結構之部分的區域
132‧‧‧用於裝置之主動結構之部分的區域
146‧‧‧導電接觸半導體層
152‧‧‧p型摻雜層
300‧‧‧單元結構
322‧‧‧填充溝渠
461‧‧‧劃分格柵
463‧‧‧中線
圖1說明根據本發明之切換裝置的局部放大橫截面圖；圖2-7說明圖1之切換裝置在各種製造階段的局部放大橫截面圖；圖8為顯示圖1之切換裝置之崩潰電壓特性的曲線圖；圖9為顯示圖1之切換裝置之開啟狀態電阻特性的曲線圖；圖10說明適於根據本發明之切換裝置之蜂巢結構的局部 放大俯視圖；圖11說明本發明之切換裝置及邊緣終止結構之放大的局部橫截面圖；圖12說明根據本發明之替代性溝渠隔離結構的局部放大俯視圖；圖13說明圖12之沿著參考線13-13截取之溝渠隔離結構在初期製造階段的局部放大橫截面圖；圖14說明圖13之結構在進一步處理後的局部放大橫截面圖；及圖15說明根據本發明之進一步溝渠隔離結構的局部放大橫截面圖。
10‧‧‧切換裝置
11‧‧‧半導體材料
12‧‧‧矽基板
14‧‧‧半導體層
17‧‧‧n型區域
18‧‧‧主表面
19‧‧‧P型區
22‧‧‧電荷補償填充溝渠
23‧‧‧n型層
24、27‧‧‧本質層
26‧‧‧p型層
31‧‧‧本體區域
33‧‧‧源極區域
36‧‧‧接觸區域
41‧‧‧第一介電層
42‧‧‧第二介電層
43‧‧‧閘極介電層
45‧‧‧傳導通道
46、53‧‧‧導電層
47‧‧‧開口
48‧‧‧第三介電層
51‧‧‧第四介電層
52‧‧‧p型摻雜區域
57‧‧‧導電間隔物閘極區域
58‧‧‧控制電極或閘極結構
59‧‧‧介電質間隔物
61‧‧‧第五介電層
62‧‧‧層間介電層
63‧‧‧源極接觸層
68‧‧‧垂直表面
77‧‧‧導電連接部分

Claims (10)

  1. 一種形成一半導體裝置之方法，其包含：提供包含一基板(12)之一半導體材料區域(11)，其包括在該基板上方(overlaying)之一半導體層(14)，其中該半導體層具有與該基板間隔開之一主表面(major surface)(18)；形成一垂直方向(vertically-oriented)導電區域(23)，其自該主表面向該基板延伸；形成一水平方向摻雜(doped)區域(17)，其鄰接(adjacent)於該主表面之一部分；形成一本體(body)區域(31)，其鄰接於該主表面之另一部分；在該水平方向摻雜區域上方形成一導電層(46)，其中該導電層係與該垂直方向導電區域間隔開；及在該本體區域之一部分及該水平方向摻雜區域上方形成一閘極電極(57)，其中該閘極電極係與該本體區域及該水平方向摻雜區域間隔開且與該本體區域及該水平方向摻雜區域電絕緣。
  2. 如請求項1之形成一半導體裝置之方法，其中形成該垂直方向導電區域包含：形成一溝渠(22)，其自該主表面延伸；及於側壁及該溝渠之一較低表面上方形成該垂直方向導電區域，其中該垂直方向導電區域包含一第一導電率類型之一磊晶層。
  3. 如請求項2之形成一半導體裝置之方法，進一步包含：在該垂直方向導電區域上方形成一第一本質層(24)；在該第一本質層上方形成一第二導電率類型之一磊晶層(26)，其中該第一本質層係形成於該垂直方向導電區域及該第二導電率類型之該磊晶層之間以減少混合相反導電率類型摻雜物；及在該第二導電率類型之該磊晶層上方形成一第二本質層(27)。
  4. 如請求項3之形成一半導體裝置之方法，其中提供該半導體材料區域包含提供包含該第一導電率類型的該基板及包含該第二導電率類型的該半導體層。
  5. 如請求項3之形成一半導體裝置之方法，其中形成該導電層包含使該導電層電性耦合至該第二導電率類型之該磊晶層。
  6. 一種形成一半導體裝置之方法，其包含：提供一半導體材料之本體(11)，其包括一第一導電率類型之一基板(12)及一半導體層(14)，該半導體層係形成為與該基板為間隔關係且該半導體層具有一主表面(18)；於該半導體層中形成一第二導電率類型之一本體區域(31)，其鄰接於該主表面；於該半導體材料之本體中形成該第一導電率類型之一第一導電層(23)，其自該主表面向該基板延伸，其中該第一導電層係與該本體區域間隔開且經組態以提供用於 該半導體裝置之一主要垂直低電阻電流路徑；形成該第一導電率類型之一第二導電層(17)，其鄰接於該主表面且聯接(adjoin)該本體區域及該第一導電層，其中該第二導電層係經組態為用於該半導體裝置之一水平低電阻電流路徑；及形成一絕緣閘極層(57)，其鄰接該本體區域及該第二導電層。
  7. 如請求項6之形成一半導體裝置之方法，其中形成該第一導電層包含：形成一溝渠(22)，其自該主表面延伸；及在該溝渠之表面上方形成該第一導電層，其中該第一導電層包含一磊晶層。
  8. 如請求項7之形成一半導體裝置之方法，進一步包含下列步驟：在該第一導電層上形成一第一本質層(24)；在該第一本質層上方形成一第二導電率類型之一磊晶層(26)，其中該第一本質層係被形成於該第一導電層及該第二導電率類型之該磊晶層之間以減少混合相反導電率類型摻雜物；及在該第二導電率類型之該磊晶層上方形成一第二本質層(27)。
  9. 如請求項6之形成一半導體裝置之方法，其進一步包含在該第一導電層上方形成一遮護電極(46)之步驟。
  10. 如請求項6之形成一半導體裝置之方法，其中提供該半 導體材料之本體包含提供包含該第二導電率類型的該半導體層。
TW101132234A 2005-02-15 2005-11-16 形成具深溝式電荷補償區域之半導體裝置之方法 TWI464883B (zh)

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