TWI464746B - A clearing circuit for memory - Google Patents
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Description
本發明係有關於一種電子裝置之控制電路，特別是指一種記憶體之清除電路。
The present invention relates to a control circuit for an electronic device, and more particularly to a memory clearing circuit.
近年來，資訊技術與電腦技術不斷演進，讓電腦系統從伺服器發展到個人電腦，又從桌上型電腦發展到可攜式電腦(例如:筆記型電腦)。在電腦系統之發展演進過程中，電腦系統皆需要依據系統晶片之記憶體所儲存之系統設定值進行開機程序，以進入作業系統中，但電腦系統在發生異常時，即會發生無法執行開機程序的問題，此時，使用者會重啟動電腦系統，以排除異常。一般電腦系統之異常是藉由開啟與關閉電腦系統之電源而排除，但使用者在藉由切換電源仍無法排除電腦系統之異常時，使用者即需要清除電腦系統之系統設定值，以排除異常。
一般而言，電腦系統上設有平台控制器集線器(Platform Controller Hub，PCH)、基板管理控制器(Baseboard Management Controller，BMC)或複雜可程式化邏輯裝置(Complex Programmable Logic Device)等可程式化晶片，以作為電腦系統之系統晶片。而系統晶片中一般具有一記憶體，用於儲存電腦系統現階段所使用之系統設定值，且系統晶片之記憶體係依據一獨立電源，例如:電池，而維持所儲存之資料，因此，使用者需藉由切斷供應系統晶片之記憶體的電源，才能清除系統晶片之記憶體所儲存之系統設定值而排除異常，進而電腦系統在系統晶片之記憶體於清除資料後回復記憶體之設定值至原廠預設之系統設定值，以排除異常，而正常地進行開機程序，接續於完成開機程序進入作業系統。
由於系統晶片之記憶體的電源並非電源供應器所供應之電源，而是另外設置於電腦系統之一獨立供電單元所供應之電源，例如:電池，以供記憶體儲存系統設定值，因此早期切斷系統晶片之記憶體電源之方法即為直接拔除電腦系統上的電池，以切斷電池對記憶體之供電，再將電池重新耦接系統晶片之記憶體，以讓電池重新供電至系統晶片的記憶體。
但，上述拔除電池之動作甚為麻煩。現今業者遂針對拔除供電單元不方便之問題，發展出另一種重置系統晶片之電源之方法，其設置一切換開關於系統晶片之記憶體與電池之間，以提供使用者在電腦系統關機情況下，直接操作切換開關使系統晶片之記憶體的電源供應端切換至接地端，因而切斷系統晶片之記憶體電源，以達成清除記憶體所儲存之資料的目的。
由上述可知，上述之系統重置方式因電池或切換開關係設置於電腦系統中，所以讓使用者在清除系統晶片之記憶體所儲存的資料時，需先打開電腦系統之機殼，方可清除電腦系統之系統晶片的記憶體。如此每一次清除系統晶片之記憶體時，皆需先拆卸機殼，接續切斷系統晶片之記憶體的電源，並讓系統晶片重新接上記憶體的電源，然後關閉機殼，如此對於使用者清除記憶體所儲存之資料而言，係相當不方便。再者，使用者經常需使用輔助工具用以拔除電池，所以使用者在拔除過程中會發生不小心讓輔助工具損壞電腦系統中的電路；且切換開關一般為了避免過於佔用電腦系統上的電路使用面積，會讓切換開關之體積盡可能縮減，因而導致操作上不方便，如此使用者亦需使用輔助工具，以控制切換開關之切換，使系統晶片之記憶體選擇性耦接電池與接地，如此亦會造成使用者於切換開關之操作過程中不小心讓輔助工具損壞電路。
有鑑於此，本發明提出一種記憶體之清除電路，其改善習知系統重置技術需先開啟機殼之問題，又無需拔除供電單元，亦無需操作切換開關，而方便於切斷系統晶片之記憶體的電源，以清除記憶體的系統設定值。
In recent years, information technology and computer technology have evolved, allowing computer systems to evolve from servers to personal computers, and from desktop computers to portable computers (eg, notebook computers). In the evolution of the computer system, the computer system needs to start the program according to the system setting value stored in the memory of the system chip to enter the operating system, but when the computer system is abnormal, the booting process cannot be performed. At this point, the user will restart the computer system to eliminate the anomaly. The abnormality of the general computer system is eliminated by turning on and off the power of the computer system. However, when the user cannot remove the abnormality of the computer system by switching the power, the user needs to clear the system setting value of the computer system to eliminate the abnormality. .
Generally, a programmable controller such as a platform controller hub (PCH), a baseboard management controller (BMC), or a complex programmable logic device (Complex Programmable Logic Device) is provided on a computer system. As a system chip for computer systems. The system chip generally has a memory for storing system settings used in the current stage of the computer system, and the memory system of the system chip maintains the stored data according to an independent power source, such as a battery, and thus, the user By cutting off the power supply of the memory of the supply system chip, the system setting value stored in the memory of the system chip can be cleared to eliminate the abnormality, and then the computer system restores the set value of the memory after the memory of the system chip clears the data. To the original preset system setting value, to eliminate the abnormality, and normally start the booting process, and then continue to boot the program into the operating system.
Since the power of the memory of the system chip is not the power supplied by the power supply, but is additionally provided by a power supply provided by an independent power supply unit of the computer system, for example, a battery for the memory storage system setting value, so early cut The method of disconnecting the memory power of the system chip is to directly remove the battery on the computer system to cut off the power supply of the battery to the memory, and then re-couple the battery to the memory of the system chip to re-power the battery to the system chip. Memory.
However, the above action of removing the battery is troublesome. Nowadays, in order to solve the problem of inconvenience of removing the power supply unit, another method for resetting the power of the system chip is developed, which sets a switch between the memory of the system chip and the battery to provide the user with the shutdown of the computer system. Then, the switch is directly operated to switch the power supply end of the memory of the system chip to the ground, thereby cutting off the memory power of the system chip to achieve the purpose of clearing the data stored in the memory.
It can be seen from the above that the above system reset mode is set in the computer system due to the battery or the switch-on relationship, so that the user needs to open the casing of the computer system before clearing the data stored in the memory of the system chip. Clear the memory of the system chip of the computer system. In this way, each time the memory of the system chip is removed, the chassis needs to be disassembled, the power of the memory of the system chip is continuously disconnected, and the system chip is reconnected to the power of the memory, and then the casing is closed, so that the user It is quite inconvenient to clear the data stored in the memory. Moreover, users often need to use auxiliary tools to remove the battery, so the user may accidentally damage the auxiliary circuit in the computer system during the removal process; and the switch is generally used to avoid overusing the circuit on the computer system. The area will make the size of the switch as much as possible, which will result in inconvenience in operation. Therefore, the user also needs to use an auxiliary tool to control the switching of the switch, so that the memory of the system chip is selectively coupled to the battery and the ground. It also causes the user to accidentally damage the auxiliary tool during the operation of the switch.
In view of the above, the present invention provides a memory clearing circuit, which improves the conventional system reset technology, requires the first to open the casing, does not need to remove the power supply unit, and does not need to operate the switch, but is convenient to cut off the system chip. The power of the memory to clear the system settings of the memory.
本發明之主要目的，在於提供一種記憶體之清除電路，其提供一非接觸方式重置系統晶片之電源，因而無需拆卸機殼，即可清除系統晶片之記憶體。
本發明係提供一種記憶體之清除電路，其係應用於清除一系統晶片之一記憶體。該清除電路包含一清除光電單元與一清除開關單元，該清除開關單元耦接一接地端與該系統晶片的該記憶體，且該清除光電單元係耦接該清除開關單元，並依據一清除光線產生一控制訊號，以控制該清除開關單元切換，讓該系統晶片的該記憶體經該清除開關單元耦接該接地端，以清除該記憶體所儲存之系統設定值。因此本發明無需拆卸機殼，僅藉由清除光線，即可清除系統晶片之記憶體。
SUMMARY OF THE INVENTION A primary object of the present invention is to provide a memory clearing circuit that provides a power supply for a non-contact mode reset system wafer so that the memory of the system wafer can be erased without disassembling the chassis.
The present invention provides a memory clearing circuit for cleaning a memory of a system wafer. The clearing circuit includes a clearing photoelectric unit and a clearing switch unit, the clearing switch unit is coupled to a grounding end and the memory of the system chip, and the clearing photovoltaic unit is coupled to the clearing switch unit, and is configured to clear light A control signal is generated to control the switching of the clearing switch unit, and the memory of the system chip is coupled to the ground via the clearing switch unit to clear a system setting value stored in the memory. Therefore, the present invention can remove the memory of the system chip only by removing the light without disassembling the casing.
請參閱第一圖至第三圖，其為本發明之一實施例之電子裝置的方塊圖、供電單元與清除電路的方塊圖與以及清除電路之電路示意圖。如第一圖所示，本發明之電子裝置10之一實施例為一電腦裝置，例如:伺服器，電子裝置10係包含一中央處理單元12、一主記憶體122、一南橋晶片14、一嵌入式控制單元16、一清除電路18與一周邊元件22。本發明之電子裝置10係由中央處理單元12耦接主記憶體122與南橋晶片14，並由南橋晶片14耦接嵌入式控制單元16、清除電路18與周邊元件22，且嵌入式控制單元16亦耦接清除電路18。
電子裝置10更設有一供電單元102，其係供電至電子裝置10之系統晶片，例如南橋晶片14與嵌入式控制單元16，供電單元102並耦接至清除電路18，本實施例之供電單元102係供電至南橋晶片14與嵌入式控制單元16之記憶體142、162（如第二圖所示）。由於本實施例之電子裝置10之系統晶片為南橋晶片14與嵌入式控制單元16，因此電子裝置10之系統設定值係儲存於南橋晶片14之記憶體142或嵌入式控制單元16之記憶體162。
當電子裝置10發生異常而無法完成開機程序時，根據本發明之一實施例可藉由清除電路18在電子裝置10於未使用狀態下，讓供電單元102中止供電至系統晶片的記憶體，於此實施例中也就是讓南橋晶片14或嵌入式控制單元16之記憶體142或162經該清除電路18耦接至接地端GND（如第二圖所示），以清除南橋晶片14之記憶體142或嵌入式控制單元16之記憶體162內部資料，因而清除記憶體142或162所儲存之系統設定值，藉此讓電子裝置10將原廠預設之系統設定值載入南橋晶片14之記憶體142或嵌入式控制單元16之記憶體162，如此即可排除電子裝置10之異常。上述電子裝置10載入原廠預設之系統設定值至記憶體142或記憶體162的方式，係本領域技術人員所公知的技術，所以於此不再詳述。本發明之清除電路18如何清除記憶體之詳細說明如下。
如第二圖所示，清除電路18包含一偵測單元181、一清除光電單元182與一清除開關單元184。清除開關單元184係耦接接地端GND、南橋晶片14的記憶體142、嵌入式控制單元16的記憶體162與清除光電單元182，供電單元102傳輸電源至南橋晶片14與嵌入式控制單元16，以供電至南橋晶片14與嵌入式控制單元16之記憶體142與162，供電單元102更耦接清除光電單元182，以傳輸電源至清除光電單元182。清除光電單元182係偵測ㄧ清除光線30，並在偵測到清除光線30時，產生一控制訊號Sclr(如第三圖所示)，而控制清除開關單元184切換，使南橋晶片14之記憶體142與嵌入式控制單元16之記憶體162經由清除開關單元184耦接至接地端GND，因而讓記憶體142與162耦接至接地端GND，而中止供電單元102供電至記憶體142與162，以清除記憶體142與162所儲存之系統設定值。
清除記憶體142與162所儲存之系統設定值時，為了避免讓電子裝置10受到影響，最好是在電子裝置10並未運作之狀態下進行，也就是電子裝置10並未處於使用狀態下才清除記憶體142與162。因此，本發明之清除電路18更可進一步藉由偵測單元181偵測電子裝置10是否處於使用狀態。當偵測單元181確認電子裝置10是沒有處於使用狀態下，偵測單元181會致能清除開關單元184，以讓清除開關單元184會依據控制訊號Sclr進行切換，以清除記憶體142與162所儲存之系統設定值。反之，當偵測單元181確認電子裝置10是處於使用狀態下，偵測單元181會禁能清除開關單元184，如此清除開關單元184縱使收到控制訊號Sclr也不會進行切換，而不會清除記憶體142與162所儲存之系統設定值，以避免影響在處理狀態下的電子裝置10。
本發明之一實施例中，偵測單元181係偵測電子裝置10之電源供應單元(圖未示)是否有正常供應電源至電子裝置10，若電源供應單元正常供應電源至電子裝置10，則表示電子裝置10處於使用狀態，反之則表示電子裝置10未處於使用狀態。本發明之偵測單元181偵測電子裝置10是否處於使用狀態之方式甚多，所以上述方式僅為本發明之一實施例，並未限定偵測單元181僅能偵測電源供應單元，而判斷電子裝置10是否處於使用狀態。本發明之一實施例中，偵測單元181為電子裝置10之複雜可程式化邏輯裝置（Complex Programmable Logic Device，CPLD）。
此外，本發明之供電單元102包含有ㄧ電源單元103與一限流單元104。電源單元103耦接於接地端GND且用於供應電源，限流單元104設於清除電路18之清除光電單元182與電源單元103之間，以及設於記憶體142、162與電源單元103之間，以避免電源單元103提供電流過大之電源而導致清除光電單元182、記憶體142與162受損。此外，限流單元104亦可避免供電單元102過度放電而降低使用壽命。
如第三圖所示，本實施例之清除光電單元182為一光二極體，並耦接供電單元102所提供之電源VDD與清除開關單元184。清除開關單元184係具有一第一電晶體190與一第二電晶體192和ㄧ電阻194。除此之外，本實施例之清除電路18更設有電阻195。第一電晶體190之閘極係耦接至偵測單元181而受控於偵測單元181，第一電晶體190之汲極係耦接至清除光電單元182，第一電晶體190之源極係耦接至第二電晶體192之閘極與電阻194之一端，電阻194之另ㄧ端耦接於接地端GND。第二電晶體192之汲極係耦接至南橋晶片14之記憶體142與嵌入式控制單元16之記憶體162，第二電晶體192之源極係耦接至接地端GND，其中清除電路18係耦接限流單元104，以接收電源VDD。電阻195之一端耦接於電源VDD，電阻195之另ㄧ端耦接於記憶體142與162。
當清除光線30照射至清除光電單元182時，清除光電單元182隨即依據清除光線30產生控制訊號Sclr至第一電晶體190，同時，偵測單元181若偵測到電子裝置10處於未使用狀態，因此偵測單元181驅使第一電晶體190導通，即致能清除開關單元184，以讓控制訊號Sclr藉由電阻194產生電壓訊號至第二電晶體192之閘極，藉此驅使第二電晶體192切換為導通，使電阻195、南橋晶片14之記憶體142與嵌入式控制單元16之記憶體162經第二電晶體192耦接至接地端GND。因此，南橋晶片14與嵌入式控制單元16之記憶體142、162亦隨著耦接至接地端GND，因而即可清除記憶體142、162所儲存之資料。
此外，偵測單元181於偵測到電子裝置10處於使用狀態時，隨即控制第一電晶體190截止，即禁能清除開關單元184，也就是說，清除光電單元182所產生之控制訊號Sclr無法通過第一電晶體190，導致控制訊號Sclr無法藉由電阻194產生電壓訊號至第二電晶體192，所以偵測單元181即依據電子裝置10處於使用狀態而控制清除電路18之清除開關單元184禁能，讓清除開關單元184無法依據控制訊號Sclr切換，而讓第二電晶體192截止，隨之南橋晶片14與嵌入式控制單元16之記憶體142、162並未耦接至接地端GND，所以記憶體142、162仍然維持原本資料儲存。
此外，使用人員可判斷電子裝置10是否處於使用狀態時，即不需要藉由偵測單元181判斷，如此本發明之清除電路18即無需設置偵測單元181與第一電晶體190。於本發明之一實施例，本發明之清除光線30係使用者利用手電筒或者其他攜帶式光源所產生，以進行清除記憶體142與162所儲存的資料，如此即不需要拆開電子裝置10之機殼，即可進行清除記憶體142與162之系統設定值，以回復至原廠預設之系統設定值。
請一併參閱第四圖，其為本發明控制清除電路之一實施例之流程圖。如圖所示，本實施例藉由偵測單元181針對電子裝置10是否處於使用狀態而控制清除電路18，偵測單元181逐項判斷電子裝置10之各種狀態，以判斷電子裝置10是否處於使用狀態。如步驟S100所示，電子裝置10已耦接電源後，如步驟S110所示，由偵測單元181確認電子裝置10之開啟狀態，即判斷電子裝置10之電源鍵是否被按壓，當電源鍵未被按壓時，則表示電子裝置10未被開啟，如此則重新執行步驟S110，以重新確認電子裝置10之開啟狀態。當電源鍵被按壓而確認電子裝置10已被開啟時，接續執行步驟S120；按步驟S120所示，由偵測單元181確認電子裝置10之清除開關單元184是否禁能，當清除開關單元184為禁能時，接續執行步驟S130，以接續確認電子裝置10之電源供應單元(Power Supply Unit，PSU)之狀態，當清除開關單元184為未禁能時，即清除開關單元184致能時，則接續執行步驟S170，以關閉電源供應單元。
接續上述，如步驟S130所示，偵測單元181確認電子裝置10之電源供應單元之開啟狀態，當電源供應單元為開啟時，接續執行步驟S140，以接續確認電子裝置10之主電源之狀態，當電源供應單元為未開啟時，接續執行步驟S170，以關閉電源供應單元；按步驟S140所示，偵測單元181確認電子裝置10之主電源之開啟狀態，當主電源為開啟時，接續執行步驟S150，以接續確認電子裝置10之各元件之狀態，當主電源未開啟時，接續執行步驟S170，以關閉電源供應單元；按步驟S150所示，偵測單元181偵測電子裝置10之各元件之開啟狀態，例如:主記憶體122、中央處理單元12、周邊元件22等系統元件之開啟狀態，當各元件的電源為正常而各元件為開啟時，接續執行步驟S160，以確認電子裝置10之系統平台的狀態，當各元件為未開啟時，接續執行步驟S170，以關閉電源供應單元。
按步驟S160所示，偵測單元181偵測電子裝置10之系統平台之重置狀態，當系統平台為未重置時，接續執行步驟S170，以關閉電源供應單元，當系統平台重置時，接續執行步驟S180，而禁能清除開關單元184。按步驟S190所示，於步驟S170執行關閉電源供應單元之後，偵測單元181致能清除開關單元184，因此清除光電單元182依據清除光線所產生之控制訊號Sclr可傳送至清除開關單元184，以控制清除開關單元184切換，讓系統晶片之記憶體經清除開關單元184耦接至接地端GND，因而清除系統晶片之記憶體所儲存的資料，以供電子裝置10藉此回復至原廠預設之系統設定值，其中本實施例之系統晶片為南橋晶片14與嵌入式控制單元16，其記憶體分別為記憶體142與162。上述之使用狀態偵測步驟為電子裝置之習知技術，因此本實施例不再贅述細部作動關係。
以上所述，本發明為一種記憶體之清除電路，其藉由清除光電單元182依據清除光線30產生控制訊號Sclr至清除開關單元184，而控制清除開關單元184切換，讓系統晶片之記憶體經清除開關單元184耦接至接地端，因此本發明即可清除系統晶片之記憶體中所儲存的系統設定值，以供電子裝置10重置回原廠預設之系統設定值，所以本發明無須拆卸電子裝置10之機殼即可完成系統設定值之清除，以回復至原廠預設之系統設定值。此外，本發明更可藉由偵測單元181依據電子裝置10是否處於使用狀態而禁能/致能清除開關單元184，以控制清除電路18運作於電子裝置10之非使用狀態。
請參閱第五圖，其為本發明控制清除電路之另一實施例之流程圖。其中第四圖與第五圖之差異在於第五圖更進一步包含一傳送遠端控制訊號之步驟。如圖所示，本發明之電子裝置10更可透過遠端之操作，以遠端啟動電子裝置10。如步驟S200所示，電子裝置10已耦接電源後，使用者按步驟S210所示，透過遠端作業方式，由一遠端控制單元將一遠端控制訊號藉由網際網路傳送至電子裝置10，例如:Web服務、遠端桌面服務等方式連接至電子裝置10，以傳送遠端控制訊號至電子裝置10，因而啟動電子裝置10；接續，按步驟S220至步驟S290所示，由於步驟S220至步驟S290等同於上述實施例之步驟S120至步驟S190，因此本實施例不再贅述。由於上述之遠端作業方式為電子裝置10之習知技術，因此本實施例不再贅述。
請參閱第六圖至第七圖，其為本發明之另一實施例之清除電路與供電單元之方塊圖與清除電路之電路示意圖。其中第二圖至第三圖與第六圖至第七圖之差異在於第六圖至第七圖之清除電路18更進一步包含一重置光電單元186與一重置開關單元188，以搭配電子裝置10之一重置單元106，而用於重置電子裝置10。如此，當電子裝置10運作過程中發生異常狀態而無法正常運作時，即可藉由重置光電單元186與重置開關單元188驅使重置單元106重置電子裝置10，以重新啟動電子裝置10而排除異常狀態。
接續上述，本實施例之重置開關單元188係耦接接地端GND與重置單元106，於本實施例中接地端GND為參考端。重置光電單元186係耦接該重置開關單元188，並依據一重置光線32產生一重置驅動訊號Srst(如第七圖所示)，而驅動該重置開關單元188切換，讓該重置單元106經該重置開關單元188耦接至該參考端，以驅使該重置單元106重置電子裝置10。其中，本實施例之參考端為接地端GND，除此之外，本發明之參考端可依據重置單元106之觸發條件設置參考端之電位，而非限制於接地端GND；本實施例之重置單元106更可整合於南橋晶片14或嵌入式控制單元16中，而由南橋晶片14或嵌入式控制單元16重置電子裝置10。
此外，此實施例之供電單元102更耦接重置單元106與清除電路18之重置光電單元186，以提供電源至重置單元106與重置光電單元186。此實施例之供電單元102之限流單元104更耦接於供電單元103與重置單元106之間，以及耦接於電源單元103與重置光電單元186之間，以避免電源單元103提供過大電流之電源至重置單元106與重置光電單元186，而導致重置單元106與重置光電單元186受損，限流單元104亦可避免供電單元102過度放電而降低使用壽命。
另外，此實施例之重置開關單元188更耦接偵測單元181，偵測單元181偵測電子裝置10目前還有正常執行程序或者軟體時，即電子裝置10處於正常使用狀態，偵測單元181會禁能重置開關單元188，如此重置開關單元188即無法驅動重置單元106重置電子裝置10，以避免重置單元106在電子裝置10處於正常使用狀態下被重置，如此可避免電子裝置10損壞或者遺失資料。換言之，當偵測單元181確認電子裝置10是沒有處於正常使用狀態下，偵測單元181會致能重置開關單元188，以讓重置開關單元188可以依據重置光電單元186所產生之重置驅動訊號Srst進行切換，以驅使重置單元106經重置開關單元188耦接至參考端，以驅使重置單元106重置電子裝置10而重新啟動電子裝置10，以排除異常狀態。
本發明之一實施例中，偵測單元181係偵測電子裝置10之中央處理單元12(如第一圖所示)是否有正常執行程序或者軟體，若中央處理單元12正常執行程序或者軟體，則表示電子裝置10處於正常使用狀態，反之則表示電子裝置10未處於正常使用狀態，譬如電子裝置10之中央處理單元12執行某項程序或者軟體過久而超過正常執行時間且沒有任何回應，即表示電子裝置10未處於正常使用狀態。本發明之偵測單元181偵測電子裝置10是否處於正常使用狀態之方式甚多，所以上述偵測方式僅為本發明之一實施例，並未限定偵測單元181僅能偵測中央處理單元12，而判斷電子裝置10是否處於正常使用狀態。
復參閱第七圖，由於清除光電單元182、清除開關單元184之第一電晶體190與第二電晶體192以及電阻194、195之連接關係與作動關係已在先前第三圖實施例說明，因此本實施例不再贅述。此實施例之重置光電單元186亦為一光二極體，重置開關單元188係具有一第一電晶體196與一第二電晶體197和ㄧ電阻198，清除電路18更設有ㄧ電阻199。第一電晶體196之閘極係耦接至偵測單元181而受偵測單元181控制，第一電晶體196之汲極係耦接至重置光電單元186，重置光電單元186更耦接供電單元102之電源VDD，第一電晶體196之源極係耦接至第二電晶體197之閘極與電阻198之一端，電阻198之另ㄧ端耦接至接地端GND。第二電晶體197之汲極係耦接至重置單元106以及電阻199之一端，電阻199之另ㄧ端耦接於電源VDD，第二電晶體197之源極係耦接至接地端GND，也就是第二電晶體197之源極耦接至參考端。
當重置光線32照射至重置光電單元186時，重置光電單元186隨即依據重置光線32產生重置驅動訊號Srst至第一電晶體196，同時，若偵測單元181係偵測到電子裝置10處於未正常使用狀態，因此偵測單元181驅使第一電晶體196導通，即致能重置開關單元188，以讓重置驅動訊號Srst通過第一電晶體196並藉由電阻198產生電壓訊號至第二電晶體197之閘極，藉此導通第二電晶體197，使重置單元106與電阻199經第二電晶體197耦接至接地端GND，即耦接至參考端，因此，重置單元106即被驅使重置電子裝置10，而重新啟動電子裝置10，以排除執行異常。
此外，偵測單元181於偵測到電子裝置10處於正常使用狀態時，隨即控制第一電晶體196截止，也就是說，重置光電單元186所產生之重置驅動訊號Srst無法通過第一電晶體196，導致重置驅動訊號Srst無法藉由電阻198產生電壓訊號至第二電晶體197，所以第二電晶體197為截止，也就是說偵測單元181依據電子裝置10處於正常使用狀態而禁能清除電路18之重置開關單元188，使重置開關單元188無法接收重置光電單元186依據重置光線32所產生之重置驅動訊號Srst而無法切換，讓重置單元106無法透過重置開關單元188耦接至參考端，因而不重置電子裝置10。
另外，本發明之另外ㄧ實施例，若使用者可判斷電子裝置10是否處於正常使用狀態，如此即可不需要偵測單元181與重置開關單元188的第一電晶體196，而僅需第二電晶體197，第二電晶體197依據重置驅動訊號Srst而切換，讓重置單元106經第二電晶體197耦接至參考端，以驅使重置單元106重置電子裝置10。
請參閱第八圖，其為本發明之又一實施例之電子裝置的局部方塊圖。其中第六圖與第八圖之差異在於第八圖更進一步包含一清除光源108、一重置光源110、一清除驅動單元144與一重置驅動單元146。如圖所示，本發明之電子裝置10的清除電路18更可設置清除光源108、重置光源110、清除驅動單元144與重置驅動單元146，以分別提供清除光線30與重置光線32而照射清除光電單元182與重置光電單元186。本實施例之清除驅動單元144與重置驅動單元146分別耦接至清除光源108與重置光源110，藉此，清除驅動單元144係驅動清除光源108產生清除光線30，以照射至清除光電單元182，重置驅動單元146係驅動重置光源110產生重置光線32，以照射至重置光電單元186。
本發明之一實施例中，電子裝置10之外部按鍵（圖未示）可控制清除驅動單元144與重置驅動單元146，以控制清除光源108與重置光源110產生清除光線30與重置光線32。如此，使用者即可藉由按壓電子裝置10之外部按鍵，而產生清除光線30與重置光線32，以清除記憶體的資料或者重置電子裝置10。另外，本發明之另ㄧ實施例中，使用者可以透過網際網路而遠端控制清除驅動單元144與重置驅動單元146，以控制清除光源108與重置光源110產生清除光線30與重置光線32。使用者可透過網際網路發送遠端訊號至電子裝置10之嵌入式控制單元16，而藉由嵌入式控制單元16控制清除驅動單元144與重置驅動單元146。
此外，本發明之清除光線30與重置光線32是互不相同的光線，即清除光線30的波長與重置光線32的波長是不相同，且清除光電單元182與重置光電單元186所感應之光線的波長也不相同，前述清除光線30可為一種紫外光，重置光線32可為一種可見光，但本發明不以此為限。換言之，清除光電單元182僅可感應清除光線30，而重置光電單元186僅可感應重置光線32，所以本發明之清除電路18可利用兩種不同光線的清除光線30與重置光線32進行清除記憶體的資料與重置電子裝置10。另外，本發明之清除驅動單元144與重置驅動單元146可設置於電子裝置10內部之任何晶片或者可獨立設置於電子裝置10。
綜上所述，本發明為一種記憶體之清除電路，其提供清除光電單元與清除開關單元，並藉由清除光電單元依據清除光線產生對應之控制訊號至清除開關單元，以控制清除開關單元切換，讓系統晶片之記憶體耦接至接地端，以清除記憶體所儲存之資料，如此本發明無須拆開電子裝置之機殼，即可清除系統晶片之記憶體所儲存之資料，因而方便使用者輕易排除記憶體所儲存之系統設定值異常的問題。此外，本發明之清除電路更可應用於重置電子裝置，其藉由重置光電單元依據重置光線產生對應之重置驅動訊號至重置開關單元，以控制重置開關單元切換，讓重置單元耦接至參考端，以重置電子裝置。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
Please refer to the first to third figures, which are block diagrams of the electronic device, a block diagram of the power supply unit and the clear circuit, and a circuit diagram of the clear circuit according to an embodiment of the present invention. As shown in the first figure, an embodiment of the electronic device 10 of the present invention is a computer device, such as a server. The electronic device 10 includes a central processing unit 12, a main memory 122, a south bridge 14, and a The embedded control unit 16, a clear circuit 18 and a peripheral component 22. The electronic device 10 of the present invention is coupled to the main memory 122 and the south bridge wafer 14 by the central processing unit 12, and is coupled to the embedded control unit 16, the clear circuit 18 and the peripheral component 22 by the south bridge wafer 14, and the embedded control unit 16 A clear circuit 18 is also coupled.
The electronic device 10 is further provided with a power supply unit 102, which is supplied to the system chip of the electronic device 10, for example, the south bridge chip 14 and the embedded control unit 16, and the power supply unit 102 is coupled to the clear circuit 18, and the power supply unit 102 of this embodiment. The memory is supplied to the south bridge wafer 14 and the memory 142, 162 of the embedded control unit 16 (as shown in the second figure). Since the system chip of the electronic device 10 of the embodiment is the south bridge chip 14 and the embedded control unit 16, the system setting value of the electronic device 10 is stored in the memory 142 of the south bridge chip 14 or the memory 162 of the embedded control unit 16. .
When the electronic device 10 is abnormal and the booting process cannot be completed, according to an embodiment of the present invention, the power supply unit 102 can stop the power supply to the memory of the system chip by the clearing circuit 18 in the unused state of the electronic device 10. In this embodiment, the memory 142 or 162 of the south bridge wafer 14 or the embedded control unit 16 is coupled to the ground GND via the clear circuit 18 (as shown in the second figure) to clear the memory of the south bridge wafer 14. 142 or the internal data of the memory 162 of the embedded control unit 16, thereby clearing the system setting values stored in the memory 142 or 162, thereby causing the electronic device 10 to load the factory preset system setting values into the memory of the south bridge wafer 14. The body 142 or the memory 162 of the embedded control unit 16 can eliminate the abnormality of the electronic device 10. The manner in which the above-mentioned electronic device 10 loads the factory preset system setting value to the memory 142 or the memory 162 is a technique known to those skilled in the art, and therefore will not be described in detail herein. A detailed description of how the clear circuit 18 of the present invention clears the memory is as follows.
As shown in the second figure, the clear circuit 18 includes a detecting unit 181, a clearing photo unit 182 and a clearing switch unit 184. The clear switch unit 184 is coupled to the ground GND, the memory 142 of the south bridge wafer 14, the memory 162 of the embedded control unit 16, and the clear photo unit 182. The power supply unit 102 transmits power to the south bridge wafer 14 and the embedded control unit 16, The power supply unit 102 is further coupled to the clearing photovoltaic unit 182 to supply power to the clearing photovoltaic unit 182. The power supply unit 102 is further coupled to the memory 142 and 162 of the embedded control unit 16. The clearing photocell 182 detects the chirped light 30 and generates a control signal Scrl (as shown in the third figure) when the clearing light 30 is detected, and the control clearing switch unit 184 switches to make the memory of the south bridge wafer 14 The body 142 and the memory 162 of the embedded control unit 16 are coupled to the ground GND via the clear switch unit 184, thereby coupling the memory 142 and 162 to the ground GND, and suspending the power supply unit 102 to the memory 142 and 162. To clear the system settings stored in the memories 142 and 162.
When the system setting values stored in the memories 142 and 162 are cleared, in order to avoid affecting the electronic device 10, it is preferable to perform the state in which the electronic device 10 is not in operation, that is, the electronic device 10 is not in use. Memory 142 and 162 are cleared. Therefore, the clearing circuit 18 of the present invention can further detect whether the electronic device 10 is in use by the detecting unit 181. When the detecting unit 181 confirms that the electronic device 10 is not in use, the detecting unit 181 can enable the clearing of the switch unit 184, so that the clearing switch unit 184 switches according to the control signal Sclr to clear the memory 142 and 162. The stored system settings. On the other hand, when the detecting unit 181 confirms that the electronic device 10 is in the use state, the detecting unit 181 can disable the clearing of the switch unit 184, so that the clearing of the switch unit 184 will not be switched even if the control signal Sclr is received, and will not be cleared. The system settings stored by the memories 142 and 162 are to avoid affecting the electronic device 10 in the processing state.
In an embodiment of the present invention, the detecting unit 181 detects whether the power supply unit (not shown) of the electronic device 10 has a normal power supply to the electronic device 10. If the power supply unit normally supplies power to the electronic device 10, It indicates that the electronic device 10 is in use, and vice versa, that the electronic device 10 is not in use. The detection unit 181 of the present invention detects that the electronic device 10 is in a state of being used. Therefore, the above manner is only one embodiment of the present invention, and the detection unit 181 is not limited to detect only the power supply unit. Whether the electronic device 10 is in use. In one embodiment of the present invention, the detecting unit 181 is a Complex Programmable Logic Device (CPLD) of the electronic device 10.
In addition, the power supply unit 102 of the present invention includes a power supply unit 103 and a current limiting unit 104. The power supply unit 103 is coupled to the ground GND and is used for supplying power. The current limiting unit 104 is disposed between the clearing photovoltaic unit 182 of the clearing circuit 18 and the power supply unit 103, and between the memory 142, 162 and the power supply unit 103. In order to prevent the power supply unit 103 from supplying a power source with excessive current, the clearing of the photovoltaic unit 182 and the memory 142 and 162 are damaged. In addition, the current limiting unit 104 can also avoid excessive discharge of the power supply unit 102 to reduce the service life.
As shown in the third figure, the clearing photovoltaic unit 182 of the present embodiment is a photodiode and coupled to the power supply VDD and the clearing switch unit 184 provided by the power supply unit 102. The clear switch unit 184 has a first transistor 190 and a second transistor 192 and a ㄧ resistor 194. In addition, the clear circuit 18 of this embodiment is further provided with a resistor 195. The gate of the first transistor 190 is coupled to the detecting unit 181 and is controlled by the detecting unit 181. The drain of the first transistor 190 is coupled to the clearing photo unit 182, the source of the first transistor 190. The gate is coupled to the gate of the second transistor 192 and one end of the resistor 194, and the other end of the resistor 194 is coupled to the ground GND. The drain of the second transistor 192 is coupled to the memory 142 of the south bridge wafer 14 and the memory 162 of the embedded control unit 16, and the source of the second transistor 192 is coupled to the ground GND, wherein the clear circuit 18 The current limiting unit 104 is coupled to receive the power supply VDD. One end of the resistor 195 is coupled to the power source VDD, and the other end of the resistor 195 is coupled to the memory 142 and 162.
When the clearing light 30 is irradiated to the clearing photocell 182, the clearing photocell 182 generates the control signal Scrr to the first transistor 190 according to the clearing light 30, and the detecting unit 181 detects that the electronic device 10 is in an unused state. Therefore, the detecting unit 181 drives the first transistor 190 to be turned on, that is, the switch unit 184 is enabled to enable the control signal Sclr to generate a voltage signal to the gate of the second transistor 192 through the resistor 194, thereby driving the second transistor. The switch 192 is turned on, so that the resistor 195, the memory 142 of the south bridge chip 14 and the memory 162 of the embedded control unit 16 are coupled to the ground GND via the second transistor 192. Therefore, the memory 142 and 162 of the south bridge chip 14 and the embedded control unit 16 are also coupled to the ground GND, so that the data stored in the memory 142, 162 can be cleared.
In addition, when detecting that the electronic device 10 is in the use state, the detecting unit 181 then controls the first transistor 190 to be turned off, that is, the switch unit 184 is disabled, that is, the control signal Scrr generated by the clearing the photo unit 182 cannot be cleared. The first transistor 190 causes the control signal Sclr to generate a voltage signal to the second transistor 192 through the resistor 194. Therefore, the detecting unit 181 controls the clearing switch unit 184 of the clearing circuit 18 according to the state in which the electronic device 10 is in use. The clearing switch unit 184 can not be switched according to the control signal Sclr, and the second transistor 192 is turned off, so that the memory 142, 162 of the south bridge chip 14 and the embedded control unit 16 are not coupled to the ground GND, so The memory 142, 162 still maintains the original data storage.
In addition, the user can determine whether the electronic device 10 is in the use state, that is, the detection unit 181 does not need to be determined. Thus, the clearing circuit 18 of the present invention does not need to provide the detecting unit 181 and the first transistor 190. In one embodiment of the present invention, the light-removing light 30 of the present invention is generated by a user using a flashlight or other portable light source to clear the data stored in the memory 142 and 162, so that the electronic device 10 does not need to be disassembled. The casing can be used to clear the system settings of the memory 142 and 162 to return to the factory preset system settings.
Please refer to the fourth figure, which is a flowchart of an embodiment of the control clear circuit of the present invention. As shown in the figure, in the embodiment, the detecting unit 181 controls the clearing circuit 18 for whether the electronic device 10 is in the use state, and the detecting unit 181 determines various states of the electronic device 10 item by item to determine whether the electronic device 10 is in use. status. After the electronic device 10 is coupled to the power source, as shown in step S110, the detecting unit 181 confirms the open state of the electronic device 10, that is, determines whether the power button of the electronic device 10 is pressed, when the power button is not When pressed, it means that the electronic device 10 is not turned on, and then step S110 is re-executed to reconfirm the open state of the electronic device 10. When the power button is pressed to confirm that the electronic device 10 has been turned on, step S120 is continued; according to step S120, the detecting unit 181 confirms whether the clearing switch unit 184 of the electronic device 10 is disabled, and when the clearing switch unit 184 is When the power is off, step S130 is continued to confirm the state of the power supply unit (PSU) of the electronic device 10. When the clear switch unit 184 is disabled, that is, when the clear switch unit 184 is enabled, Step S170 is continued to turn off the power supply unit.
In the above, as shown in step S130, the detecting unit 181 confirms the open state of the power supply unit of the electronic device 10. When the power supply unit is turned on, the step S140 is continued to confirm the state of the main power of the electronic device 10. When the power supply unit is not turned on, step S170 is continued to turn off the power supply unit; as shown in step S140, the detecting unit 181 confirms that the main power of the electronic device 10 is turned on, and when the main power is turned on, the connection is continued. Step S150, to confirm the state of each component of the electronic device 10, when the main power is not turned on, continue to perform step S170 to turn off the power supply unit; as shown in step S150, the detecting unit 181 detects each of the electronic devices 10 The open state of the component, for example, the open state of the system component such as the main memory 122, the central processing unit 12, and the peripheral component 22, when the power of each component is normal and each component is turned on, step S160 is continuously performed to confirm the electronic device. The state of the system platform of 10, when each component is not turned on, continues to step S170 to turn off the power supply unit.
In step S160, the detecting unit 181 detects the reset state of the system platform of the electronic device 10. When the system platform is not reset, the step S170 is continuously performed to turn off the power supply unit. When the system platform is reset, Step S180 is continued, and the switch unit 184 is disabled. After the power supply unit is turned off in step S170, the detecting unit 181 enables the clearing of the switching unit 184. Therefore, the clearing photoelectric unit 182 can transmit the control signal Sclr generated according to the clearing light to the clearing switch unit 184 to The control clear switch unit 184 switches, so that the memory of the system chip is coupled to the ground GND via the clear switch unit 184, thereby clearing the data stored in the memory of the system chip for the electronic device 10 to return to the original factory preset. The system set value is that the system wafer of the embodiment is the south bridge wafer 14 and the embedded control unit 16, and the memory thereof is the memory bodies 142 and 162, respectively. The use state detecting step described above is a conventional technique of the electronic device. Therefore, the detailed operation relationship is not described in this embodiment.
As described above, the present invention is a memory clearing circuit that controls the clear switch unit 184 to switch the memory of the system chip by clearing the photocell 182 to generate the control signal Scrl to the clear switch unit 184 according to the clear light 30. The clearing switch unit 184 is coupled to the grounding end. Therefore, the present invention can clear the system setting value stored in the memory of the system chip for the electronic device 10 to be reset back to the factory preset system setting value, so the present invention does not need to The system setting value can be removed by disassembling the casing of the electronic device 10 to return to the original preset system setting value. In addition, the detection unit 181 can disable/enable the clear switch unit 184 according to whether the electronic device 10 is in use or not, to control the clear circuit 18 to operate in the non-use state of the electronic device 10.
Please refer to the fifth figure, which is a flow chart of another embodiment of the control clearing circuit of the present invention. The difference between the fourth figure and the fifth figure is that the fifth figure further includes a step of transmitting a remote control signal. As shown, the electronic device 10 of the present invention can remotely activate the electronic device 10 through remote operation. As shown in step S200, after the electronic device 10 is coupled to the power source, the user transmits a remote control signal to the electronic device through the Internet through a remote control unit according to step S210. 10, for example, Web service, remote desktop service, etc. are connected to the electronic device 10 to transmit the remote control signal to the electronic device 10, thereby starting the electronic device 10; connecting, as shown in steps S220 to S290, due to step S220 Step S290 is equivalent to step S120 to step S190 of the above embodiment, and thus the embodiment will not be described again. Since the above-mentioned remote operation mode is a conventional technique of the electronic device 10, the present embodiment will not be described again.
Please refer to FIG. 6 to FIG. 7 , which are circuit diagrams of a block diagram and a clear circuit of a clearing circuit and a power supply unit according to another embodiment of the present invention. The difference between the second to third and sixth to seventh embodiments is that the clear circuit 18 of the sixth to seventh embodiments further includes a reset photo unit 186 and a reset switch unit 188 to match the electronic One of the devices 10 resets the unit 106 for resetting the electronic device 10. In this way, when the abnormal state occurs during the operation of the electronic device 10 and the normal operation cannot be performed, the reset unit 106 can be driven to reset the electronic device 10 by resetting the photo unit 186 and the reset switch unit 188 to restart the electronic device 10 . Exclude abnormal conditions.
In the embodiment, the reset switch unit 188 is coupled to the ground GND and the reset unit 106. In this embodiment, the ground GND is a reference end. The reset photo unit 186 is coupled to the reset switch unit 188, and generates a reset driving signal Srst according to a reset light 32 (as shown in FIG. 7), and drives the reset switch unit 188 to switch. The reset unit 106 is coupled to the reference terminal via the reset switch unit 188 to drive the reset unit 106 to reset the electronic device 10. The reference end of the present invention is the ground GND. In addition, the reference end of the present invention can set the potential of the reference end according to the trigger condition of the reset unit 106, instead of being limited to the ground GND; The reset unit 106 can be integrated into the south bridge wafer 14 or the embedded control unit 16, and the electronic device 10 is reset by the south bridge wafer 14 or the embedded control unit 16.
In addition, the power supply unit 102 of this embodiment is further coupled to the reset photo unit 186 of the reset unit 106 and the clear circuit 18 to provide power to the reset unit 106 and the reset photo unit 186. The current limiting unit 104 of the power supply unit 102 of the embodiment is further coupled between the power supply unit 103 and the reset unit 106, and coupled between the power supply unit 103 and the reset photo unit 186 to prevent the power supply unit 103 from being provided too large. The power supply of the current to the reset unit 106 and the reset photo unit 186 causes the reset unit 106 and the reset photo unit 186 to be damaged, and the current limiting unit 104 can also prevent the power supply unit 102 from being over-discharged to reduce the service life.
In addition, the reset switch unit 188 of the embodiment is further coupled to the detecting unit 181. When the detecting unit 181 detects that the electronic device 10 still has a normal execution program or software, the electronic device 10 is in a normal use state, and the detecting unit 181 can disable the reset switch unit 188, such that the reset switch unit 188 can not drive the reset unit 106 to reset the electronic device 10, so as to prevent the reset unit 106 from being reset when the electronic device 10 is in normal use. Avoid damage to the electronic device 10 or loss of data. In other words, when the detecting unit 181 confirms that the electronic device 10 is not in the normal use state, the detecting unit 181 enables the resetting of the switch unit 188 so that the reset switch unit 188 can be generated according to the weight of the resetting photoelectric unit 186. The driving signal Srst is switched to drive the reset unit 106 to be coupled to the reference terminal via the reset switch unit 188 to drive the reset unit 106 to reset the electronic device 10 to restart the electronic device 10 to eliminate the abnormal state.
In an embodiment of the present invention, the detecting unit 181 detects whether the central processing unit 12 of the electronic device 10 (shown in the first figure) has a normal execution program or software. If the central processing unit 12 executes the program or software normally, It means that the electronic device 10 is in the normal use state, otherwise the electronic device 10 is not in the normal use state. For example, the central processing unit 12 of the electronic device 10 executes a certain program or the software is too long and exceeds the normal execution time without any response, that is, It indicates that the electronic device 10 is not in the normal use state. The detection unit 181 of the present invention detects that the electronic device 10 is in a normal state of use. Therefore, the detection method is only one embodiment of the present invention, and the detection unit 181 is not limited to detect only the central processing unit. 12, and it is judged whether the electronic device 10 is in a normal use state.
Referring to the seventh figure, since the connection relationship and the actuation relationship between the first transistor 190 and the second transistor 192 and the resistors 194 and 195 of the clearing photocell 182 and the clearing switch unit 184 have been described in the previous third embodiment, This embodiment will not be described again. The reset photocell 186 of this embodiment is also a photodiode. The reset switch unit 188 has a first transistor 196 and a second transistor 197 and a resistor 198. The erase circuit 18 is further provided with a resistor 199. . The gate of the first transistor 196 is coupled to the detection unit 181 and is controlled by the detection unit 181. The drain of the first transistor 196 is coupled to the reset photo unit 186, and the reset photo unit 186 is coupled. The power source VDD of the power supply unit 102, the source of the first transistor 196 is coupled to the gate of the second transistor 197 and one end of the resistor 198, and the other end of the resistor 198 is coupled to the ground GND. The drain of the second transistor 197 is coupled to the reset unit 106 and one end of the resistor 199. The other end of the resistor 199 is coupled to the power supply VDD, and the source of the second transistor 197 is coupled to the ground GND. That is, the source of the second transistor 197 is coupled to the reference terminal.
When the reset light 32 is irradiated to the reset photocell 186, the reset photocell 186 then generates the reset driving signal Srst to the first transistor 196 according to the reset light 32, and at the same time, if the detecting unit 181 detects the electron The device 10 is in an abnormal state of use. Therefore, the detecting unit 181 drives the first transistor 196 to be turned on, that is, the resetting of the switching unit 188 to allow the reset driving signal Srst to pass through the first transistor 196 and generate a voltage through the resistor 198. The signal is applied to the gate of the second transistor 197, thereby turning on the second transistor 197, so that the reset unit 106 and the resistor 199 are coupled to the ground GND via the second transistor 197, that is, coupled to the reference terminal. The reset unit 106 is driven to reset the electronic device 10 and restarts the electronic device 10 to eliminate execution anomalies.
In addition, when detecting that the electronic device 10 is in the normal use state, the detecting unit 181 then controls the first transistor 196 to be turned off, that is, the reset driving signal Srst generated by the resetting the photo unit 186 cannot pass the first power. The crystal 196 causes the reset driving signal Srst to generate a voltage signal to the second transistor 197 through the resistor 198. Therefore, the second transistor 197 is turned off, that is, the detecting unit 181 is disabled according to the normal use state of the electronic device 10. The reset switch unit 188 of the circuit 18 can be cleared, so that the reset switch unit 188 cannot receive the reset drive signal Srst generated by the reset photo unit 186 according to the reset light signal Srst, so that the reset unit 106 cannot be reset. The switch unit 188 is coupled to the reference terminal, and thus the electronic device 10 is not reset.
In addition, in another embodiment of the present invention, if the user can determine whether the electronic device 10 is in a normal use state, the detection unit 181 and the first transistor 196 of the reset switch unit 188 are not required, and only the second The transistor 197, the second transistor 197 is switched according to the reset driving signal Srst, and the reset unit 106 is coupled to the reference terminal via the second transistor 197 to drive the reset unit 106 to reset the electronic device 10.
Please refer to FIG. 8 , which is a partial block diagram of an electronic device according to still another embodiment of the present invention. The difference between the sixth figure and the eighth figure is that the eighth figure further includes a clearing light source 108, a resetting light source 110, a clearing driving unit 144 and a reset driving unit 146. As shown, the clearing circuit 18 of the electronic device 10 of the present invention can further provide a clear light source 108, a reset light source 110, a clear driving unit 144 and a reset driving unit 146 to provide clear light 30 and reset light 32, respectively. The illumination clear unit 106 and the reset photo unit 186 are illuminated. The clearing driving unit 144 and the reset driving unit 146 of the embodiment are respectively coupled to the clearing light source 108 and the resetting light source 110, whereby the clearing driving unit 144 drives the clearing light source 108 to generate the clearing light 30 to illuminate the clearing photoelectric unit. 182. The reset driving unit 146 drives the reset light source 110 to generate a reset light 32 to illuminate the reset photo unit 186.
In an embodiment of the present invention, an external button (not shown) of the electronic device 10 can control the clear driving unit 144 and the reset driving unit 146 to control the clear light source 108 and the reset light source 110 to generate the clear light 30 and reset the light. 32. In this way, the user can generate the clear light 30 and the reset light 32 by pressing the external button of the electronic device 10 to clear the data of the memory or reset the electronic device 10. In addition, in another embodiment of the present invention, the user can remotely control the clearing driving unit 144 and the reset driving unit 146 through the Internet to control the clearing light source 108 and the resetting light source 110 to generate the clearing light 30 and reset. Light 32. The user can send the remote signal to the embedded control unit 16 of the electronic device 10 through the Internet, and the clear driving unit 144 and the reset driving unit 146 are controlled by the embedded control unit 16.
In addition, the clearing light 30 and the resetting light 32 of the present invention are mutually different light, that is, the wavelength of the clearing light 30 is different from the wavelength of the resetting light 32, and the light removing unit 182 and the resetting photoelectric unit 186 are sensed. The wavelength of the light is also different. The clear light 30 can be an ultraviolet light, and the reset light 32 can be a visible light, but the invention is not limited thereto. In other words, the clear photocell 182 can only sense the clear light 30, and the reset photocell 186 can only sense the reset light 32. Therefore, the clear circuit 18 of the present invention can utilize the clear light 30 and the reset light 32 of two different rays. The data of the memory is cleared and the electronic device 10 is reset. In addition, the clear driving unit 144 and the reset driving unit 146 of the present invention may be disposed on any chip inside the electronic device 10 or may be independently disposed on the electronic device 10.
In summary, the present invention is a memory clearing circuit that provides a clearing photocell and a clearing switch unit, and controls the clearing switch unit to switch by clearing the photocell to generate a corresponding control signal according to the clearing light to the clearing switch unit. The memory of the system chip is coupled to the ground to remove the data stored in the memory, so that the invention can remove the data stored in the memory of the system chip without disassembling the casing of the electronic device, thereby facilitating the use. It is easy to eliminate the problem that the system settings stored in the memory are abnormal. In addition, the clearing circuit of the present invention is further applicable to the resetting electronic device, which resets the photoelectric unit to generate a corresponding reset driving signal according to the reset light to the reset switch unit to control the reset switch unit to switch. The unit is coupled to the reference end to reset the electronic device.
Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope is subject to the definition of the scope of the patent application attached.
10．．．電子裝置10. . . Electronic device
102．．．供電單元102. . . Power supply unit
103．．．電源單元103. . . Power unit
104．．．限流單元104. . . Current limiting unit
106．．．重置單元106. . . Reset unit
108．．．清除光源108. . . Clear light source
110．．．重置光源110. . . Reset light source
12．．．中央處理單元12. . . Central processing unit
122．．．主記憶體122. . . Main memory
14．．．南橋晶片14. . . South Bridge Chip
142．．．記憶體142. . . Memory
144．．．清除驅動單元144. . . Clear drive unit
146．．．重置驅動單元146. . . Reset drive unit
16．．．嵌入式控制單元16. . . Embedded control unit
162．．．記憶體162. . . Memory
18．．．清除電路18. . . Clear circuit
181．．．偵測單元181. . . Detection unit
182．．．清除光電單元182. . . Clear photocell
184．．．清除開關單元184. . . Clear switch unit
186．．．重置光電單元186. . . Reset photocell
188．．．重置開關單元188. . . Reset switch unit
190．．．第一電晶體190. . . First transistor
192．．．第二電晶體192. . . Second transistor
194．．．電阻194. . . resistance
195．．．電阻195. . . resistance
196．．．第一電晶體196. . . First transistor
197．．．第二電晶體197. . . Second transistor
198．．．第一電晶體198. . . First transistor
199．．．第二電晶體199. . . Second transistor
22．．．周邊元件twenty two. . . Peripheral component
30．．．清除光線30. . . Clear light
32．．．重置光線32. . . Reset light
GND．．．接地端GND. . . Ground terminal
Sclr．．．控制訊號Sclr. . . Control signal
Srst．．．重置驅動訊號Srst. . . Reset drive signal
VDD．．．電源VDD. . . power supply
第一圖為本發明之一實施例之電子裝置的方塊圖；
第二圖為本發明之一實施例之清除電路與供電單元的方塊圖；
第三圖為本發明之一實施例之清除電路的電路示意圖；
第四圖為本發明之一實施例之流程圖；
第五圖為本發明之另一實施例之流程圖；
第六圖為本發明之另一實施例之清除電路與供電單元的方塊圖；
第七圖為本發明之另一實施例之清除電路的電路示意圖；以及
第八圖為本發明之又一實施例之電子裝置之局部方塊圖。
The first figure is a block diagram of an electronic device according to an embodiment of the present invention;
The second figure is a block diagram of a clearing circuit and a power supply unit according to an embodiment of the present invention;
The third figure is a circuit diagram of a clearing circuit according to an embodiment of the present invention;
The fourth figure is a flow chart of an embodiment of the present invention;
Figure 5 is a flow chart of another embodiment of the present invention;
Figure 6 is a block diagram of a clearing circuit and a power supply unit according to another embodiment of the present invention;
7 is a circuit diagram of a clearing circuit according to another embodiment of the present invention; and FIG. 8 is a partial block diagram of an electronic device according to still another embodiment of the present invention.
10．．．電子裝置10. . . Electronic device
102．．．供電單元102. . . Power supply unit
103．．．電源單元103. . . Power unit
104．．．限流單元104. . . Current limiting unit
14．．．南橋晶片14. . . South Bridge Chip
142．．．記憶體142. . . Memory
16．．．嵌入式控制單元16. . . Embedded control unit
162．．．記憶體162. . . Memory
18．．．清除電路18. . . Clear circuit
181．．．偵測單元181. . . Detection unit
182．．．清除光電單元182. . . Clear photocell
184．．．清除開關單元184. . . Clear switch unit
30．．．清除光線30. . . Clear light
Claims (10)
一清除開關單元，其耦接一接地端與該系統晶片的該記憶體；以及
一清除光電單元，其耦接該清除開關單元，並依據一清除光線產生一控制訊號，而控制該清除開關單元切換，讓該系統晶片的該記憶體經該清除開關單元耦接該接地端，以清除該記憶體。A memory clearing circuit for removing a memory of a system wafer, the clearing circuit comprising:
a clear switch unit coupled to a ground terminal and the memory of the system chip; and a clear photocell coupled to the clear switch unit and generating a control signal according to a clear light to control the clear switch unit Switching, the memory of the system chip is coupled to the ground via the clear switch unit to clear the memory.
一偵測單元，其設置於一電子裝置並耦接該清除開關單元，該偵測單元偵測該電子裝置是否處於使用狀態，當該電子裝置處於該使用狀態時，該偵測單元禁能該清除開關單元，當該電源狀態為未處於該使用狀態時，該偵測單元致能該清除開關單元。For example, the clearing circuit described in claim 1 of the patent scope further includes:
a detecting unit is disposed in an electronic device and coupled to the clearing switch unit, the detecting unit detects whether the electronic device is in use, and when the electronic device is in the use state, the detecting unit disables the The switch unit is cleared, and when the power state is not in the use state, the detecting unit enables the clear switch unit.
一第一電晶體，其耦接該清除光電單元與該偵測單元，該偵測單元在該電子裝置未處於使用狀態時，控制該第一電晶體切換，以傳送該控制訊號；以及
一第二電晶體，其耦接該接地端與該系統晶片的該記憶體，並依據該控制訊號而切換，讓該記憶體經該第二電晶體耦接該接地端，以清除該記憶體。The cleaning circuit of claim 2, wherein the clearing switch unit comprises:
a first transistor coupled to the clearing photocell and the detecting unit, the detecting unit controlling the first transistor switching to transmit the control signal when the electronic device is not in use; The second transistor is coupled to the ground and the memory of the system chip, and is switched according to the control signal, so that the memory is coupled to the ground via the second transistor to clear the memory.
一電晶體，其耦接該接地端與該系統晶片的該記憶體，並依據該控制訊號而切換，讓該記憶體經該電晶體耦接該接地端，以清除該記憶體。The clearing circuit of claim 1, wherein the clearing switch unit comprises:
A transistor is coupled to the ground and the memory of the system chip, and is switched according to the control signal, and the memory is coupled to the ground via the transistor to clear the memory.
一清除光源，其產生該清除光線；以及
一清除驅動單元，其耦接該清除光源，以驅動該清除光源產生該清除光線。For example, the clearing circuit described in claim 1 of the patent scope further includes:
a clearing light source that generates the clearing light; and a clearing drive unit coupled to the clearing light source to drive the clearing light source to generate the clearing light.
一重置開關單元，其耦接一參考端與一重置單元；以及
一重置光電單元，其耦接該重置開關單元，並依據一重置光線產生一重置驅動訊號，而驅動該重置開關單元切換，讓該重置單元經該重置開關單元耦接至該參考端，以驅使該重置單元重置一電子裝置。For example, the clearing circuit described in claim 1 of the patent scope further includes:
a reset switch unit coupled to a reference terminal and a reset unit; and a reset photocell coupled to the reset switch unit and generating a reset drive signal according to a reset light The switching unit is switched, and the reset unit is coupled to the reference terminal via the reset switch unit to drive the reset unit to reset an electronic device.
一偵測單元，其設置於一電子裝置並耦接該重置開關單元，該偵測單元偵測該電子裝置是否處於正常使用狀態；
該重置開關單元包含:
一第一電晶體，其耦接該重置光電單元與該偵測單元，該偵測單元在該電子裝置未處於正常使用狀態時，控制該第一電晶體切換，以傳送該重置驅動訊號；以及
一第二電晶體，其耦接該參考端與該重置單元，並依據該重置驅動訊號而切換，讓該重置單元經該第二電晶體耦接該參考端，以重置該電子裝置。For example, the clearing circuit described in claim 7 of the patent scope further includes:
a detecting unit is disposed on an electronic device and coupled to the reset switch unit, the detecting unit detecting whether the electronic device is in a normal use state;
The reset switch unit includes:
a first transistor coupled to the reset photocell and the detecting unit, the detecting unit controlling the first transistor switching to transmit the reset driving signal when the electronic device is not in a normal use state And a second transistor coupled to the reference terminal and the reset unit, and switched according to the reset driving signal, wherein the reset unit is coupled to the reference terminal via the second transistor to reset The electronic device.
一電晶體，其耦接該參考端與該重置單元，並依據該重置驅動訊號而切換，讓該重置單元經該電晶體耦接至該參考端，以驅使該重置單元重置該電子裝置。The clearing circuit of claim 7, wherein the reset switch unit comprises:
a transistor coupled to the reference terminal and the reset unit, and switched according to the reset driving signal, and the reset unit is coupled to the reference terminal via the transistor to drive the reset unit to reset The electronic device.
一重置光源，其產生該重置光線；以及
一重置驅動單元，其耦接該重置光源，以驅動該重置光源產生該重置光線。For example, the clearing circuit described in claim 7 of the patent scope further includes:
a reset light source that generates the reset light; and a reset drive unit coupled to the reset light source to drive the reset light source to generate the reset light.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| TW101111280A TWI464746B (en) | 2012-03-30 | 2012-03-30 | A clearing circuit for memory |
| CN2012101172580A CN103365387A (en) | 2012-03-30 | 2012-04-19 | Clearing circuit of memory |
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| TW101111280A TWI464746B (en) | 2012-03-30 | 2012-03-30 | A clearing circuit for memory |
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| TWI464746B true TWI464746B (en) | 2014-12-11 |
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| US6253319B1 (en) * | 1998-10-22 | 2001-06-26 | Compaq Computer Corporation | Method and apparatus for restoring a computer to a clear CMOS configuration |
| TW561336B (en) * | 2002-06-21 | 2003-11-11 | Via Tech Inc | Detection circuit and method of clearing bios configuration memory for computer main board |
| US7210009B2 (en) * | 2003-09-04 | 2007-04-24 | Advanced Micro Devices, Inc. | Computer system employing a trusted execution environment including a memory controller configured to clear memory |
| CN100361049C (en) * | 2005-03-08 | 2008-01-09 | 华硕电脑股份有限公司 | Computer system and method for clearing control circuit and environment set memory |
| CN101430926B (en) * | 2007-11-08 | 2010-09-22 | 英业达股份有限公司 | Resetting apparatus of memory |
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| TWI231916B (en) * | 2002-06-04 | 2005-05-01 | Micro Star Int Co Ltd | Data clearing circuit for CMOS of motherboard |
| CN2735426Y (en) * | 2004-07-15 | 2005-10-19 | 联想(北京)有限公司 | Real-time clock feed circuit capable of clearing CMOS settings |
| CN201369042Y (en) * | 2008-11-20 | 2009-12-23 | 名硕电脑(苏州)有限公司 | Test device |
| CN201562230U (en) * | 2009-12-25 | 2010-08-25 | 深圳市普联技术有限公司 | Electronic system and resetting device thereof |
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| US6253319B1 (en) * | 1998-10-22 | 2001-06-26 | Compaq Computer Corporation | Method and apparatus for restoring a computer to a clear CMOS configuration |
| TW561336B (en) * | 2002-06-21 | 2003-11-11 | Via Tech Inc | Detection circuit and method of clearing bios configuration memory for computer main board |
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| US7210009B2 (en) * | 2003-09-04 | 2007-04-24 | Advanced Micro Devices, Inc. | Computer system employing a trusted execution environment including a memory controller configured to clear memory |
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| CN103365387A (en) | 2013-10-23 |
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