TWI463654B - 奈米管／奈米導線場效電晶體之自行對準製程 - Google Patents

奈米管／奈米導線場效電晶體之自行對準製程 Download PDF

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TWI463654B
TWI463654B TW095100291A TW95100291A TWI463654B TW I463654 B TWI463654 B TW I463654B TW 095100291 A TW095100291 A TW 095100291A TW 95100291 A TW95100291 A TW 95100291A TW I463654 B TWI463654 B TW I463654B
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dimensional nanostructure
gate
metal
dielectric layer
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Phaedon Avouris
Roy A Carruthers
Jia Chen
Christophe G M M Detavernier
Christian Lavoie
Hon-Sum Philip Wong
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Description

奈米管/奈米導線場效電晶體之自行對準製程
本發明係關於一種半導體結構以及製造此結構的方法。本發明尤其是關於一種互補式金氧半導體(CMOS)裝置，例如場效電晶體(FET)，其包含至少一個一維奈米結構(一般為碳基礎的奈米材料)作為裝置通道，以及與裝置的閘極區域自行對準的金屬碳化物接觸，亦即對準閘極區域的邊緣。本發明亦提供製造此類CMOS裝置的方法。
在分子奈米電子領域中，很少材料可有如同一維奈米結構的前景，尤其是奈米碳管，其包含直徑只有數埃(Angstrom)的中空石墨管。奈米管以及其他類似的一維奈米結構可依奈米微粒的電子特性應用於電子裝置中，例如二極體以及電晶體。一維奈米結構具有獨特的大小、形狀及物理特性。舉例而言，碳基礎的奈米管具有類似將碳滾成管狀的六角晶格。
碳基礎的奈米管除了可以在室溫下顯示耐人尋味的量子行為，還顯示至少兩個重要的特性，奈米管可以依其對掌性(chirality)，亦即共形幾何，而呈現金屬性或是半導體性。金屬性的奈米管可載相當大的電流密度且維持固定的阻抗。半導體性的奈米管可如場效電晶體(FETs)電性地”開”或”關”。這兩種型態可以共價(分享電子)地結合。這些特性使得奈米管成為製造奈米尺寸半導體電路的優良材料。其他一維奈米結構也有類似的特性。
碳基礎的奈米管以及其他類似的一維奈米結構，因而在後SiFET縮放技術變得策略地重要。然而，並無已知的自行對準製程可與習知CMOS技術相比擬。相較於非自行對準製程，包含一維奈米結構的CMOS裝置的自行對準製程可以提供較簡單的製程步驟順序，而且可以減少一般發生在非自行對準製程中的製程失誤。再者，相較於非自行對準製程，自行對準製程提供可減少寄生的結構。
從上所述可知，需要提供一種自行對準製程，製造包含一維奈米結構(例如奈米管以及奈米導線)的CMOS裝置。
本發明提供一種自行對準的含一維奈米結構之場效電晶體(FET)及其製造方法。本發明自行對準的含一維奈米結構之FET包含作為接觸之一金屬碳化物，其與包含奈米結構作為裝置通道的閘極區域的邊緣對準。
在本發明中，「一維奈米結構」一詞係用來描述至少一奈米管或至少一奈米導線。奈米管和奈米導線的差異在於奈米管通常具有中空的洞，而奈米導線則是完全填滿奈米材料。「奈米桿(nanorods)」有時候用來描述奈米導線。一維奈米結構是具有奈米尺寸的直徑，以及相對而言長度相當長的結構。換言之，這樣的結構具有很大的外觀比(aspect ratio)，而且量子效應對於這些系統變得很重要。
具體且廣義而言，本發明之含一維奈米結構的FET包含：一基板，包含至少一閘極區域位於其上，至少一閘極區域包含至少一個一維奈米結構之層；以及一金屬碳化物接觸位於基板之表面上，係與至少一個一維奈米結構之層的邊緣對準。
在本發明之一實施例中，一維奈米結構係一奈米管。在本發明之另一實施例中，一維奈米結構係一奈米導線。本發明中之至少一個一維奈米結構一般是碳基礎的奈米材料，並以熟知相關奈米技術人士所知悉的技術形成。
除了提供前述的半導體結構，本發明亦提供製造此類結構的方法。本發明的方法包含：提供一結構，其包含至少一閘極堆疊於至少一個一維奈米結構之層的表面上；形成源極/汲極金屬於包含至少一個一維奈米結構之結構上；以及源極/汲極金屬與至少一個一維奈米結構之層反應，以形成一金屬碳化物。
在本發明的一些實施例中，摻雜至少一個一維奈米結構之層未被至少一個閘極堆疊保護的部分。於此實施例中，金屬碳化物形成於至少一個一維奈米結構之層中裸露且未摻雜的部分上。
在本發明的另一實施例中，在形成金屬碳化物前，間隙壁形成於至少一個閘極堆疊的側壁上。當使用自行對準矽化物退火製程時，使用間隙壁。當使用非自行對準矽化物退火製程，則可以省略間隙壁。
在本發明的另一實施例中，至少一個一維奈米結構係嵌入導電化合物中，係藉由源極/汲極金屬與下方含碳(C)或氧化物的基板反應而產生。嵌入係發生於前述碳化物退火的步驟。
藉由參考本申請案的圖式，將對本發明中包含一維奈米結構的場效電晶體及其製造方法提供更詳細的描述。本發明中的圖式係用以舉例說明，因此並非依照實際的比例繪製。此外，圖式中僅揭示單一閘極區域。此處所使用的「閘極區域」係用以表示閘極、閘極電極以及其下的裝置通道。雖然僅揭示描述單一閘極區域，本發明亦考量形成複數個此類的閘極區域，因此在基板的表面上可形成複數個包含一維奈米結構的場效電晶體。
本發明首先開始於提供圖1A或圖1B中所示的初始基板。圖1A所示的初始基板10A包含半導體層12，其上包含介電層14。半導體層12包含任何形式的半導體材料，包含但不限於：矽(Si)、矽鍺(SiGe)、矽碳(SiC)、矽鍺碳(SiGeC)、砷化鎵(GaAs)、砷化銦(InAs)、磷化銦(InP)或是任何三五族(III/V)或是二六族(II/VI)的化合物半導體。半導體層12亦可包含層狀半導體，例如Si/SiGe或是Si/SiGeC。選替地，半導體層12亦可包含絕緣層上矽(SOI)或是絕緣層上矽鍺(SGOI)。在本發明的這個階段，半導體層12可以是未摻雜，或是經摻雜具有一或多個摻雜區域。再者，半導體層12也可以是應變或是未應變的，且也可以具有例如(111)、(110)或(100)等的結晶方向。再者，半導體基板12可用於背閘(backgate)或以習知技術建構其他鄰近的裝置(不論是否在同一晶片)。
在本發明的一些實施例中，當介電層14很厚時，半導體層12可以操作基板取代，例如金屬或玻璃。本發明也考量當整個基板以介電層14組成時的實施例。
介電層14可包含氧化物、氮化物、氮氧化物、含碳介電層，例如類鑽碳(DLC)或是氟化類鑽碳、高k介電質(k大於4.0，一般大於7.0)、有機介電質或其多層結構。於一實施例中，介電層14包含例如SiO2 的氧化物或是例如Si3 N4 的氮化物。於另一實施例中，介電層14包含DLC層。
圖1A所示的介電層14係使用習知沉積步驟形成在半導體層12的表面上，例如化學氣相沉積(CVD)、電漿強化化學氣相沉積(PECVD)、化學溶液沉積、濺鍍、原子層沉積(ALD)、物理氣相沉積(PVD)、旋轉塗佈、磊晶成長或是其他類似的沉積步驟。本發明選替實施例中，介電層14亦可利用熱氧化、氮化或是氮氧化形成。
形成於半導體層12上的介電層14厚度，依所使用的介電材料種類及形成技術而異。一般而言，介電層14的厚度約從奈米以下(fraction of a nanometer)至約500奈米，而更典型為約1至約10奈米。前述的範圍適用於半導體基板及背閘製程。對於不具有電性功能的基板，整個基板可以是介電層，或介電層的厚度可以相當厚。
圖1B顯示可用於本發明的另一基板10B。尤其是，圖1B所示的初始基板10B包含半導體層12、介電層14以及嵌入介電層14內的含碳化合物16區域。含碳化合物16可以是任何包含碳的化合物材料，例如DLC或是氟化DLC。含碳化合物16係先在半導體層12的表面毯覆式沉積介電層14；在介電層14的表面形成圖案化光阻(未在圖中顯示)；接著在介電層14蝕刻開口，以界定嵌入含碳化合物16的區域。圖案化光阻係以習知步驟形成，包含在介電層14的表面形成光阻；以圖案照射曝光光阻，並以習知光阻顯影劑顯影經曝光的光阻。在介電層14形成開口的蝕刻步驟包含乾蝕刻製程，例如反應式離子蝕刻、離子束蝕刻、電漿蝕刻或是雷熱融熔。除乾蝕刻外，本發明也可使用濕蝕刻以形成開口，而在介電層14中形成嵌入區域。
當圖案化遮罩在適當位置時，沉積含碳化合物16以形成例如圖1B所示的結構。形成在介電層14內之含碳化合物16深度，自介電層14的上表面量起，則約1奈米至約500奈米或是更深，而更典型的深度為約5至20奈米。
除非特別說明，以下描述均使用初始基板10A說明。雖然是使用初始基板10A說明，本發明以及接下來的步驟可適用於圖1B所示的初始基板10B或是非半導體基板。
接著，如圖2所示，至少一個一維奈米結構的層18形成在介電層14頂部。在使用初始基板10B的範例中，至少一個一維奈米結構之層18係形成在介電層14及嵌入的含碳化合物16的表面上。
至少一個一維奈米結構之層18可包含奈米管、奈米導線或是這兩種奈米材料的組合。如前所述，奈米管和奈米導線的差異在於奈米管一般具有中空的洞，而奈米導線則完全填滿奈米材料。一維奈米結構為具有奈米尺寸的直徑以及相對而言長度相當長的結構。換言之，這樣的結構具有大的外觀比，而且量子效應對於這些系統很重要。
於本發明之一較佳實施例中，至少一個一維奈米結構之層18包含奈米管，而於本發明之另一較佳實施例中，至少一個一維奈米結構之層18包含奈米導線。
可用於本發明的奈米管為單壁或是多壁的奈米材料，其具有一般是約0.4奈米至約30奈米之外徑，更典型的外徑約0.8奈米至約2.5奈米。而長度一般是約5奈米至約100微米，更典型的長度約10奈米至約10微米。可用於本發明的奈米管除了外徑，其內徑一般是約0.4奈米至約15奈米，更典型的內徑約0.8奈米至約2.5奈米。可用於本發明的奈米管進一步特色為具有大的外觀比，一般約為5的數級(order of about 5)或更大，更典型的外觀比約5至約5000。
可用於本發明的奈米導線包含不同的原子層，也就是多於一層，而其外徑一般是約0.4奈米至約100奈米，更典型的外徑約0.8奈米至約50奈米。而長度是約5奈米至約100微米，更典型的長度約10奈米至約10微米。可用於本發明的奈米導線的進一步特色為具有大的外觀比，一般約為5的數級或更大，更典型的外觀比約5至約5000。
本發明使用的至少一個一維奈米結構之層18一般包括碳基礎的奈米材料，其具有捲起來的六角晶格結構。也就是說，本發明的奈米結構一般包含碳，例如石墨(graphite)。雖然碳基礎的奈米材料為較佳的實施例，本發明也包含其他種類的奈米材料，例如金屬類或碳基礎與金屬類的組合。
在本發明的這個階段之至少一個一維奈米結構之層18的厚度，取決於形成的技術。一般而言，至少一個一維奈米結構之層18的厚度約為0.4至約500奈米，更典型的厚度為約0.8至約50奈米。在使用奈米管的實施例中，奈米管層18一般的厚度約為0.8至約3奈米。
在此所謂「至少一個一維奈米結構之層」一詞，係表示包含至少一奈米管或奈米導線的一層，以及含有受控制以及選定數量的此類一維奈米結構的一層。層18較佳是包含複數個一維奈米結構，因此接下來的文字將使用「一維奈米結構層」一詞。
一維奈米結構層18可使用已知的技術形成。舉例而言，碳基礎的奈米管可用電弧放電及碳靶材的雷射融熔形成。選替地，碳基礎的奈米管也可用有金屬微粒存在的化學氣相沉積形成。可用於本發明的奈米管之形成方法的製程詳細內容，可於下列文獻中找到，例如S.Iijima等所著，刊登於1991年Nature 354，56的「Helical Microtubes of Graphite Carbon」、D.S.Bethune等所著，刊登於1993年Nature 363，605的「Cobalt Catalyzed Growth of Carbon Nanotubes with Single－Atomic－Layer Walls」，以及R.Saito等所著，刊登於1998年的Imperial College Press的「Physical Properties of Carbon Nanotubes」，這些文獻的全部內容在此列為參考。再者，同受讓人之美國專利申請案第2004/0035355 A1號所提到的無催化劑成長方法也可用以形成作為層18的奈米管。’355公開申請案的全部內容在此也列為參考。在本發明之一實施例中，碳奈米管層18係以使用鐵催化微粒的化學氣相沉積在900℃下進行10分鐘來形成。
碳基礎的奈米導線也可以使用電弧放電以及碳靶材的雷射融熔形成。選替地，碳基礎的奈米導線可在含有金屬微粒的化學氣相沉積形成。可用於本發明的奈米導線之形成方法的製程詳細內容，可以在下列參考文獻中找到，例如：S.Botti等於2002年4月8日的Chemical Physics Letters,vol.355,no.5－6：385－9的文獻，其全部內容在此列為參考。於本發明之一實施例，碳奈米導線18的形成係使用雷射誘發的化學氣相沉積的氫化非晶碳奈米微粒(自乙烯和乙炔的混合物)作為前驅物(請參考S.Botti等於J.Appl.Phys.88,3396,2000的文獻)，並利用下面的條件將其沉積於加熱的表面：約0.04大氣壓力，基板溫度約為1100℃，沉積時間約為90分鐘在約300 sccm流量的Ar載氣中形成。
除了前述形成一維奈米結構層18的技術，本發明也包含其他可以形成類似奈米結構的技術。舉例而言，溶液相分解(solution phase decomposition)、溶膠電泳(sol－gel electrophoresis)，或是濕式化學氫熱合成均可用以形成一維奈米結構。
在圖1A或圖1B所示的初始基板的表面形成一維奈米結構層18後，閘極介電層20形成在層18的表面上，如圖3所示。在至少一個一維結構直接形成於半導體基板內的實施例中，閘極介電層20可藉由熱成長製程形成，例如氧化、氮化或是氮氧化。選替地，閘極介電層20可以用沉積製程形成，例如化學氣相沉積(CVD)、電漿輔助CVD、原子層沉積(ALD)、蒸鍍、反應式濺鍍、化學溶液沉積或是其他類似的沉積製程。閘極介電層20也可以藉由上述技術的組合而形成。
閘極介電層20包含絕緣材料，其包含但不限於：氧化物、氮化物、氮氧化物及/或包含金屬矽酸鹽和氮化金屬矽酸鹽的矽酸鹽類。於一實施例中，閘極介電層20較佳包含氧化物，舉例而言如SiO2 、HfO2 、ZrO2 、Al2 O3 、TiO2 、La2 O3 、SrTiO3 、LaAlO3 或是其混合物。
閘極介電層20的實體厚度可能不同，但一般而言，閘極介電層20的厚度約0.5至約100奈米，更典型的厚度約0.5至約10奈米。
形成閘極介電層20後，藉由習知沉積技術，例如物理氣相沉積、CVD或是蒸鍍，形成閘極電極22的毯覆層於閘極介電層20上。所沉積的閘極電極22厚度，亦即高度，依所使用的沉積技術而異。一般而言閘極電極22的垂直厚度約5至約180奈米，更典型的厚度約5至約50奈米。
閘極電極22可以包含任何一般用於CMOS結構閘極的導電金屬。可用於閘極電極22的此類導電金屬舉例而言包含但不限於：多晶矽、導電金屬、導電金屬合金、導電矽化物、導電氮化物、多晶SiGe或其組合，同時也包含其多層的結構。於一些實施例中(未顯示)，包含氧化物或氮化物的閘極帽蓋層可形成在閘極電極22上方。再者，也可能在閘極電極材料的多層結構之間形成阻障層。
接著圖案化閘極電極22的毯覆層，以提供圖3所示的結構。可利用習知技術圖案化閘極電極22的毯覆層。舉例而言，可藉由微影及蝕刻圖案化閘極電極22。微影步驟包含塗佈光阻於閘極電極22的上表面(或如果有選用則於選用的閘極帽蓋層上)(未顯示)；將光阻曝光於所需圖案的照射下；以及使用習知光阻顯影劑顯影經曝光的光阻。接著使用一或多道蝕刻製程，將光阻圖案轉移到閘極電極22的毯覆層(或先轉移至選用的閘極帽蓋層，其次到閘極電極22)。蝕刻包含乾蝕刻製程，例如反應式離子蝕刻、離子束蝕刻、電漿蝕刻或是雷射融熔。濕蝕刻也可以用來圖案化閘極電極22。如圖所示，蝕刻步驟選擇性地蝕刻部分的閘極電極22，並停止於閘極介電層20。當圖案已轉移到閘極電極後，以習知剝除步驟移除圖案化光阻。所形成的閘極尺寸可能約3奈米至數微米，較佳為介於7奈米及1微米。
圖4顯示類似於圖3的結構，除了所使用的初始基板為圖1B所示者，而且使用了對準標記100及/或101。對準標記100形成在基板內，而對準標記101形成在閘極介電層20的表面上。對準標記100和101係使用習知步驟形成，且係用以對準閘極層與其下基板。
圖5顯示移除閘極介電層20裸露的部分(不包含圖案化的閘極電極22(以及閘極帽蓋層))後的結構。移除閘極介電層20的裸露部分係以蝕刻製程進行，相較於閘極導體及/或一維奈米結構層18，其選擇性地移除閘極介電材料。此處包含乾蝕刻或是濕蝕刻，以選擇性地移除閘極介電層20裸露的部分。如圖所示，移除步驟裸露出層18與閘極堆疊24相鄰的部分。閘極堆疊24至少包含圖案化閘極電極22以及圖案化閘極介電層20。雖然顯示單一閘極堆疊24，也可以如前所述形成複數個閘極堆疊。
接著，如圖6所示，選擇性地摻雜第一導電類型的摻雜質26(可為n型或p型)至層18裸露的部分，以提供選擇性摻雜區域28。在此要強調的是，對層18裸露部分的摻雜是選擇性進行的，並不是所有範例都必須使用。摻雜可以靜電摻雜、氣相摻雜或其他類似摻雜技術進行。若一維奈米結構層18包含奈米導線，則可使用離子植入。摻雜質26可以是n型摻雜質，其包含元素週期表中五A族的至少一元素。摻雜質26也可以是p型摻雜質，其包含元素週期表中三A族的至少一元素。摻雜步驟提供的摻雜區域28一般濃度約101 9 至約102 2 原子/cm3 。尤其是，位於層18裸露區域中的摻雜區域28之摻雜濃度約102 1 至大約102 2 原子/cm3 。
接著，如圖7所示，選擇性地形成包含一或多層介電層的介電層堆疊29。請注意，介電層堆疊29係用來在閘極堆疊24的側壁提供間隙壁。在一些使用自行對準退火的實施例中，需要形成間隙壁。在一些其他使用非自行對準退火的實施例中，則無須形成間隙壁。
在本發明的一些實施例中，摻雜質植入步驟可以在間隙壁形成之前，或是在間隙壁之其一形成後及在其他間隙壁形成後。
在所示的實施例中，介電堆疊29包含第一介電層30以及第二介電層32。介電堆疊29包含介電材料，例如氧化物、氮化物或是氮氧化物。一般習知用以形成閘極介電層20的沉積技術，可用來形成介電層堆疊29。選替地，介電層堆疊29可由熱製程形成。介電層堆疊29的厚度可有不同，一般而言整體介電層堆疊29的厚度約5至約100奈米。
在一些實施例中，介電層堆疊29及後續間隙壁的形成，可以在前述選擇性摻雜步驟前進行。
在圖7中，介電層堆疊29包含由不同介電材料組成的第一介電層(亦即內間隙壁材料)30以及第二介電層(亦即外間隙壁材料)32。於一實施例中，第一介電材料30包含氮化物(例如氮化矽)，而第二介電材料32包含氧化物(例如氧化矽)。
接著，進行蝕刻步驟，以自先前沉積過程中所有被覆蓋的水平表面，移除介電層堆疊29。蝕刻步驟如圖8和圖9所示。乾蝕刻、濕蝕刻或其組合均可使用。如實施例所示，第一次蝕刻係選擇性地自結構水平表面移除第二介電層32(如圖8所示)，第二次蝕刻接著自結構的水平表面移除第一介電層30。最終結構包含如圖9所示的內間隙壁30’及外間隙壁32’。雖然顯示雙間隙壁，本發明亦包含在閘極堆疊24的側壁上形成單一間隙壁或是多個間隙壁。
在本發明之一選擇性實施例中，如圖10所示，一金屬化合物層34形成於先前形成在一維奈米結構層18中的摻雜區域28上。當選擇形成此類結構時，金屬化合物層34也可以形成於層18裸露且未摻雜的區域上。金屬化合物層34係使摻雜區域28(或層18裸露且未摻雜部分)作用，並有協助形成金屬碳化物區域。金屬化合物層34舉例包含c－C4 H6 ＝Mo＝O(其中的c表示環狀)，如H.Oudghiri－Hassani等所著，2003年於Applied Surface Science,212－213，第4－9頁發表的「Passivation of metal carbide surfaces：relevance to carbon nanotube－metal interconnections」中所描述，其中有機群及導電碳化物之間的雙鍵可用於：1)分子電子應用；2)一些鉬亞烷基(molybdenum alkylidene)化合物對反應的置換族(metathesis family)為活性的，以長出共價嫁接的(grafted)聚合物層作為鈍化層或是金屬碳化物接觸的操控(例如請參照K.J.Ivin等於1997年的Olefin Metathesis and Metathesis Polymerization,Academic Press，San Diego所發表的文章，以及A.Furstner等於2000年Angew.Chem.Int.Ed.Engl.39 3012所發表的文章)。
金屬化合物層34可選擇性地沉積，使得其與一維奈米結構層進行化學反應。當進行選擇性沉積時，如果發生底切時(發生於使用非等向性蝕刻時)，層34可以進入側壁的底下。於一些實施例中，以反應式離子蝕刻或剝離製程形成的遮罩層可用於層34的沉積，使得層34不會延伸至側壁底下。金屬化合物層34的厚度因所使用的錯合物及所使用的技術而異。
接著，源極/汲極金屬36至少形成在先前形成於層18部分內的裸露摻雜區域28上，如圖11所示。在另一實施例中，源極/汲極金屬36形成在如圖10所示之金屬化合物層34上。在本發明的另一實施例中，源極/汲極金屬36至少形成在層18裸露且未摻雜的部分上。本發明中形成的源極/汲極金屬36使用共形沉積製程，例如：CVD、PECVD、化學溶液沉積、ALD、濺鍍、電鍍、蒸鍍或是其他類似製程。在本發明之一實施例中，源極/汲極金屬36係從一含碳靶材/來源(source)沉積。在本發明之一較佳實施例中，源極/汲極金屬36係以ALD沉積，以增加金屬至奈米結構的電流注入區域。尤其是，ALD提供源極/汲極金屬36在每個奈米結構周圍均勻覆蓋的方法。也就是說，可以形成源極/汲極金屬36的袖套，環繞每個層18中的奈米結構。
源極/汲極金屬36包含任何金屬或是類金屬元素，其足以與碳反應而形成穩定的二元金屬碳化物相。選替地，源極/汲極金屬可包含碳或是選擇性的其他元素。此類源極/汲極金屬範例包含：鋁(Al)、矽(Si)、鈧(Sc)、鈦(Ti)、釩(V)、鉻(Cr)、錳(Mn)、鐵(Fe)、釔(Y)、鋯(Zr)、鈮(Nb)、鉬(Mo)、鉿(Hf)、鉭(Ta)、鎢(W)及其混合物或其合金。較佳者，Al、Ti、Cr、Mo、W、Zr、Hf或Ta之至少其中之一係用於源極/汲極金屬36。化合物的形成可以在不同的氛圍中進行，例如氮氣、形成氣體、氯化物、溴化物、氟化物、氧化物及其他。不同的氛圍氣體會形成不同的導電化合物，其含有來自奈米管的碳，或嵌入奈米管本身。
源極/汲極金屬36的厚度依所使用的金屬及技術而異。一般而言，層36的厚度約3至約200奈米，更典型的厚度約5至約20奈米。
形成源極/汲極金屬36於結構上後，將結構進行退火步驟，其係進行於使奈米結構所含的摻雜區域28和源極/汲極金屬36反應的條件。在進行退火後所致的結構如圖12所示。如圖所示，金屬－碳化物區域38形成相鄰於閘極堆疊24；金屬－碳化物區域38對準閘極堆疊24的邊緣以及一維奈米結構層18剩餘層的邊緣。一維奈米結構的剩餘層係作為裝置通道。請注意：退火步驟可以在結構上留下一些源極/汲極金屬36。
在另一實施例(未顯示)中，退火導致源極/汲極金屬36與層18裸露且未摻雜的部分反應。此實施例亦形成金屬－碳化物區域。在另一實施例中，退火導致源極/汲極金屬36、選擇性的金屬化合物層34及層18摻雜或未摻雜部分的反應。在本發明另一實施例中，退火步驟導致一維奈米結構的嵌入導電化合物區域，其係因為金屬及其下包含碳或是氧化物的基板反應而產生。當嵌入發生時，間隙壁必須包含氮化物才不會喪失蝕刻選擇性。
本發明此時形成金屬碳化物38使用的退火步驟，係在約600℃或更高的溫度進行。一般而言，形成金屬－碳化物的退火是在約750℃至約1100℃。形成金屬－碳化物的退火係在鈍氣氛圍進行，例如He、Ar、Ne、Kr、Xe、N2 或是其混合物，例如He－Ar。退火進行次毫秒或更久，更典型的退火時間約10秒至約30分鐘。非常短時間的退火係以雷射退火達成。退火可以使用單一退火溫度或是多段退火溫度。退火可依所需包含不同的升溫循環、浸置循環及冷卻循環。
在形成金屬－碳化物區域38後，剩餘的源極/汲極金屬36，相較於金屬碳化物，使用蝕刻步驟選擇性移除金屬。圖13顯示使用上述步驟形成的可能結構。圖14和圖13的差異在於所使用的初始基板的形式。在兩個情況中，顯示一半導體結構，其包含基板10A或10B，並有至少一閘極區域於其上。至少一閘極區域包含圖案化閘極堆疊及一維奈米結構18的剩餘層。金屬碳化物接觸，亦即區域38，位於基板表面，並對準至少一閘極區域的邊緣及一維奈米結構18的剩餘層。
以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍內。
10A、10B．．．初始基板
12．．．半導體層
14．．．介電層
16．．．含碳化合物
18．．．一維奈米結構層
20．．．閘極介電層
22．．．閘極電極
24．．．閘極堆疊
26．．．摻雜質
28．．．摻雜區域
29．．．介電層堆疊
30．．．第一介電層
30’．．．內間隙壁
32’．．．外間隙壁
32．．．第二介電層
34．．．金屬化合物層
36．．．源極/汲極金屬
38．．．金屬－碳化物區域
100、101．．．對準標記
圖1A至圖1B係透過剖面圖，顯示可應用於本發明之不同形式的初始基板。
圖2係透過剖面圖，顯示圖1A之初始基板在形成至少一個一維奈米結構後的示意圖。
圖3係透過剖面圖，顯示圖2的結構在形成閘極介電層及圖案化閘極電極後的示意圖。
圖4係透過剖面圖，顯示類似於圖3所示的結構，除了其係使用圖1B中所示的初始基板並且使用對準標記。請注意當閘極遠小於接觸蝕，部分的裝置可以金屬性的奈米管製造而不用半導體性的奈米管。
圖5係透過剖面圖，顯示圖3的結構在圖案化閘極介電層後的示意圖。
圖6係透過剖面圖，顯示圖5的結構在對至少一個一維奈米結構層裸露部分選擇性摻雜時的示意圖。
圖7係透過剖面圖，顯示圖6的結構在形成選擇性的第一和第二介電層後的示意圖。
圖8係透過剖面圖，顯示圖7的結構在第二介電層被選擇性蝕刻後的示意圖。
圖9係透過剖面圖，顯示圖8的結構在第一介電層被選擇性蝕刻後的示意圖。
圖10係透或剖面圖，顯示圖9在進行一選擇性步驟後的示意圖，其中一金屬化合物形成於至少一個一維奈米結構層之選擇性摻雜部分上。
圖11係透過剖面圖，顯示圖9的結構在形成源極\汲極後的示意圖。
圖12係透過剖面圖，顯示圖11的結構在進行碳化物退火步驟後的示意圖。
圖13係透過剖面圖，顯示圖12的結構在蝕刻去額外的源極/汲極金屬後的示意圖。
圖14係透過剖面圖，顯示類似於圖13之結構，除了其係使用圖1B所顯示之初始基板的示意圖。
12．．．半導體層
14．．．介電層
18．．．一維奈米結構層
20．．．閘極介電層
22．．．閘極電極
28．．．摻雜區域
30’．．．內間隙壁
32’．．．外間隙壁
38．．．金屬－碳化物區域

Claims (26)

  1. 一種半導體結構，包含：一基板，包含至少一閘極區域於其上，該至少一閘極區域包含至少一個一維奈米結構之一層、位於該至少一個一維奈米結構之一表面上的一閘極介電層、以及位於該閘極介電層之一表面上的一閘極電極，其中該至少一個一維奈米結構之層係位於該基板與該閘極電極之間；至少一個間隙壁，位於該至少一個一維奈米結構之層的一表面上，其中該至少一個間隙壁之一內部邊緣(inner edge)係與該閘極電極之一側壁以及該閘極介電層之一側壁兩者皆側向(laterally)相鄰；以及一金屬碳化物接觸，位於該基板之一表面上，其中該金屬碳化物接觸係與該至少一個一維奈米結構之層之一側壁邊緣以及該至少一個間隙壁之一側壁邊緣兩者皆對準且側向相鄰但不重疊。
  2. 如申請專利範圍第1項所述之半導體結構，其中該至少一個一維奈米結構之層包含至少一奈米管。
  3. 如申請專利範圍第1項所述之半導體結構，其中該至少一個一維奈米結構之層包含至少一奈米導線。
  4. 如申請專利範圍第1項所述之半導體結構，其中該至少一個一維奈米結構之層包含奈米管和奈米導線的組合。
  5. 如申請專利範圍第1項所述之半導體結構，其中該至少一個一維奈米結構之層包含一碳基礎的奈米材料。
  6. 如申請專利範圍第1項所述之半導體結構，其中該基板包含一半導體層，具有一介電層於其中。
  7. 如申請專利範圍第6項所述之半導體結構，其中該介電層包含一含碳化合物之嵌入區域。
  8. 如申請專利範圍第7項所述之半導體結構，其中該含碳化合物係類鑽碳。
  9. 如申請專利範圍第1項所述之半導體結構，其中該金屬碳化物接觸包含一源極/汲極金屬以及該至少一個一維奈米結構之一預摻雜區域。
  10. 如申請專利範圍第9項所述之半導體結構，其中該源極/汲極金屬包含鋁(Al)、矽(Si)、鈧(Sc)、鈦(Ti)、釩(V)、鉻(Cr)、錳(Mn)、鐵(Fe)、釔(Y)、鋯(Zr)、鈮(Nb)、鉬(Mo)、鉿(Hf)、鉭(Ta)或是鎢(W)之至少其中之一。
  11. 如申請專利範圍第9項所述之半導體結構，其中該至少一個一維奈米結構之該選擇性預摻雜區域包含n型或p型摻雜質。
  12. 如申請專利範圍第1項所述之半導體結構，其中該至少一個一維奈米結構係嵌入一導電化合物區域中。
  13. 一種製造一半導體結構的方法，包含：提供至少一圖案化閘極堆疊於至少一個一維奈米結構之一層之一部份上，該至少一圖案化閘極堆疊由下而上包含一閘極介電層與一閘極電極，其中該閘極介電層與該閘極電極具有彼此對準的外部邊緣，且該至少一個一維奈米結構之層係直接位於一半導體層之一上表面上方的一介電層之一上表面上方；形成至少一間隙璧於該至少一個一維奈米結構之層的一表面上，其中該至少一個間隙壁之一內部邊緣(inner edge)係與該閘極電極之一側壁以及該閘極介電層之一側壁兩者皆側向(laterally)相鄰；形成一源極/汲極金屬於該至少一個一維奈米結構之層之其它部分上以及該圖案化閘極堆疊附近(around)，該至少一個一維奈米結構之層之該其它部分係與該至少一個一維奈米結構之層之該一部分側向相鄰；以及 藉由使該源極/汲極金屬與該至少一個一維奈米結構之層的該其它部分反應，以形成一金屬碳化物，其中該金屬碳化物接觸係與該至少一個一維奈米結構之層之一側壁邊緣以及該至少一個間隙壁之一側壁邊緣兩者皆對準且側向相鄰但不重疊。
  14. 如申請專利範圍第13項所述之方法，其中該至少一個一維奈米結構之層包含至少一奈米管。
  15. 如申請專利範圍第13項所述之方法，其中該至少一個一維奈米結構之層包含至少一奈米導線。
  16. 如申請專利範圍第13項所述之方法，其中該至少一個一維奈米結構之層包含奈米管和奈米導線的組合。
  17. 如申請專利範圍第13項所述之方法，其中該至少一個一維奈米結構之層包含一碳基礎的奈米材料。
  18. 如申請專利範圍第13項所述之方法，其中該至少一個一維奈米結構之層係藉由電弧放電、一碳靶材之雷射融熔或化學氣相沉積形成。
  19. 如申請專利範圍第13項所述之方法，其中該介電層包含 一含碳化合物嵌入的區域。
  20. 如申請專利範圍第13項所述之方法，更包含在形成源極/汲極金屬前，摻雜該至少一個一維奈米結構之層未直接位於該至少一圖案化閘極堆疊下方之該其它部分，該摻雜包含靜電摻雜、離子摻雜或是氣相摻雜。
  21. 如申請專利範圍第13項所述之方法，其中形成該源極/汲極金屬包含選擇並沉積鋁(Al)、矽(Si)、鈧(Sc)、鈦(Ti)、釩(V)、鉻(Cr)、錳(Mn)、鐵(Fe)、釔(Y)、鋯(Zr)、鈮(Nb)、鉬(Mo)、鉿(Hf)、鉭(Ta)或是鎢(W)之至少其中之一。
  22. 如申請專利範圍第21項所述之方法，其中該沉積包含一原子層沉積製程或是自一含碳靶材之沉積。
  23. 如申請專利範圍第13項所述之方法，更包含在形成該源極/汲極金屬前，形成一金屬化合物，作為該至少一個一維奈米結構之層的該其它部份。
  24. 如申請專利範圍第13項所述之方法，其中形成該金屬碳化物包含退火並移除未與該至少一個一維奈米結構之層之該其它部份反應的剩餘源極/汲極金屬，其中該退火 引起該至少一些源極/汲極金屬與該至少一個一維奈米結構之層之該其它部份間的反應。
  25. 如申請專利範圍第24項所述之方法，其中該退火係在600℃或是更高溫度的鈍氣氛圍進行。
  26. 如申請專利範圍第13項所述之方法，其中該金屬碳化物係以退火形成，該退火亦使得該至少一個一維奈米結構嵌入一導電化合物區域中。
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