TWI463326B - Flash memory of the smart selector - Google Patents
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Description
本發明係有關於一種快閃記憶體之智慧型選擇器，尤其是可針對主要快閃記憶體及備用快閃記憶體進行讀取及寫入操作的智慧型選擇器。The present invention relates to a smart selector for flash memory, and more particularly to a smart selector for reading and writing operations for primary flash memory and spare flash memory.
不論是桌上型電腦、筆記型電腦、平板電腦乃至於工業電腦，它的組成都脫離不了硬體(Hardware)、韌體(Firmware)、作業系統(Operation System，OS)及軟體(Software)的架構，其中使用者較熟悉的是OS(比如微軟公司的Windows視窗作業系統)、軟體及硬體，而韌體則往往被忽略。如果單就系統角度而言，韌體可簡單的定義為「電腦管理者」，是介於OS與硬體之間，主要在於驅動、初始化硬體，比如鍵盤、軟碟裝置、輸出輸入埠，檢測硬體功能，以及引導作業系統，還可讓使用者選擇由哪個裝置啟動電腦，如光碟機、硬碟、軟碟、隨身碟，對於安裝作業系統、以光碟片啟動電腦或改變找尋開機媒體的順序而言，特別有用。Whether it's a desktop computer, a notebook computer, a tablet computer or even an industrial computer, its composition can't be separated from hardware, firmware, operation system (OS) and software (Software). Architecture, in which users are more familiar with OS (such as Microsoft's Windows Windows operating system), software and hardware, and firmware is often ignored. From a system perspective, the firmware can be simply defined as a "computer administrator", which is between the OS and the hardware, mainly to drive and initialize the hardware, such as the keyboard, floppy device, and output input. Detecting hardware functions and guiding the operating system, and allowing the user to select which device to boot the computer, such as a CD player, hard drive, floppy disk, flash drive, to install the operating system, boot the computer with a CD or change the boot media The order is particularly useful.
具體而言，在x86架構下的電腦裡，韌體通常被稱做基本輸入輸出系統(Basic Input/Output System，BIOS)，當電腦系統在通電或重置(reset)時，中央處理器(CPU)所執行的第一條指令的位址是定位到BIOS的記憶體中，讓初始化程式開始執行。BIOS是載入在電腦硬體系統上的最基本的軟體程式碼，而考量到接腳(Pin)、體積大小、價格，BIOS一般是儲存在唯讀記憶體(ROM)或快閃記憶體(flash memory)中，因此，斷電後不會丟失。Specifically, in a computer with an x86 architecture, the firmware is usually referred to as a Basic Input/Output System (BIOS). When the computer system is powered on or reset, the CPU (CPU) The address of the first instruction executed is located in the memory of the BIOS, allowing the initialization program to begin execution. The BIOS is the most basic software code loaded on the computer hardware system. Considering the pin, size, and price, the BIOS is usually stored in read-only memory (ROM) or flash memory ( Flash memory), therefore, will not be lost after power off.
常用的快閃記憶體包括序列周邊介面匯流排(Serial Peripheral Interface Bus，SPI)的快閃記憶體(flash memory)，一般通稱為SPI-Flash，其中序列周邊介面匯流排(SPI)是一種4線同步序列資料協定，包括4線信號：SCLK(Serial Clock，序列時鐘)、MOSI/SIMO(Master Output/Slave Input，主控輸出/從屬輸入)、MISO/SOMI(Master Input/Slave Output，主控輸入/從屬輸出)、CS/SS(Chip Select/Slave Select，晶片選擇/樸從選擇)。Commonly used flash memory includes a flash memory of a Serial Peripheral Interface Bus (SPI), generally referred to as SPI-Flash, in which a sequence peripheral interface bus (SPI) is a 4-wire. Synchronous sequence data protocol, including 4-wire signals: SCLK (Serial Clock), MOSI/SIMO (Master Output/Slave Input), MISO/SOMI (Master Input/Slave Output) / slave output), CS / SS (Chip Select / Slave Select, wafer selection / Parker selection).
然而，隨著電腦系統中不同裝置的升級或更換，BIOS也需適當的更新以配合新的硬體平台，一般存放於主要快閃記憶體的內容大致可分Describe Table、ME、EEPROM、PDR與BIOS五個區塊，前面4個跟晶片程式有關，而最後一個區塊為存放系統功能設定，使用者可以從開機的BIOS視窗去修改這些設定，但若使用者同時修改到多個功能設定而導致系統無法開啟，則需有一個備份的BIOS區塊，確保系統能正常啟動。且新設定的BIOS內容只會儲存在主要快閃記憶體，備用快閃記憶體則一直保留原有的內容。However, with the upgrade or replacement of different devices in the computer system, the BIOS also needs to be updated to match the new hardware platform. Generally, the contents stored in the main flash memory can be roughly divided into Describe Table, ME, EEPROM, PDR and The five blocks of the BIOS, the first four are related to the chip program, and the last block is for storing the system function settings, the user can modify these settings from the boot BIOS window, but if the user simultaneously modifies multiple function settings If the system fails to open, you need to have a backup BIOS block to ensure that the system can start normally. And the newly set BIOS content will only be stored in the main flash memory, and the spare flash memory will retain the original content.
由上所述，為了使系統更為強健，則需要一種快閃記憶體之智慧型選擇器，提供主要快閃記憶體及備用快閃記憶體以個別儲存BIOS，能針對主要快閃記憶體及備用快閃記憶體分別進行切換讀取及寫入操作，提高BOIS的操作穩定性，以解決上述習用技術的問題。As mentioned above, in order to make the system more robust, a smart selector of flash memory is needed, which provides main flash memory and spare flash memory to store BIOS separately, and can be used for main flash memory and The spare flash memory respectively performs switching read and write operations to improve the operational stability of the BOIS to solve the above-mentioned problems of the conventional technology.
本發明之主要目的在提供一種快閃記憶體之智慧型選擇器，具有序列輸入資料接腳、第一序列輸入資料接腳、第二序列輸入資料接腳、第一序列輸出資料接腳、第二序列輸出資料接腳、多工序列輸出資料接腳、輸入切換信號接腳、輸出切換信號接腳及限制切換信號接腳，係電氣連接控制核心單元、主要快閃記憶體及備用快閃記憶體，用以 接收來自控制核心單元的控制信號，並依據控制信號以控制主要快閃記憶體及備用快閃記憶體的寫入及讀出操作。The main purpose of the present invention is to provide a smart selector for a flash memory, comprising a sequence input data pin, a first sequence input data pin, a second sequence input data pin, a first sequence output data pin, and a first sequence output data pin. Two sequence output data pin, multiplex sequence output data pin, input switching signal pin, output switching signal pin and limit switching signal pin, electrical connection control core unit, main flash memory and spare flash memory Body A control signal from the control core unit is received, and the write and read operations of the primary flash memory and the spare flash memory are controlled according to the control signal.
控制核心單元具有SPI的主控功能，而主要快閃記憶體及備用快閃記憶體具有SPI的從屬功能，用以個別儲存BIOS的程式碼，且具有SPI接腳，包括序列時鐘接腳、序列輸入資料接腳、序列輸出資料接腳及晶片選擇接腳，而來自控制核心單元的控制信號包括序列時鐘信號、序列輸入資料、序列輸出資料、晶片選擇信號、輸入切換信號、輸出切換信號及限制切換信號。The control core unit has the SPI master function, while the main flash memory and the spare flash memory have SPI slave functions for individually storing the BIOS code, and have SPI pins, including sequence clock pins, sequences. The input data pin, the sequence output data pin and the chip select pin, and the control signals from the control core unit include a sequence clock signal, a sequence input data, a sequence output data, a chip selection signal, an input switching signal, an output switching signal, and a limit. Switch the signal.
控制核心單元的序列時鐘信號及晶片選擇信號分別是連接至主要快閃記憶體及備用快閃記憶體的序列時鐘接腳及晶片選擇接腳，序列輸入資料是連接至智慧型選擇器及主要快閃記憶體的序列輸入資料接腳，輸入切換信號、輸出切換信號及限制切換信號是連接至智慧型選擇器的輸入切換信號接腳、輸出切換信號接腳及限制切換信號接腳，智慧型選擇器的第一序列輸入資料接腳及/或第二序列輸入資料接腳分別連接主要快閃記憶體及備用快閃記憶體的序列輸入資料接腳，而主要快閃記憶體及備用快閃記憶體的序列輸出資料接腳分別連接第一序列輸出資料接腳及第二序列輸出資料接腳。The serial clock signal and the chip selection signal of the control core unit are respectively a serial clock pin and a chip selection pin connected to the main flash memory and the spare flash memory, and the serial input data is connected to the smart selector and mainly fast. Flash memory serial input data pin, input switching signal, output switching signal and limit switching signal are input switching signal pin connected to smart selector, output switching signal pin and limit switching signal pin, intelligent selection The first sequence input data pin and/or the second sequence input data pin are respectively connected to the serial input data pin of the main flash memory and the spare flash memory, and the main flash memory and the spare flash memory are respectively connected. The serial sequence output data pins are respectively connected to the first sequence output data pin and the second sequence output data pin.
智慧型選擇器依據輸入切換信號，將序列輸入資料傳送至第一序列輸入資料接腳及/或第二序列輸入資料接腳，且依據輸出切換信號，選取來自主要快閃記憶體或備用快閃記憶體的序列輸出資料而傳送至多工序列輸出資料接腳。此外，智慧型選擇器依據限制切換信號決定定址邊限，用以配合序列輸入資料中包含的定址位址，重置主要快閃記憶體或備用快閃記憶體的相對應定址位址。The smart selector transmits the sequence input data to the first sequence input data pin and/or the second sequence input data pin according to the input switching signal, and selects from the main flash memory or the standby flash according to the output switching signal. The sequence output data of the memory is transferred to the multiplex sequence output data pin. In addition, the smart selector determines the addressing margin according to the limit switching signal, and matches the address address included in the sequence input data to reset the corresponding address address of the primary flash memory or the spare flash memory.
因此，本發明的智慧型選擇器能分別針對主要快閃記憶體及備用快閃記憶體，進行主要快閃記憶體的同時寫入、讀 取操作、主要快閃記憶體與備用快閃記憶體區間切換讀取，其中上述切換讀取為讀取主要快閃記憶體的前四個區塊與備用快閃記憶體的BIOS區塊，對於系統來說周邊只有一個單一的主要快閃記體，但是實際上是由主要快閃記憶體與備用快閃記憶體所組成的。Therefore, the smart selector of the present invention can perform simultaneous writing and reading of the main flash memory for the main flash memory and the spare flash memory, respectively. The operation, the main flash memory and the spare flash memory area are switched and read, wherein the switching is performed to read the first four blocks of the main flash memory and the BIOS block of the spare flash memory. The system has only a single main flash memory in the periphery, but it is actually composed of the main flash memory and the spare flash memory.
如上所述，當切換區間讀取時，系統讀到的BIOS區塊為備用記憶體的BIOS區塊，此區塊為預設且無修改過的區塊，可改善因主要快閃記憶體的BIOS區塊因不正常的設定，導致系統錯誤，而無法啟動的問題，所以，當進行主要快閃記憶體、備用快閃記憶體切換讀取時，系統還是認定其為單一顆快閃記憶體。As described above, when the switching interval is read, the BIOS block read by the system is the BIOS block of the spare memory, and the block is a preset and unmodified block, which can improve the main flash memory. The BIOS block is caused by an abnormal setting, which causes a system error and cannot be started. Therefore, when the main flash memory or the spare flash memory is switched, the system still recognizes it as a single flash memory. .
110‧‧‧快閃記憶體之智慧型選擇器110‧‧‧Smart Memory Smart Selector
20‧‧‧從屬單元20‧‧‧Subordinate unit
21‧‧‧主要快閃記憶體21‧‧‧Main flash memory
23‧‧‧備用快閃記憶體23‧‧‧Alternate flash memory
30‧‧‧控制核心單元30‧‧‧Control core unit
40‧‧‧主控單元40‧‧‧Master unit
CS‧‧‧晶片選擇信號CS‧‧‧ wafer selection signal
CS_P‧‧‧晶片選擇接腳CS_P‧‧‧ wafer selection pin
LIM_SW‧‧‧限制切換信號LIM_SW‧‧‧Restricted switching signal
LIM_SW_P‧‧‧限制切換信號接腳LIM_SW_P‧‧‧Limit switching signal pin
SI1_P‧‧‧第一序列輸入資料接腳SI1_P‧‧‧ first sequence input data pin
SI2_P‧‧‧第二序列輸入資料接腳SI2_P‧‧‧Second sequence input data pin
SCLK‧‧‧序列時鐘信號SCLK‧‧‧sequence clock signal
SCLK_P‧‧‧序列時鐘接腳SCLK_P‧‧‧Sequence Clock Pins
SI‧‧‧序列輸入資料信號SI‧‧‧Sequence input data signal
SI_P‧‧‧序列輸入資料接腳SI_P‧‧‧Sequence input data pin
SI_SW‧‧‧輸入切換信號SI_SW‧‧‧ input switching signal
SI_SW_P‧‧‧輸入切換信號接腳SI_SW_P‧‧‧ input switching signal pin
SO‧‧‧序列輸出資料信號SO‧‧‧Sequence output data signal
SO_MUX_P‧‧‧多工序列輸出資料接腳SO_MUX_P‧‧‧Multiplex sequence output data pin
SO_P‧‧‧序列輸出資料接腳SO_P‧‧‧Sequence output data pin
SO_SW‧‧‧輸出切換信號SO_SW‧‧‧ output switching signal
SO_SW_P‧‧‧輸出切換信號接腳SO_SW_P‧‧‧ output switching signal pin
SO1_P‧‧‧第一序列輸出資料接腳SO1_P‧‧‧ first sequence output data pin
SO2_P‧‧‧第二序列輸出資料接腳SO2_P‧‧‧Second sequence output data pin
第一圖顯示本發明快閃記憶體之智慧型選擇器的示意圖。The first figure shows a schematic diagram of the smart selector of the flash memory of the present invention.
第二圖顯示本發明快閃記憶體之智慧型選擇器的詳細電氣連接示意圖。The second figure shows a detailed electrical connection diagram of the smart selector of the flash memory of the present invention.
第三圖顯示本發明快閃記憶體控制主要快閃記憶體的寫入操作波形示意圖。The third figure shows a waveform diagram of the write operation of the main flash memory of the flash memory control of the present invention.
第四圖顯示本發明快閃記憶體控制備用快閃記憶體的寫入操作波形示意圖。The fourth figure shows a waveform diagram of the write operation of the flash memory control spare flash memory of the present invention.
以下配合圖式及元件符號對本發明之實施方式做更詳細的說明，俾使熟習該項技藝者在研讀本說明書後能據以實施。The embodiments of the present invention will be described in more detail below with reference to the drawings and the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;
參閱第一圖，本發明快閃記憶體之智慧型選擇器的示意圖。如第一圖所示，本發明的快閃記憶體之智慧型選擇器10係電氣連接主要快閃記憶體21、備用快閃記憶體23及控制核心單元30，其中主要快閃記憶體21及備用快閃記憶體23係結合成序列周邊介面匯流排(SPI)從屬單元20，而智慧型選擇器10及控制核心單元30係結合成SPI主控單元40，且主要快閃記憶體21及備用快閃記憶體23具有SPI 的從屬(Slave)功能，並用以個別儲存基本輸入輸出系統(BIOS)的程式碼，同時控制核心單元30具有SPI的主控(Master)功能，以使得智慧型選擇器10接收來自控制核心單元30的控制信號，並依據控制信號而藉SPI協定，同時對主要快閃記憶體21及備用快閃記憶體23進行寫入、區間切換讀取主要快閃記憶體21及備用快閃記憶體操作，亦即更新或讀取主要快閃記憶體21及備用快閃記憶體23所儲存的BIOS。Referring to the first figure, a schematic diagram of a smart selector of the flash memory of the present invention. As shown in the first figure, the smart memory selector 10 of the flash memory of the present invention is electrically connected to the main flash memory 21, the spare flash memory 23 and the control core unit 30, wherein the main flash memory 21 and The spare flash memory 23 is combined into a sequence peripheral interface bus (SPI) slave unit 20, and the smart selector 10 and the control core unit 30 are combined into the SPI master unit 40, and the main flash memory 21 and the spare Flash memory 23 has SPI The slave function is used to store the code of the basic input/output system (BIOS) separately, while the control core unit 30 has the SPI master function to enable the smart selector 10 to receive from the control core unit 30. Control signal, and according to the control signal by the SPI protocol, while writing to the main flash memory 21 and the spare flash memory 23, the interval switching reads the main flash memory 21 and the spare flash memory operation, That is, the BIOS stored in the primary flash memory 21 and the spare flash memory 23 is updated or read.
本發明的快閃記憶體之智慧型選擇器10可藉微處理器執行特定韌體程式而實現，或直接以積體電路(IC)或多個分立電子元件構成的硬體電路而實現。此外，本發明的智慧型選擇器10也可與控制核心單元30整合成單一積體電路的SPI主控單元40。The smart selector 10 of the flash memory of the present invention can be implemented by a microprocessor executing a specific firmware program, or directly by a hardware circuit composed of an integrated circuit (IC) or a plurality of discrete electronic components. In addition, the smart selector 10 of the present invention can also be integrated with the control core unit 30 into a single integrated circuit SPI master unit 40.
以下，為進一步詳細說明本發明的技術特徵，請配合參閱第二圖，本發明快閃記憶體之智慧型選擇器的詳細電氣連接示意圖。智慧型選擇器10主要具有多個輸出輸入接腳，包括序列輸入資料接腳SI_P、第一序列輸入資料接腳SI1_P、第二序列輸入資料接腳SI2_P、第一序列輸出資料接腳SO1_P、第二序列輸出資料接腳SO2_P、多工序列輸出資料接腳SO_MUX_P、輸入切換信號接腳SI_SW_P、輸出切換信號接腳SO_SW_P及限制切換信號接腳LIM_SW_P，而主要快閃記憶體21及備用快閃記憶體23個別具有SPI接腳，包括序列時鐘接腳SCLK_P、序列輸入資料接腳SI_P、序列輸出資料接腳SO_P及晶片選擇接腳CS_P。Hereinafter, in order to further explain the technical features of the present invention in detail, please refer to the second figure, a detailed electrical connection diagram of the smart selector of the flash memory of the present invention. The smart selector 10 mainly has a plurality of output input pins, including a sequence input data pin SI_P, a first sequence input data pin SI1_P, a second sequence input data pin SI2_P, a first sequence output data pin SO1_P, a first The second sequence output data pin SO2_P, the multiplex sequence output data pin SO_MUX_P, the input switching signal pin SI_SW_P, the output switching signal pin SO_SW_P, and the limit switching signal pin LIM_SW_P, and the main flash memory 21 and the spare flash memory The body 23 has an SPI pin, and includes a sequence clock pin SCLK_P, a sequence input data pin SI_P, a sequence output data pin SO_P, and a chip select pin CS_P.
此外，上述來自控制核心單元30的控制信號包括序列時鐘信號SCLK、序列輸入資料信號SI、序列輸出資料信號SO、晶片選擇信號CS、輸入切換信號SI_SW、輸出切換信號SO_SW及限制切換信號LIM_SW。Further, the above control signals from the control core unit 30 include a sequence clock signal SCLK, a sequence input data signal SI, a sequence output data signal SO, a wafer selection signal CS, an input switching signal SI_SW, an output switching signal SO_SW, and a limit switching signal LIM_SW.
上述智慧型選擇器10的輸出輸入接腳、主要快閃記憶體21及備用快閃記憶體23的SPI接腳以及控制信號之間的電氣連接關係為如第二圖所示，不過要注意的是，本發明的範圍並不限於第二圖的連接方式，而是可包含能實現智慧型選擇器10、主要快閃記憶體21及備用快閃記憶體23、控制核心單元30之間控制功能的其他連接方式。The electrical connection relationship between the output input pin of the smart selector 10, the SPI pin of the main flash memory 21 and the spare flash memory 23, and the control signal is as shown in the second figure, but it should be noted. However, the scope of the present invention is not limited to the connection manner of the second figure, but may include the control function between the smart selector 10, the main flash memory 21 and the spare flash memory 23, and the control core unit 30. Other connection methods.
具體而言，來自控制核心單元30的序列時鐘信號SCLK及晶片選擇信號CS分別是連接至主要快閃記憶體21及備用快閃記憶體23的序列時鐘接腳SCLK_P及晶片選擇接腳CS_P，序列輸入資料信號SI是連接至智慧型選擇器10的序列輸入資料接腳SI_P及主要快閃記憶體21的序列輸入資料接腳SI_P。此外，來自控制核心單元30的輸入切換信號SI_SW、輸出切換信號SO_SW及限制切換信號LIM_SW是連接至智慧型選擇器10的輸入切換信號接腳SI_SW_P、輸出切換信號接腳SO_SW_P及限制切換信號接腳LIM_SW_P，且智慧型選擇器10的第一序列輸入資料接腳SI1_P及/或第二序列輸入資料接腳SI2_P分別連接主要快閃記憶體21及備用快閃記憶體23的序列輸入資料接腳SI_P，而主要快閃記憶體221及備用快閃記憶體23的序列輸出資料接腳SO_P分別連接智慧型選擇器10的第一序列輸出資料接腳SO1_P及第二序列輸出資料接腳SO2_P。Specifically, the sequence clock signal SCLK and the chip selection signal CS from the control core unit 30 are a serial clock pin SCLK_P and a chip select pin CS_P connected to the main flash memory 21 and the spare flash memory 23, respectively. The input data signal SI is a serial input data pin SI_P connected to the smart selector 10 and a serial input data pin SI_P of the main flash memory 21. Further, the input switching signal SI_SW, the output switching signal SO_SW, and the limit switching signal LIM_SW from the control core unit 30 are an input switching signal pin SI_SW_P connected to the smart selector 10, an output switching signal pin SO_SW_P, and a limit switching signal pin. LIM_SW_P, and the first sequence input data pin SI1_P and/or the second sequence input data pin SI2_P of the smart selector 10 are respectively connected to the serial input data pin SI_P of the main flash memory 21 and the spare flash memory 23, respectively. The sequence output data pins SO_P of the main flash memory 221 and the spare flash memory 23 are respectively connected to the first sequence output data pin SO1_P and the second sequence output data pin SO2_P of the smart selector 10.
智慧型選擇器10可依據輸入切換信號SI_SW，將序列輸入資料信號SI傳送至第一序列輸入資料接腳SI1_P及/或第二序列輸入資料接腳SI2_P，且依據輸出切換信號SO_SW，選取來自主要快閃記憶體21或備用快閃記憶體23的序列輸出資料接腳SO_P之資料而傳送至多工序列輸出資料接腳SO_MUX。此外，智慧型選擇器10可依據限制切換信號LIM_SW決定主要快閃記憶體21或備用快閃記憶體23的預設定址邊界，用以配合序列輸入資料信號SI中所包含 的定址位址，以重置主要快閃記憶體21或備用快閃記憶體23的相對應定址位址，亦即在主要快閃記憶體21或備用快閃記憶體23的定址位址達到相對應的預設定址邊限時，將定址位址重置回啟始位址，亦即位址0x0(h)。The smart selector 10 can transmit the sequence input data signal SI to the first sequence input data pin SI1_P and/or the second sequence input data pin SI2_P according to the input switching signal SI_SW, and select the main switch signal SO_SW according to the output switching signal SO_SW. The data of the sequence output data pin SO_P of the flash memory 21 or the spare flash memory 23 is transferred to the multiplex sequence output data pin SO_MUX. In addition, the smart selector 10 can determine the pre-address boundary of the primary flash memory 21 or the spare flash memory 23 according to the limit switching signal LIM_SW for matching the sequence input data signal SI. Addressing address to reset the corresponding address address of the primary flash memory 21 or the spare flash memory 23, that is, the address of the address of the primary flash memory 21 or the spare flash memory 23 When the corresponding pre-set address margin is reached, the address address is reset back to the start address, that is, the address 0x0 (h).
為更加有效使用主要快閃記憶體21及備用快閃記憶體23，可將主要快閃記憶體21及備用快閃記憶體23以適當的分割位址分割成A區塊及B區塊。以32M的主要快閃記憶體21為例，其定址位址範圍為0x000000(h)~0x3FFFFF(h)，可將A區塊配置成定址位址範圍為0x000000(h)~0x0FFFFF(h)，而B區塊的定址位址範圍為剩餘的0x1000000(h)~0x3FFFFF(h)，亦即分割位址為0x0FFFFF(h)。同理，備用快閃記憶體23也以相同方式分割成A區塊及B區塊。In order to use the main flash memory 21 and the spare flash memory 23 more effectively, the main flash memory 21 and the spare flash memory 23 can be divided into the A block and the B block by the appropriate split address. Taking the 32M main flash memory 21 as an example, the address range of the address is 0x000000(h)~0x3FFFFF(h), and the A block can be configured to address the address range from 0x000000(h)~0x0FFFFF(h). The address range of the B block is the remaining 0x1000000(h)~0x3FFFFF(h), that is, the split address is 0x0FFFFF(h). Similarly, the spare flash memory 23 is also divided into the A block and the B block in the same manner.
以下將進一步說明本發明的輸入切換信號SI_SW、輸出切換信號SO_SW及限制切換信號LIM_SW的特點，其中輸入切換信號SI_SW、輸出切換信號SO_SW及限制切換信號LIM_SW可較佳的配置為二位元信號。The characteristics of the input switching signal SI_SW, the output switching signal SO_SW, and the limit switching signal LIM_SW of the present invention are further described below. The input switching signal SI_SW, the output switching signal SO_SW, and the limit switching signal LIM_SW may be preferably configured as a two-bit signal.
在進行資料輸入或資料寫入時，可依據輸入切換信號SI_SW以設定主要快閃記憶體21及/或備用快閃記憶體23為禁輸入(亦即禁寫入)，或可輸入(亦即可寫入)，其中二位元的輸入切換信號SI_SW具有四種設定方式，因此相當具有彈性，當然，還可適當增加輸入切換信號SI_SW的位元數，以提高系統應用的使用彈性。When data input or data writing is performed, the input flash signal SI_SW may be used to set the main flash memory 21 and/or the spare flash memory 23 as prohibited inputs (ie, forbidden writing), or may be input (ie, It can be written), wherein the two-bit input switching signal SI_SW has four setting modes, so it is quite flexible. Of course, the number of bits of the input switching signal SI_SW can also be appropriately increased to improve the flexibility of use of the system application.
第三圖及第四圖分別顯示主要快閃記憶體21及備用快閃記憶體23在特定輸入切換信號SI_SW下的寫入操作波形，其中主要快閃記憶體21為可寫入，而備用快閃記憶體23為禁寫入，且實際作法可為，主要快閃記憶體21的序列輸入資料接腳SI_P接收來自智慧型選擇器10的第一序列輸入資料接腳SI1_P之信號，同時備用快閃記憶體23的序列 輸入資料接腳SI_P被智慧型選擇器10的第二序列輸入資料接腳SI2_P拉為低態。The third and fourth figures respectively show the write operation waveforms of the main flash memory 21 and the spare flash memory 23 under the specific input switching signal SI_SW, wherein the main flash memory 21 is writable, and the standby is fast. The flash memory 23 is forbidden to write, and the actual method may be that the serial input data pin SI_P of the main flash memory 21 receives the signal from the first sequence input data pin SI1_P of the smart selector 10, and the standby is fast. Flash memory 23 sequence The input data pin SI_P is pulled to the low state by the second sequence input data pin SI2_P of the smart selector 10.
由上述說明可知，在寫入時，可透過輸入切換信號SISW的切換，來選擇要寫入主要快閃記憶體21及/或備用快閃記憶體23。一般來說，備用快閃記憶體23所儲存的內容極為重要，可在主要快閃記憶體21的內容不正確或導致系統操作不正常時，用來恢復系統正常操作，所以不輕易進行寫入動作。此外，在系統操作上，主要快閃記憶體21及備用快閃記憶體23在本質上是當作單一記憶體而操作，只是以相對應的定址位址區別，同時可減少接腳數目，簡化硬體架構。As apparent from the above description, at the time of writing, the main flash memory 21 and/or the spare flash memory 23 can be selected to be written by switching the input switching signal SISW. Generally, the content stored in the spare flash memory 23 is extremely important, and can be used to restore the normal operation of the system when the content of the main flash memory 21 is incorrect or the system is not operating normally, so the writing is not easy. action. In addition, in the system operation, the main flash memory 21 and the spare flash memory 23 are essentially operated as a single memory, but are distinguished by corresponding address addresses, and the number of pins can be reduced and simplified. Hardware architecture.
此外，在資料讀取時，可依據二位元的輸出切換信號SO_SW，選取主要快閃記憶體21及/或備用快閃記憶體23的A區塊或B區塊之資料輸出，當作本發明智慧型選擇器10的多工序列輸出資料接腳SO_MUX_P之序列輸出資料信號SO。例如，可利用輸出切換信號SO_SW設定成對應A區塊位址的序列輸出資料信號SO是來自主要快閃記憶體21的A區塊，而對應B區塊位址的序列輸出資料信號SO是來自備用快閃記憶體23的A區塊。In addition, when the data is read, the data output of the A block or the B block of the main flash memory 21 and/or the spare flash memory 23 may be selected according to the binary output switching signal SO_SW. The sequence output data signal SO of the multiplex sequence output data pin SO_MUX_P of the smart selector 10 is invented. For example, the sequence output data signal SO that is set to the corresponding A block address by the output switching signal SO_SW is the A block from the main flash memory 21, and the sequence output data signal SO corresponding to the B block address is from A block of spare flash memory 23.
本發明可進一步利用限制切換信號LIM_SW選擇主要快閃記憶體21及備用快閃記憶體23的邊界位址，使得在進行連續讀取時，當智慧型選擇器10經第一序列輸入資料接腳SI1_P及/或第二序列輸入資料接腳SI2_P所傳送的定址位址是主要快閃記憶體21及/或備用快閃記憶體23的最大位址時，能確保第一序列輸入資料接腳SI1_P及/或第二序列輸入資料接腳SI2_P的下一個定址位址會從0x000000開始。例如，限制切換信號LIM_SW可設定相對應的最大位址(記憶容量)為0x1fffff(16M)、0x3fffff(32M)、0x7fffff(64M)、0xffffff(128M)。要注意的是，可增加限制切換信號 LIM_SW的位元數，藉以對應到其他具不同記憶容量的快閃記憶體，比如N位元可指定2N種記憶容量。The present invention can further select the boundary address of the primary flash memory 21 and the spare flash memory 23 by using the limit switching signal LIM_SW, so that when the continuous reading is performed, the smart selector 10 inputs the data pin through the first sequence. When the address address transmitted by SI1_P and/or the second sequence input data pin SI2_P is the maximum address of the main flash memory 21 and/or the spare flash memory 23, the first sequence input data pin SI1_P can be ensured. And / or the next address of the second sequence input data pin SI2_P will start from 0x000000. For example, the limit switching signal LIM_SW may set a corresponding maximum address (memory capacity) to be 0x1fffff (16M), 0x3fffff (32M), 0x7fffff (64M), 0xffffff (128M). It should be noted that the limit switching signal can be increased. The number of bits of LIM_SW, corresponding to other flash memory with different memory capacity, such as N bits can specify 2N kinds of memory capacity.
因此，本發明的特點在於，能分別針對儲存基本輸入輸出系統的主要快閃記憶體及備用快閃記憶體，利用SPI協定以進行獨立的寫入、讀取操作，進而改善基本輸入輸出系統的操作穩定性，亦即可在主要快閃記憶體中的基本輸入輸出系統被不適當更新或未能配合其他硬體裝置的變換而導致整體系統操作不正常或甚至失效時，藉讀取備用快閃記憶體中能匹配原有硬體系統的基本輸入輸出系統，以恢復系統操作，或提供系統修復功能。Therefore, the present invention is characterized in that the SPI protocol can be used for independent writing and reading operations for the main flash memory and the spare flash memory storing the basic input/output system, thereby improving the basic input/output system. Operational stability, or when the basic input/output system in the main flash memory is improperly updated or fails to adapt to other hardware devices, causing the overall system to operate abnormally or even fail, The flash memory can match the basic input and output system of the original hardware system to restore system operation or provide system repair function.
本發明的另一特點在於利用輸入切換信號、輸出切換信號及限制切換信號，藉以更加彈性的控制主要快閃記憶體及備用快閃記憶體的寫入、讀取操作，尤其是能配合不同記憶容量的快閃記憶體，以避免超出相對應的最大可定址位址，確保正常操作，雖然本發明是由主要快閃記憶體、備用閃記憶體共兩個快閃記憶體所組成的記憶體單元，但對於系統來說，仍可被視為單一個快閃記憶體。Another feature of the present invention is that the input switching signal, the output switching signal, and the limit switching signal are utilized to more flexibly control the writing and reading operations of the main flash memory and the spare flash memory, especially to match different memories. The capacity of the flash memory to avoid exceeding the corresponding maximum addressable address, ensuring normal operation, although the present invention is a memory composed of two main flash memories, a spare flash memory and two flash memories. Unit, but for the system, it can still be considered as a single flash memory.
以上所述者僅為用以解釋本發明之較佳實施例，並非企圖據以對本發明做任何形式上之限制，是以，凡有在相同之發明精神下所作有關本發明之任何修飾或變更，皆仍應包括在本發明意圖保護之範疇。The above is only a preferred embodiment for explaining the present invention, and is not intended to limit the present invention in any way, and any modifications or alterations to the present invention made in the spirit of the same invention. All should still be included in the scope of the intention of the present invention.
10‧‧‧快閃記憶體之智慧型選擇器10‧‧‧Smart Memory Smart Selector
20‧‧‧SPI從屬單元20‧‧‧SPI slave unit
21‧‧‧主要快閃記憶體21‧‧‧Main flash memory
23‧‧‧備用快閃記憶體23‧‧‧Alternate flash memory
30‧‧‧控制核心單元30‧‧‧Control core unit
40‧‧‧SPI主控單元40‧‧‧SPI master unit
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| TW200912639A (en) * | 2007-09-06 | 2009-03-16 | Ite Tech Inc | Integrated memory control apparatus |
| TW200928717A (en) * | 2007-12-21 | 2009-07-01 | Asustek Comp Inc | Computer system, detecting device and controlling method thereof |
| US8230150B2 (en) * | 2007-11-27 | 2012-07-24 | Microsoft Corporation | Interface protocol and API for a wireless transceiver |
| US8291126B2 (en) * | 2010-03-23 | 2012-10-16 | Spansion Llc | Variable read latency on a serial memory bus |
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| TW200912639A (en) * | 2007-09-06 | 2009-03-16 | Ite Tech Inc | Integrated memory control apparatus |
| US8230150B2 (en) * | 2007-11-27 | 2012-07-24 | Microsoft Corporation | Interface protocol and API for a wireless transceiver |
| TW200928717A (en) * | 2007-12-21 | 2009-07-01 | Asustek Comp Inc | Computer system, detecting device and controlling method thereof |
| US8291126B2 (en) * | 2010-03-23 | 2012-10-16 | Spansion Llc | Variable read latency on a serial memory bus |
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