TWI459529B - Chip package and method for forming the same - Google Patents
Chip package and method for forming the same Download PDFInfo
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Description
本發明係有關於晶片封裝體，且特別是有關於具有穿基底導通結構(through-substrate via，TSV)之晶片封裝體。This invention relates to wafer packages, and more particularly to chip packages having through-substrate vias (TSVs).
近來，業界常於晶片封裝體中形成穿基底導通結構以因應晶片之尺寸縮小化與多功能化。為進一步增進晶片封裝體之功能性，需設法提升與穿基底導通結構連結之導電通路，使晶片封裝體在持續縮小化之餘，仍能具有高密度之導電通路。此外，業界亦亟需增進穿基底導通結構之結構穩定性。Recently, the industry often forms a through-substrate conductive structure in a chip package to reduce the size and multi-function of the wafer. In order to further enhance the functionality of the chip package, it is necessary to improve the conductive path connected to the through-substrate conductive structure, so that the chip package can still have a high-density conductive path while continuing to be reduced. In addition, there is an urgent need in the industry to improve the structural stability of the through-substrate conductive structure.
本發明實施例提供一種晶片封裝體，包括：一基底，具有一上表面及一下表面；複數個導電墊，位於該基底之該下表面之下；一介電層，位於該些導電墊之間；一溝槽，自該基底之該上表面朝該下表面延伸；一孔洞，自該溝槽之一底部朝該基底之該下表面延伸，其中該孔洞之一上側壁傾斜於該基底之該下表面，且該孔洞之一下側壁或一底部露出部分的該些導電墊；以及一導電層，位於該孔洞之中且電性接觸至少一該些導電墊。Embodiments of the present invention provide a chip package including: a substrate having an upper surface and a lower surface; a plurality of conductive pads located under the lower surface of the substrate; and a dielectric layer between the conductive pads a groove extending from the upper surface of the substrate toward the lower surface; a hole extending from a bottom of one of the grooves toward the lower surface of the substrate, wherein an upper sidewall of the hole is inclined to the substrate a lower surface, and a conductive pad on a lower sidewall or a bottom exposed portion of the hole; and a conductive layer located in the hole and electrically contacting at least one of the conductive pads.
本發明一實施例提供一種晶片封裝體的形成方法，包括：提供一基底，具有一上表面及一下表面，其中該 基底包括：複數個導電墊，位於該基底之該下表面之下；以及一介電層，位於該些導電墊之間；自該基底之該上表面移除部分的該基底以形成朝該些導電墊延伸之一孔洞；在形成該孔洞之後，自該基底之該上表面移除部分的該基底以形成朝該基底之該下表面延伸之一溝槽，其中該溝槽與該孔洞連結；於該溝槽之側壁及該孔洞之側壁與底部上形成一絕緣層；移除部分的該絕緣層及部分的該介電層以露出部分的該些導電墊；以及於該溝槽之側壁及該孔洞之側壁與底部上形成一導電層，該導電層電性接觸該些導電墊。An embodiment of the present invention provides a method of forming a chip package, including: providing a substrate having an upper surface and a lower surface, wherein the The substrate includes: a plurality of conductive pads under the lower surface of the substrate; and a dielectric layer between the conductive pads; removing a portion of the substrate from the upper surface of the substrate to form the The conductive pad extends a hole; after forming the hole, a portion of the substrate is removed from the upper surface of the substrate to form a trench extending toward the lower surface of the substrate, wherein the groove is coupled to the hole; Forming an insulating layer on the sidewall of the trench and the sidewall and the bottom of the hole; removing a portion of the insulating layer and a portion of the dielectric layer to expose portions of the conductive pads; and sidewalls of the trench and A conductive layer is formed on the sidewall and the bottom of the hole, and the conductive layer electrically contacts the conductive pads.
本發明一實施例提供一種晶片封裝體的形成方法，包括：提供一基底，具有一第一表面及一第二表面，其中該基底包括：位於該基底之該第一表面之上的複數個導電墊；以及位於該些導電墊之間的一介電層；於該基底之該第一表面之上該些導電墊及該介電層之上設置一承載基底；自該承載基底之一上表面移除部分的該承載基底以形成朝該些導電墊延伸之一孔洞；在形成該孔洞之後，自該承載基底之該上表面移除部分的該承載基底以形成朝該基底延伸之一溝槽，其中該溝槽與該孔洞連結；於該溝槽之側壁及該孔洞之側壁與底部上形成一絕緣層；移除部分的該絕緣層及部分的該介電層以露出部分的該些導電墊；以及於該溝槽之側壁及該孔洞之側壁與底部上形成一導電層，該導電層電性接觸該些導電墊。An embodiment of the present invention provides a method of forming a chip package, comprising: providing a substrate having a first surface and a second surface, wherein the substrate comprises: a plurality of conductive layers on the first surface of the substrate a pad; and a dielectric layer between the conductive pads; a conductive substrate and a carrier substrate disposed on the first surface of the substrate; and an upper surface of the carrier substrate Removing a portion of the carrier substrate to form a hole extending toward the conductive pads; after forming the hole, removing a portion of the carrier substrate from the upper surface of the carrier substrate to form a trench extending toward the substrate The trench is connected to the hole; an insulating layer is formed on the sidewall of the trench and the sidewall and the bottom of the hole; and the insulating layer and a portion of the dielectric layer are removed to expose the conductive portion a conductive layer is formed on the sidewall of the trench and the sidewall and the bottom of the hole, and the conductive layer electrically contacts the conductive pads.
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。The manner of making and using the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many inventive concepts that can be applied in various specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the invention and are not to be construed as a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers.
在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)、噴墨頭(ink printer heads)、或功率模組(power modules)等半導體晶片進行封 裝。In the embodiment of the chip package of the present invention, it can be applied to various electronic components including integrated circuits such as active or passive elements, digital circuits or analog circuits (electronic circuits). Components), for example, related to opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or physical measurements measured by changes in physical quantities such as heat, light, and pressure. Sensor (Physical Sensor). In particular, wafer scale package (WSP) processes can be used for image sensing components, light-emitting diodes (LEDs), solar cells, RF circuits, Accelerators, gyroscopes, micro actuators, surface acoustic wave devices, process sensors, ink printer heads, or power modules Semiconductor chips such as power modules are sealed Installed.
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also applicable to a chip package in which a plurality of wafers having integrated circuits are arranged by a stack to form multi-layer integrated circuit devices.
本發明實施例之晶片封裝體主要係透過分別對多層導電墊之圖案進行設計，使封裝體中所形成之穿基底導電結構(TSV)可同時與多層導電墊電性接觸，可增進結構可靠度外，並增加穿基底導電結構所連結之導電通路。The chip package of the embodiment of the invention mainly designs the pattern of the plurality of conductive pads by respectively, so that the through-substrate conductive structure (TSV) formed in the package can be electrically contacted with the plurality of conductive pads at the same time, thereby improving structural reliability. In addition, the conductive path connected through the conductive structure of the substrate is increased.
第1A-1C圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。如第1A圖所示，提供基底100，其具有上表面100a及下表面100b。基底100例如包括半導體材料或陶瓷材料。在一實施例中，基底100為一半導體晶圓(例如是矽晶圓)而便於進行晶圓級封裝。採用晶圓級封裝來形成晶片封裝體可降低成本並節省製程時間。1A-1C are cross-sectional views showing a process of a chip package in accordance with an embodiment of the present invention. As shown in FIG. 1A, a substrate 100 having an upper surface 100a and a lower surface 100b is provided. The substrate 100 includes, for example, a semiconductor material or a ceramic material. In one embodiment, substrate 100 is a semiconductor wafer (eg, a germanium wafer) for wafer level packaging. Wafer-level packaging to form a chip package reduces cost and saves process time.
在一實施例中，基底100包括導電墊結構110，其位於基底100之下表面100b之下。然在其他實施例中，導電墊結構110可位於基底100之中。導電墊結構110為複數個導電墊之堆疊結構，例如包括彼此間夾置有介電層之數個導電墊。導電墊結構110之詳細結構後續將配合第2A-2C圖所顯示之根據本發明一實施例之晶片封裝 體的局部放大製程剖面圖作說明。在第1A圖之實施例中，導電墊結構110位於基底100之下表面100b之下，且與基底100之下表面100b之間隔有絕緣層102。此外，基底100及導電墊結構110之下可設置有基板106。基板106例如可包括絕緣材料。在一實施例中，基板106為設置於玻璃基板上之間隔層。In an embodiment, the substrate 100 includes a conductive pad structure 110 that is positioned below the lower surface 100b of the substrate 100. In other embodiments, the conductive pad structure 110 can be located within the substrate 100. The conductive pad structure 110 is a stacked structure of a plurality of conductive pads, for example, including a plurality of conductive pads with a dielectric layer interposed therebetween. The detailed structure of the conductive pad structure 110 will be followed by the chip package according to an embodiment of the present invention as shown in FIG. 2A-2C. A partial enlargement process profile of the body is illustrated. In the embodiment of FIG. 1A, the conductive pad structure 110 is located under the lower surface 100b of the substrate 100, and has an insulating layer 102 spaced apart from the lower surface 100b of the substrate 100. In addition, a substrate 106 may be disposed under the substrate 100 and the conductive pad structure 110. Substrate 106 can include, for example, an insulating material. In one embodiment, the substrate 106 is a spacer layer disposed on the glass substrate.
請參照第2A圖，其顯示第1A圖之實施例於區域A處的局部放大剖面圖。在基板106上形成有導電墊110b、介電層113、導電墊110a、及絕緣層102。在一實施例中，導電墊110a之圖案係經特別設計以露出其下之部分的導電墊110b。在一實施例中，導電墊110a具有至少一開口(或溝槽)602，開口602露出介電層113及正下方之導電墊110b。即，在此實施例中，上層導電墊(110a)具有至少一開口(或溝槽)，其露出下層導電墊(110b)。應注意的是，此處之“露出”非指視覺上實質可看見導電墊110b，而是指開口602之正下方與部分的導電墊110b重疊。Please refer to FIG. 2A, which shows a partially enlarged cross-sectional view of the embodiment of FIG. 1A at a region A. A conductive pad 110b, a dielectric layer 113, a conductive pad 110a, and an insulating layer 102 are formed on the substrate 106. In one embodiment, the pattern of conductive pads 110a is specifically designed to expose portions of conductive pads 110b. In one embodiment, the conductive pad 110a has at least one opening (or trench) 602 that exposes the dielectric layer 113 and the conductive pad 110b directly underneath. That is, in this embodiment, the upper conductive pad (110a) has at least one opening (or trench) that exposes the underlying conductive pad (110b). It should be noted that "exposed" herein does not mean that the conductive pad 110b is visually substantially visible, but rather that the portion directly under the opening 602 overlaps with a portion of the conductive pad 110b.
接著，於基底100中形成孔洞，孔洞係自基底100之上表面100a朝下表面100b延伸，且孔洞露出部分的導電墊110a及部分的導電墊110b。在一實施例中，孔洞係於單一蝕刻製程中形成。在另一實施例中，孔洞係分段形成。以下，將舉例說明分段形成露出部分的導電墊110a及部分的導電墊110b之孔洞的形成過程。Next, a hole is formed in the substrate 100, the hole extending from the upper surface 100a of the substrate 100 toward the lower surface 100b, and the hole exposes a portion of the conductive pad 110a and a portion of the conductive pad 110b. In one embodiment, the holes are formed in a single etch process. In another embodiment, the holes are formed in segments. Hereinafter, a process of forming the holes of the conductive pad 110a and the portion of the conductive pad 110b which are formed in the exposed portion will be exemplified.
例如，請參照第1A圖，在此實施例中，自基底100之上表面100a形成第一孔洞108，第一孔洞108朝導電 墊結構110延伸(即，朝導電墊110a延伸)。以第1A圖之實施例為例，第一孔洞108貫穿基底100，並停止於基底100與導電墊結構110之間的絕緣層102上。接著，可選擇性於第一孔洞108之側壁與底部上形成絕緣層104以電性隔離基底100與後續將形成於孔洞中之導電層。For example, referring to FIG. 1A, in this embodiment, a first hole 108 is formed from the upper surface 100a of the substrate 100, and the first hole 108 is electrically conductive. The pad structure 110 extends (ie, extends toward the conductive pad 110a). Taking the embodiment of FIG. 1A as an example, the first hole 108 penetrates through the substrate 100 and stops on the insulating layer 102 between the substrate 100 and the conductive pad structure 110. Next, an insulating layer 104 may be selectively formed on the sidewalls and the bottom of the first hole 108 to electrically isolate the substrate 100 from the conductive layer to be formed in the hole.
接著，如第1B圖所示，自第一孔洞108之底部形成第二孔洞112。即，移除部分的絕緣層104與102以使下方之導電墊結構110露出。此外，第二孔洞112還進一步使導電墊110a與110b露出。請參照第2B圖，顯示第1B圖之實施例於區域A處的局部放大剖面圖。Next, as shown in FIG. 1B, a second hole 112 is formed from the bottom of the first hole 108. That is, portions of the insulating layers 104 and 102 are removed to expose the underlying conductive pad structure 110. In addition, the second holes 112 further expose the conductive pads 110a and 110b. Referring to FIG. 2B, a partially enlarged cross-sectional view of the embodiment of FIG. 1B at area A is shown.
如第2A圖及第2B圖所示，第二孔洞112之形成包括移除導電墊110a之開口602中的絕緣層102與其下之介電層113的一部分。在一實施例中，所形成之第二孔洞112之側壁露出部分的導電墊110a，例如露出導電墊110a之側邊，如第2B圖所示。在一實施例中，所形成之第二孔洞112之底部露出部分的導電墊110b，例如露出導電墊110b之上表面，如第2B圖所示。由於第二孔洞112之形成僅涉及絕緣材質之移除，因此其可於單一蝕刻製程中形成。此外，所選用之蝕刻劑較佳對介電材料或絕緣材料之蝕刻速度大於對金屬材料或導電材料之蝕刻速度。As shown in FIGS. 2A and 2B, the formation of the second hole 112 includes removing the insulating layer 102 in the opening 602 of the conductive pad 110a and a portion of the dielectric layer 113 thereunder. In one embodiment, the sidewalls of the formed second holes 112 expose portions of the conductive pads 110a, such as the sides of the conductive pads 110a, as shown in FIG. 2B. In one embodiment, the bottom of the formed second hole 112 exposes a portion of the conductive pad 110b, for example, the upper surface of the conductive pad 110b, as shown in FIG. 2B. Since the formation of the second hole 112 involves only the removal of the insulating material, it can be formed in a single etching process. In addition, the etchant selected preferably has a higher etching rate for the dielectric material or the insulating material than for the metal material or the conductive material.
如先前所敘述，導電墊110a之圖案係經特別設計以露出其下之部分的導電墊110b。因此，在形成第二孔洞112的過程中，所移除之材料大抵為導電墊110a之開口602中之絕緣材料與下方之介電材料，因而可於單一蝕刻 製程中形成出第二孔洞112。As previously described, the pattern of conductive pads 110a is specifically designed to expose the underlying portions of conductive pads 110b. Therefore, in the process of forming the second hole 112, the removed material is substantially the insulating material in the opening 602 of the conductive pad 110a and the dielectric material underneath, and thus can be etched in a single manner. A second hole 112 is formed in the process.
第6A圖顯示根據本發明一實施例之晶片封裝體的局部上視圖，其僅顯示導電墊110a與110b之相對關係。應注意的是，第6A圖所示之上視圖僅為舉例說明用，非用以限定本發明實施例之實施方式。如第6A圖所示，導電墊110a中具有至少一開口602，其露出下方之導電墊110b。即，在第二孔洞112中露出深度不同之導電墊110a與110b。Figure 6A shows a partial top view of a chip package in accordance with an embodiment of the present invention showing only the relative relationship of conductive pads 110a and 110b. It should be noted that the top view shown in FIG. 6A is for illustrative purposes only and is not intended to limit the embodiments of the embodiments of the present invention. As shown in FIG. 6A, the conductive pad 110a has at least one opening 602 that exposes the underlying conductive pad 110b. That is, the conductive pads 110a and 110b having different depths are exposed in the second holes 112.
接著，請參照第1C圖，於第一孔洞108與第二孔洞112所共同組成之孔洞中形成導電層114。請同時參照第2C圖，其顯示第1C圖之實施例於區域A處的局部放大剖面圖。如第2C圖所示，導電層114延伸進入第二孔洞112中而與導電墊110a及導電墊110b電性接觸。在一實施例中，導電層114可固定於第二孔洞112中而具有較佳之結構穩定度，且導電層114還同時與導電墊110a及導電墊110b接觸，可連結至較多的導電通路。在一實施例中，導電墊110a及導電墊110b係連結至同一電子元件。由於導電層114同時與導電墊110a及導電墊110b電性接觸，可確保連接至該電子元件之導電通路不發生斷路。在另一實施例中，導電墊110a及導電墊110b分別連結至不同的電子元件。不同的電子元件可分別經由導電墊110a及導電墊110b而透過導電層114傳送或接收電子訊號。Next, referring to FIG. 1C, a conductive layer 114 is formed in the hole formed by the first hole 108 and the second hole 112. Please also refer to FIG. 2C, which shows a partially enlarged cross-sectional view of the embodiment of FIG. 1C at region A. As shown in FIG. 2C, the conductive layer 114 extends into the second hole 112 to be in electrical contact with the conductive pad 110a and the conductive pad 110b. In one embodiment, the conductive layer 114 can be fixed in the second hole 112 to have better structural stability, and the conductive layer 114 is also in contact with the conductive pad 110a and the conductive pad 110b, and can be connected to more conductive paths. In one embodiment, the conductive pads 110a and the conductive pads 110b are bonded to the same electronic component. Since the conductive layer 114 is electrically contacted with the conductive pad 110a and the conductive pad 110b at the same time, it is ensured that the conductive path connected to the electronic component does not open. In another embodiment, the conductive pad 110a and the conductive pad 110b are respectively coupled to different electronic components. Different electronic components can transmit or receive electronic signals through the conductive layer 114 via the conductive pads 110a and the conductive pads 110b, respectively.
本發明實施例之導電墊結構110除了可包括兩個導電墊(110a、110b)之外，還可包括其他導電墊。第3A-3C 圖顯示根據本發明另一實施例之晶片封裝體的局部放大製程剖面圖，其中相同或相似之元件將採用相同或相似之標號標示。此外，由於第3圖所示實施例與第2圖之實施例相比，主要是導電墊結構110之設計不同，其形成方式可參照相應於第1A-1C圖之敘述，以下將不再贅述。The conductive pad structure 110 of the embodiment of the present invention may include other conductive pads in addition to the two conductive pads (110a, 110b). 3A-3C The figure shows a partial enlarged process cross-sectional view of a chip package in accordance with another embodiment of the present invention, wherein the same or similar elements will be designated by the same or similar reference numerals. In addition, since the embodiment shown in FIG. 3 is different from the embodiment in FIG. 2, the design of the conductive pad structure 110 is mainly different, and the manner of forming the conductive pad structure 110 can be referred to the description corresponding to FIG. 1A-1C, and will not be described below. .
如第3A圖所示，在一實施例中，晶片封裝體除了包括導電墊110a及導電墊110b之外，更包括至少一導電墊110c，其位於導電墊110a與110b之間的介電層之中。如第3A圖所示，在基板106上形成有導電墊110b、介電層113a、導電墊110c、介電層113b、導電墊110a、及絕緣層102。在一實施例中，導電墊110a之圖案係經特別設計以露出其下之部分的導電墊110c與部分的導電墊110b。在一實施例中，導電墊110a具有至少一開口(或溝槽)602，開口602露出介電層113b、下方之導電墊110c、介電層113a、及下方之導電墊110b。此外，導電墊110c之圖案亦經設計而具有至少一開口(或溝槽)604，開口604露出介電層113a及下方之導電墊110b。As shown in FIG. 3A, in one embodiment, the chip package further includes at least one conductive pad 110c, which is located between the conductive pads 110a and 110b, in addition to the conductive pad 110a and the conductive pad 110b. in. As shown in FIG. 3A, a conductive pad 110b, a dielectric layer 113a, a conductive pad 110c, a dielectric layer 113b, a conductive pad 110a, and an insulating layer 102 are formed on the substrate 106. In one embodiment, the pattern of conductive pads 110a is specifically designed to expose portions of conductive pads 110c and portions of conductive pads 110b. In one embodiment, the conductive pad 110a has at least one opening (or trench) 602 that exposes the dielectric layer 113b, the underlying conductive pad 110c, the dielectric layer 113a, and the underlying conductive pad 110b. In addition, the pattern of the conductive pad 110c is also designed to have at least one opening (or trench) 604 that exposes the dielectric layer 113a and the underlying conductive pad 110b.
換言之，本發明一實施例之晶片封裝體中包括複數個導電墊(例如是導電墊110a、110c、110b)，且這些導電墊中的一上層導電墊具有至少一開口或溝槽，露出這些導電墊中的一下層導電墊。例如，對於導電墊110a(上層導電墊)而言，其具有開口602，其露出導電墊110c及110b(下層導電墊)。相似地，對於導電墊110c(上層導電墊)而言，其具有開口604，其露出導電墊110b(下層導電 墊)。In other words, the chip package of one embodiment of the present invention includes a plurality of conductive pads (eg, conductive pads 110a, 110c, 110b), and an upper conductive pad of the conductive pads has at least one opening or trench to expose the conductive The lower conductive pad in the pad. For example, for the conductive pad 110a (upper conductive pad), it has an opening 602 that exposes the conductive pads 110c and 110b (lower conductive pads). Similarly, for the conductive pad 110c (upper conductive pad), it has an opening 604 that exposes the conductive pad 110b (lower layer conductive pad).
接著，於基底100中形成孔洞，孔洞係自基底100之上表面100a朝下表面100b延伸，且孔洞露出部分的導電墊110a、部分的導電墊110c、及部分的導電墊110b。在一實施例中，孔洞係於單一蝕刻製程中形成。在另一實施例中，孔洞係分段形成。Next, a hole is formed in the substrate 100, and the hole extends from the upper surface 100a of the substrate 100 toward the lower surface 100b, and the hole exposes a portion of the conductive pad 110a, a portion of the conductive pad 110c, and a portion of the conductive pad 110b. In one embodiment, the holes are formed in a single etch process. In another embodiment, the holes are formed in segments.
相似地，在此實施例中，亦可先形成第一孔洞108(如第1A圖所示)，接著於第一孔洞108之底部形成第二孔洞112，如第1B圖所示。第3B圖顯示第二孔洞112附近之局部放大剖面圖。Similarly, in this embodiment, the first hole 108 may be formed first (as shown in FIG. 1A), and then the second hole 112 may be formed at the bottom of the first hole 108, as shown in FIG. 1B. Figure 3B shows a partial enlarged cross-sectional view of the vicinity of the second hole 112.
相似地，在形成第二孔洞112的過程中，所移除之材料大抵為導電墊110a之開口602中之絕緣材料與下方之介電材料，因而可於單一蝕刻製程中形成出第二孔洞112。Similarly, during the formation of the second hole 112, the removed material is substantially the insulating material in the opening 602 of the conductive pad 110a and the underlying dielectric material, so that the second hole 112 can be formed in a single etching process. .
第6B圖顯示根據本發明一實施例之晶片封裝體的局部上視圖，其僅顯示導電墊110a、110b、及110c之相對關係。應注意的是，第6B圖所示之上視圖僅為舉例說明用，非用以限定本發明實施例之實施方式。如第6B圖所示，導電墊110a中具有至少一開口602，其露出下方之導電墊110c及110b。此外，導電墊110c中具有至少一開口604，其露出下方之導電墊110b。即，在第二孔洞112中露出深度不同之導電墊110a、110c、及110b。Figure 6B shows a partial top view of a chip package in accordance with an embodiment of the present invention showing only the relative relationship of the conductive pads 110a, 110b, and 110c. It should be noted that the top view shown in FIG. 6B is for illustrative purposes only and is not intended to limit the embodiments of the embodiments of the present invention. As shown in FIG. 6B, the conductive pad 110a has at least one opening 602 that exposes the underlying conductive pads 110c and 110b. In addition, the conductive pad 110c has at least one opening 604 that exposes the underlying conductive pad 110b. That is, the conductive pads 110a, 110c, and 110b having different depths are exposed in the second holes 112.
相似地，如第3C圖所示，接著形成導電層114，其延伸進入第二孔洞112中而與導電墊110a、110c、及110b電性接觸。在一實施例中，導電層114可固定於第二孔 洞112中而具有較佳之結構穩定度，且導電層114還同時與導電墊110a、110c、及110b接觸，可連結至較多的導電通路。Similarly, as shown in FIG. 3C, a conductive layer 114 is then formed which extends into the second via 112 to be in electrical contact with the conductive pads 110a, 110c, and 110b. In an embodiment, the conductive layer 114 can be fixed to the second hole. The hole 112 has better structural stability, and the conductive layer 114 is also in contact with the conductive pads 110a, 110c, and 110b, and can be connected to more conductive paths.
如上所述，透過對導電墊之圖案設計，可於單一蝕刻製程中形成出同時露出數個導電墊之孔洞，可使後續形成於孔洞中之導電層(穿基底導電結構)所連結之導電通路的數目增加。再者，由於所形成之孔洞之表面輪廓較為粗糙(因具有深度不同之數個導電墊)，可提升導電層與孔洞側壁間之黏著性，因而提升穿基底導電結構之結構穩定度。As described above, through the pattern design of the conductive pad, a hole in which a plurality of conductive pads are simultaneously exposed can be formed in a single etching process, and the conductive path connected to the conductive layer (through the base conductive structure) formed in the hole can be electrically connected. The number has increased. Moreover, since the surface contour of the formed hole is rough (because of several conductive pads having different depths), the adhesion between the conductive layer and the sidewall of the hole can be improved, thereby improving the structural stability of the conductive structure passing through the substrate.
應注意的是，導電墊之圖案設計可有各種形式，不限於第6A-6B圖所述之形式。第6C-6E圖顯示根據本發明數個實施例之晶片封裝體的局部上視圖。同樣地，第6C-6E圖亦僅為舉例說明用，非用以限定本發明實施例之時施方式。It should be noted that the pattern design of the conductive pads can take various forms and is not limited to the form described in Figures 6A-6B. 6C-6E is a partial top plan view of a chip package in accordance with several embodiments of the present invention. Similarly, the 6C-6E diagram is also for illustrative purposes only and is not intended to limit the manner of the embodiments of the present invention.
如第6C圖所示，在一實施例中，導電墊110a具有一矩形開口602，其露出下方之導電墊110c及110b。導電墊110c具有複數個矩形開口604，其露出下方之導電墊110b。As shown in FIG. 6C, in one embodiment, the conductive pad 110a has a rectangular opening 602 that exposes the underlying conductive pads 110c and 110b. The conductive pad 110c has a plurality of rectangular openings 604 that expose the underlying conductive pads 110b.
如第6D圖所示，在另一實施例中，導電墊110a具有一矩形開口602，其露出下方之導電墊110c及110b。導電墊110c具有複數個長方形開口604(或稱溝槽)，其露出下方之導電墊110b。As shown in FIG. 6D, in another embodiment, the conductive pad 110a has a rectangular opening 602 that exposes the underlying conductive pads 110c and 110b. The conductive pad 110c has a plurality of rectangular openings 604 (or grooves) that expose the underlying conductive pads 110b.
如第6E圖所示，在又一實施例中，導電墊110a具有一矩形開口602，其露出下方之導電墊110c及110b。 導電墊110c具有複數個開口604，包括有矩形開口及長方形開口(或稱溝槽)，其露出下方之導電墊110b。如上述，導電墊之開口的形狀、數目、及分佈皆可視需求而調整。As shown in FIG. 6E, in yet another embodiment, the conductive pad 110a has a rectangular opening 602 that exposes the underlying conductive pads 110c and 110b. The conductive pad 110c has a plurality of openings 604 including rectangular openings and rectangular openings (or grooves) that expose the underlying conductive pads 110b. As mentioned above, the shape, number, and distribution of the openings of the conductive pads can be adjusted as needed.
第4A-4B圖顯示根據本發明一實施例之晶片封裝體的局部放大製程剖面圖，且相同或相似之元件將以相同或相似之標號標示。其中，第4A圖所示之結構與第3A圖之實施例相似，主要差異請參照第4B圖。4A-4B are partial enlarged process cross-sectional views of a chip package in accordance with an embodiment of the present invention, and the same or similar elements will be designated by the same or similar reference numerals. The structure shown in FIG. 4A is similar to the embodiment in FIG. 3A, and the main difference is shown in FIG. 4B.
如上述，第二孔洞112之形成包括使用單一蝕刻製程。在一情形下，蝕刻形成第二孔洞112的過程中可能會部分移除兩側之導電墊。如第4B圖所示，部分的導電墊110a與110c在形成第二孔洞112的過程中亦被蝕刻移除。在此情形下，導電墊110a接近孔洞112的部分之厚度係朝遠離孔洞112之方向遞增。相似地，在一實施例中，導電墊110c接近孔洞112的部分之厚度係朝遠離孔洞112之方向遞增。雖然如此，後續於第二孔洞112中形成導電層114時，導電層114仍可電性接觸導電墊110a、110c、及110b。而且，基於部分的導電墊110a與110c被移除，導電層114與導電墊110a及110c之間的接觸面積還可因而增加，如第4B圖所示。As described above, the formation of the second holes 112 includes the use of a single etching process. In one case, the conductive pads on both sides may be partially removed during the etching to form the second holes 112. As shown in FIG. 4B, portions of the conductive pads 110a and 110c are also etched away during the formation of the second holes 112. In this case, the thickness of the portion of the conductive pad 110a that is close to the hole 112 is increased toward the direction away from the hole 112. Similarly, in one embodiment, the thickness of the portion of the conductive pad 110c proximate to the aperture 112 increases in a direction away from the aperture 112. Nonetheless, when the conductive layer 114 is formed in the second hole 112, the conductive layer 114 can still electrically contact the conductive pads 110a, 110c, and 110b. Moreover, the portion-based conductive pads 110a and 110c are removed, and the contact area between the conductive layer 114 and the conductive pads 110a and 110c may thus be increased, as shown in FIG. 4B.
第5圖顯示根據本發明一實施例之晶片封裝體的局部放大剖面圖。相似地，在此實施例中，在形成第二孔洞112之過程中，部分的導電墊110a及110b係被移除。在此情形下，導電墊110a接近孔洞112的部分之厚度係朝遠離孔洞112之方向遞增。相似地，導電墊110b接近 孔洞112的部分之厚度係朝遠離孔洞112之方向遞增。此外，在此實施例中，導電墊110b係經特別設計而具有開口605，其露出下方之基板106。在一實施例中，第二孔洞112可進一步延伸至基板106中。例如，在一實施例中，第二孔洞112可延伸進入基板106之間隔層中。Figure 5 is a partially enlarged cross-sectional view showing a chip package in accordance with an embodiment of the present invention. Similarly, in this embodiment, portions of the conductive pads 110a and 110b are removed during the formation of the second holes 112. In this case, the thickness of the portion of the conductive pad 110a that is close to the hole 112 is increased toward the direction away from the hole 112. Similarly, the conductive pad 110b is close to The thickness of the portion of the hole 112 increases in a direction away from the hole 112. Moreover, in this embodiment, the conductive pad 110b is specifically designed to have an opening 605 that exposes the underlying substrate 106. In an embodiment, the second aperture 112 can extend further into the substrate 106. For example, in one embodiment, the second holes 112 can extend into the spacer layer of the substrate 106.
第7圖顯示根據本發明一實施例之晶片封裝體的剖面圖，相同或相似之元件將以相同或相似之標號標示。在此實施例中，晶片封裝體更包括溝槽702，其自基底100之上表面100a朝下表面100b延伸。溝槽702之底部形成有複數個接觸孔704。接觸孔704露出基底100下之導電墊結構110。導電層114可延著基底100之上表面100a、溝槽702之側壁、接觸孔704之側壁而延伸至導電墊結構110。其中，導電墊結構110可類似於先前所述之實施例而包括數個具有特殊圖案設計之導電墊。導電層114可沿著所形成之孔洞的側壁而與所露出之數個導電墊電性接觸。此外，在此實施例中，基板106可包括透明基板106b及設置於其上之間隔層106a。間隔層106a、基底100、及透明基板106b可圍繞出一空腔。空腔中可設置晶片700，其例如可為(但不限於)感光晶片或發光晶片。Figure 7 is a cross-sectional view of a chip package in accordance with an embodiment of the present invention, and the same or similar elements will be designated by the same or similar reference numerals. In this embodiment, the chip package further includes a trench 702 that extends from the upper surface 100a of the substrate 100 toward the lower surface 100b. A plurality of contact holes 704 are formed at the bottom of the trench 702. The contact hole 704 exposes the conductive pad structure 110 under the substrate 100. The conductive layer 114 may extend to the conductive pad structure 110 along the upper surface 100a of the substrate 100, the sidewall of the trench 702, and the sidewall of the contact hole 704. The conductive pad structure 110 can include a plurality of conductive pads having a special pattern design similar to the previously described embodiments. The conductive layer 114 can be in electrical contact with the exposed conductive pads along the sidewalls of the formed holes. Further, in this embodiment, the substrate 106 may include a transparent substrate 106b and a spacer layer 106a disposed thereon. The spacer layer 106a, the substrate 100, and the transparent substrate 106b may surround a cavity. A wafer 700 may be disposed in the cavity, which may be, for example, but not limited to, a photosensitive wafer or a light emitting wafer.
本發明實施例之晶片封裝體主要係透過分別對多層導電墊之圖案進行設計，使封裝體中所形成之穿基底導電結構(TSV)可同時與多層導電墊電性接觸，可增進結構可靠度外，並增加穿基底導電結構所連結之導電通路。The chip package of the embodiment of the invention mainly designs the pattern of the plurality of conductive pads by respectively, so that the through-substrate conductive structure (TSV) formed in the package can be electrically contacted with the plurality of conductive pads at the same time, thereby improving structural reliability. In addition, the conductive path connected through the conductive structure of the substrate is increased.
第8-13圖顯示根據本發明一實施例之晶片封裝體的 製程剖面圖。如第8圖所示，提供一晶圓1，包括複數個晶片3，例如是CMOS影像感測器晶片，晶片包括一基底5，依區域可分成主動區10A和周邊電路區10B，晶片3具有正面100A及背面100B，主動區10A和周邊電路區10B在正面100A的位置分別設置有影像感測元件7和導電墊結構9。基底5例如包括半導體材料或陶瓷材料。在一實施例中，基底5為一半導體晶圓(例如是矽晶圓)而便於進行晶圓級封裝。採用晶圓級封裝來形成晶片封裝體可降低成本並節省製程時間。8-13 are diagrams showing a chip package according to an embodiment of the present invention. Process profile. As shown in FIG. 8, a wafer 1 is provided, including a plurality of wafers 3, such as CMOS image sensor wafers. The wafer includes a substrate 5, which can be divided into an active region 10A and a peripheral circuit region 10B. The wafer 3 has The front surface 100A and the back surface 100B, the active area 10A and the peripheral circuit area 10B are respectively provided with an image sensing element 7 and a conductive pad structure 9 at the position of the front surface 100A. The substrate 5 includes, for example, a semiconductor material or a ceramic material. In one embodiment, the substrate 5 is a semiconductor wafer (eg, a germanium wafer) for wafer level packaging. Wafer-level packaging to form a chip package reduces cost and saves process time.
在一實施例中，導電墊結構9可由一層金屬構成，或是由複數個導電墊組成之堆疊結構，例如包括彼此間夾置有介電層11之數個導電墊。導電墊結構9之詳細結構後續將配合實施例說明。一般而言，位於晶片正面係覆蓋著一層晶片保護層13，例如是氧化層、氮化層或其複合層，晶片保護層13在導電墊結構的位置上則可選擇是否形成開口，其依後續封裝形式而定。In one embodiment, the conductive pad structure 9 may be composed of a layer of metal or a stacked structure composed of a plurality of conductive pads, for example, including a plurality of conductive pads with the dielectric layer 11 interposed therebetween. The detailed structure of the conductive pad structure 9 will be described later in conjunction with the embodiments. Generally, the front surface of the wafer is covered with a protective layer 13 of a wafer, such as an oxide layer, a nitride layer or a composite layer thereof. The position of the wafer protection layer 13 at the position of the conductive pad structure can be selected to form an opening. Depending on the package form.
請參閱第9圖，接著將上述晶片晶圓1之正面100A接合於承載晶圓17上而形成一接合面，其中在一實施例中，可透過接合層15來接合晶片晶圓1和承載晶圓17，其端視各種晶圓接合技術而定。因此，在一實施例中，導電墊結構9在晶片晶圓1之正面100A與承載晶圓17之間的接合面係包括一中間層19，例如是晶片保護層13及/或接合層15。此時可對晶片晶圓1之背面100B施予薄化製程，以使光線足以自其背面進入影像感測區。Referring to FIG. 9, the front surface 100A of the wafer wafer 1 is bonded to the carrier wafer 17 to form a bonding surface. In an embodiment, the wafer wafer 1 and the carrier crystal are bonded through the bonding layer 15. Round 17, which depends on various wafer bonding techniques. Thus, in one embodiment, the conductive pad structure 9 includes an intermediate layer 19, such as a wafer cap layer 13 and/or a bonding layer 15, at the interface between the front side 100A of the wafer wafer 1 and the carrier wafer 17. At this time, the back surface 100B of the wafer wafer 1 can be subjected to a thinning process so that light is sufficient to enter the image sensing area from the back side thereof.
請參閱第10圖，依序製程為貼合另一承載晶圓23 於晶片晶圓的基底5之背面100B，例如是由透光材料如玻璃等物質構成之晶圓，基底5和承載晶圓23之間可形成一間隔層21，在一實施例中，於基底5之主動區上、承載晶圓23、和間隔層21之間可形成空腔。此時可選擇實施另一薄化製程，以減少承載晶圓17的厚度。Please refer to FIG. 10, in order to fit another carrier wafer 23 The back surface 100B of the substrate 5 of the wafer wafer is, for example, a wafer made of a material such as a light-transmitting material such as glass. A spacer layer 21 may be formed between the substrate 5 and the carrier wafer 23, in one embodiment, on the substrate. A cavity may be formed between the active region of 5, the carrier wafer 23, and the spacer layer 21. At this point, another thinning process can be optionally implemented to reduce the thickness of the carrier wafer 17.
請參閱第11圖，接續於承載晶圓17對應導電墊結構之位置處形成一導通孔25，在本例中，其係選擇蝕刻形成一倒角，角度θ約為大於90度至92度之間，然後順應性形成一絕緣層27，例如是氧化層或是感光性絕緣層、光阻等，以自承載晶圓17延伸進入導通孔25內側壁及底部。Referring to FIG. 11, a via hole 25 is formed at a position corresponding to the conductive pad structure of the carrier wafer 17. In this example, it is selectively etched to form a chamfer, and the angle θ is greater than about 90 degrees to 92 degrees. Between the two, an insulating layer 27, such as an oxide layer or a photosensitive insulating layer, a photoresist or the like, is formed to extend from the carrier wafer 17 into the inner sidewall and the bottom of the via hole 25.
請參閱第12圖，其係顯示實施一暴露導電墊結構9之製程步驟，以於導通孔25之底部形成開口30，在本實施例中，此開口可貫穿兩晶圓間之接合面如中間層19，而停在導電墊結構之上表面及/或通過部份之導電墊結構而連通至晶片絕緣層11，或是進一步地部份或完全穿過基底5而停留在間隔層21上，有關上述製程及其結構將詳如後述。Referring to FIG. 12, it is shown that a process of exposing the conductive pad structure 9 is performed to form an opening 30 at the bottom of the via hole 25. In this embodiment, the opening can penetrate the interface between the two wafers, such as the middle. The layer 19 is stopped on the upper surface of the conductive pad structure and/or communicates to the wafer insulating layer 11 through a portion of the conductive pad structure, or further partially or completely passes through the substrate 5 to stay on the spacer layer 21, The above process and its structure will be described later.
請參閱第13圖，於承載晶圓17表面順應性形成一導電層32如由金屬材料構成，並延伸進入導通孔側壁、底部及開口30中，以接觸導電墊結構而構成一導電路徑。之後，填入封裝保護層34，如由阻銲材料所構成，接著製作電性連接導電層32之銲墊等外部連接元件，進行晶圓切割步驟以完成晶片封裝體之製作(未顯示)。Referring to FIG. 13, a conductive layer 32 is formed on the surface conformance of the carrier wafer 17, such as a metal material, and extends into the via sidewalls, the bottom portion, and the opening 30 to contact the conductive pad structure to form a conductive path. Thereafter, the encapsulating protective layer 34 is filled, such as a solder resist material, and then an external connection member such as a pad electrically connected to the conductive layer 32 is formed, and a wafer dicing step is performed to complete the fabrication of the chip package (not shown).
在另一實施例中，如第14A、14B圖所示，其係顯示 另一種導通孔結構之剖面圖及上視圖。在本例中，承載晶圓17表面會先行利用如蝕刻步驟等方式去除一部份之基底材料而形成一具有既定深度D之溝槽T，在承載晶圓17為一空白晶圓的場合中，由於無電路元件在其中，因此溝槽T的開口、位置或深度彈性較大，溝槽T可形成於涵蓋切割道SC的位置，同時溝槽T的範圍可一次對應多個導電墊結構9，例如是整個邊線區域，接著對溝槽底部利用如蝕刻步驟等方式再去除一部份之基底材料而形成多個具有既定深度D1之導通孔H，其中由於溝槽T可以大幅降低導通孔H之深寬比，因此於導通孔H之底部形成上述開口30之製程難度可以降低。In another embodiment, as shown in Figures 14A and 14B, the display is Another cross-sectional view and top view of the via structure. In this example, the surface of the carrier wafer 17 is first removed by a portion such as an etching step to form a trench T having a predetermined depth D, in the case where the carrier wafer 17 is a blank wafer. Since the circuit, the position or the depth of the trench T is more flexible, the trench T can be formed at a position covering the scribe line SC, and the range of the trench T can correspond to the plurality of conductive pad structures at a time. For example, the entire edge region, and then removing a portion of the base material by using an etching step or the like to form a plurality of via holes H having a predetermined depth D1, wherein the via hole H can be greatly reduced due to the trench T The aspect ratio is such that the process of forming the opening 30 at the bottom of the via hole H can be reduced.
以下說明開口30之製程與多層導電墊結構9之堆疊結構(多層導電墊)。The stacking structure (multilayer conductive pad) of the process of the opening 30 and the multilayer conductive pad structure 9 will be described below.
請參照第15A圖，其顯示第12或14A圖之實施例於開口30及導電墊9之區域處的局部放大剖面圖。在晶片基底5上形成有多層導電墊9A、9B、層間介電層11、及接合面如中間層19。在一實施例中，上層導電墊9A之圖案係經特別設計以露出下層之部分導電墊9B。在一實施例中，上層導電墊9A具有至少一絕緣窗36，絕緣窗36對應正下方之導電墊9B。即，上層導電墊9A係在製程中同步被定義出一開口、缺口或溝槽，並由層間介電層11所填充，在此實施例中，絕緣窗36與部分的下層導電墊9B重疊，且絕緣窗36係於形成導通孔之前或接合承載晶圓17之前形成。Please refer to FIG. 15A, which shows a partially enlarged cross-sectional view of the embodiment of FIG. 12 or 14A at the region of the opening 30 and the conductive pad 9. A plurality of conductive pads 9A, 9B, an interlayer dielectric layer 11, and a bonding surface such as the intermediate layer 19 are formed on the wafer substrate 5. In one embodiment, the pattern of the upper conductive pads 9A is specifically designed to expose portions of the lower conductive pads 9B. In one embodiment, the upper conductive pad 9A has at least one insulating window 36, and the insulating window 36 corresponds to the conductive pad 9B directly below. That is, the upper conductive pad 9A is defined as an opening, a notch or a trench in the process, and is filled by the interlayer dielectric layer 11. In this embodiment, the insulating window 36 overlaps with a portion of the lower conductive pad 9B. And the insulating window 36 is formed before the via holes are formed or before the carrier wafer 17 is bonded.
接著，參照第14A圖所述，於承載晶圓之基底17中 形成導通孔H及絕緣層27後，於導通孔H底部去除部分絕緣層27而形成開口30，其中此步驟可同時或先後地執行以下製程，如第15B圖所示，包括去除中間層19以形成絕緣窗36、及部份層間介電層11以暴露出上層導電墊9A之側壁及下層導電墊9B之表面，例如可利用微影製程及絕緣層對金屬之蝕刻選擇比，選擇適當之蝕刻方式完成上述製程。Next, referring to FIG. 14A, in the substrate 17 carrying the wafer After the via hole H and the insulating layer 27 are formed, a portion of the insulating layer 27 is removed at the bottom of the via hole H to form an opening 30, wherein the step may perform the following processes simultaneously or sequentially, as shown in FIG. 15B, including removing the intermediate layer 19 An insulating window 36 and a portion of the interlayer dielectric layer 11 are formed to expose the sidewalls of the upper conductive pad 9A and the surface of the lower conductive pad 9B. For example, a lithography process and an etching selectivity of the insulating layer to the metal can be selected, and an appropriate etching is selected. The way to complete the above process.
之後如第15C圖所示，形成導電層32以電性連接導電墊結構之一或多層，例如導電層32可同時接觸上層導電墊之側邊及/或下層導電墊之上表面。Thereafter, as shown in FIG. 15C, the conductive layer 32 is formed to electrically connect one or more layers of the conductive pad structure. For example, the conductive layer 32 may simultaneously contact the side of the upper conductive pad and/or the upper surface of the lower conductive pad.
請參閱第16A至16C圖，其係顯示三層之導電墊堆疊結構之製程剖面圖，其包括具有絕緣窗36A之上層導電墊9A，具有絕緣窗36B之中層導電墊9B、及下層導電墊9C。其中絕緣窗36A係大於絕緣窗36B，兩者並對應著下層導電墊9C之上表面。在本實施例中，如第16C圖所示，形成之導電層32可以電性連接導電墊結構之一或多層，例如導電層32可同時接觸上層導電墊9A之側邊、中層導電墊結構9B之上表面及側邊、及/或下層導電墊9C之上表面。Please refer to FIGS. 16A-16C, which are process cross-sectional views showing a three-layer conductive pad stack structure including a conductive pad 9A having an insulating window 36A, a conductive pad 9B having an insulating window 36B, and a lower conductive pad 9C. . The insulating window 36A is larger than the insulating window 36B, and the two correspond to the upper surface of the lower conductive pad 9C. In this embodiment, as shown in FIG. 16C, the formed conductive layer 32 may be electrically connected to one or more layers of the conductive pad structure. For example, the conductive layer 32 may simultaneously contact the side of the upper conductive pad 9A and the middle conductive pad structure 9B. The upper surface and the side edges, and/or the upper surface of the lower conductive pad 9C.
接著，參照第17A至17C圖所述，其係顯示三層之導電墊堆疊結構之製程剖面圖，其與前述實施例之差異在於下層導電墊9C亦包括一絕緣窗36C，其與上層導電墊9A之絕緣窗36A及中層導電墊9B之絕緣窗36B具有對應關係，另下層導電墊9C之絕緣窗36C係小於絕緣窗36A及36B。Next, referring to FIGS. 17A to 17C, which is a process sectional view showing a three-layer conductive pad stack structure, the difference from the foregoing embodiment is that the lower conductive pad 9C also includes an insulating window 36C, which is combined with the upper conductive pad. The insulating window 36A of 9A and the insulating window 36B of the middle conductive pad 9B have a corresponding relationship, and the insulating window 36C of the lower conductive pad 9C is smaller than the insulating windows 36A and 36B.
形成開口30之步驟包括去除中間層19、絕緣窗36A、36B、36C、及部份層間介電層11以暴露出多層導電墊之側壁及部份上表面，例如可利用微影製程及絕緣層對金屬之蝕刻選擇比，選擇適當之蝕刻方式完成上述製程，如此可增加後續導電層32與導電墊堆疊結構之接觸面積，並有利於導電層32之順應性形成。The step of forming the opening 30 includes removing the intermediate layer 19, the insulating windows 36A, 36B, 36C, and a portion of the interlayer dielectric layer 11 to expose the sidewalls and a portion of the upper surface of the plurality of conductive pads, for example, a lithography process and an insulating layer. For the etching selectivity of the metal, the appropriate etching method is selected to complete the above process, which can increase the contact area between the subsequent conductive layer 32 and the conductive pad stack structure, and facilitate the formation of the compliance of the conductive layer 32.
其中依據製程之特性，亦可選擇以間隔層21為阻擋層，進一步去除部分矽基底5而形成開口30A，此開口30A可以是位於矽基底5中或暴露出間隔層21。之後如第17C圖所示，形成導電層32以電性連接導電墊結構之一或多層，或是可同時接觸導電墊之側邊及/或上表面。同時導電層32可自開口30A延伸進入矽基底5，而在一實施例中，於形成導電層32之前，可另形成一絕緣層38於開口30A內，或是例如實施一氧化步驟而於開口30A內之矽基底5上形成氧化層。Depending on the characteristics of the process, the spacer layer 21 may be selected as a barrier layer to further remove a portion of the germanium substrate 5 to form an opening 30A. The opening 30A may be located in the germanium substrate 5 or expose the spacer layer 21. Thereafter, as shown in FIG. 17C, the conductive layer 32 is formed to electrically connect one or more layers of the conductive pad structure, or to simultaneously contact the side and/or the upper surface of the conductive pad. At the same time, the conductive layer 32 can extend from the opening 30A into the 矽 substrate 5. In an embodiment, an insulating layer 38 can be additionally formed in the opening 30A before forming the conductive layer 32, or for example, an oxidation step can be performed at the opening. An oxide layer is formed on the germanium substrate 5 in 30A.
第18A-18G圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。如第18A圖所示，提供基底300，其具有表面300a及300b。基底300例如可為半導體晶圓，如矽晶圓。在一實施例中，基底300上可定義有複數個預定切割道SC，其將基底300劃分成複數個區域。每一區域中，形成有至少一元件區302。在一實施例中，元件區302可包括光電元件，例如是影像感測元件或發光元件。在基底300之表面300a上形成有複數個導電墊結構306，其位於表面300上之絕緣層304(或稱介電層)之中。每一導電墊結構306可包括複數個堆疊的導電墊。這些 堆疊的導電墊可彼此電性連接(例如，透過形成於堆疊導電墊之間的垂直導電結構)。或者，這些堆疊的導電墊可彼此不電性連接。在一實施例中，這些導電墊中之至少其中之一電性連接元件區302。應注意的是，絕緣層304及導電墊結構306之厚度實際上較薄，為了清楚觀察細部結構，圖式中之絕緣層304及導電墊結構306之厚度係經放大而未照實際比例。18A-18G are cross-sectional views showing a process of a chip package in accordance with an embodiment of the present invention. As shown in Fig. 18A, a substrate 300 is provided having surfaces 300a and 300b. Substrate 300 can be, for example, a semiconductor wafer such as a germanium wafer. In an embodiment, a plurality of predetermined scribe lines SC may be defined on the substrate 300, which divide the substrate 300 into a plurality of regions. In each of the regions, at least one component region 302 is formed. In an embodiment, component region 302 can include a photovoltaic component, such as an image sensing component or a light emitting component. A plurality of conductive pad structures 306 are formed on the surface 300a of the substrate 300, which are located in the insulating layer 304 (or dielectric layer) on the surface 300. Each of the conductive pad structures 306 can include a plurality of stacked conductive pads. These ones The stacked conductive pads can be electrically connected to each other (eg, through a vertical conductive structure formed between the stacked conductive pads). Alternatively, the stacked conductive pads can be electrically connected to each other. In one embodiment, at least one of the conductive pads is electrically coupled to the component region 302. It should be noted that the thickness of the insulating layer 304 and the conductive pad structure 306 is actually thin. In order to clearly observe the detailed structure, the thickness of the insulating layer 304 and the conductive pad structure 306 in the drawing are enlarged and not in actual proportion.
接著，於基底300上設置承載基底310。承載基底310與基底300之間可設置有數個間隔層308。間隔層308及承載基底310可於基底300上圍出複數個空腔，每一空腔下可包括有至少一元件區302。間隔層308可覆蓋於導電墊結構306之上。在元件區302中包括光電元件(例如，影像感測元件或發光元件)的實施例中，可選用透明基板(例如，玻璃基板、石英基板、或透明高分子基板)作為承載基底310以利光線進入元件區302或自元件區302發出。Next, a carrier substrate 310 is disposed on the substrate 300. A plurality of spacer layers 308 may be disposed between the carrier substrate 310 and the substrate 300. The spacer layer 308 and the carrier substrate 310 can enclose a plurality of cavities on the substrate 300, and each of the cavities can include at least one component region 302. The spacer layer 308 can overlie the conductive pad structure 306. In an embodiment in which the photo-element (for example, an image sensing element or a light-emitting element) is included in the element region 302, a transparent substrate (for example, a glass substrate, a quartz substrate, or a transparent polymer substrate) may be selected as the carrier substrate 310 to facilitate light. The component area 302 is entered or emitted from the component area 302.
如第18B圖所示，可接著選擇性薄化基底300以利後續製程之進行。例如，可以承載基底310為支撐，自基底300之表面300b薄化基底300。適合的薄化製程例如是機械研磨或化學機械研磨。As shown in FIG. 18B, the substrate 300 can then be selectively thinned to facilitate subsequent processing. For example, the substrate 310 can be supported as a support, and the substrate 300 can be thinned from the surface 300b of the substrate 300. Suitable thinning processes are, for example, mechanical or chemical mechanical polishing.
接著，如第18C圖所示，移除部分的基底300以形成自基底300之表面300b朝導電墊結構306延伸之孔洞312。例如，可採用微影及蝕刻製程形成孔洞312。在一實施例中，孔洞312之側壁大抵垂直於基底300之表面300b。Next, as shown in FIG. 18C, a portion of the substrate 300 is removed to form a hole 312 extending from the surface 300b of the substrate 300 toward the conductive pad structure 306. For example, the holes 312 can be formed using a lithography and etching process. In one embodiment, the sidewalls of the holes 312 are substantially perpendicular to the surface 300b of the substrate 300.
如第18D圖所示，接著移除部分的基底300以形成自基底300之表面300b朝表面300a延伸之凹陷314。在一實施例中，凹陷314的形成方式例如是微影及蝕刻製程。凹陷314可與數個孔洞312重疊。例如，凹陷314可與一切割道SC兩側之不同區域中之孔洞312重疊。凹陷314亦可與切割道SC所劃分之同一區域中之相鄰的孔洞312重疊。例如，凹陷314與孔洞312之關係可類似於第14B圖所示之情形。As shown in Fig. 18D, a portion of the substrate 300 is then removed to form a recess 314 extending from the surface 300b of the substrate 300 toward the surface 300a. In one embodiment, the formation of the recess 314 is, for example, a lithography and etching process. The recess 314 can overlap with the plurality of holes 312. For example, the recess 314 can overlap the aperture 312 in a different region on either side of a scribe lane SC. The recess 314 may also overlap an adjacent hole 312 in the same region divided by the scribe line SC. For example, the relationship of the recess 314 to the aperture 312 can be similar to that shown in Figure 14B.
在一實施例中，由於凹陷314係形成於孔洞312之後，因此在形成凹陷314的過程之中，蝕刻氣體或蝕刻液體會進入孔洞312之中而部分移除基底300。因此，在一實施例中，在形成凹陷314之後，孔洞312將變大，並改以標號312a標示。孔洞312a之側壁係傾斜於基底300之表面300b。或者，孔洞312a之側壁係傾斜於凹陷314之底部。在一實施例中，孔洞312a之開口尺寸朝表面300b之方向遞增。In an embodiment, since the recess 314 is formed behind the hole 312, during the process of forming the recess 314, an etching gas or an etching liquid may enter the hole 312 to partially remove the substrate 300. Thus, in an embodiment, after the recess 314 is formed, the aperture 312 will become larger and will be designated by reference numeral 312a. The sidewall of the hole 312a is inclined to the surface 300b of the substrate 300. Alternatively, the sidewall of the hole 312a is inclined to the bottom of the recess 314. In one embodiment, the opening size of the aperture 312a increases in the direction of the surface 300b.
接著，可於基底300之表面300b上形成絕緣層316。絕緣層316之材質例如包括氧化物、氮化物、氮氧化物、高分子材料、或前述之組合。絕緣層316可以氣相沉積法、熱氧化法、或塗佈法形成。在一實施例中，絕緣層316大抵順應性位於基底300之表面300b、凹陷314之側壁、孔洞312a之側壁及底部上。Next, an insulating layer 316 may be formed on the surface 300b of the substrate 300. The material of the insulating layer 316 includes, for example, an oxide, a nitride, an oxynitride, a polymer material, or a combination thereof. The insulating layer 316 may be formed by a vapor deposition method, a thermal oxidation method, or a coating method. In one embodiment, the insulating layer 316 is substantially conformable to the surface 300b of the substrate 300, the sidewalls of the recess 314, the sidewalls and the bottom of the aperture 312a.
接著，如第18E圖所示，移除孔洞312a底部上之部分的絕緣層316，並接著形成孔洞312b。在一實施例中，可例如以微影及蝕刻製程移除部分的絕緣層304、部分的 導電墊結構306、及部分的間隔層308以形成孔洞312b。在另一實施例中，導電墊結構306中之各導電墊已預先圖案化而具有露出下層導電墊之開口。在此情形下，在形成孔洞312b的過程中，僅需蝕刻絕緣層304而不需蝕刻導電墊。Next, as shown in Fig. 18E, a portion of the insulating layer 316 on the bottom of the hole 312a is removed, and then a hole 312b is formed. In an embodiment, a portion of the insulating layer 304, a portion of which may be removed, for example, by a lithography and etching process. Conductive pad structure 306, and a portion of spacer layer 308 to form holes 312b. In another embodiment, each of the conductive pads in the conductive pad structure 306 has been pre-patterned to have an opening that exposes the underlying conductive pads. In this case, in the process of forming the holes 312b, it is only necessary to etch the insulating layer 304 without etching the conductive pads.
如第18F圖所示，接著於基底300之表面300b上形成圖案化導電層318。導電層318之材質例如包括銅、鋁、鎳、金、鉑、或前述之組合。導電層318之形成方式例如包括物理氣相沉積、化學氣相沉積、塗佈法、電鍍、無電鍍、或前述之組合。As shown in FIG. 18F, a patterned conductive layer 318 is then formed on the surface 300b of the substrate 300. The material of the conductive layer 318 includes, for example, copper, aluminum, nickel, gold, platinum, or a combination thereof. The manner in which the conductive layer 318 is formed includes, for example, physical vapor deposition, chemical vapor deposition, coating, electroplating, electroless plating, or a combination of the foregoing.
導電層318可自基底300之表面300b沿著凹陷314之側壁、孔洞312a之側壁、及孔洞312b之側壁朝導電墊結構306延伸，並與導電墊結構306電性接觸。The conductive layer 318 can extend from the surface 300b of the substrate 300 along the sidewall of the recess 314, the sidewall of the hole 312a, and the sidewall of the hole 312b toward the conductive pad structure 306, and is in electrical contact with the conductive pad structure 306.
應注意的是，雖然第18F圖之實施例中，導電層318係電性接觸三層的導電墊，並穿過絕緣層304而延伸進入間隔層308之中而直接接觸間隔層308，但本發明實施例不限於此。本發明實施例之孔洞312b不限於延伸進入間隔層308之中。本發明實施例之導電層318與導電墊結構306亦可具有類似於第2C圖、第3C圖、或第4B圖所示之結構。此外，導電墊結構306亦可有許多其他變化。例如，導電墊結構306可具有類似於第6A-6E圖所示之結構。It should be noted that, in the embodiment of FIG. 18F, the conductive layer 318 is electrically contacted with the three conductive pads and extends through the insulating layer 304 into the spacer layer 308 to directly contact the spacer layer 308. The embodiment of the invention is not limited thereto. The aperture 312b of the embodiment of the invention is not limited to extending into the spacer layer 308. The conductive layer 318 and the conductive pad structure 306 of the embodiment of the present invention may also have a structure similar to that shown in FIG. 2C, FIG. 3C, or FIG. 4B. In addition, the conductive pad structure 306 can have many other variations. For example, the conductive pad structure 306 can have a structure similar to that shown in Figures 6A-6E.
請繼續參照第18F圖，可接著於基底300之表面300b上形成防銲層320。在一實施例中，防銲層320可具有露出導電層318之開口(未顯示)，並可於露出的導電層318 上形成導電結構(未顯示)，例如銲球。在一實施例中，由於凹陷314與孔洞(312a及312b)具有傾斜的側壁，因此用以形成防銲層320之材料可較輕易地填入孔洞之中。在一實施例中，防銲層320大抵完全填滿凹陷314及孔洞(312a及312b)而不具有空隙或氣泡形成於防銲層320之中。Referring to FIG. 18F, a solder resist layer 320 may be formed on the surface 300b of the substrate 300. In an embodiment, the solder resist layer 320 may have an opening (not shown) exposing the conductive layer 318, and may be exposed to the conductive layer 318. A conductive structure (not shown), such as a solder ball, is formed thereon. In one embodiment, since the recess 314 and the holes (312a and 312b) have inclined side walls, the material used to form the solder resist 320 can be more easily filled into the holes. In one embodiment, the solder resist layer 320 substantially completely fills the recesses 314 and the holes (312a and 312b) without voids or bubbles formed in the solder resist layer 320.
接著，沿著預定切割道SC切割第18F圖所示之結構而形成複數個彼此分離的晶片封裝體，如第18G圖所示。Next, the structure shown in Fig. 18F is cut along the predetermined scribe line SC to form a plurality of chip packages separated from each other as shown in Fig. 18G.
第19A-19F圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。如第19A圖所示，提供基底400，其具有表面400a及400b。基底400例如可為半導體晶圓，如矽晶圓。在一實施例中，基底400上可定義有複數個預定切割道SC，其將基底400劃分成複數個區域。每一區域中，形成有至少一元件區402。在一實施例中，元件區402可包括光電元件，例如是影像感測元件或發光元件。在基底400之表面400a上形成有複數個導電墊結構406，其位於表面400a上之絕緣層404(或稱介電層)之中。每一導電墊結構406可包括複數個堆疊的導電墊。這些堆疊的導電墊可彼此電性連接(例如，透過形成於堆疊導電墊之間的垂直導電結構)。或者，這些堆疊的導電墊可彼此不電性連接。在一實施例中，這些導電墊中之至少其中之一電性連接元件區402。應注意的是，絕緣層404及導電墊結構406之厚度實際上較薄，為了清楚觀察細部結構，圖式中之絕緣層404及導電墊結構406之厚度係經放大而未照實際比例。19A-19F are cross-sectional views showing a process of a chip package in accordance with an embodiment of the present invention. As shown in Fig. 19A, a substrate 400 is provided having surfaces 400a and 400b. Substrate 400 can be, for example, a semiconductor wafer such as a germanium wafer. In an embodiment, a plurality of predetermined scribe lines SC may be defined on the substrate 400 that divide the substrate 400 into a plurality of regions. In each of the regions, at least one component region 402 is formed. In an embodiment, component region 402 can include a photovoltaic component, such as an image sensing component or a light emitting component. A plurality of conductive pad structures 406 are formed on the surface 400a of the substrate 400, which are located in the insulating layer 404 (or dielectric layer) on the surface 400a. Each of the conductive pad structures 406 can include a plurality of stacked conductive pads. The stacked conductive pads can be electrically connected to each other (eg, through a vertical conductive structure formed between the stacked conductive pads). Alternatively, the stacked conductive pads can be electrically connected to each other. In one embodiment, at least one of the conductive pads is electrically coupled to the component region 402. It should be noted that the thickness of the insulating layer 404 and the conductive pad structure 406 is actually thin. In order to clearly observe the detailed structure, the thickness of the insulating layer 404 and the conductive pad structure 406 in the drawing are enlarged and not in actual proportion.
接著，於基底400之表面400a上設置承載基底407。承載基底407例如是透過黏著層(未顯示)或其他型式之鍵結而固定於基底400上之絕緣層404之上。在一實施例中，承載基底407之尺寸與形狀大抵相同於其下之基底400。在一實施例中，承載基底407為一半導體晶圓，如矽晶圓。Next, a carrier substrate 407 is disposed on the surface 400a of the substrate 400. The carrier substrate 407 is secured to the insulating layer 404 on the substrate 400, for example, by an adhesive layer (not shown) or other type of bonding. In one embodiment, the carrier substrate 407 is substantially the same size and shape as the substrate 400 underneath. In one embodiment, the carrier substrate 407 is a semiconductor wafer, such as a germanium wafer.
如第19B圖所示，以承載基底407為支撐，自基底400之表面400b薄化基底400。適合的薄化製程例如是機械研磨或化學機械研磨。As shown in FIG. 19B, the substrate 400 is thinned from the surface 400b of the substrate 400 with the carrier substrate 407 as a support. Suitable thinning processes are, for example, mechanical or chemical mechanical polishing.
接著，於基底400上設置另一承載基底410。承載基底410與基底400之間可設置有數個間隔層408。間隔層408及承載基底410可於基底400上圍出複數個空腔，每一空腔下可包括有至少一元件區402。間隔層408可覆蓋於導電墊結構406之上。在元件區402中包括光電元件(例如，影像感測元件或發光元件)的實施例中，可選用透明基板(例如，玻璃基板、石英基板、或透明高分子基板)作為承載基底410以利光線進入元件區402或自元件區402發出。此外，由於基底400已經薄化，因此光線進入或輸出時僅需經過透明基板(承載基底410)及薄化後的基底400而不需經過絕緣層404及導電墊結構406，光線之進入或輸出可更為順利。Next, another carrier substrate 410 is disposed on the substrate 400. A plurality of spacer layers 408 may be disposed between the carrier substrate 410 and the substrate 400. The spacer layer 408 and the carrier substrate 410 can enclose a plurality of cavities on the substrate 400, and each of the cavities can include at least one component region 402. The spacer layer 408 can overlie the conductive pad structure 406. In an embodiment in which the photocell (for example, an image sensing component or a light emitting component) is included in the element region 402, a transparent substrate (for example, a glass substrate, a quartz substrate, or a transparent polymer substrate) may be selected as the carrier substrate 410 to facilitate light. Entry into component area 402 or from component area 402. In addition, since the substrate 400 has been thinned, the light enters or outputs only through the transparent substrate (the carrier substrate 410) and the thinned substrate 400 without passing through the insulating layer 404 and the conductive pad structure 406, and the light enters or outputs. It can be smoother.
接著，如第19C圖所示，在一實施例中，改以承載基底410為支撐，自承載基底407之上表面移除部分的承載基底407(例如，可採用微影及蝕刻製程)以形成自承載基底407之上表面朝導電墊結構406延伸之孔洞。在 一實施例中，所形成之孔洞(未顯示)之側壁大抵垂直於承載基底407之上表面。Next, as shown in FIG. 19C, in an embodiment, the carrier substrate 410 is supported, and a portion of the carrier substrate 407 is removed from the upper surface of the carrier substrate 407 (for example, a lithography and etching process may be employed) to form A hole extending from the upper surface of the carrier substrate 407 toward the conductive pad structure 406. in In one embodiment, the sidewalls of the formed holes (not shown) are substantially perpendicular to the upper surface of the carrier substrate 407.
接著，移除部分的承載基底407以形成自承載基底407之上表面朝基底400延伸之凹陷414。在一實施例中，凹陷414的形成方式例如是微影及蝕刻製程。凹陷414可與數個孔洞重疊。例如，凹陷414可與一切割道SC兩側之不同區域中之孔洞重疊。凹陷414亦可與切割道SC所劃分之同一區域中之相鄰的孔洞重疊。例如，凹陷414與孔洞之關係可類似於第14B圖所示之情形。Next, a portion of the carrier substrate 407 is removed to form a recess 414 that extends from the upper surface of the carrier substrate 407 toward the substrate 400. In one embodiment, the formation of the recess 414 is, for example, a lithography and etching process. The recess 414 can overlap with a plurality of holes. For example, the recess 414 can overlap a hole in a different region on both sides of a scribe line SC. The recess 414 may also overlap an adjacent hole in the same region divided by the scribe line SC. For example, the relationship of the recess 414 to the hole can be similar to that shown in Figure 14B.
在一實施例中，由於凹陷414係形成於上述孔洞之後，因此在形成凹陷414的過程之中，蝕刻氣體或蝕刻液體會進入孔洞之中而部分移除承載基底407。因此，在一實施例中，在形成凹陷414之後，孔洞將變大，並以標號412a標示。孔洞412a之側壁係傾斜於承載基底407之上表面。或者，孔洞412a之側壁係傾斜於凹陷414之底部。在一實施例中，孔洞412a之開口尺寸朝承載基底407之上表面之方向遞增。In an embodiment, since the recess 414 is formed after the hole, an etching gas or an etching liquid may enter the hole to partially remove the carrier substrate 407 during the process of forming the recess 414. Thus, in an embodiment, after forming the recess 414, the hole will become larger and designated by reference numeral 412a. The sidewall of the hole 412a is inclined to the upper surface of the carrier substrate 407. Alternatively, the sidewall of the aperture 412a is inclined to the bottom of the recess 414. In one embodiment, the opening size of the aperture 412a increases in the direction of the upper surface of the carrier substrate 407.
接著，可於承載基底407之上表面上形成絕緣層416。絕緣層416之材質例如包括氧化物、氮化物、氮氧化物、高分子材料、或前述之組合。絕緣層416可以氣相沉積法、熱氧化法、或塗佈法形成。在一實施例中，絕緣層416大抵順應性位於承載基底407之上表面、凹陷414之側壁、孔洞412a之側壁及底部上。Next, an insulating layer 416 may be formed on the upper surface of the carrier substrate 407. The material of the insulating layer 416 includes, for example, an oxide, a nitride, an oxynitride, a polymer material, or a combination thereof. The insulating layer 416 may be formed by a vapor deposition method, a thermal oxidation method, or a coating method. In one embodiment, the insulating layer 416 is substantially conformable on the upper surface of the carrier substrate 407, the sidewalls of the recess 414, the sidewalls and the bottom of the aperture 412a.
接著，如第19D圖所示，移除孔洞312a底部上之部分的絕緣層416，並接著形成孔洞412b。在一實施例中， 可例如以微影及蝕刻製程移除部分的絕緣層404、部分的導電墊結構406、及部分的間隔層408以形成孔洞412b。在另一實施例中，導電墊結構406中之各導電墊已預先圖案化而具有露出下層導電墊之開口。在此情形下，在形成孔洞412b的過程中，僅需蝕刻絕緣層404而不需蝕刻導電墊。Next, as shown in Fig. 19D, a portion of the insulating layer 416 on the bottom of the hole 312a is removed, and then a hole 412b is formed. In an embodiment, A portion of the insulating layer 404, a portion of the conductive pad structure 406, and a portion of the spacer layer 408 can be removed, for example, by a lithography and etching process to form the holes 412b. In another embodiment, each of the conductive pads in the conductive pad structure 406 has been pre-patterned to have an opening that exposes the underlying conductive pads. In this case, in the process of forming the holes 412b, it is only necessary to etch the insulating layer 404 without etching the conductive pads.
如第19D圖所示，在一實施例中，可選擇性於孔洞412b之底部及部分側壁上形成圖案化絕緣層417。絕緣層417覆蓋原於孔洞412b中所露出的基底400。絕緣層417不覆蓋導電墊結構406。As shown in FIG. 19D, in an embodiment, a patterned insulating layer 417 may be selectively formed on the bottom portion and a portion of the sidewalls of the hole 412b. The insulating layer 417 covers the substrate 400 originally exposed in the holes 412b. The insulating layer 417 does not cover the conductive pad structure 406.
接著，如第19E圖所示，於承載基底407之上表面上形成圖案化導電層418。導電層418之材質例如包括銅、鋁、鎳、金、鉑、或前述之組合。導電層418之形成方式例如包括物理氣相沉積、化學氣相沉積、塗佈法、電鍍、無電鍍、或前述之組合。Next, as shown in FIG. 19E, a patterned conductive layer 418 is formed on the upper surface of the carrier substrate 407. The material of the conductive layer 418 includes, for example, copper, aluminum, nickel, gold, platinum, or a combination thereof. The formation of the conductive layer 418 includes, for example, physical vapor deposition, chemical vapor deposition, coating, electroplating, electroless plating, or a combination of the foregoing.
導電層418可自承載基底407之上表面沿著凹陷414之側壁、孔洞412a之側壁、及孔洞412b之側壁朝導電墊結構406延伸，並與導電墊結構406電性接觸。The conductive layer 418 can extend from the upper surface of the carrier substrate 407 along the sidewall of the recess 414, the sidewall of the hole 412a, and the sidewall of the hole 412b toward the conductive pad structure 406, and is in electrical contact with the conductive pad structure 406.
應注意的是，雖然第19E圖之實施例中，導電層418係電性接觸三層的導電墊，並穿過絕緣層404而延伸進入間隔層408之中而直接接觸間隔層408，但本發明實施例不限於此。本發明實施例之孔洞412b不限於延伸進入間隔層408之中。本發明實施例之導電層418與導電墊結構406亦可具有類似於第2C圖、第3C圖、或第4B圖所示之結構。此外，導電墊結構406亦可有許多其他 變化。例如，導電墊結構406可具有類似於第6A-6E圖所示之結構。It should be noted that, in the embodiment of FIG. 19E, the conductive layer 418 is electrically contacted with the three conductive pads and extends through the insulating layer 404 into the spacer layer 408 to directly contact the spacer layer 408. The embodiment of the invention is not limited thereto. The aperture 412b of the embodiment of the present invention is not limited to extend into the spacer layer 408. The conductive layer 418 and the conductive pad structure 406 of the embodiment of the present invention may also have a structure similar to that shown in FIG. 2C, FIG. 3C, or FIG. 4B. In addition, the conductive pad structure 406 can have many other Variety. For example, the conductive pad structure 406 can have a structure similar to that shown in Figures 6A-6E.
請繼續參照第19E圖，可接著於承載基底407之上表面上形成防銲層420。在一實施例中，防銲層420可具有露出導電層418之開口(未顯示)，並可於露出的導電層418上形成導電結構(未顯示)，例如銲球。在一實施例中，由於凹陷414與孔洞(412a及412b)具有傾斜的側壁，因此用以形成防銲層420之材料可較輕易地填入孔洞之中。在一實施例中，防銲層420大抵完全填滿凹陷414及孔洞(412a及412b)而不具有空隙或氣泡形成於防銲層420之中。Referring to FIG. 19E, a solder resist layer 420 may be formed on the upper surface of the carrier substrate 407. In an embodiment, the solder mask layer 420 can have openings (not shown) that expose the conductive layer 418 and can form a conductive structure (not shown), such as solder balls, on the exposed conductive layer 418. In one embodiment, since the recess 414 and the holes (412a and 412b) have inclined side walls, the material used to form the solder resist layer 420 can be more easily filled into the holes. In one embodiment, the solder resist layer 420 is substantially completely filled with the recesses 414 and the holes (412a and 412b) without voids or bubbles formed in the solder resist layer 420.
接著，沿著預定切割道SC切割第19E圖所示之結構而形成複數個彼此分離的晶片封裝體，如第19F圖所示。Next, the structure shown in Fig. 19E is cut along the predetermined scribe line SC to form a plurality of chip packages separated from each other as shown in Fig. 19F.
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.
1‧‧‧晶圓1‧‧‧ wafer
3‧‧‧晶片3‧‧‧ wafer
5‧‧‧基底5‧‧‧Base
7‧‧‧影像感測元件7‧‧‧Image sensing components
9‧‧‧導電墊結構9‧‧‧Electrical pad structure
9A、9B、9C‧‧‧導電墊9A, 9B, 9C‧‧‧ conductive pads
10A‧‧‧主動區10A‧‧‧Active Area
10B‧‧‧周邊電路區10B‧‧‧ peripheral circuit area
11‧‧‧介電層11‧‧‧Dielectric layer
13‧‧‧保護層13‧‧‧Protective layer
15‧‧‧接合層15‧‧‧Connection layer
17‧‧‧承載晶圓17‧‧‧Loading wafer
19‧‧‧中間層19‧‧‧Intermediate
21‧‧‧間隔層21‧‧‧ spacer
23‧‧‧承載晶圓23‧‧‧Loading wafer
25‧‧‧穿孔25‧‧‧Perforation
27‧‧‧絕緣層27‧‧‧Insulation
30、30A‧‧‧開口30, 30A‧‧‧ openings
32‧‧‧導電層32‧‧‧ Conductive layer
34‧‧‧保護層34‧‧‧Protective layer
36、36A、36B、36C‧‧‧絕緣窗36, 36A, 36B, 36C‧‧‧ insulated windows
100A‧‧‧正面100A‧‧‧ positive
100B‧‧‧背面100B‧‧‧back
100‧‧‧基底100‧‧‧Base
100a、100b‧‧‧表面100a, 100b‧‧‧ surface
102、104‧‧‧絕緣層102, 104‧‧‧Insulation
106‧‧‧基板106‧‧‧Substrate
106a‧‧‧間隔層106a‧‧‧ spacer
106b‧‧‧透明基板106b‧‧‧Transparent substrate
108、112‧‧‧孔洞108, 112‧‧‧ holes
110‧‧‧導電墊結構110‧‧‧Electrical pad structure
110a、110b、110c‧‧‧導電墊110a, 110b, 110c‧‧‧ conductive pads
113、113a、113b‧‧‧介電層113, 113a, 113b‧‧‧ dielectric layer
114‧‧‧導電層114‧‧‧ Conductive layer
300‧‧‧基底300‧‧‧Base
300a、300b‧‧‧表面300a, 300b‧‧‧ surface
302‧‧‧元件區302‧‧‧Component area
304‧‧‧絕緣層304‧‧‧Insulation
306‧‧‧導電墊結構306‧‧‧Electrical pad structure
308‧‧‧間隔層308‧‧‧ spacer
310‧‧‧承載基底310‧‧‧bearing substrate
312、312a、312b‧‧‧孔洞312, 312a, 312b‧‧ holes
314‧‧‧凹陷314‧‧‧ dent
316‧‧‧絕緣層316‧‧‧Insulation
318‧‧‧導電層318‧‧‧ Conductive layer
320‧‧‧防銲層320‧‧‧ solder mask
400‧‧‧基底400‧‧‧Base
400a、400b‧‧‧表面400a, 400b‧‧‧ surface
402‧‧‧元件區402‧‧‧Component area
404‧‧‧絕緣層404‧‧‧Insulation
406‧‧‧導電墊結構406‧‧‧Electrical pad structure
407‧‧‧承載基底407‧‧‧bearing substrate
408‧‧‧間隔層408‧‧‧ spacer
410‧‧‧承載基底410‧‧‧bearing substrate
412a、412b‧‧‧孔洞412a, 412b‧‧‧ holes
414‧‧‧凹陷414‧‧‧ dent
416、417‧‧‧絕緣層416, 417‧‧‧ insulation
418‧‧‧導電層418‧‧‧ Conductive layer
420‧‧‧防銲層420‧‧‧ solder mask
602、604、606‧‧‧開口602, 604, 606‧‧‧ openings
700‧‧‧晶片700‧‧‧ wafer
702‧‧‧溝槽702‧‧‧ trench
704‧‧‧接觸孔704‧‧‧Contact hole
A‧‧‧區域A‧‧‧ area
D、D1‧‧‧深度D, D1‧‧ depth
H‧‧‧穿孔H‧‧‧Perforation
SC‧‧‧切割道SC‧‧‧Cut Road
T‧‧‧溝槽T‧‧‧ trench
θ‧‧‧角度Θ‧‧‧ angle
第1A-1C圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。1A-1C are cross-sectional views showing a process of a chip package in accordance with an embodiment of the present invention.
第2A-2C圖顯示根據本發明一實施例之晶片封裝體的局部放大製程剖面圖。2A-2C are cross-sectional views showing a partially enlarged process of a chip package in accordance with an embodiment of the present invention.
第3A-3C圖顯示根據本發明一實施例之晶片封裝體的局部放大製程剖面圖。3A-3C are cross-sectional views showing a partially enlarged process of a chip package in accordance with an embodiment of the present invention.
第4A-4B圖顯示根據本發明一實施例之晶片封裝體的局部放大製程剖面圖。4A-4B are cross-sectional views showing a partially enlarged process of a chip package in accordance with an embodiment of the present invention.
第5圖顯示根據本發明一實施例之晶片封裝體的局部放大剖面圖。Figure 5 is a partially enlarged cross-sectional view showing a chip package in accordance with an embodiment of the present invention.
第6A-6E圖顯示根據本發明實施例之晶片封裝體的局部上視圖。6A-6E are partial top views of a chip package in accordance with an embodiment of the present invention.
第7圖顯示根據本發明一實施例之晶片封裝體的剖面圖。Figure 7 is a cross-sectional view showing a chip package in accordance with an embodiment of the present invention.
第8-13圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。8-13 are cross-sectional views showing a process of a chip package in accordance with an embodiment of the present invention.
第14A-14B圖顯示根據本發明另一實施例之晶片封裝體的製程剖面圖。14A-14B are cross-sectional views showing a process of a chip package in accordance with another embodiment of the present invention.
第15A-15C圖顯示根據本發明一實施例之晶片封裝體的局部放大製程剖面圖。15A-15C are cross-sectional views showing a partially enlarged process of a chip package in accordance with an embodiment of the present invention.
第16A-16C圖顯示根據本發明一實施例之晶片封裝體的局部放大製程剖面圖。16A-16C are cross-sectional views showing a partially enlarged process of a chip package in accordance with an embodiment of the present invention.
第17A-17C圖顯示根據本發明一實施例之晶片封裝體的局部放大製程剖面圖。17A-17C are cross-sectional views showing a partially enlarged process of a chip package in accordance with an embodiment of the present invention.
第18A-18G圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。18A-18G are cross-sectional views showing a process of a chip package in accordance with an embodiment of the present invention.
第19A-19F圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。19A-19F are cross-sectional views showing a process of a chip package in accordance with an embodiment of the present invention.
400‧‧‧基底400‧‧‧Base
400a、400b‧‧‧表面400a, 400b‧‧‧ surface
402‧‧‧元件區402‧‧‧Component area
404‧‧‧絕緣層404‧‧‧Insulation
406‧‧‧導電墊結構406‧‧‧Electrical pad structure
407‧‧‧承載基底407‧‧‧bearing substrate
408‧‧‧間隔層408‧‧‧ spacer
410‧‧‧承載基底410‧‧‧bearing substrate
412a、412b‧‧‧孔洞412a, 412b‧‧‧ holes
414‧‧‧凹陷414‧‧‧ dent
416、417‧‧‧絕緣層416, 417‧‧‧ insulation
418‧‧‧導電層418‧‧‧ Conductive layer
420‧‧‧防銲層420‧‧‧ solder mask
Claims (19)
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| TW100125763A TWI459529B (en) | 2011-07-21 | 2011-07-21 | Chip package and method for forming the same |
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| TW100125763A TWI459529B (en) | 2011-07-21 | 2011-07-21 | Chip package and method for forming the same |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200950040A (en) * | 2008-05-21 | 2009-12-01 | Xintec Inc | Electronics device package and method for fabricating thereof |
| TW200950132A (en) * | 2008-05-23 | 2009-12-01 | Xintec Inc | Light emitting device package structure and fabricating method thereof |
| TW201027641A (en) * | 2009-01-06 | 2010-07-16 | Xintec Inc | Electronic device package and fabrication method thereof |
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| TW200950040A (en) * | 2008-05-21 | 2009-12-01 | Xintec Inc | Electronics device package and method for fabricating thereof |
| TW200950132A (en) * | 2008-05-23 | 2009-12-01 | Xintec Inc | Light emitting device package structure and fabricating method thereof |
| TW201027641A (en) * | 2009-01-06 | 2010-07-16 | Xintec Inc | Electronic device package and fabrication method thereof |
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