TWI459512B - Vertically packaged mosfet and ic power devices as integrated module using 3d interconnected laminates - Google Patents

Vertically packaged mosfet and ic power devices as integrated module using 3d interconnected laminates Download PDF

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TWI459512B
TWI459512B TW095147535A TW95147535A TWI459512B TW I459512 B TWI459512 B TW I459512B TW 095147535 A TW095147535 A TW 095147535A TW 95147535 A TW95147535 A TW 95147535A TW I459512 B TWI459512 B TW I459512B
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laminate
package module
package
semiconductor wafer
solder
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TW095147535A
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TW200725830A (en
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Sun Ming
Se Ho Yueh
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Alpha & Omega Semiconductor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Description

使用相互連接的三維層片將垂直封裝的MOSFET和積體電路功率器件構建成集成模組Vertically packaged MOSFET and integrated circuit power devices are built into integrated modules using interconnected 3D layers

本發明一般地涉及封裝積體電路的工藝和結構，例如功率MOSFETs和諸如功率IC的其他類型積體電路。更具體地，本發明涉及一種新的改進型方法和結構，能使MOSFET和IC器件的封裝過程簡化和合理，從而得到一個高度集成的模組，降低生產成本，提高封裝能力，增強封裝的可靠性。The present invention generally relates to processes and structures for packaging integrated circuits, such as power MOSFETs and other types of integrated circuits such as power ICs. More particularly, the present invention relates to a new and improved method and structure for simplifying and rationalizing the packaging process of MOSFETs and IC devices, thereby obtaining a highly integrated module, reducing production cost, improving package capability, and enhancing package reliability. Sex.

目前已有的封裝技術和通常用來封裝諸如功率MOSFET器件的垂直半導體器件的結構仍然面臨著普遍使用引線框架或陶瓷基板的問題，在引線框架的金屬線與支援電子器件和引線框架的印刷電路板(PCB)之間存在著熱失配。由於熱失配，焊接接縫的失敗率極高。另外，常規的機械結構具有多個缺點，例如矽晶片引線框架系統的不勻性，因引線框架的限制矽晶片尺寸的有限性，以及插板層次安裝期間應力吸收的局限性。當前的封裝技術還存在著裝配接受的難題，常常造成極高的裝配成本，且難於取代常規的大量封裝件，例如SO(Small Outline Package，小尺寸外型封裝)、TO(Thin Outline Package，薄型外型封裝)和TSSOP(Thin Shrink Small Outline Package，薄型縮小尺寸外型封裝)系列，以降低封裝成本。這些問題都是因這些封裝件實際上既不能用引線框架型封裝技術也不能用正規的表面安裝封裝技術進行徹底的封裝而產生的。這些封 裝件還在插板層次階段帶來了另一個棘手的問題，因為在預安裝和測試過程期間，操作是在封裝件與PCB之間的焊接接縫處不可見的狀態下進行的。在這些封裝技術中，使用引線框架也進一步將封裝件限制成單個的矽晶片結構，因為引線框架不具有能夠適應多晶片結構的靈活性，這種多晶片結構要麼是單個模組要麼是由幾個模組構成的元件。The current packaging technology and the structure commonly used to package vertical semiconductor devices such as power MOSFET devices still face the problem of the widespread use of lead frames or ceramic substrates, the metal lines in the lead frame and the printed circuits supporting the electronics and lead frames. There is a thermal mismatch between the plates (PCB). Due to the thermal mismatch, the failure rate of the welded joint is extremely high. In addition, conventional mechanical structures have a number of disadvantages, such as the unevenness of the tantalum wafer leadframe system, the limitations of the leadframe, the limited size of the wafer, and the limitations of stress absorption during plug-in layer mounting. The current packaging technology still has the problem of assembly acceptance, often resulting in extremely high assembly costs, and it is difficult to replace a large number of conventional packages, such as SO (Small Outline Package), TO (Thin Outline Package, thin type). The external package) and the TSSOP (Thin Shrink Small Outline Package) series to reduce the cost of packaging. These problems are caused by the fact that these packages can not be completely packaged by either lead frame type packaging technology or formal surface mount packaging technology. These seals The assembly also poses another thorny problem in the plug-in stage because during the pre-installation and testing process, the operation is performed in a state where the solder joint between the package and the PCB is not visible. In these packaging techniques, the use of leadframes further limits the package to a single germanium wafer structure because the leadframe does not have the flexibility to accommodate multi-wafer structures that are either a single module or a few The components of the module.

Joshi在專利6,133,634中公開了一種第1A圖所示的半導體封裝件，矽晶片102與載體106連接，載體106具有大體上圍繞矽晶片102的空腔，空腔尺寸的設計應該是使空腔的深度基本等於矽晶片102的厚度加晶粒安裝融合線104的厚度。矽晶片活性表面與PCB的直接連接包括接觸分佈在矽晶片底面上的一系列焊料凸塊以及矽晶片102周圍載體106底邊上的球柵陣列(BGA)108的電接頭，生成的載體106要麼是銅載體要麼是陶瓷載體。即使這種封裝件具有降低封裝件電阻的好處並能提供大大改進的熱性能，但由於需要特殊地生產具有特異形狀空腔的載體106，這種封裝件的生產成本較高。此外，由於載體106的幾何形狀，Joshi所公開的封裝件仍然缺乏適應包括多晶片模組(MCM)結構在內的不同封裝結構的靈活性。Joshi, in Japanese Patent No. 6,133,634, discloses a semiconductor package as shown in FIG. 1A. The germanium wafer 102 is connected to a carrier 106 having a cavity substantially surrounding the germanium wafer 102. The cavity size is designed to be a cavity. The depth is substantially equal to the thickness of the germanium wafer 102 plus the thickness of the die mounted fuse line 104. The direct connection of the active surface of the wafer to the PCB includes contacting a series of solder bumps distributed over the bottom surface of the germanium wafer and electrical contacts of a ball grid array (BGA) 108 on the bottom edge of the carrier 106 around the germanium wafer 102, the resulting carrier 106 being either It is a copper carrier or a ceramic carrier. Even though such a package has the benefit of reducing the resistance of the package and provides greatly improved thermal performance, the cost of production of such a package is high due to the need to specifically produce the carrier 106 having a cavity having a specific shape. Moreover, due to the geometry of the carrier 106, the package disclosed by Joshi still lacks the flexibility to accommodate different package configurations including multi-chip module (MCM) structures.

在另一個發明名稱為“圓柱球柵陣列封裝件”的美國專利6,391,687中，Cabahug等人公開了一種包括一個扁平引線框架的半導體器件，該扁平引線框架包括一個在引線框架表面上的晶粒安裝區，包括有焊料凸塊的矽晶片置於此處。該 (封裝)封裝件還進一步包括多個環繞至少部分晶粒安裝區周邊的圓柱，矽晶片置於晶粒安裝區中，圓柱的高度基本與凸塊相同，引線框架上的矽晶片如第1B圖和第1C圖所示。In another U.S. Patent No. 6,391,687, the disclosure of which is incorporated herein by reference in its entirety in its entirety, the disclosure of the disclosure of the entire disclosure of the disclosure of the disclosure of the disclosure of the disclosure of The region, including the germanium wafer with solder bumps, is placed here. The The (package) package further includes a plurality of cylinders surrounding at least a portion of the periphery of the die mounting region, the germanium wafer being disposed in the die mounting region, the height of the cylinder being substantially the same as the bump, and the germanium wafer on the lead frame being as shown in FIG. And shown in Figure 1C.

在另一個專利6,624,522中，Standing等人公開了一種矽晶片級封裝件(CSP)，這種矽晶片級封裝件有一個半導體MOSFET晶片，在其頂部電極表面覆蓋有一層光敏的液態環氧基樹脂，樹脂光刻形成的圖案可暴露部分電極表面，起到鈍化層和焊接掩模的作用。然後在鈍化層上生成一層焊接接觸層，個別的晶粒安裝在汲極一側的金屬夾或與從管殼底部伸出的凸緣共平面。In another patent 6,624,522, Standing et al. discloses a tantalum wafer level package (CSP) having a semiconductor MOSFET wafer covered with a photosensitive liquid epoxy resin on the top electrode surface. The pattern formed by resin lithography exposes a portion of the electrode surface and functions as a passivation layer and a solder mask. A layer of solder contact layer is then formed over the passivation layer, with individual dies mounted on the side of the drain on the side of the metal clip or coplanar with the flange extending from the bottom of the tube.

在另一個專利6,661,082中，Granada等人公開了一種包括具有晶粒安裝空腔的引線框架的晶片裝置，該記憶體件進一步包括一個置於管晶片安裝空腔中的晶片。晶粒安裝空腔的厚度基本與晶片相同，晶片置於空腔中，並採用標準的晶片固定工藝將其連接於此。In another patent 6,661,082, Granada et al. disclose a wafer device including a lead frame having a die mounted cavity, the memory device further including a wafer placed in the tube wafer mounting cavity. The die mounting cavity is substantially the same thickness as the wafer, the wafer is placed in the cavity, and is attached thereto using a standard wafer mounting process.

在另一個專利6,469,384中，Joshi公開了一種包括基板和與基板連接的晶片的半導體器件，MOSFET晶片與基板連接使得MOSFET晶片的源和閘極區與基板連接，在鄰近晶片的地方提供有焊球，當半導體器件與印刷電路板連接時，封裝或晶片暴露的表面起著汲極的連接的作用，而焊球則起著源極和閘極的連接。正如第1D圖所示，基板包括一層基極層20和一層頂部金屬層21，基極層和頂部金屬層被一層絕緣層22隔開，該絕緣層可能是一種連接這兩層的 絕緣環氧基樹脂。基極的材料可能包括金屬化於案，而頂部金屬層優選包括另一種圖案，金屬層還可以起到散熱器的作用。然而，由於這種多層的基板中至少有一層或兩層由金屬構成，在金屬層與支援封裝的印刷電路板之間的熱膨脹失配仍然會導致熱應力。因此，在熱挑戰性環境下工作時，這種封裝因可靠性問題仍然存在著局限性。此外，基板仍舊是為了生成金屬層而採用一種特殊的設計過程生產的，正如本發明所公開的那樣，由於封裝基板的特殊生產要求，因而生產成本極大地增加。In another patent 6,469,384, Joshi discloses a semiconductor device comprising a substrate and a wafer connected to the substrate, the MOSFET wafer being connected to the substrate such that the source and gate regions of the MOSFET wafer are connected to the substrate, and solder balls are provided adjacent to the wafer. When the semiconductor device is connected to the printed circuit board, the exposed surface of the package or the wafer acts as a connection of the drain, and the solder ball acts as a connection between the source and the gate. As shown in FIG. 1D, the substrate includes a base layer 20 and a top metal layer 21, the base layer and the top metal layer being separated by an insulating layer 22, which may be a connection between the two layers. Insulating epoxy resin. The base material may include metallization, while the top metal layer preferably includes another pattern, and the metal layer may also function as a heat sink. However, since at least one or two of the multilayer substrates are made of metal, thermal expansion mismatch between the metal layer and the printed circuit board supporting the package still causes thermal stress. Therefore, this package still has limitations due to reliability issues when working in a thermally challenging environment. In addition, the substrate is still produced by a special design process for the purpose of forming a metal layer. As disclosed in the present invention, the production cost is greatly increased due to the special production requirements of the package substrate.

專利5,222,014公開了一種堆疊式三維多晶片模組(MCM)。如第1E圖所示，這種堆疊式三維MCM中的晶片載體的每一級都是通過軟熔事先凸起的焊球與晶片載體的另一級相互連接，直至每個載體。除了頂部載體之外，晶片載體的每一級都在基板的頂部和底部表面上具有焊球。用可選擇的蓋密封每個器件，蓋的高度可在載體的每一級之間扮演一個天然的正向傳輸線固定器的角色，從而產生砂漏型焊接接縫，使接頭的疲勞壽命最大化。該專利所公開的封裝結構提供了一種生成三維堆疊式模組增大多晶片封裝密度的方法，不過，這種方法僅適用於只是在同一表面上生成電接觸的半導體晶片。Patent 5,222,014 discloses a stacked three-dimensional multi-chip module (MCM). As shown in FIG. 1E, each stage of the wafer carrier in such a stacked three-dimensional MCM is interconnected to another stage of the wafer carrier by reflowing previously raised solder balls to each carrier. In addition to the top carrier, each stage of the wafer carrier has solder balls on the top and bottom surfaces of the substrate. Each device is sealed with an optional cover that acts as a natural forward transfer line anchor between each stage of the carrier, creating an hourglass-type welded joint that maximizes the fatigue life of the joint. The package structure disclosed in this patent provides a method of generating a three-dimensional stacked module to increase the density of a multi-chip package, however, this method is only applicable to semiconductor wafers that only generate electrical contacts on the same surface.

Ameen等人在專利5,715,144中公開了另一種設計有金字塔的多層、多晶片模組。這裏使用了多帶自動結合(ATAB)載體支援在此的晶片在一個金字塔結構中相互堆疊，並與基板連接，以便縮小在供安裝元件生成電路板的 基板上所需的面積。但是，ATAB載體因太薄不能維持其形狀需要使用硬化劑來增加其組成和封裝尺寸。另外，公開的封裝技術僅適用於只是在同一表面(平面器件)上生成電接觸的封裝半導體晶片。類似地，Akram等人在專利5,994,166中公開的、第1F圖所示的堆疊式封裝也有同樣的局限性，因為每個單個的晶片僅在晶片的一個表面上接觸。Another multi-layer, multi-chip module designed with a pyramid is disclosed in U.S. Patent 5,715,144. Here, a multi-band automatic bonding (ATAB) carrier is used to support the wafers stacked thereon in a pyramid structure and connected to the substrate to reduce the number of boards on which the components are mounted. The required area on the substrate. However, the ATAB carrier is too thin to maintain its shape and requires a hardener to increase its composition and package size. Additionally, the disclosed packaging techniques are only applicable to packaged semiconductor wafers that only make electrical contact on the same surface (planar device). Similarly, the stacked package shown in FIG. 1F disclosed by Akram et al. in U.S. Patent No. 5,994,166 has the same limitation, as each individual wafer is only in contact on one surface of the wafer.

因此，以上的專利公開者不能提供實際的、能克服目前在半導體器件封裝設計和生產領域技術人員中所面臨的局限性和難題的解決方案。所以，在該領域仍然存在著要求提供一種新的、改進的結構和方法，能夠解決以上討論的問題和困難，對垂直半導體器件進行封裝。此外，在上述專利公開者中，沒有一個能夠用來立體封裝垂直的功率MOSFET器件和功率IC模組。Accordingly, the above patent disclosures do not provide an actual solution that overcomes the limitations and challenges currently faced by those skilled in the art of semiconductor device package design and production. Therefore, there is still a need in the art to provide a new and improved structure and method that can solve the above discussed problems and difficulties in packaging vertical semiconductor devices. Moreover, none of the above patent applicants can be used to stereoscopically package vertical power MOSFET devices and power IC modules.

本發明的目的是採用改進的、能封裝諸如MOSFET器件的垂直半導體器件的結構，通過在薄片層生成相互連接的接觸線，能夠將MOSFET器件與功率IC和其他無源元件，例如電容器和電阻器一起封裝成三維集成的模組堆疊形式。薄片層由與印刷電路板具有類似的熱膨脹係數、能減少熱失配麻煩的材料構成。It is an object of the present invention to employ an improved structure capable of packaging a vertical semiconductor device such as a MOSFET device by enabling the generation of interconnected contact lines in the lamella layer, enabling MOSFET devices and power ICs and other passive components such as capacitors and resistors. Packaged together into a three-dimensional integrated module stack. The sheet layer is composed of a material having a thermal expansion coefficient similar to that of a printed circuit board and which can reduce the trouble of thermal mismatch.

本發明的另一方面，即薄片多層載體，例如具有相互連接接觸線的PCB或柔性板，能夠改善封裝過程的得率，生產出改進的、擁有長時間可靠性的封裝件。因擁有經過特殊加工的矽晶片固定載體，這種封裝結構還能進一步提 供更加靈活的、可調節的、不受限制的晶片尺寸，該矽晶片固定載體具有特殊空腔或形狀以及如同上面所示具有延伸邊緣的尺寸。目前，伴隨普通的PCB技術在半導體封裝過程中的應用，本發明的再一個方面是此次公開的結構能夠方便地作為表面安裝技術(SMT)封裝使用。由於該結構的靈活性和適用性，本發明的封裝結構可以方便地取代常規的引線框架型封裝，例如SO、TO和TSSOP系列。本發明還有一個方面便是它所取得的改進，即工藝改善了對焊接接縫的可視度，從而極大地改進了封裝過程的方便程度和工藝性。Another aspect of the invention, i.e., a sheet multilayer carrier, such as a PCB or flexible board having interconnected contact lines, can improve the yield of the packaging process, resulting in an improved package with long-term reliability. This package structure can be further improved by having a specially processed silicon wafer fixed carrier. For a more flexible, adjustable, and unrestricted wafer size, the crucible wafer carrier has a particular cavity or shape and dimensions as shown above with extended edges. At present, with the application of ordinary PCB technology in the semiconductor packaging process, another aspect of the present invention is that the structure disclosed herein can be conveniently used as a surface mount technology (SMT) package. Due to the flexibility and applicability of the structure, the package structure of the present invention can conveniently replace conventional lead frame type packages such as the SO, TO and TSSOP series. Still another aspect of the present invention is the improvement achieved by the process that improves the visibility of the welded joints, thereby greatly improving the ease of packaging and processability.

本發明的另一方面是提供一種改進的結構，通過將已有的多種晶片封裝在同一層上對MOSFET器件進行封裝，從而解決在常規封裝結構中上面所討論到的局限性和難題。Another aspect of the present invention is to provide an improved structure that addresses the limitations and challenges discussed above in conventional package structures by packaging existing MOSFET devices on the same layer.

本發明的再一個方面是提供一種能夠將矽晶片或封裝件堆疊在兩層或多層上進行封裝過程的結構，因為現已位於薄片層中的相互連接的接觸線業已集成為封裝件的一部分。與引線框架使用的封裝件比較，當其用於本發明所公開的封裝結構時，在積體電路(IC)晶片之間的安排和相互連接的自由度要大得多。可仿效的實施例包括多晶片模組的結構安排是所有源極和閘極均晶面朝下或所有閘極均晶面朝下或某些汲極的連接晶面朝下，而某些源極和閘極安排為晶面朝下。Still another aspect of the present invention is to provide a structure capable of stacking a tantalum wafer or package on two or more layers for the packaging process, since the interconnected contact lines that are now in the sheet layer have been integrated as part of the package. The degree of freedom of arrangement and interconnection between integrated circuit (IC) wafers is much greater when compared to packages used in leadframes when used in the package structures disclosed herein. An exemplary embodiment includes a multi-wafer module that is structured such that all source and gate are face down or all gates are face down or some of the drain faces are facing down, while some sources The poles and gates are arranged with the facets facing down.

在一個優選的實施例中，本發明簡要地公開了一個包 括在底部封裝模組上垂直堆疊有至少一個頂部封裝模組的電子封裝件。每個封裝模組包括一個通過連接頭和位於層壓板上的連接頭封裝和連接的半導體晶片，層壓板採用標準的印刷電路板工藝製造，頂部和底部封裝模組在此的結構進一步成為表面安裝模組，可以方便地堆疊和安裝到預先安排好的電接觸上，無須使用引線框架。在一個優選的實施例中，至少一個頂部和底部封裝模組是包括至少兩個半導體晶片的多晶片模組(MCM)，至少一個頂部和底部封裝模組包括一個表面安裝到預先安排好的電接觸上的球柵陣列(BGA)，至少一個頂部和底部封裝模組包括在一個半導體晶片上、用來表面安裝到預先安排好的電接觸上的多個焊料凸塊，而且底部封裝模組的層壓板的熱膨脹係數還進一步與印刷電路板(PCB)的熱膨脹係數基本相同，這樣，溫度變化對表面安裝到PCB的影響就不大了。In a preferred embodiment, the present invention briefly discloses a package An electronic package in which at least one top package module is vertically stacked on the bottom package module. Each package module includes a semiconductor wafer packaged and connected through a connector and a connector on the laminate. The laminate is fabricated using a standard printed circuit board process, and the top and bottom package modules are further surface mounted. Modules can be easily stacked and mounted to pre-arranged electrical contacts without the use of lead frames. In a preferred embodiment, at least one of the top and bottom package modules is a multi-chip module (MCM) including at least two semiconductor wafers, and at least one of the top and bottom package modules includes a surface mount to a pre-arranged power Contact ball grid array (BGA), at least one top and bottom package module comprising a plurality of solder bumps on a semiconductor wafer for surface mounting to pre-arranged electrical contacts, and a bottom package module The thermal expansion coefficient of the laminate is further substantially the same as the thermal expansion coefficient of the printed circuit board (PCB), so that the temperature change has little effect on the surface mount to the PCB.

本發明還進一步公開了一種配置至少包括一個垂直堆疊在底部封裝模組上的頂部封裝模組的電子封裝件的方法。該方法包括採用標準印刷電路板工藝製造多層層壓板，從而提供連接頭和連接將半導體封裝在每個頂部和底部封裝模組中的接觸線的步驟。該方法還進一步包括製造和配置頂部和底部封裝模組成為表面安裝模組，從而能方便地堆疊和安裝到預先安排好的電接觸上而不需要使用引線框架的步驟。在一個優選的實施例中，該方法還進一步包括製造和配置至少一個頂部和底部封裝模組成為包含至少兩個半導體晶片的多晶片模組(MCM)的步驟。在另一 個優選實施例中，該方法還進一步包括在至少一個頂部和底部封裝模組的底面上製造和配置一個球柵陣列(BGA)，供表面安裝到預先安排好的電接觸上的步驟。在另一個優選實施例中，該方法還進一步包括在至少一個頂部和底部封裝模組的底面上製造和配置一個焊料凸塊陣列，供表面安裝到預先安排好的電接觸上的步驟。The present invention still further discloses a method of configuring an electronic package including at least one top package module stacked vertically on a bottom package module. The method includes the steps of fabricating a multilayer laminate using a standard printed circuit board process to provide a connector and a contact line that connects the semiconductor in each of the top and bottom package modules. The method further includes the steps of fabricating and configuring the top and bottom package modules as surface mount modules for easy stacking and mounting onto pre-arranged electrical contacts without the use of lead frames. In a preferred embodiment, the method further includes the step of fabricating and configuring the at least one top and bottom package module into a multi-chip module (MCM) comprising at least two semiconductor wafers. In another In a preferred embodiment, the method further includes the step of fabricating and configuring a ball grid array (BGA) on the bottom surface of the at least one top and bottom package module for surface mounting to the pre-arranged electrical contacts. In another preferred embodiment, the method still further includes the step of fabricating and configuring an array of solder bumps on the bottom surface of the at least one top and bottom package module for surface mounting to the pre-arranged electrical contacts.

結合各個附圖閱讀以下有關優選實施例的詳細說明後，本領域的技術人員就會一目了然地理解本發明的這些以及其他一些目標和優點。These and other objects and advantages of the present invention will become apparent to those skilled in the <RTIgt;

參看第2A圖和第2B圖中本發明的一個新的MOSFET封裝件100的側面截面圖和底視圖。MOSFET封裝件100包括一個MOSFET半導體晶片110，該半導體晶片110含有多個焊料凸塊120和121，焊料凸塊120和121與位於MOSFET晶片110表面上的源極襯墊和閘極襯墊具有電接觸關係。多個銅接觸線125與位於MOSFET晶片110底面上的汲極接觸相連，銅板125'電鍍到層壓板，例如印刷電路板(PCB)130，從而具有多個填充有銅的連接頭135，與頂面連接。頂部銅板140進一步電鍍到層壓板，例如PCB 130的頂面，包括多個焊球150的球柵陣列(BGA)位於PCB 130的底面，BGA的焊球150通過焊接掩模125"的孔與銅接觸線125電接觸。Referring to Figures 2A and 2B, a side cross-sectional view and a bottom view of a new MOSFET package 100 of the present invention. MOSFET package 100 includes a MOSFET semiconductor wafer 110 that includes a plurality of solder bumps 120 and 121 that are electrically connected to source pads and gate pads on the surface of MOSFET wafer 110. Contact relationship. A plurality of copper contact lines 125 are connected to the drain contacts on the bottom surface of the MOSFET wafer 110, and the copper plates 125' are plated to a laminate, such as a printed circuit board (PCB) 130, thereby having a plurality of copper-filled connectors 135, and a top Face connection. The top copper plate 140 is further electroplated to a laminate, such as the top surface of the PCB 130, a ball grid array (BGA) comprising a plurality of solder balls 150 is located on the bottom surface of the PCB 130, and the BGA solder balls 150 pass through the solder mask 125" holes and copper. Contact line 125 is in electrical contact.

再看第2C圖和第2D圖中PCB 130底部沿第2圖A所示的A-A線的底視圖。PCB 130底面具有電鍍到PCB 130 底面的銅板125'，將MOSFET 110的汲極與銅板125'連接。PCB 130底面剩餘的區域被焊接掩模125"覆蓋，生成從銅板125'延伸到BGA襯墊150'的銅接觸線125，將BGA焊球150焊接於此。BGA襯墊150'進一步與PCB 130上生成的、充填有銅的通路開口的連接頭135電連接。請看第2D圖中具有銅層140的封裝件的頂視圖，銅層140的的中心部分被蝕刻，蝕刻區域141是供選擇使用的，可用於鐳射標記或其他用途。Referring again to the bottom views of the bottom of the PCB 130 in the 2C and 2D drawings along the A-A line shown in Fig. 2A. The bottom surface of PCB 130 has plating to PCB 130 The bottom plate of the copper plate 125' connects the drain of the MOSFET 110 to the copper plate 125'. The remaining area of the bottom surface of the PCB 130 is covered by the solder mask 125", creating a copper contact line 125 extending from the copper plate 125' to the BGA pad 150', where the BGA solder ball 150 is soldered. The BGA pad 150' is further with the PCB 130 The connector 135, which is formed on the copper via opening, is electrically connected. Looking at the top view of the package having the copper layer 140 in Fig. 2D, the central portion of the copper layer 140 is etched, and the etched region 141 is optional. Used, it can be used for laser marking or other purposes.

參看第3A圖和第3B圖中根據本發明的一個新的MOSFET封裝件200的側面截面圖和底視圖。MOSFET封裝件200包括一個封裝成倒裝結構的MOSFET半導體晶片210，其中，多個焊料凸塊220與在薄片多層基板載體，例如PCB板載體230底面上生成的焊料襯墊連接，焊料凸塊220-G與焊接到閘極焊球250-G的閘極襯墊225-GP電接觸，焊料凸塊220-S與源極襯墊225-SP電接觸，每個源極襯墊225-SP都焊接到源極焊球250-S上。MOSFET晶片210底面上生成有一個汲極接觸245，汲極接觸245的底面提高的高度校準到分別與閘極和源極焊球250-G和250-S相同。因此，封裝件200可進一步用作一個通常由PCB載體250支持的表面安裝技術(SMT)的封裝件，與其他支援在PCB載體250上的電子器件(圖中未畫出)連接，成為一個多晶片模組(MCM)。由於薄片多層基板載體230的熱膨脹係數基本與PCB載體的熱膨脹係數相同，因此封裝件200焊接接縫的可靠性得到了極大的改善。Referring to Figures 3A and 3B, side cross-sectional and bottom views of a new MOSFET package 200 in accordance with the present invention. The MOSFET package 200 includes a MOSFET semiconductor wafer 210 packaged in a flip-chip structure in which a plurality of solder bumps 220 are connected to solder pads formed on a bottom surface of a thin-film multilayer substrate carrier, such as a PCB board carrier 230, solder bumps 220. -G is in electrical contact with the gate pad 225-GP soldered to the gate solder ball 250-G, the solder bump 220-S is in electrical contact with the source pad 225-SP, and each source pad 225-SP is Soldered to the source solder ball 250-S. A drain contact 245 is formed on the bottom surface of the MOSFET wafer 210, and the height of the bottom surface of the drain contact 245 is calibrated to be the same as the gate and source solder balls 250-G and 250-S, respectively. Therefore, the package 200 can be further used as a surface mount technology (SMT) package that is usually supported by the PCB carrier 250, and is connected to other electronic devices (not shown) that support the PCB carrier 250. Chip Module (MCM). Since the thermal expansion coefficient of the sheet multilayer substrate carrier 230 is substantially the same as the thermal expansion coefficient of the PCB carrier, the reliability of the solder joint of the package 200 is greatly improved.

參看第3C圖中PCB 230底部沿第3A圖所示的C-C線的底視圖。PCB 230的底面具有一個焊接掩模225"，焊料凸塊開口215-S和215-G將其下面電鍍到PCB 230的底面銅層暴露，以便將MOSFET 210的焊料凸塊220-G和220-S與銅板225-S'和225-G'連接。PCB 230底面剩餘的區域被焊接掩模225"覆蓋，絕緣從銅板225-G'和225-S'延伸到BGA閘極襯墊225-GP和BGA源極襯墊225-SP的銅接觸線225，以便焊接在此的BGA閘極焊球250G和源極焊球250S。BGA閘極焊球250G或源極焊球250S進一步與PCB 230中生成的、充填有銅的通路開口的連接頭235電連接。請看第3D圖中封裝件的頂視圖，該封裝件在封裝件頂部生成有一個銅層240S和240G，作為外部連接使用的源極和閘極接觸襯墊。See the bottom view of the bottom of the PCB 230 in Figure 3C along line C-C shown in Figure 3A. The bottom surface of the PCB 230 has a solder mask 225", and the solder bump openings 215-S and 215-G are exposed to the underside copper layer of the PCB 230 to expose the solder bumps 220-G and 220- of the MOSFET 210. S is connected to copper plates 225-S' and 225-G'. The remaining area of the bottom surface of PCB 230 is covered by solder mask 225", and the insulation extends from copper plates 225-G' and 225-S' to BGA gate pad 225-GP The copper contact line 225 of the BGA source pad 225-SP is used to solder the BGA gate solder ball 250G and the source solder ball 250S. The BGA gate ball 250G or the source ball 250S is further electrically connected to a connector 235 of the PCB 230 that is filled with a copper via opening. Looking at the top view of the package in Figure 3D, the package has a copper layer 240S and 240G formed on top of the package as a source and gate contact pad for external connections.

參看第4A圖-第4C圖中根據本發明的三維堆疊式MOSFET和功率IC模組。第4A圖顯示了三維堆疊式模組(3DSM)的截面圖，其中，頂部模組構建成一個類似第2A圖-第2D圖所示的MOSFET模組100，第4B圖顯示了第4A圖中沿A-A線的截面區域的底視圖。特別地，MOSFET模組100包括一個MOSFET半導體晶片110，該半導體晶片具有多個起著源極凸塊120-S和閘極凸塊120-G作用的焊料凸塊120。焊料凸塊120-G和120-S分別與位於MOSFET晶片110頂面上的閘極襯墊及源極襯墊電接觸。多個銅接觸線125與位於MOSFET晶片110底面上的汲極接觸連接，印刷電路板(PCB)130具有多個如第2A圖所 示在此充填有銅的連接頭。頂部銅板還可以進一步電鍍到層壓板，例如PCB 130的頂面，包括多個焊球150的球柵陣列(BGA)位於PCB 130的底面，焊球150可以與第2A圖所示的連接頭電接觸。Referring to Figures 4A-4C, a three-dimensional stacked MOSFET and power IC module in accordance with the present invention. Figure 4A shows a cross-sectional view of a three-dimensional stacked module (3DSM) in which the top module is constructed like a MOSFET module 100 similar to that shown in Figures 2A-2D, and Figure 4B shows Figure 4A. A bottom view of the cross-sectional area along the AA line. In particular, MOSFET module 100 includes a MOSFET semiconductor wafer 110 having a plurality of solder bumps 120 that function as source bumps 120-S and gate bumps 120-G. Solder bumps 120-G and 120-S are in electrical contact with the gate pads and source pads on the top surface of MOSFET wafer 110, respectively. A plurality of copper contact lines 125 are in contact with the drains on the bottom surface of the MOSFET wafer 110, and the printed circuit board (PCB) 130 has a plurality of layers as shown in FIG. 2A. A connector filled with copper is shown here. The top copper plate may be further plated to a laminate, such as the top surface of the PCB 130. A ball grid array (BGA) comprising a plurality of solder balls 150 is located on the bottom surface of the PCB 130, and the solder balls 150 may be electrically connected to the connector shown in FIG. 2A. contact.

MOSFET模組100堆疊在支援於第二個薄片多層的PCB板160之上的第二個模組上，第二個PCB板160提供層間的相互連接以及層間的通路連接(為了簡潔起見，圖中未畫出)。層間通路連接提供焊球150之間與位於第二個層壓板160之下的焊球180的電連接，焊球180與通常行使與供電電壓連接功能的半導體功率器件110的汲極連接。第二個模組進一步包括另一個積體電路晶片170，該積體電路晶片可以是一個控制晶片，也可以是一個電源晶片，用戶通常可根據特定的應用而決定購買一種三維模組來執行具體的應用。集成的三維模組構建成一個表面安裝模組，包括有焊球180和連接到如第4C圖所示的接觸襯墊190-D、190-vdd、190-do、190-vss、190-vm等的焊料凸塊，如185-co、185-vdd、185-do、185-vss、185-vm等，其中，Vdd表示電源電壓，Vss表示地面電壓，Vco、Vdo和Vmm表示信號電壓。這些焊球和凸塊與支持在層壓板，例如印刷電路板195上的不同電路連接，印刷電路板195的特異連接和特殊結構是根據用戶的應用決定的，如在第4A圖-第4C圖中，用戶購買三維功率晶片模組時要求其結構是堆疊在控制IC晶片模組頂部的堆疊式MOSFET模組。The MOSFET module 100 is stacked on a second module supported on the second sheet multilayer PCB board 160. The second PCB board 160 provides interlayer interconnection and interlayer connection (for the sake of brevity, Not shown in the middle). The interlayer via connections provide electrical connections between the solder balls 150 and the solder balls 180 under the second laminate 160, which is connected to the drain of the semiconductor power device 110 that typically functions as a supply voltage connection. The second module further includes another integrated circuit chip 170. The integrated circuit chip can be a control chip or a power chip. The user can usually purchase a three-dimensional module to execute a specific application according to a specific application. Applications. The integrated 3D module is constructed as a surface mount module comprising solder balls 180 and connection pads 190-D, 190-vdd, 190-do, 190-vss, 190-vm as shown in Figure 4C. Solder bumps such as 185-co, 185-vdd, 185-do, 185-vss, 185-vm, etc., where Vdd represents the supply voltage, Vss represents the ground voltage, and Vco, Vdo and Vmm represent the signal voltage. These solder balls and bumps are connected to different circuits supported on a laminate, such as printed circuit board 195. The specific connections and special construction of printed circuit board 195 are determined by the user's application, as in Figure 4A - Figure 4C. In the case of purchasing a three-dimensional power chip module, the user is required to have a stacked MOSFET module stacked on top of the control IC chip module.

參看第5A圖-第5C圖中具有堆疊式多晶片模組的三維 MOSFET和功率IC多晶片模組(3DMCM)的結構。多晶片模組(MCM)的每一級使用層壓板封裝，層壓板的結構與第2A圖-第2B圖所示的結構類似。在一個如第5A圖所示的一個優選實施例中，4個MOSFET晶片110-1到110-4封裝成一個頂部的MCM模組100'，每個MOSFET用層壓板130'封裝，層壓板的結構與第2A圖-第2B圖所示的結構類似，其沿A-A線的截面圖顯示在第5B圖中，其分隔線和絕緣線位於頂部層壓板130'底面上，用來將MOSFET晶片110-1到110-4相互分開和絕緣。然後將頂部MCM模組表面安裝到起著如第4A圖所示的類似連接和支持功能的第二級層壓板160'上，通過層壓板160'的多個層間通路連接(圖中未畫出)將球柵陣列150與普通汲極以及底部BGA陣列180連接，為MOSFET晶片提供電源電壓。然後根據用戶所要求的特異連接和結構將這兩級堆疊式MCM模組安裝到底部層壓板195'上，如第5C圖所示，使用層壓板160'將4個控制IC晶片或功率晶片170-1到170-4封裝，其中，每個晶片都包括有焊料凸塊，根據用戶的特定應用規定位於層壓板195'上用來接觸接觸襯墊190-co'、190-vm'、190-vss'、190-vdd'、190-do'和必要時其他的接觸襯墊。See Figure 5A - Figure 5C for three-dimensional stacked multi-chip modules Structure of MOSFET and Power IC Multi-Chip Module (3DMCM). Each stage of the Multi-Chip Module (MCM) uses a laminate package having a structure similar to that shown in Figures 2A-2B. In a preferred embodiment as shown in FIG. 5A, four MOSFET wafers 110-1 through 110-4 are packaged into a top MCM module 100', each MOSFET being packaged in a laminate 130', laminated The structure is similar to that shown in FIGS. 2A-2B, and its cross-sectional view along line AA is shown in FIG. 5B with the dividing lines and insulated lines on the bottom surface of the top laminate 130' for MOSFET wafer 110. -1 to 110-4 are separated and insulated from each other. The top MCM module surface is then mounted to a second level laminate 160' that functions as a similar connection and support function as shown in FIG. 4A, through a plurality of interlayer vias of the laminate 160' (not shown) The ball grid array 150 is connected to the common drain and the bottom BGA array 180 to provide a supply voltage for the MOSFET wafer. The two stages of stacked MCM modules are then mounted to the bottom laminate 195' according to the specific connections and structures required by the user. As shown in FIG. 5C, four control IC wafers or power chips 170 are used using the laminate 160'. -1 to 170-4 packages, wherein each wafer includes solder bumps on the laminate 195' for contacting the contact pads 190-co', 190-vm', 190-, depending on the particular application of the user. Vss', 190-vdd', 190-do' and other contact pads if necessary.

根據上述介紹，本發明公開了使用不需要引線框架的標準表面安裝元件(SMT)工藝封裝垂直功率MOSFET和IC器件的結構和方法。鑒於直截了當的SMT過程，它不需要使用引線框架相關的封裝過程和設備。公開的這種結構還將元件級BGA工藝，例如BGA陣列150和180與晶片 級焊料凸塊工藝，例如焊料凸塊120-G和120-S結合起來，因此可以實現更加靈活安排的封裝結構，多級基於聚合物的層壓板，例如層壓板130和160均可使用。能夠在板的兩邊提供相互連接、銅接觸線、焊接掩模開口和大型暴露的金屬區的層壓板技術已早為人們所熟知，並已得到充地實踐，這種封裝結構最大程度地減少了涉及採用新的、不為人們知曉技術的危險性，而且還能降低封裝成本。第4圖和第5圖所示的結構提供了一個平臺，它使採用無須使用引線框架的表面安裝工藝在集成層壓的BGA封裝件上堆疊多個晶片成為可能，並得到優良的成本效益比。這種封裝結構可應用於單個功率IC和MOSFET器件，以及所有其他類型的半導體IC器件，或這些單個功率IC、MOSFET器件與其他類型半導體IC器件的混合或組合。In light of the above, the present invention discloses a structure and method for packaging vertical power MOSFETs and IC devices using a standard surface mount component (SMT) process that does not require a leadframe. In view of the straightforward SMT process, it does not require the use of leadframe-related packaging processes and equipment. This disclosed structure will also feature component level BGA processes such as BGA arrays 150 and 180 and wafers. The stage solder bump process, such as solder bumps 120-G and 120-S, combine to provide a more flexible package structure, and multi-stage polymer-based laminates, such as laminates 130 and 160, can be used. Laminate technology capable of providing interconnects, copper contact lines, solder mask openings, and large exposed metal regions on both sides of the board has long been known and practiced to minimize the package structure. It involves the risk of adopting new, unrecognized technologies and reducing packaging costs. The structure shown in Figures 4 and 5 provides a platform that makes it possible to stack multiple wafers on an integrated laminated BGA package using a surface mount process that does not require the use of a leadframe, and achieves an excellent cost-benefit ratio. . This package structure can be applied to a single power IC and MOSFET device, as well as all other types of semiconductor IC devices, or a mixture or combination of these individual power ICs, MOSFET devices, and other types of semiconductor IC devices.

如上所述，MOSFET晶片可以通過有凸塊的MOSFET晶片的汲極與層壓板的連接進行封裝。或者，使用一個倒裝結構，即採用導電的粘結劑或焊膏將有凸塊的MOSFET晶片與金屬全然暴露的焊接掩模開口連接，也可以對MOSFET晶片進行封裝。這時焊球通過層壓板的焊接掩模開口與金屬連接，而晶圓凸塊與也是在層壓板上生成的金屬接觸線連接。除了使用簡化的表面安裝技術的優點之外，模組可以很方便地堆疊，這種類型的連接又進一步提供了另一個優點，因為可以得到較好的熱消散和較短的相互連接通路，從而降低了寄生電感和電阻。這種公開的立體模組還能進一步做到結構靈活，形成緊湊的封裝件，適 合於封裝矽晶片尺寸大於使用基於引線框架封裝件得到的矽晶片尺寸的IC晶片。此外，由於層壓板，包括PCB板上所有的工藝，已為人們所熟知，並能方便地實施，公開的封裝元件可在短時間內以低廉的成本裝備生產線。與基於引線框架的封裝件或倒裝封裝件比較，由於涉及生產過程的不同階段的成本結構得到改進，生產成本得到降低。層壓的PCB板還進一步具有額外的優點，銅接觸線和通路連接可以十分靈活的方式方便地生成，與MOSFET晶片和功率IC連接，可以提供各種應用需求。由於高溫MOSFET和功率IC可以堆疊於一個集成模組上，可以得到具有廣闊應用前景的封裝件上的系統(SIP)或模組上的系統(SIM)，這些應用可能包括，但決不是僅限於此，動力管理、廣級別封裝等。As noted above, MOSFET wafers can be packaged by the connection of the bumps of the bumped MOSFET wafer to the laminate. Alternatively, the MOSFET wafer can be packaged using a flip-chip structure that uses a conductive adhesive or solder paste to bond the bumped MOSFET wafer to the fully exposed solder mask opening of the metal. The solder balls are then joined to the metal through the solder mask openings of the laminate, and the wafer bumps are connected to metal contact lines that are also formed on the laminate. In addition to the advantages of using simplified surface mount technology, the modules can be easily stacked, and this type of connection further provides another advantage because better heat dissipation and shorter interconnect paths are obtained, thereby Reduced parasitic inductance and resistance. The disclosed three-dimensional module can further flexibly structure and form a compact package. An IC wafer that is larger in package size than a tantalum wafer size obtained using a lead frame package. In addition, since the laminate, including all processes on the PCB, is well known and can be easily implemented, the disclosed package components can be used to equip the production line at a low cost in a short period of time. Compared to lead frame based packages or flip chip packages, production costs are reduced due to improved cost structures involving different stages of the production process. Laminated PCBs further have the added advantage that copper contact lines and via connections can be easily generated in a flexible manner, connected to MOSFET wafers and power ICs to provide a variety of application requirements. Since high-temperature MOSFETs and power ICs can be stacked on one integrated module, a system (SIP) or a system on a module (SIM) on a package with broad application prospects can be obtained. These applications may include, but are not limited to, This, power management, wide-level packaging and so on.

雖然本發明是採用目前較好的實施例進行介紹的，必須認識到這種公開並非僅限於此。毫無疑問，本領域技術人員在閱讀上述介紹後，便會清楚地發現還存在著許多變更和修改。因此，本發明期望，附加的申請專利範圍第包括了在本發明的真實精神和範圍之內的所有這些變更和修改。Although the present invention has been described in terms of a presently preferred embodiment, it must be recognized that the disclosure is not limited thereto. Undoubtedly, after reading the above description, those skilled in the art will clearly recognize that there are many variations and modifications. Accordingly, the invention is intended to embrace all such modifications and alternatives

100‧‧‧模組圖100‧‧‧Module diagram

100’‧‧‧模組100’‧‧‧ modules

102‧‧‧矽晶片102‧‧‧矽 wafer

104‧‧‧晶粒安裝融合線104‧‧‧ die mounting fusion line

106‧‧‧載體106‧‧‧ Carrier

110‧‧‧半導體晶片110‧‧‧Semiconductor wafer

120,121‧‧‧焊料凸塊120,121‧‧‧ solder bumps

120-G‧‧‧柵凸塊120-G‧‧‧Gate bump

120-S‧‧‧源極凸塊120-S‧‧‧ source bump

125‧‧‧銅接觸線125‧‧‧ copper contact line

125’‧‧‧銅板125’‧‧‧ copper plate

125”,225”‧‧‧焊接掩模125", 225" ‧‧‧ solder mask

130,195‧‧‧印刷電路板(PCB)130,195‧‧‧Printed circuit board (PCB)

130’,160’,195’‧‧‧層壓板130', 160', 195' ‧ ‧ laminate

140,225-G’,225-S’‧‧‧銅板140,225-G’, 225-S’‧‧‧ copper plate

141‧‧‧蝕刻區域141‧‧‧etched area

150,180‧‧‧焊球150,180‧‧‧ solder balls

150’‧‧‧BGA襯墊150’‧‧‧BGA pad

110-1~110-4,170,170-1~170-4,210‧‧‧晶片110-1~110-4,170,170-1~170-4,210‧‧‧ wafer

185-VSS,185-VDD,185-CO,215-G,215-S,220-G,220-S‧‧‧焊料凸塊185-VSS, 185-VDD, 185-CO, 215-G, 215-S, 220-G, 220-S‧‧‧ solder bumps

190-CO,190-D,190-DO,190VDD,190-VM,190-VSS, 190-CO’,190-D’,190-DO’,190-VDD’,190-VM’,190-VSS’‧‧‧接觸襯墊190-CO, 190-D, 190-DO, 190VDD, 190-VM, 190-VSS, 190-CO', 190-D', 190-DO', 190-VDD', 190-VM', 190-VSS'‧‧‧ contact pads

225,225-SP‧‧‧源極襯墊225,225-SP‧‧‧Source pad

225-GP‧‧‧閘極襯墊225-GP‧‧‧gate pad

230‧‧‧PCB板載體230‧‧‧PCB board carrier

235‧‧‧連接頭235‧‧‧Connecting head

240,240-G,240-S‧‧‧銅層240,240-G, 240-S‧‧‧ copper layer

245‧‧‧汲極接觸245‧‧‧汲contact

250‧‧‧BGA焊球250‧‧‧BGA solder balls

250-G‧‧‧BGA閘極焊球250-G‧‧‧BGA gate solder ball

250-S‧‧‧源極焊球250-S‧‧‧ source solder ball

第1A圖－第1F圖是常規封裝結構的截面圖、立體圖和透視圖；第2A圖－第2D圖是根據本發明改進的MOSFET器件封裝結構的側面截面圖和頂視圖和底視圖；第3A圖－第3D圖是根據本發明的另一個改進的MOSFET器件封裝結構的側面截面圖和頂視圖和底視圖；第4A圖－第4C圖是根據本發明的三維堆疊式MOSFET和功率IC模組(3DSM)沿第4A圖所示的A－A和B－B部分的各個側面截面圖和頂視圖和底視圖；第5A圖－第5C圖是根據本發明的三維堆疊式MOSFET和功率IC多晶片模組(3DSMCM)沿第5A圖所示的A－A和B－B部分的各個側面截面圖和頂視圖和底視圖。1A-F1F are cross-sectional, perspective, and perspective views of a conventional package structure; FIGS. 2A-2D are side cross-sectional views and top and bottom views of a modified MOSFET device package structure in accordance with the present invention; Figure 3D is a side cross-sectional view and a top and bottom view of another improved MOSFET device package structure in accordance with the present invention; Figures 4A-4C are three-dimensional stacked MOSFETs and power IC modules in accordance with the present invention. (3DSM) respective side cross-sectional views and top and bottom views of the A-A and B-B portions shown in FIG. 4A; FIGS. 5A-5C are three-dimensional stacked MOSFETs and power ICs according to the present invention The wafer module (3DSMCM) is a side cross-sectional view and a top view and a bottom view of the A-A and B-B portions shown in Fig. 5A.

110．．．半導體晶片110. . . Semiconductor wafer

120．．．焊料凸塊120. . . Solder bump

125．．．銅接觸線125. . . Copper contact line

125”．．．焊接掩模125"... solder mask

130．．．印刷電路板(PCB)130. . . Printed circuit board (PCB)

140．．．頂部銅板140. . . Top copper plate

150．．．焊球150. . . Solder ball

Claims (28)

一種連接至少一個垂直堆疊在底部封裝模組上的頂部封裝模組的電子封裝件，該頂部封裝模組和底部封裝模組分別至少包含一個頂部半導體晶片和一個底部半導體晶片，其特徵在於，該電子封裝件還包括：一個頂部層壓板和一個底部層壓板，所述頂部層壓板和底部層壓板均具有貫穿層壓板的連接頭和分佈在與某些選定的連接頭連接的層壓板多層上的導電接觸線，並且所述頂部層壓板和底部層壓板均包含有覆蓋在層壓板底面的圖案化的銅板；所述頂部半導體晶片和底部半導體晶片均設置有一個位於半導體晶片底面的電極，頂部半導體晶片底面的電極焊接至設置於頂部層壓板底面的銅板上，底部半導體晶片底面的電極焊接至設置於底部層壓板底面的銅板上，並且底部層壓板的頂面還設置有與頂部封裝模組電極區域相適配的電接觸襯墊以剛好表面安裝所述頂部封裝模組至所述底部層壓板上；所述頂部封裝模組進一步包含第一球閘陣列BGA，第一球閘陣列BGA所包含的焊球貫穿頂部層壓板底面的焊接掩模從而與頂部半導體晶片底面的電極連接，第一球閘陣列BGA所包含的焊球從頂部封裝模組的頂部層壓板的底面向下延伸直至接觸設置於底部層壓板頂面的電接觸襯墊並就此形成底部封裝模組和頂部封裝模組的垂直堆疊，並且底部 封裝模組的底部半導體晶片包含的焊料凸塊從底部半導體晶片表面上的電極向下延伸至與底部封裝模組的第二球閘陣列BGA所包含的焊球的水準平面基本相同，以便方便地直接安裝到位於印刷電路板PCB上的接頭上。 An electronic package connecting at least one top package module vertically stacked on a bottom package module, the top package module and the bottom package module respectively comprising at least one top semiconductor wafer and one bottom semiconductor wafer, wherein The electronic package further includes: a top laminate and a bottom laminate, each having a connector penetrating the laminate and a plurality of laminate layers disposed adjacent to the selected connector. a conductive contact line, and the top laminate and the bottom laminate each comprise a patterned copper plate overlying the bottom surface of the laminate; the top semiconductor wafer and the bottom semiconductor wafer are each provided with an electrode on the bottom surface of the semiconductor wafer, the top semiconductor The electrode on the bottom surface of the wafer is soldered to a copper plate disposed on the bottom surface of the top laminate, the electrode on the bottom surface of the bottom semiconductor wafer is soldered to the copper plate disposed on the bottom surface of the bottom laminate, and the top surface of the bottom laminate is further provided with an electrode of the top package module Area-fitted electrical contact pads in just the surface mount a top package module to the bottom laminate; the top package module further includes a first ballast array BGA, the first ball gate array BGA comprising solder balls passing through the solder mask of the bottom surface of the top laminate and thus the top An electrode connection on the bottom surface of the semiconductor wafer, the solder balls included in the first ballast array BGA extending downward from the bottom surface of the top laminate of the top package module until contacting the electrical contact pads disposed on the top surface of the bottom laminate and forming the bottom Vertical stacking of package modules and top package modules, and bottom The bottom semiconductor wafer of the package module includes solder bumps extending from the electrodes on the surface of the bottom semiconductor wafer to substantially the same level as the solder balls included in the second ball grid array BGA of the bottom package module, so as to be convenient Mount directly to the connector on the PCB of the printed circuit board. 根據權利要求1所述的電子封裝件，其特徵在於，底部封裝模組的第二球閘陣列BGA所包含的焊球貫穿底部層壓板底面的焊接掩模從而與底部半導體晶片底面的電極連接，並且第二球閘陣列BGA所包含的焊球從底部封裝模組的底部層壓板的底面向下延伸以便方便地安裝到設置於印刷電路板PCB上的電接頭上，其中所述底部封裝模組是表面安裝到印刷電路板PCB上。 The electronic package of claim 1 , wherein the solder ball of the second ball grid array BGA of the bottom package module passes through the solder mask on the bottom surface of the bottom laminate to be connected to the electrode on the bottom surface of the bottom semiconductor wafer. And the solder ball included in the second ball gate array BGA extends downward from the bottom surface of the bottom laminate of the bottom package module for convenient mounting on the electrical connector disposed on the printed circuit board PCB, wherein the bottom package module It is surface mounted to the printed circuit board PCB. 根據權利要求1所述的電子封裝件，其特徵在於，所述頂部封裝模組的頂部半導體晶片所包含的焊料凸塊從頂部半導體晶片表面上的電極向下延伸至與第一球閘陣列BGA所包含的焊球的水準平面基本相同，以便方便地直接安裝到設置於底部層壓板頂面的且與頂部封裝模組電極區域相適配的所述電接觸襯墊上。 The electronic package of claim 1 wherein the top semiconductor wafer of the top package module comprises solder bumps extending downward from the electrodes on the surface of the top semiconductor wafer to the first ball gate array BGA The level of solder balls included is substantially the same in order to be conveniently mounted directly onto the electrical contact pads disposed on the top surface of the bottom laminate and adapted to the top package module electrode regions. 根據權利要求1所述的電子封裝件，其特徵在於，所述頂部封裝模組的至少一個頂部半導體晶片包括一個金屬氧化物半導體場效應電晶體MOSFET晶片，第一球閘陣列BGA所包含的焊球貫穿設置於頂部層壓板底面的焊接掩模從而與作為所述半導體場效應電晶體MOSFET晶片的汲極的所述頂部半導體晶片底面的電極連接。 The electronic package of claim 1 wherein the at least one top semiconductor wafer of the top package module comprises a metal oxide semiconductor field effect transistor MOSFET chip, the solder included in the first ball gate array BGA The ball is passed through a solder mask disposed on the bottom surface of the top laminate to be coupled to the electrode of the bottom surface of the top semiconductor wafer that is the drain of the semiconductor field effect transistor MOSFET. 根據權利要求1所述的電子封裝件，其特徵在於，所述底部封裝模組的第二球閘陣列BGA所包含的焊球連接貫穿設置於底部層壓板底面的焊接掩模與底部半導體晶片底面的電極，其中第二球閘陣列BGA所包含的焊球從底部層壓板的底面向下延伸以表面安裝至設置於印刷電路板PCB上的電接頭上；所述底部封裝模組的第二球閘陣列BGA所包含的焊球通過貫穿底部層壓板的連接頭從而與頂部封裝模組的第一球閘陣列BGA所包含的焊球電連接。 The electronic package of claim 1 , wherein the solder ball connection included in the second ball grid array BGA of the bottom package module passes through the solder mask and the bottom surface of the bottom semiconductor wafer disposed on the bottom surface of the bottom laminate The electrode, wherein the solder ball included in the second ball gate array BGA extends downward from the bottom surface of the bottom laminate to be surface mounted to the electrical connector disposed on the printed circuit board PCB; the second ball of the bottom package module The solder balls included in the gate array BGA are electrically connected to the solder balls included in the first ballast array BGA of the top package module through the connectors passing through the bottom laminate. 根據權利要求2所述的電子封裝件，其特徵在於，所述底部封裝模組的至少一個底部半導體晶片包含一個金屬氧化物半導體場效應電晶體MOSFET晶片，第二球閘陣列BGA所包含的焊球貫穿設置於底部層壓板底面的焊接掩模從而與作為所述半導體場效應電晶體MOSFET晶片的汲極的所述底部半導體晶片底面的電極連接。 The electronic package of claim 2, wherein at least one of the bottom semiconductor wafers of the bottom package module comprises a metal oxide semiconductor field effect transistor MOSFET chip, and the second ball gate array BGA comprises a solder The ball is passed through a solder mask disposed on the bottom surface of the bottom laminate to be coupled to the electrode of the bottom surface of the bottom semiconductor wafer which is the drain of the semiconductor field effect transistor MOSFET. 根據權利要求3所述的電子封裝件，其特徵在於，所述底部封裝模組的底部半導體晶片所包含的焊料凸塊從底部半導體晶片表面上的電極向下延伸至與第二球閘陣列BGA所包含的焊球的水準平面基本相同，以便方便地直接安裝到設置於印刷電路板PCB上的接頭上。 The electronic package of claim 3, wherein the bottom semiconductor wafer of the bottom package module comprises solder bumps extending downward from the electrodes on the bottom semiconductor wafer surface to the second ball gate array BGA The level planes of the included solder balls are substantially the same for convenient mounting directly to the connectors disposed on the PCB of the printed circuit board. 根據權利要求7所述的電子封裝件，其特徵在於，所述底部封裝模組的第二球閘陣列BGA所包含的焊球通過貫穿底部層壓板的連接頭從而與頂部封裝模組的第一球閘陣 列BGA所包含的焊球電連接。 The electronic package of claim 7 , wherein the solder ball of the second ball grid array BGA of the bottom package module passes through the connector of the bottom laminate to be the first of the top package module Ball gate array The solder balls included in the column BGA are electrically connected. 根據權利要求7所述的電子封裝件，其特徵在於，第二球閘陣列BGA所包含的焊球中的至少一個焊球與電源電壓的連接。 The electronic package according to claim 7, wherein at least one of the solder balls included in the second ball grid array BGA is connected to a power supply voltage. 根據權利要求7所述的電子封裝件，其特徵在於，底部封裝模組的底部半導體晶片所包含的焊料凸塊中的至少一個焊料凸塊與Vco信號電壓連接。 The electronic package of claim 7 wherein at least one of the solder bumps included in the bottom semiconductor wafer of the bottom package module is coupled to the Vco signal voltage. 根據權利要求7所述的電子封裝件，其特徵在於，底部封裝模組的底部半導體晶片所包含的焊料凸塊中的至少一個焊料凸塊與Vdd電源電壓連接。 The electronic package of claim 7 wherein at least one of the solder bumps included in the bottom semiconductor wafer of the bottom package module is coupled to the Vdd supply voltage. 根據權利要求7所述的電子封裝件，其特徵在於，底部封裝模組的底部半導體晶片所包含的焊料凸塊中的至少一個焊料凸塊與Vdo信號電壓連接。 The electronic package of claim 7 wherein at least one of the solder bumps included in the bottom semiconductor wafer of the bottom package module is voltage coupled to the Vdo signal. 根據權利要求7所述的電子封裝件，其特徵在於，底部封裝模組的底部半導體晶片所包含的焊料凸塊中的至少一個焊料凸塊與Vss地面電壓連接。 The electronic package of claim 7 wherein at least one of the solder bumps included in the bottom semiconductor wafer of the bottom package module is connected to the Vss ground voltage. 根據權利要求7所述的電子封裝件，其特徵在於，底部封裝模組的底部半導體晶片所包含的焊料凸塊中的至少一個焊料凸塊與Vmm信號電壓連接。 The electronic package of claim 7 wherein at least one of the solder bumps included in the bottom semiconductor wafer of the bottom package module is coupled to the Vmm signal voltage. 一種連接至少一個垂直堆疊在底部封裝模組上的頂部封裝模組的電子封裝件，該頂部封裝模組和底部封裝模組分別至少包含一個頂部半導體晶片和一個底部半導體晶片，其特徵在於，該電子封裝件還包括： 一個頂部層壓板和一個底部層壓板，所述頂部層壓板和底部層壓板均具有貫穿層壓板的連接頭和分佈在與某些選定的連接頭連接的層壓板多層上的導電接觸線，並且所述頂部層壓板和底部層壓板均包含有覆蓋在層壓板底面的圖案化的銅板及形成在銅板上的焊接掩模；所述頂部半導體晶片和底部半導體晶片均設置有一個位於半導體晶片底面的電極，頂部半導體晶片底面的電極焊接至設置於頂部層壓板底面的形成有焊接掩模的銅板上，底部半導體晶片底面的電極焊接至設置於底部層壓板底面的形成有焊接掩模的銅板上，並且底部層壓板的頂面還設置有與頂部封裝模組電極區域相適配的電接觸襯墊以剛好表面安裝所述頂部封裝模組至所述底部層壓板上；至少一個頂部封裝模組或底部封裝模組所包含的個頂部半導體晶片或底部半導體晶片為一個垂直的半導體場效應電晶體MOSFET晶片，並且位於該半導體場效應電晶體MOSFET晶片底面的電極作為汲極焊接至該半導體場效應電晶體MOSFET晶片所在的頂部封裝模組或底部封裝模組所包含的頂部層壓板或底部層壓板上的形成有焊接掩模的銅板上。 An electronic package connecting at least one top package module vertically stacked on a bottom package module, the top package module and the bottom package module respectively comprising at least one top semiconductor wafer and one bottom semiconductor wafer, wherein The electronic package also includes: a top laminate and a bottom laminate, each having a joint extending through the laminate and a conductive contact line distributed over the plurality of laminate layers joined to selected joints, and The top laminate and the bottom laminate each comprise a patterned copper plate overlying the bottom surface of the laminate and a solder mask formed on the copper plate; the top semiconductor wafer and the bottom semiconductor wafer are each provided with an electrode on the bottom surface of the semiconductor wafer The electrode of the bottom surface of the top semiconductor wafer is soldered to a copper plate formed on the bottom surface of the top laminate formed with the solder mask, and the electrode of the bottom surface of the bottom semiconductor wafer is soldered to the copper plate formed with the solder mask disposed on the bottom surface of the bottom laminate, and The top surface of the bottom laminate is further provided with an electrical contact pad adapted to the top package module electrode area to just surface mount the top package module to the bottom laminate; at least one top package module or bottom The top semiconductor wafer or the bottom semiconductor wafer included in the package module is a vertical semiconductor a field effect transistor MOSFET chip, and the electrode on the bottom surface of the semiconductor field effect transistor MOSFET is soldered as a top laminate included in the top package module or the bottom package module where the semiconductor field effect transistor MOSFET chip is located Or a copper plate on the bottom laminate formed with a solder mask. 根據權利要求15所述的電子封裝件，其特徵在於，所述頂部封裝模組包含的頂部半導體晶片為所述的垂直的半導體場效應電晶體MOSFET晶片，該頂部半導體晶片所包含的焊料凸塊從設置於半導體場效應電晶體MOSFET晶片 表面上的電極向下延伸至與設置於底部封裝模組的底部層壓板頂面的電接觸襯墊的水準平面基本相同，以便安裝至該電接觸襯墊上。 The electronic package of claim 15 wherein the top package module comprises a top semiconductor wafer as the vertical semiconductor field effect transistor MOSFET wafer, the solder bumps included in the top semiconductor wafer From a semiconductor field effect transistor MOSFET chip The electrodes on the surface extend down to substantially the same level as the level of the electrical contact pads disposed on the top surface of the bottom laminate of the bottom package module for mounting to the electrical contact pads. 根據權利要求15所述的電子封裝件，其特徵在於，所述底部封裝模組包含的底部半導體晶片為一個底部半導體場效應電晶體MOSFET晶片，該底部半導體晶片所包含的焊料凸塊從設置於半導體場效應電晶體MOSFET晶片表面上的電極向下延伸至與設置於底部封裝模組的第二球閘陣列BGA所包含的焊球的水準平面基本相同，以便方便地安裝到位於印刷電路板PCB上的電接頭上。 The electronic package of claim 15 wherein the bottom package module comprises a bottom semiconductor wafer as a bottom semiconductor field effect transistor MOSFET, and the bottom semiconductor wafer comprises solder bumps disposed from The electrodes on the surface of the semiconductor field effect transistor MOSFET extend downward to substantially the same level as the solder balls included in the second ball grid array BGA disposed in the bottom package module for convenient mounting to the printed circuit board PCB. On the electrical connector. 根據權利要求16所述的電子封裝件，其特徵在於，在所述頂部封裝模組中所述垂直的半導體場效應電晶體MOSFET晶片進一步所包含的焊料凸塊電連接到設置在該半導體場效應電晶體MOSFET晶片的源極和閘極接觸襯墊上。 The electronic package of claim 16 wherein said vertical semiconductor field effect transistor MOSFET wafer further comprises solder bumps electrically connected to said semiconductor field effect in said top package module The source and gate of the transistor MOSFET chip are in contact with the pad. 根據權利要求17所述的電子封裝件，其特徵在於，在所述底部封裝模組中所述底部半導體場效應電晶體MOSFET晶片進一步所包含的焊料凸塊電連接到設置在該底部半導體場效應電晶體MOSFET晶片的源極和閘極接觸襯墊上。 The electronic package of claim 17, wherein the bottom semiconductor package MOSFET wafer further comprises a solder bump electrically connected to the bottom semiconductor field effect disposed in the bottom package module The source and gate of the transistor MOSFET chip are in contact with the pad. 一種連接至少一個垂直堆疊在底部封裝模組上的頂部封裝模組的電子封裝件，該頂部封裝模組和底部封裝模組分別至少包含一個頂部半導體晶片和一個底部半導體晶 片，其特徵在於，該電子封裝件還包括：一個頂部層壓板和一個底部層壓板，所述頂部層壓板和底部層壓板均具有貫穿層壓板的連接頭和分佈在與某些選定的連接頭連接的層壓板多層上的導電接觸線，並且所述頂部層壓板和底部層壓板均包含有覆蓋在層壓板底面的圖案化的銅板及形成在銅板上的焊接掩模；所述頂部半導體晶片和底部半導體晶片均為半導體場效應電晶體MOSFET晶片，並且在位於半導體晶片底面上設置有一個作為半導體場效應電晶體MOSFET晶片汲極的電極，頂部半導體晶片底面的電極焊接至設置於頂部層壓板底面的形成有焊接掩模的銅板上，底部半導體晶片底面的電極焊接至設置於底部層壓板底面的形成有焊接掩模的銅板上，其中底部層壓板的頂面還設置有與頂部封裝模組電極區域相適配的電接觸襯墊以剛好表面安裝所述頂部封裝模組至所述底部層壓板上。 An electronic package connecting at least one top package module vertically stacked on a bottom package module, the top package module and the bottom package module respectively including at least one top semiconductor wafer and one bottom semiconductor crystal a sheet, characterized in that the electronic package further comprises: a top laminate and a bottom laminate, each of the top laminate and the bottom laminate having a connector penetrating the laminate and being distributed over the selected connector Conductive contact wires on the laminated laminate layers, and the top laminate and the bottom laminate each comprise a patterned copper plate overlying the bottom surface of the laminate and a solder mask formed on the copper plate; the top semiconductor wafer and The bottom semiconductor wafers are all semiconductor field effect transistor MOSFET wafers, and an electrode serving as a drain of the semiconductor field effect transistor MOSFET is disposed on the bottom surface of the semiconductor wafer, and the electrodes on the bottom surface of the top semiconductor wafer are soldered to the bottom surface of the top laminate. The copper plate on which the solder mask is formed, the electrode on the bottom surface of the bottom semiconductor wafer is soldered to the copper plate formed on the bottom surface of the bottom laminate formed with the solder mask, wherein the top surface of the bottom laminate is further provided with the top package module electrode The area-matched electrical contact pads are just surface mounted to the top package module to Said bottom laminate. 根據權利要求20所述的電子封裝件，其特徵在於，所述頂部封裝模組進一步包含第一球閘陣列BGA，第一球閘陣列BGA所包含的焊球貫穿頂部層壓板底面的焊接掩模從而與頂部封裝模組所包含的半導體場效應電晶體MOSFET晶片的汲極電連接，第一球閘陣列BGA所包含的焊球從頂部封裝模組的頂部層壓板的底面向下延伸直至接觸設置於底部層壓板頂面的電接觸襯墊並就此形成底部封裝模組和頂部封裝模組的垂直堆疊；以及 包含的焊球從頂部封裝模組的頂部層壓板的底面向下延伸直至接觸設置於底部層壓板頂面的電接觸襯墊並就此形成底部封裝模組和頂部封裝模組的垂直堆疊；以及底部封裝模組的第二球閘陣列BGA所包含的焊球貫穿底部層壓板底面的焊接掩模從而與底部封裝模組所包含的半導體場效應電晶體MOSFET晶片的汲極電連接，並且第二球閘陣列BGA所包含的焊球從底部封裝模組的底部層壓板的底面向下延伸以便安裝到設置於印刷電路板PCB上的電接頭上，其中所述底部封裝模組是表面安裝到印刷電路板PCB上。 The electronic package according to claim 20, wherein the top package module further comprises a first ball gate array BGA, and the solder ball included in the first ball gate array BGA passes through a solder mask on the bottom surface of the top laminate Thereby electrically connecting to the drain of the semiconductor field effect transistor MOSFET chip included in the top package module, the solder ball included in the first ball grid array BGA extends downward from the bottom surface of the top laminate of the top package module until the contact setting Electrically contacting the top surface of the bottom laminate and forming a vertical stack of the bottom package module and the top package module; The included solder balls extend downwardly from the bottom surface of the top laminate of the top package module to contact the electrical contact pads disposed on the top surface of the bottom laminate and thereby form a vertical stack of the bottom package module and the top package module; and the bottom The solder ball of the second ballast array BGA of the package module penetrates the solder mask on the bottom surface of the bottom laminate to electrically connect with the drain of the semiconductor field effect transistor MOSFET chip included in the bottom package module, and the second ball The solder ball included in the gate array BGA extends downward from the bottom surface of the bottom laminate of the bottom package module for mounting to an electrical connector disposed on the printed circuit board PCB, wherein the bottom package module is surface mounted to the printed circuit On the board PCB. 根據權利要求20所述的電子封裝件，其特徵在於，所述底部封裝模組的所述底部層壓板的熱膨脹係數還進一步與位於底部層壓板之下並作為支撐底部層壓板的負載基板的印刷電路板PCB的熱膨脹係數基本相同，從而溫度變化對表面安裝到所述PCB影響不大。 The electronic package according to claim 20, wherein said bottom laminate of said bottom package module has a coefficient of thermal expansion further with printing under the bottom laminate and as a supporting substrate for supporting the bottom laminate The thermal expansion coefficients of the circuit board PCB are substantially the same, so that temperature changes have little effect on surface mounting to the PCB. 根據權利要求21所述的電子封裝件，其特徵在於，所述底部封裝模組的第二球閘陣列BGA所包含的焊球通過貫穿底部層壓板的連接頭從而與頂部封裝模組的第一球閘陣列BGA所包含的焊球電連接。 The electronic package according to claim 21, wherein the solder ball of the second ball grid array BGA of the bottom package module passes through the connector of the bottom laminate to be the first of the top package module The solder balls included in the ball gate array BGA are electrically connected. 一種包括至少一個垂直堆疊在一個底部封裝模組上的頂部封裝模組的電子封裝件，其特徵在於：每個所述的封裝模組均包括一個半導體晶片，半導體晶片直接接觸位於採用標準印刷電路板工藝製造的層 壓板上的連接頭並通過所述連接頭進行封裝和連接；其中，所述頂部和所述底部封裝模組進一步構建成一個表面安裝模組，以便方便地堆疊和安裝到預先安排的電接觸上，該電接觸在堆疊和安裝後係位於所述頂部和所述底部封裝模組之下方，而不需要使用引線框架。 An electronic package comprising at least one top package module vertically stacked on a bottom package module, wherein each of the package modules comprises a semiconductor wafer, and the semiconductor wafer is directly in contact with a standard printed circuit Board manufacturing layer a connector on the platen and packaged and connected by the connector; wherein the top and bottom package modules are further configured as a surface mount module for convenient stacking and mounting to pre-arranged electrical contacts The electrical contacts are placed under the top and the bottom package module after stacking and mounting without the use of a lead frame. 根據權利要求24所述的電子封裝件，其特徵在於，至少一個所述頂部和所述底部封裝模組是包含至少兩個半導體晶片的多晶片模組MCM。 The electronic package of claim 24 wherein at least one of said top and said bottom package modules are multi-wafer modules MCM comprising at least two semiconductor wafers. 根據權利要求24所述的電子封裝件，其特徵在於，至少一個所述頂部和所述底部封裝模組包括一個球閘陣列BGA，以便表面安裝到所述預先安排的電接觸上。 The electronic package of claim 24 wherein at least one of said top and said bottom package modules includes a ball gate array BGA for surface mounting to said pre-arranged electrical contacts. 根據權利要求24所述的電子封裝件，其特徵在於，至少一個所述頂部和所述底部封裝模組包括位於一個所述半導體晶片上的多個焊料凸塊，以便表面安裝到所述預先安排的電接觸上。 The electronic package of claim 24 wherein at least one of said top and said bottom package modules comprises a plurality of solder bumps on one of said semiconductor wafers for surface mounting to said pre-arranged On the electrical contact. 根據權利要求24所述的電子封裝件，其特徵在於，所述底部封裝模組的所述層壓板的熱膨脹係數還進一步與印刷電路板PCB的熱膨脹係數基本相同，從而溫度變化對表面安裝到所述PCB影響不大。 The electronic package according to claim 24, wherein the thermal expansion coefficient of the laminate of the bottom package module is further substantially the same as the thermal expansion coefficient of the printed circuit board PCB, so that the temperature change is applied to the surface. The PCB has little effect.
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