TWI454054B - Switching system with linearizing circuit - Google Patents

Switching system with linearizing circuit Download PDF

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TWI454054B
TWI454054B TW102126962A TW102126962A TWI454054B TW I454054 B TWI454054 B TW I454054B TW 102126962 A TW102126962 A TW 102126962A TW 102126962 A TW102126962 A TW 102126962A TW I454054 B TWI454054 B TW I454054B
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switch
signal
circuit
replica
switching element
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TW102126962A
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Chinese (zh)
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TW201415796A (en
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Ibrahim Engin Pehlivanoglu
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Skyworks Solutions Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1441—Balanced arrangements with transistors using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1466—Passive mixer arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/04106—Modifications for accelerating switching without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C2200/00—Indexing scheme relating to details of modulators or modulation methods covered by H03C
    • H03C2200/0037—Functional aspects of modulators
    • H03C2200/0079—Measures to linearise modulation or reduce distortion of modulation characteristics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0043—Bias and operating point
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0066—Mixing
    • H03D2200/0074—Mixing using a resistive mixer or a passive mixer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0088—Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Electronic Switches (AREA)

Description

具有線性化電路之開關系統Switching system with linearized circuit

本發明關於具有線性化電路之開關系統。The present invention relates to a switching system having a linearization circuit.

金氧半(MOS)場效應電晶體(MOSFET)可在電晶體的三極管或線性區之中***作成為開關。此一開關可形成為電阻器之概念，而其之值係由電晶體閘極一源極電壓所控制。當該閘極電壓致使開關成為閉合時，則電阻可僅為數歐姆，而有效地呈現閉路電路。當該閘極電壓致使開關打開時，則電阻會變高，以致有效地呈現開路電路。然而，實際上，在電晶體中存在有寄生電容。在某些情況中，該電阻可為非線性，其中電阻由於電容的充電時間而變成相依於電晶體源極端子電壓。例如，在若千無線電路手機中所使用之類型的混波器中之以MOS電晶體為主的開關，可由於一般使用於直接轉換式無線電接收器及發射器中以提供雜訊免除力之更大的電壓信號，而被驅動成為非線性操作。非線性操作可導致相互調變失真，而妨礙接收器或發射器性能。A gold-oxide half (MOS) field effect transistor (MOSFET) can be operated as a switch in the transistor or linear region of the transistor. This switch can be formed as a resistor concept whose value is controlled by the gate voltage of the transistor gate. When the gate voltage causes the switch to become closed, the resistance can be only a few ohms, effectively presenting a closed circuit. When the gate voltage causes the switch to open, the resistance will become high, effectively presenting an open circuit. However, in reality, there is a parasitic capacitance in the transistor. In some cases, the resistance can be non-linear, where the resistance becomes dependent on the transistor source terminal voltage due to the charging time of the capacitor. For example, a MOS transistor-based switch in a type of mixer used in a thousand wireless circuit handsets can be commonly used in direct conversion radio receivers and transmitters to provide noise immunity. A larger voltage signal is driven into a non-linear operation. Non-linear operations can cause mutual distortion and interfere with receiver or transmitter performance.

具有傳輸闆構造以促進線性之典型的正交混波器10係描繪於第1圖中。混波器10具有在此為便利起見而可稱作開關12，13，14，15，16，17，18，及19的部分。如在此所使用之“開關”用語，意指執行開關功能且可包含諸如電晶體或電晶體組群之一或更多個個別開關元件的任何電路。開關12混波正的同相輸入信號(在第1圖中標記為“I_P”之Ip，用於易讀性。)與本地振盪器(LO)信號及倍頻本地振盪器 (2LO)信號。開關14混波負的同相輸入信號(在第1圖中標記為“I_M”之Im，用於易讀性。)與LO及2LO信號。開關16混波正的正交輸入信號(在第1圖中標記為“Q_P”之Qp，用於易讀性。)與LO及2LO信號。開關18混波負的正交輸入信號(在第1圖中標記為“Q_M”之Qm，用於易讀性。)與LO及2LO信號。如本項技藝中所熟知地，時序電路(未顯示)致使各個該等輸入信號順序地被起作用，且同時使其他者不起作用：Ip，Qp，Im，Qm，Ip，Qp，...。因而，混波器輸出信號OUT_P及OUT_M順序地顯示混波Ip，Qp，Im，Qm，等等，與LO及2LO信號的結果。混波器10的架構有時候被稱作“LO-2LO”。A typical orthogonal mixer 10 having a transmission plate configuration to facilitate linearity is depicted in FIG. The mixer 10 has portions that may be referred to herein as switches 12, 13, 14, 15, 16, 17, 18, and 19 for convenience. As used herein, the term "switch" means any circuit that performs a switching function and may include one or more individual switching elements, such as a transistor or group of transistors. Switch 12 mixes positive non-inverting input signal (Ip labeled "I_P" in Figure 1 for readability.) and local oscillator (LO) signal and multiplier local oscillator (2LO) signal. The switch 14 mixes a negative in-phase input signal (Im labeled "I_M" in Figure 1 for readability.) and LO and 2LO signals. Switch 16 mixes the positive quadrature input signal (Qp labeled "Q_P" in Figure 1 for readability.) and LO and 2LO signals. Switch 18 mixes the negative quadrature input signal (Qm labeled "Q_M" in Figure 1 for readability.) and LO and 2LO signals. As is well known in the art, sequential circuits (not shown) cause each of the input signals to be sequentially enabled, while at the same time rendering the others inoperative: Ip, Qp, Im, Qm, Ip, Qp, .. . . . Thus, the mixer output signals OUT_P and OUT_M sequentially display the results of the mixed Ip, Qp, Im, Qm, etc., and the LO and 2LO signals. The architecture of the mixer 10 is sometimes referred to as "LO-2LO."

各個開關12，13，14，15，16，17，18，及19包含至少一傳輸閘，該傳輸閘包含彼此相互並聯的n通道MOS(nMOS)電晶體及p通道MOS(pMOS)電晶體。開關12包含傳輸閘20及傳輸閘32，傳輸閘20包含nMOS電晶體22及pMOS電晶體24，以及傳輸閘32包含nMOS電晶體34及pMOS電晶體36。開關13包含傳輸閘26及傳輸閘50，傳輸閘26包含nMOS電晶體28及pMOS電晶體30，以及傳輸閘50包含nMOS電晶體52及pMOS電晶體54。開關14包含傳輸閘38及傳輸閘32，傳輸閘38包含nMOS電晶體40及pMOS電晶體42，以及傳輸閘32包含nMOS電晶體34及pMOS電晶體36。開關15包含傳輸閘44及傳輸閘50，傳輸閘44包含nMOS電晶體46及pMOS電晶體48，以及傳輸閘50包含nMOS電晶體52及pMOS電晶體54。開關16包含傳輸閘56及傳輸閘68，傳輸閘56包含nMOS電晶體58及pMOS電晶體60，以及傳輸閘68包含nMOS電晶體70及pMOS電晶體72。開關17包含傳輸閘62及傳輸閘86，傳輸閘62包含nMOS電晶體64及pMOS電晶體66，以及傳輸閘86包含nMOS電晶體88及pMOS電晶體90。開關18包含傳輸閘74及傳輸閘68，傳輸閘74包含nMOS電晶體76及pMOS電晶體78，以及傳輸閘68包含nMOS電晶體70及pMOS電晶體72。開關19包含傳輸閘80及傳輸閘86，傳輸閘80包 含nMOS電晶體82及pMOS電晶體84，以及傳輸閘86包含nMOS電晶體88及pMOS電晶體90。注意的是，某些傳輸閘係包含於二個開關之中。Each of the switches 12, 13, 14, 15, 16, 17, 18, and 19 includes at least one transfer gate including n-channel MOS (nMOS) transistors and p-channel MOS (pMOS) transistors connected in parallel with each other. The switch 12 includes a transfer gate 20 including a nMOS transistor 22 and a pMOS transistor 24, and a transfer gate 32 including an nMOS transistor 34 and a pMOS transistor 36. The switch 13 includes a transfer gate 26 including a nMOS transistor 28 and a pMOS transistor 30, and a transfer gate 50 including an nMOS transistor 52 and a pMOS transistor 54. The switch 14 includes a transfer gate 38 and a transfer gate 32. The transfer gate 38 includes an nMOS transistor 40 and a pMOS transistor 42, and the transfer gate 32 includes an nMOS transistor 34 and a pMOS transistor 36. The switch 15 includes a transfer gate 44 and a transfer gate 50. The transfer gate 44 includes an nMOS transistor 46 and a pMOS transistor 48, and the transfer gate 50 includes an nMOS transistor 52 and a pMOS transistor 54. The switch 16 includes a transfer gate 56 and a transfer gate 68. The transfer gate 56 includes an nMOS transistor 58 and a pMOS transistor 60, and the transfer gate 68 includes an nMOS transistor 70 and a pMOS transistor 72. Switch 17 includes a transfer gate 62 that includes an nMOS transistor 64 and a pMOS transistor 66, and a transfer gate 86 that includes an nMOS transistor 88 and a pMOS transistor 90. Switch 18 includes a transfer gate 74 that includes an nMOS transistor 76 and a pMOS transistor 78, and a transfer gate 68 that includes an nMOS transistor 70 and a pMOS transistor 72. The switch 19 includes a transmission gate 80 and a transmission gate 86, and the transmission gate 80 package The nMOS transistor 82 and the pMOS transistor 84 are included, and the transfer gate 86 includes an nMOS transistor 88 and a pMOS transistor 90. Note that some transmission gates are included in the two switches.

LO信號係耦接至電晶體22，24，28，30，40，42，46，48，58，60，64，66，76，78，82，及84的閘極端子；且同時，2LO信號係耦接至電晶體34，36，52，54，70，72，88及90的閘極端子。雖然針對簡明之目的而僅顯示一電容器92，但LO信號係經由多數之該電容器92以耦接至該等閘極端子(在此，省略符號(“...”)係使用以指示未顯示之電路或連接)。同樣地，雖然針對簡明之目的而僅顯示一電容器93，但2LO信號係經由多數之該電容器93以耦接至該等閘極端子。雖然針對簡明之目的而僅顯示一電阻器94，但該等閘極端子亦經由多數之該電阻器94以耦接至固定或恆定的偏壓V_BIAS。可注意的是，上述閘極端子係耦接至各式各樣時移型式的LO及2LO信號，雖然在第1圖中，針對簡明之目的，該等信號係單純地標記為“LO”或“2LO”(亦即，並無區別)，但可將其稱作LO_I_P，LO_I_M，LO_Q_M，2LO_P及2LO_M。The LO signal is coupled to the gate terminals of the transistors 22, 24, 28, 30, 40, 42, 46, 48, 58, 60, 64, 66, 76, 78, 82, and 84; and at the same time, the 2LO signal It is coupled to the gate terminals of transistors 34, 36, 52, 54, 70, 72, 88 and 90. Although only one capacitor 92 is shown for the sake of brevity, the LO signal is coupled to the gate terminals via a plurality of capacitors 92 (here, the ellipsis ("...") is used to indicate that no display is shown. Circuit or connection). Similarly, although only one capacitor 93 is shown for the sake of brevity, the 2LO signal is coupled to the gate terminals via a plurality of capacitors 93. Although only one resistor 94 is shown for the sake of brevity, the gate terminals are also coupled via a majority of the resistors 94 to a fixed or constant bias voltage V_BIAS. It can be noted that the above-mentioned gate terminals are coupled to various time-shifted LO and 2LO signals, although in Figure 1, for the sake of brevity, the signals are simply labeled "LO" or "2LO" (ie, no difference), but can be referred to as LO_I_P, LO_I_M, LO_Q_M, 2LO_P and 2LO_M.

包含pMOS電晶體可促進線性開關操作。熟知的是，藉由以大於nMOS電晶體大約三倍來定pMOS電晶體尺寸於各個傳輸閘之中，可使傳輸閘實質線性地開關(亦即，使傳輸閘電阻線性)於一般使用在直接轉換式無線電接收器及發射器中之混波器中所使用的電壓範圍之上。若pMOS電晶體並不存在(亦即，僅nMOS電晶體存在)或並未以此方式來定尺寸時，且若並耒探取其他措施以促進線性操作時，則由於開關之間的寄生電容，開關切換將易於非線性操作．在非線性操作中，由於該等電容的．充電時間，所以自一輸出信號Ip，Qp，Im，Qm，等等，至順序中之下一者的變遷時間將根據該等信號的電壓。也就是說，寄生電容的前一電壓狀態會引入記憶效應，而為非線性之 根源。The inclusion of a pMOS transistor facilitates linear switching operation. It is well known that by setting the pMOS transistor size into the respective transfer gates by about three times larger than the nMOS transistor, the transfer gate can be substantially linearly switched (that is, the transmission gate resistance is linear) for general use in direct use. Above the voltage range used in the converters in switched radio receivers and transmitters. If the pMOS transistor does not exist (ie, only the nMOS transistor is present) or is not sized in this way, and if other measures are taken to facilitate linear operation, then due to parasitic capacitance between the switches Switching will be easy to operate nonlinearly. In nonlinear operation, due to the capacitance of the capacitor. Charging time, so the transition time from one of the output signals Ip, Qp, Im, Qm, etc., to one of the following will be based on the voltage of the signals. In other words, the previous voltage state of the parasitic capacitance introduces a memory effect and is nonlinear. source.

已敘述用以改善開關線性的其他技術，例如將開關電晶體之源極端子處的信號回授至nMOS電晶體之閘極以使閘極電壓隨耜於源極電壓，使得閘極對源極電壓幾乎恆定。惟，此“回授”或“自舉”技術無法提供良好的結果於使用在某些直接轉換式無線電接收器及發射器中的被動混波器類型之中，因為在混波器操作之期間，對稱之CMOS電晶體的源極及汲極端子電壓會互相交換，亦即，互相切換。Other techniques for improving the linearity of the switch have been described, such as feeding back the signal at the source terminal of the switching transistor to the gate of the nMOS transistor such that the gate voltage follows the source voltage, causing the gate to source The voltage is almost constant. However, this "feedback" or "bootstrap" technique does not provide good results for use in passive mixer types in some direct conversion radio receivers and transmitters, as it is during operation of the mixer. The source and the 汲 terminal voltages of the symmetrical CMOS transistor are exchanged, that is, switched to each other.

本發明之實施例有關開關系統及方法，其中包含與對應開關的開關電路相似之電晶體電路的複製電路藉由調整電晶體閘極偏壓，而使該開關的操作線性化，亦即，使開關電阻線性化於開關之期問。在本發明之代表性實施例中，開關回應於開關信號而切換於至少二信號之，間。例如，該開關可為無線電接收器或發射器中之混波器，其混波一或更多個本地振盪器信號與接收之信號，而成為部分之向下轉換或相似的步驟。在混波器中，本地振盪器信號扮演開關信號之角色。 例如，在正交混波器之中，開關切換於其間以回應於該等本地振盪器信號的信號包含正的同相(Ip)信號，負的同相(In)信號，正的正交(Qp)信號，及負的正交(Qm)信號(如在此所使用地，在該等信號名稱中之“p”表示差動信號的“正”或“+”側，以及“m”表示“負”或“-”側。)。該開關具有一或更多個開關元件，各個開關元件包含包括至少一開關電晶體之︸或更多個電晶體，該開關電晶體可回應於開關信號而開啟及關閉。例如，在正交混波器之中，可具有Ip、Im、Qp及Qm開關元件。 複製電路產生偏壓，該偏壓被施加至開關電晶體的閘極端子或其他控制端子以促進線性開關操作。本發明之實施例可包含任何數目的開關，各個開關具有任何數目的開關元件。各個開關元件可具有任何數目的電晶體。在具有超過一開關元件的實施例中，可具有用於各個開 關元件之對應的複製電路。Embodiments of the present invention relate to a switching system and method, wherein a replica circuit including a transistor circuit similar to a switching circuit of a corresponding switch linearizes operation of the switch by adjusting a transistor gate bias, that is, The switch resistance is linearized during the switch. In a representative embodiment of the invention, the switch is switched between at least two signals in response to the switching signal. For example, the switch can be a mixer in a radio receiver or transmitter that mixes one or more local oscillator signals with the received signal to become a partial down conversion or similar step. In the mixer, the local oscillator signal acts as a switching signal. For example, in a quadrature mixer, a switch is switched between signals in response to the local oscillator signals including a positive in-phase (Ip) signal, a negative in-phase (In) signal, and a positive quadrature (Qp). Signal, and negative quadrature (Qm) signals (as used herein, "p" in the signal names indicate the "positive" or "+" side of the differential signal, and "m" indicates "negative" Or "-" side.). The switch has one or more switching elements, each of which includes one or more transistors including at least one switching transistor that can be turned on and off in response to the switching signal. For example, among the orthogonal mixers, there may be Ip, Im, Qp, and Qm switching elements. The replica circuit generates a bias voltage that is applied to the gate terminal or other control terminal of the switching transistor to facilitate linear switching operation. Embodiments of the invention may include any number of switches, each having any number of switching elements. Each switching element can have any number of transistors. In embodiments having more than one switching element, there may be The corresponding copy circuit of the component.

在本發明之代表性實施例中，複製電路包含複製之開關元件電路，參考電阻，及運算放大器(op-amp)電路。複製之開關元件電路具有與對應之開開元件的該等電晶體相對應之一或更多個電晶體(如在此於有關代表性實施例之此情況中所使用之“對應”意指的是，複製之開關元件電路的電晶體係以實質相同於開關元件之該等電晶體的配置而配置，且係與該開關元件之該等電晶體的尺寸及構造實質地相同，或係該開關元件之該等電晶體的縮放型式。)。在各情況中，複製之開關元件的電晶體電路複製或相似於該開關之開關元件的電晶體電路(“複製”之用語並不打算意指二電路係完全地相同)。同樣地，參考電阻具有對應於開關元件之電阻的值(亦即，實質地相同或係縮放型式)。該參考電阻具有耦接至複製之開關元件電路的第一端子之第一端子。op-amp電路具有耦接至參考電阻之第二端子的第一輸入，耦接至複製之開關元件電路的第二端子之第二輸入，以及耦接至開關電晶體之控制端子及複製之開關元件電路的對應控制端子之輸出。In a representative embodiment of the invention, the replica circuit includes a replicated switching element circuit, a reference resistor, and an operational amplifier (op-amp) circuit. The replicated switching element circuit has one or more transistors corresponding to the transistors of the corresponding open element (as used herein in the context of the representative embodiment) That is, the electro-optic system of the replicated switching element circuit is configured substantially the same as the configuration of the transistors of the switching element, and is substantially the same as the size and configuration of the transistors of the switching element, or is the switch The scaled version of the transistors of the component.). In each case, the transistor circuit of the replicated switching element replicates or resembles the transistor circuit of the switching element of the switch (the term "copy" is not intended to mean that the two circuit systems are completely identical). Likewise, the reference resistor has a value corresponding to the resistance of the switching element (ie, substantially the same or a scaled version). The reference resistor has a first terminal coupled to the first terminal of the replicated switching element circuit. The op-amp circuit has a first input coupled to the second terminal of the reference resistor, a second input coupled to the second terminal of the replicated switching element circuit, and a control terminal coupled to the switching transistor and the replicated switch The output of the corresponding control terminal of the component circuit.

當查驗以下圖式以及詳細說明時，本發明之其他的系統、方法、特性、及優點將呈現或變成明顯於熟習本項技藝之人土。Other systems, methods, features, and advantages of the present invention will be apparent or become apparent to those skilled in the art.

10‧‧‧混波器10‧‧‧Mixer

12，13，14，15，16，17，18，19‧‧‧開關12,13,14,15,16,17,18,19‧‧

20，32，26，56，68，62，86，74，80，136，138，50，38，44‧‧‧傳輸閘20,32,26,56,68,62,86,74,80,136,138,50,38,44‧‧‧transmission gate

92，93，110，111‧‧‧電容器92,93,110,111‧‧‧ capacitor

94，112，194，196，178，180，182，184，186，188，190，192‧‧‧電阻器94,112,194,196,178,180,182,184,186,188,190,192‧‧‧Resistors

22，24，28，30，40，42，46，48，58，60，64，66，76，78，82，84，34，36，52，54，70，72，88，90，124，126，154，156，158，160，162，164，166，168，170，172，174，176‧‧‧電晶體22,24,28,30,40,42,46,48,58,60,64,66,76,78,82,84,34,36,52,54,70,72,88,90,124, 126,154,156,158,160,162,164,166,168,170,172,174,176‧‧‧Optoelectronics

100，152‧‧‧開關系統100,152‧‧‧Switch system

102‧‧‧開關102‧‧‧ switch

104，104’，144，146，148，150‧‧‧線性化複製電路104,104',144,146,148,150‧‧‧ linearized replica circuit

106‧‧‧開關電晶體106‧‧‧Switching transistor

108‧‧‧第二電晶體108‧‧‧Second transistor

114‧‧‧複製之開關元件電路114‧‧‧Replicated switching element circuit

116‧‧‧參考電阻116‧‧‧Reference resistor

118，120‧‧‧複製之負戰電阻118,120‧‧‧Replicated negative resistance

122‧‧‧運算放大器(op-amp)電路122‧‧‧Operational Amplifier (op-amp) Circuit

128‧‧‧開關元件128‧‧‧Switching elements

130‧‧‧位準移位器130‧‧‧ position shifter

132‧‧‧開關式op-amp電路132‧‧‧Switching op-amp circuit

134‧‧‧運算放大器(op-amp)134‧‧‧Operational Amplifier (op-amp)

140‧‧‧極性選擇電路140‧‧‧Polar selection circuit

142‧‧‧比較器電路142‧‧‧ Comparator circuit

在圖式內之組件耒必一定按照比例，而是取代地著重於配置，以便清楚地描繪本發明的原理．此外，在該等圖式中，相同的參考符號在不同的視圖中指示對應的部件。Components within the drawings must be proportionate, but instead instead focus on the configuration in order to clearly depict the principles of the invention. In addition, in the drawings, like reference characters refer to the

第1圖係依據先前技藝之正交混波器的方塊圖；第2圖係開關系統的方塊圖，其包含例如第1圖之正交混波器的開關元件及依據本發明代表性實施例之線性化複製電路；第3圖係與第2圖相似，其進一步詳細地顯示代表性之線性化複製電路； 第4圖係與第2圖相似，其顯示選擇性之代表性的線性化複製電路；第5圖係與第3圖相似，其進一步詳細地顯示選擇性之線性化複製電路；以及第6圖係依據本發明代表性實施例之開關系統的方塊圖，該開關系統包含具有由對應之複製電路所線性化的開關元件之正交混波器。1 is a block diagram of a prior art orthogonal mixer; FIG. 2 is a block diagram of a switching system including a switching element such as the orthogonal mixer of FIG. 1 and a representative embodiment in accordance with the present invention a linearized replica circuit; FIG. 3 is similar to FIG. 2, showing a representative linearized replica circuit in further detail; Figure 4 is similar to Figure 2, showing a representative representative linearized replica circuit; Figure 5 is similar to Figure 3, which shows the linearized replica circuit in more detail; and Figure 6 A block diagram of a switching system in accordance with a representative embodiment of the present invention, the switching system including a quadrature mixer having switching elements linearized by corresponding replica circuits.

如第2圖中所描繪地，依據本發明之描繪性或代表性的實施例，如下文所進一步詳細描述之開關系統100可包含例如混波器，其可藉由將執行開關系統100之部分或所有開關功能的開關102耦合至線性化複製電路(LRC)104而被線性化，亦即，使該混波器更線性地開關。雖然混波器或其他的開關系統100可包含任何數目的開關，但由該代表性實施例中之開關102所顯示的部分包含開關電晶體106及第二電晶體108。在具有LO-2LO架構之混波器的情況中，開關電晶體106可為具有LO信號被耦接至閘極端子的任一電晶體，以及第二電晶體108可為對應地具有2LO信號被耦接至閘極端子的任一電晶體。該LO信號係經由電容器110而耦接至開關電晶體106的閘極端子。該2LO信號係經由電容器111而耦接至第二電晶體108的閘極端子。(如在此所使用之“耦接”意指經由零個或更多個中間元件而連接)開關電晶體106的汲極端子係連接至電晶體108的源極端子。開關電晶體106的源極端子係耦接至由開關102所開關之信號IN_A。例如，在正交混波器中，IN_A可為Ip、Qp、Im、及Qm信號之其中任一者。該信號IN_A亦被提供至LRC I04。在依序地自混波器輸入信號(例如，Ip、Qp、Im、Qm，等等)之一者來變遷輸出至下一者的混波器中，由於開關102操作的結果而使混波器變遷於其間之二信號均被提供至LRC 104。因此，雖然信號IN_A係提供至用於開關之開關102，但IN_A及另一信號IN_B二者均 被提供至LRC 104。例如，IN_A可為混波器所變遷至之信號，且同時，IN_B可為混波器變遷自其之信號。根據由IN_A及IN_B所提供之回授，LRC 104產生偏壓信號V_BIAS。該偏壓信號V_BIAS係經由電阻器112而耦接至開關電晶體106的閘極端子，以便促進開關電晶體106之操作的線性化。As depicted in FIG. 2, in accordance with a descriptive or representative embodiment of the present invention, switching system 100, as described in further detail below, can include, for example, a mixer that can be implemented by a portion of switching system 100 The switch 102 of all or all of the switching functions is coupled to the linearization replica circuit (LRC) 104 to be linearized, i.e., the mixer is more linearly switched. While the mixer or other switching system 100 can include any number of switches, the portion shown by the switch 102 in the representative embodiment includes the switching transistor 106 and the second transistor 108. In the case of a mixer having an LO-2LO architecture, the switching transistor 106 can be any transistor having an LO signal coupled to a gate terminal, and the second transistor 108 can have a 2LO signal correspondingly Any transistor coupled to the gate terminal. The LO signal is coupled to the gate terminal of switching transistor 106 via capacitor 110. The 2LO signal is coupled to the gate terminal of the second transistor 108 via the capacitor 111. (As used herein, "coupled" means connected via zero or more intermediate elements) the 汲 terminal of the switching transistor 106 is connected to the source terminal of the transistor 108. The source terminal of the switching transistor 106 is coupled to the signal IN_A that is switched by the switch 102. For example, in a quadrature mixer, IN_A can be any of the Ip, Qp, Im, and Qm signals. This signal IN_A is also supplied to LRC I04. In the case of one of the self-mixer input signals (eg, Ip, Qp, Im, Qm, etc.), the output is shifted to the next mixer, and the mixing is performed as a result of the operation of the switch 102. The two signals that are transitioned between them are supplied to the LRC 104. Therefore, although the signal IN_A is supplied to the switch 102 for the switch, both the IN_A and the other signal IN_B are It is provided to the LRC 104. For example, IN_A can be the signal to which the mixer is shifted, and at the same time, IN_B can be the signal from which the mixer changes. The LRC 104 generates a bias signal V_BIAS based on the feedback provided by IN_A and IN_B. The bias signal V_BIAS is coupled to the gate terminal of the switching transistor 106 via a resistor 112 to facilitate linearization of operation of the switching transistor 106.

如第3圖中所描繪地，LRC 104包含複製之開關元件電路114，參考電阻116，複製之負戰電阻118及120，以及運算放大器(op-amp)電路122。負載電阻表示混波器輸出(例如，下文所述之第6圖中的OUT_P及OUT_M)處的平均負載，亦即，在各混波器輸出(例如，OUT_P或OUT_M)處所見到之電容的時間罕均阻抗。負載電阻118及120之電阻係相互相等。複製之開關元件電路114包含電晶體124及126，其係與包含開關電晶體106及第二電晶體108的開關元件128實質地相同，且以實質相同的配置來配置。開關元件128及對應的複製之開關元件電路114各包含二電晶體，因為在代表性實施例中，開關102係部分之LO-2LIO混波器。然而，在其中該開關係另一類型或包含於不同類型的開關系統中之實施例中，開關元件可包含超過二電晶體或少至單一電晶體。As depicted in FIG. 3, LRC 104 includes replicated switching element circuitry 114, reference resistor 116, replicating negative combat resistors 118 and 120, and an operational amplifier (op-amp) circuitry 122. The load resistance represents the average load at the mixer output (eg, OUT_P and OUT_M in Figure 6 below), that is, the capacitance seen at each mixer output (eg, OUT_P or OUT_M) Time is almost average impedance. The resistances of the load resistors 118 and 120 are equal to each other. The replicated switching element circuit 114 includes transistors 124 and 126 that are substantially identical to the switching elements 128 that include the switching transistor 106 and the second transistor 108, and are configured in substantially the same configuration. Switching element 128 and corresponding replicated switching element circuit 114 each comprise a second transistor, as in a representative embodiment, switch 102 is part of a LO-2LIO mixer. However, in embodiments in which the relationship is of another type or is included in a different type of switching system, the switching element may comprise more than two transistors or as few as a single transistor.

參考電阻116具有實質相同於複製之開關元件電路114的電阻，亦即，串聯之電晶體124及126的電阻之值。(如在此所使用之“實質”的用語意指的是，雖然欲使參考電阻116具有與開關元件128之電阻相同的值，但可能無法精確地達成此目標，且參考電阻116的值可大於或小於開關元件128之電阻一數量，而該數量係極小以致不會阻礙電路以所打算的方式夾操作。)該參考電阻116的值亦可被選擇，以確保op-amp電路122的輸出並不會在任何所預期之操作性輸入信號位準處飽和。The reference resistor 116 has substantially the same resistance as the replicated switching element circuit 114, that is, the value of the resistance of the series of transistors 124 and 126. (As used herein, the term "substantial" means that although the reference resistor 116 is to have the same value as the resistance of the switching element 128, this goal may not be accurately achieved and the value of the reference resistor 116 may be Greater than or less than the amount of resistance of switching element 128, which is so small that it does not prevent the circuit from being manipulated in the intended manner.) The value of reference resistor 116 can also be selected to ensure the output of op-amp circuit 122. It does not saturate at any desired operational input signal level.

負載電阻118及120的第一端子係連接在一起，且連接至信號 IN_B。參考電阻116的第一端子係耦接至複製之開關元件電路114的第一端子(特定地，至電晶體124的源極端子)。參考電阻116的第二端子係耦接至op-amp電路122的第一輸入(例如，正的或非反相的輸入)，且至負載電阻118的第二端子。op-amp電路122的第二端子(例如，負的或反相的輸入)係耦接至複製之開關元件電路114的第二端子及負載電阻120的第二端子。op-amp電路122的輸出係耦接至電晶體124的閘極端子。op-amp電路122所輸出之信號係由位準移位器130所先位準偏移，且所偏移的信號係偏壓信號V_BIAS。電晶體126的閘極端子係連接至維持電晶體126於“開啟(on)”狀態中之“高”壓的來源(V_HIGH)。電壓V_HIGH係相同於足以致使第二電晶體108導通之耦接至第二電晶體108的閘極端子處之2LO信號的電壓位準。The first terminals of the load resistors 118 and 120 are connected together and connected to the signal IN_B. The first terminal of the reference resistor 116 is coupled to the first terminal of the replicated switching element circuit 114 (specifically, to the source terminal of the transistor 124). The second terminal of the reference resistor 116 is coupled to a first input (eg, a positive or non-inverting input) of the op-amp circuit 122 and to a second terminal of the load resistor 118. A second terminal (eg, a negative or inverted input) of the op-amp circuit 122 is coupled to the second terminal of the replicated switching element circuit 114 and the second terminal of the load resistor 120. The output of the op-amp circuit 122 is coupled to the gate terminal of the transistor 124. The signal output by the op-amp circuit 122 is offset by the level of the level shifter 130, and the offset signal is the bias signal V_BIAS. The gate terminal of transistor 126 is coupled to a source (V_HIGH) that maintains the "high" voltage of transistor 126 in an "on" state. The voltage V_HIGH is the same as the voltage level of the 2LO signal coupled to the gate terminal of the second transistor 108 that is sufficient to cause the second transistor 108 to conduct.

op-amp電路122包含op-amp，或選擇性地，以與op-amp相似之方式而操作的電路。在操作中，op-amp電路122藉由調整其之輸出信號以使其之輸入端子處的電壓相互相等。因而，跨越複製之開關元件電路114(亦即，跨越串聯之電晶體124及126)的壓降必須等於跨越參考電阻116的壓降。為了要達成此操作之狀態，op-amp電路122的輸出調整電晶體124的閘極電壓，使得複製之開關元件電路114的電阻(亦即，電晶體124及126的串聯電阻)相等於參考電阻116的值。電晶體124之調整的閘極電壓亦施加(經由位準移位器130)至開關電晶體106的閘極端子，做為偏壓V-BIAS。當參考電阻116線性地回應於跨越其之電壓中的改變時，複製之參考元件電路114的電阻同樣線性地回應於跨越其之電壓中的改變。當致使複製之開關元件電路114線性地動作之偏壓V_BIAS亦施加至開關電晶體106時，開關電晶體106及其之開關元件128同樣線性地動作。The op-amp circuit 122 includes an op-amp, or alternatively, a circuit that operates in a similar manner to op-amp. In operation, the op-amp circuit 122 adjusts its output signal such that the voltages at its input terminals are equal to each other. Thus, the voltage drop across the replicated switching element circuit 114 (i.e., across the series of transistors 124 and 126) must be equal to the voltage drop across the reference resistor 116. In order to achieve this state of operation, the output of the op-amp circuit 122 adjusts the gate voltage of the transistor 124 such that the resistance of the replicated switching element circuit 114 (i.e., the series resistance of the transistors 124 and 126) is equal to the reference resistance. The value of 116. The adjusted gate voltage of transistor 124 is also applied (via level shifter 130) to the gate terminal of switching transistor 106 as bias voltage V-BIAS. When reference resistor 116 linearly responds to a change in voltage across it, the resistance of replicaped reference component circuit 114 also responds linearly to changes in the voltage across it. When the bias voltage V_BIAS causing the replicated switching element circuit 114 to operate linearly is also applied to the switching transistor 106, the switching transistor 106 and its switching element 128 also operate linearly.

如第4及5圖中所描繪地，在其他的實施例中，開關式op-amp電路132可包含於相似的LRC I04’中，而取代op-amp電路122(第3圖)。 op-amp電路122係以上述方式操作，只要信號IN_A大於信號IN_B即可。然而，在諸如其中開關系統係上述類型之被動混波器的實施例之一些情況中，信號IN_A可偶爾大於信號IN_B，而在其他的時間，信號IN_B則可大於信號IN_A。當IN_B大於IN_A時，電流方向會反向，且電路產生正的而非負的回授，而阻礙op-amp電路122逵成其中複製之開關元件電路114的電阻相等於參考電阻116之值的狀態。在第5圖中所示的實施例中，開關式op-amp電路132包含額外的電路，該電路輸出具有極性的信號，而該極性係根據IN_A及IN_B之何者較大而定。As depicted in Figures 4 and 5, in other embodiments, the switched op-amp circuit 132 can be included in a similar LRC I04' instead of the op-amp circuit 122 (Fig. 3). The op-amp circuit 122 operates in the above manner as long as the signal IN_A is greater than the signal IN_B. However, in some cases, such as embodiments in which the switching system is a passive mixer of the type described above, the signal IN_A may occasionally be greater than the signal IN_B, while at other times, the signal IN_B may be greater than the signal IN_A. When IN_B is greater than IN_A, the current direction is reversed, and the circuit produces a positive rather than a negative feedback, and the op-amp circuit 122 is prevented from being in a state in which the resistance of the switching switching element circuit 114 is equal to the value of the reference resistor 116. . In the embodiment shown in FIG. 5, the switched op-amp circuit 132 includes an additional circuit that outputs a signal having a polarity that is dependent on which of IN_A and IN_B is larger.

開關式op-amp電路包含：op-amp 134，或選擇性地，以與op-amp相似之方式而操作的電路：二傳輸閘136及138，其形成極性選擇電路140；以及比較器電路142。比較器電路142可包含比較器，op-amp，或可決定二信號的何者較大之相似的電路。比較器電路142之一輸入(例如，正的或非反相的輸入)係耦接至信號IN_A，且比較器電路142之另一輸入(例如，負的或反相的輸入)係耦接至信號IN_B。若信號IN_A大於信號IN_B時，比較器電路142使其之正的或非反相的輸出起作用，且使其之負的或反相的輸出不起作用。若信號IN_B大於信號IN_A時，比較器電路142使其之負的或反相的輸出起作用，且使其之正的或非反相的輸出不起作用。比較器電路142之正的或非反相的輸出係竊接至各個傳輸閘之一電晶體的閘極端子，以及比較器電路142之負的或反相的輸出係耦接至各個傳輸閘之另一電晶體的閘極端子。 極性選擇電路140具有耦接至op-amp 134之正的或非反相的輸出之第一輸入，以及耦接至op-amp 134之負的或反相的輸出之第二輸入。因此，若比較器電路142決定IN_A大於IN_B時，則來自比較器電路142的輸出信號閉合或激活傳輸閘136，藉以邋過由op-amp 134之正的或非反相的輸出所提供之信號，以及打開或去激活傳輸閘138，藉以阻 擋由op-amp 134之負的或反相的輸出所提供之信號。相反地，若比較器電路142決定IN_B大於IN_A時，則來自比較器電路142的輸出信號閉合或激活傳輸閘136，藉以通過由op-amp 134之正的或非反相的輸出所提供之信號，以及打開或去激活傳輸閘138，藉以阻擋由op-amp 134之負的或反相的輸出所提供之信號。極性選擇電路140所通過之信號(藉由傳輸閘136及138之上述操作)係提供做為偏壓信號V_BIAS(經由位準移位器130)。The switched op-amp circuit includes: op-amp 134, or alternatively, a circuit that operates in a similar manner to op-amp: two transfer gates 136 and 138 that form polarity selection circuit 140; and comparator circuit 142 . Comparator circuit 142 may include a comparator, op-amp, or a similar circuit that may determine which of the two signals is larger. One input (eg, a positive or non-inverting input) of comparator circuit 142 is coupled to signal IN_A, and another input (eg, a negative or inverted input) of comparator circuit 142 is coupled to Signal IN_B. If signal IN_A is greater than signal IN_B, comparator circuit 142 causes its positive or non-inverted output to function and its negative or inverted output to be inactive. If signal IN_B is greater than signal IN_A, comparator circuit 142 causes its negative or inverted output to function and its positive or non-inverted output to be inactive. The positive or non-inverting output of the comparator circuit 142 is stalked to the gate terminal of one of the transistors of the respective transfer gate, and the negative or inverted output of the comparator circuit 142 is coupled to each of the transfer gates. The gate terminal of another transistor. The polarity selection circuit 140 has a first input coupled to the positive or non-inverted output of the op-amp 134 and a second input coupled to the negative or inverted output of the op-amp 134. Thus, if comparator circuit 142 determines that IN_A is greater than IN_B, then the output signal from comparator circuit 142 closes or activates transfer gate 136, thereby bypassing the signal provided by the positive or non-inverted output of op-amp 134. And opening or deactivating the transfer gate 138 to block The signal provided by the negative or inverted output of op-amp 134. Conversely, if comparator circuit 142 determines that IN_B is greater than IN_A, then the output signal from comparator circuit 142 closes or activates transmission gate 136, thereby passing the signal provided by the positive or non-inverted output of op-amp 134. And opening or deactivating the transfer gate 138 to block the signal provided by the negative or inverted output of the op-amp 134. The signals passed by the polarity selection circuit 140 (as described above by the transfer gates 136 and 138) are provided as a bias signal V_BIAS (via the level shifter 130).

如第6圖中所描繪地，關於第2至5圖之上述類型(例如，LRC 104或104’)的LRC 144，146，148，及150可使用於包含若干無線電接收器中所使用類型之正交混波器的開關系統152之中。注意的是，開關系統152僅包含nMOS電晶體154，156，158，160，162，164，166，168，170，172，174，及176，且並不包含pMOS電晶體。pMOS電晶體的使用可增加負載至產生LO及2LO信號且因而，電流之電路(未顯示)。所欲的是，使諸如無線電路手機之攜帶式無線電接收器中的電流最小化，以便使電池的消耗最小化。因此，在第6圖中所示的實施例中，混波器的開關元件不包含pMOS。當LRC 144，146，148，及150促進線性開關操作時，並不需要pMOS以供該目的之用。As depicted in Figure 6, the LRCs 144, 146, 148, and 150 of the above type (e.g., LRC 104 or 104') of Figures 2 through 5 can be used to include the types used in several radio receivers. Among the switching systems 152 of the quadrature mixer. It is noted that the switching system 152 includes only nMOS transistors 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, and 176 and does not include a pMOS transistor. The use of a pMOS transistor increases the load to a circuit that produces LO and 2LO signals and, therefore, current (not shown). It is desirable to minimize the current in a portable radio receiver such as a wireless circuit handset in order to minimize battery drain. Therefore, in the embodiment shown in Fig. 6, the switching elements of the mixer do not contain pMOS. When LRC 144, 146, 148, and 150 facilitate linear switching operations, pMOS is not required for this purpose.

開關系統152具有LO-2LO架構，該架構係大致類似於有關第1圖之上述架構，除了電晶體154，156，158，160，162，164，166，及168之閘極端子係耦接至LRC 144，146，148，及150以提供偏壓V_BIAS，而取代固定或恆定的偏壓之外。更特定地，電晶體154及156的閘極端子係經由電阻器178及180而分別耦接至LRC 144；電晶體158及160的閘極端子係經由電阻器182及184而分別耦接至LRC 146；電晶體162及164的閘極端子係經由電阻器186及188而分別耦接至LRC 148；以及電晶體166及168的閘極端子係經由電阻器190及192而分別耦接至LRC 150。雖然針對簡明之緣故而僅顯示一電容器 194，但LO信號係經由對應的電容器194而耦接至電晶體154，156，158，160，162，164，166，及168的閘極端子。同樣地，雖然針對簡明之緣故而僅顯示一電容器196，但2LO信號係經由其他的電容器196而耦接至電晶體170，172，174，及176的閘極端子。雖然在第6圖中，針對簡明之緣故，僅標記所有該等信號為“LO”及“2LO”(亦即，無區別)，但可注意的是，該等閘極端子係耦接至可稱作LO_I_P，LO_I_M，LO_Q_P，LO_Q_M，2LO_P，及2LO_M之各式各樣時移型式的LO及2LO信號。熟習於本項技藝之人土應熟悉該等信號及其時序關係，且將能立即提供合適的電路，以供產生該等信號且提供它們至適當電晶體之用。Switching system 152 has an LO-2LO architecture that is substantially similar to the above-described architecture of Figure 1, except that the gate terminals of transistors 154, 156, 158, 160, 162, 164, 166, and 168 are coupled to LRCs 144, 146, 148, and 150 provide a bias voltage V_BIAS instead of a fixed or constant bias voltage. More specifically, the gate terminals of the transistors 154 and 156 are respectively coupled to the LRC 144 via resistors 178 and 180; the gate terminals of the transistors 158 and 160 are coupled to the LRC via resistors 182 and 184, respectively. 146; the gate terminals of the transistors 162 and 164 are respectively coupled to the LRC 148 via resistors 186 and 188; and the gate terminals of the transistors 166 and 168 are coupled to the LRC 150 via resistors 190 and 192, respectively. . Although only one capacitor is shown for the sake of simplicity 194, but the LO signal is coupled to the gate terminals of transistors 154, 156, 158, 160, 162, 164, 166, and 168 via corresponding capacitors 194. Similarly, although only one capacitor 196 is shown for simplicity, the 2LO signal is coupled to the gate terminals of transistors 170, 172, 174, and 176 via other capacitors 196. Although in Figure 6, for the sake of brevity, only all of the signals are labeled "LO" and "2LO" (ie, no difference), it may be noted that the gate terminals are coupled to The various LO and 2LO signals are called LO_I_P, LO_I_M, LO_Q_P, LO_Q_M, 2LO_P, and 2LO_M. Those skilled in the art should be familiar with the signals and their timing relationships and will be able to immediately provide suitable circuitry for generating such signals and providing them to the appropriate transistors.

雖然已敘述本發明之各式各樣的實施例，但對於一般熟習於本項技藝之該等人士而言，將呈明顯的是，在本發明範疇之內的更多實施以及施行係可能的。因而，除非依照下文之申請專利範圍，否則本發明不應受到限制。Having described various embodiments of the present invention, it will be apparent to those skilled in the art of the present invention that further implementations within the scope of the present invention are possible. . Thus, the invention should not be limited unless it is in accordance with the scope of the claims below.

10‧‧‧混波器10‧‧‧Mixer

12，13，14，15，16，17，18，19‧‧‧開關12,13,14,15,16,17,18,19‧‧

20，32，26，56，68，62，86，74，80，50，38，44‧‧‧傳輸閘20,32,26,56,68,62,86,74,80,50,38,44‧‧‧Transmission gate

92，93‧‧‧電容器92,93‧‧‧ capacitor

94‧‧‧電阻器94‧‧‧Resistors

22，24，28，30，40，42，46，48，58，60，64，66，76，78，82，84，34，36，52，54，70，72，88，90‧‧‧電晶體22,24,28,30,40,42,46,48,58,60,64,66,76,78,82,84,34,36,52,54,70,72,88,90‧‧ Transistor

OUT_P，OUT_M‧‧‧混波器輸出信號OUT_P, OUT_M‧‧‧ mixer output signal

Claims (20)

一種開關系統，包含：一開關，其包括一或多個電晶體及一控制端子；及一包括一參考電阻之線性化電路、一具有一或多個電晶體之複製開關元件電路、及一電耦接至該開關之該控制端子之開關控制輸出，該線性化電路提供一複製控制信號至該複製開關元件電路，以控制該複製開關元件電路以維持跨越該複製開關元件電路之壓降在對應於跨越該參考電阻之壓降之一位準，該開關控制輸出回應於該複製控制信號從而促進該開關之線性操作。 A switching system comprising: a switch comprising one or more transistors and a control terminal; and a linearization circuit including a reference resistor, a replica switching element circuit having one or more transistors, and an electric a switching control output coupled to the control terminal of the switch, the linearization circuit providing a copy control signal to the replica switching element circuit to control the replica switching element circuit to maintain a voltage drop across the replica switching element circuit The switch control output is responsive to the copy control signal to facilitate linear operation of the switch at a level across the voltage drop of the reference resistor. 如請求項1之開關系統，其中該開關僅包括nMOS電晶體且不包括任何pMOS電晶體。 A switching system as claimed in claim 1, wherein the switch comprises only nMOS transistors and does not include any pMOS transistors. 如請求項2之開關系統，其中該複製開關元件電路僅包括nMOS電晶體且不包括任何pMOS電晶體。 A switching system as claimed in claim 2, wherein the replica switching element circuit comprises only nMOS transistors and does not include any pMOS transistors. 如請求項2之開關系統，其中該開關控制輸出將該複製控制信號之一位準偏移版本提供至該開關之該控制端子。 The switching system of claim 2, wherein the switch control output provides a level offset version of the copy control signal to the control terminal of the switch. 如請求項1之開關系統，其中該線性化電路進一步包括一經組態以提供該複製控制信號之運算放大器。 The switching system of claim 1, wherein the linearization circuit further comprises an operational amplifier configured to provide the copy control signal. 如請求項5之開關系統，其中該運算放大器之一第一輸入耦接至該複製開關元件電路之一第一端子，該運算放大器之一第二輸入耦接至該參考電阻之一第一端子，且該運算放大器之一輸出經組態以提供該複製控制信號。 The switching system of claim 5, wherein a first input of the operational amplifier is coupled to a first terminal of the replica switching element circuit, and a second input of the operational amplifier is coupled to the first terminal of the reference resistor And one of the operational amplifier outputs is configured to provide the copy control signal. 如請求項6之開關系統，其中該開關經組態以回應於一射頻接收器電路或傳輸器電路之一本地震盪器(LO)信號及一倍頻本地震盪器(2LO)信號而切換。 The switching system of claim 6, wherein the switch is configured to switch in response to the one of the radio frequency receiver circuit or the transmitter circuit, the local oscillator (LO) signal and the one frequency local oscillator (2LO) signal. 如請求項7之開關系統，其中該開關系統形成一正交混波器(quadrature mixer)之部分。 The switching system of claim 7, wherein the switching system forms part of a quadrature mixer. 如請求項8之開關系統，其中該正交混波器經組態以接收複數個混波器輸入信號，該等混波器輸入信號包括一正的同相(Ip)信號、一負的同相(Im)信號、一正的正交(Op)信號、及一負的正交(Om)信號，該正交混波器進一步經組態以將該混波器輸入信號與該LO及2LO信號混波以產生對應之複數個經混波輸出信號，且在該正交混波器之一輸出依序輸出該等經混波輸出信號。 The switching system of claim 8, wherein the quadrature mixer is configured to receive a plurality of mixer input signals comprising a positive in-phase (Ip) signal, a negative in-phase ( Im) a signal, a positive quadrature (Op) signal, and a negative quadrature (Om) signal, the quadrature mixer being further configured to mix the mixer input signal with the LO and 2LO signals The wave generates a corresponding plurality of mixed wave output signals, and sequentially outputs the mixed output signals at one of the outputs of the orthogonal mixer. 如請求項5之開關系統，其中該開關之該一或多個電晶體對應於該複製開關元件電路之該一或多個電晶體。 The switching system of claim 5, wherein the one or more transistors of the switch correspond to the one or more transistors of the replica switching element circuit. 一種無線裝置，其包含：一射頻天線；一射頻傳輸器，其耦接至該天線；及一射頻接收器，其耦接至該天線且包括一開關系統，該開關系統包括一具有一或多個電晶體及一控制端子之開關，該開關系統進一步包括一包括一參考電阻之線性化電路、一具有一或多個電晶體之複製開關元件電路、及一電耦接至該開關之該控制端子之開關控制輸出，該線性化電路提供一複製控制信號至該複製開關元件電路，以控制該複製開關元件電路以維持跨越該複製開關元件電路之壓降在對應於跨越該參考電阻之壓降之一位準，該開關控制輸出回應於該複製控制信號從而促進該開關元件電路之線性操作。 A wireless device, comprising: a radio frequency antenna; an RF transmitter coupled to the antenna; and a radio frequency receiver coupled to the antenna and including a switching system, the switching system including one or more a switch of a transistor and a control terminal, the switch system further comprising a linearization circuit including a reference resistor, a replica switch component circuit having one or more transistors, and a control electrically coupled to the switch a switch control output of the terminal, the linearization circuit providing a copy control signal to the replica switch element circuit to control the replica switch element circuit to maintain a voltage drop across the replica switch element circuit corresponding to a voltage drop across the reference resistor At one level, the switch control output is responsive to the copy control signal to facilitate linear operation of the switching element circuit. 如請求項11之無線裝置，其中該開關及該複製開關元件電路僅包括nMOS電晶體且不包括任何pMOS電晶體。 The wireless device of claim 11, wherein the switch and the replica switching element circuit comprise only nMOS transistors and do not include any pMOS transistors. 如請求項12之無線裝置，其中該開關控制輸出將該複製控制信號之一位準偏移版本提供至該開關之該控制端子。 The wireless device of claim 12, wherein the switch control output provides a level offset version of the copy control signal to the control terminal of the switch. 如請求項11之無線裝置，其中該線性化電路進一步包括一經組態以提供該複製控制信號之運算放大器。 The wireless device of claim 11, wherein the linearization circuit further comprises an operational amplifier configured to provide the copy control signal. 如請求項14之無線裝置，其中該運算放大器之一第一輸入耦接至該複製開關元件電路之一第一端子，該運算放大器之一第二輸入耦接至該參考電阻之一第一端子，且該運算放大器之一輸出經組態以提供該複製控制信號。 The wireless device of claim 14, wherein a first input of the operational amplifier is coupled to a first terminal of the replica switching element circuit, and a second input of the operational amplifier is coupled to the first terminal of the reference resistor And one of the operational amplifier outputs is configured to provide the copy control signal. 如請求項11之無線裝置，其中該開關經組態以回應於一射頻接收器電路或傳輸器電路之一或多個本地震盪器信號而切換。 The wireless device of claim 11, wherein the switch is configured to switch in response to one or more of the present antenna signals of a radio frequency receiver circuit or a transmitter circuit. 如請求項16之無線裝置，其中該開關經組態以回應於一射頻接收器電路或傳輸器電路之一本地震盪器(LO)信號及一倍頻本地震盪器(2LO)信號而切換。 The wireless device of claim 16, wherein the switch is configured to switch in response to a single oscillator (LO) signal and a frequency double present (2LO) signal of a radio frequency receiver circuit or a transmitter circuit. 如請求項17之無線裝置，其中該開關系統形成一正交混波器之部分。 The wireless device of claim 17, wherein the switching system forms part of a quadrature mixer. 如請求項17之無線裝置，其中該正交混波器經組態以接收複數個混波器輸入信號，該等混波器輸入信號包括一正的同相(Ip)信號、一負的同相(Im)信號、一正的正交(Op)信號、及一負的正交(Om)信號，以將該混波器輸入信號與該LO及2LO信號混波以產生對應之複數個經混波輸出信號，且依序輸出該等經混波輸出信號。 The wireless device of claim 17, wherein the quadrature mixer is configured to receive a plurality of mixer input signals comprising a positive in-phase (Ip) signal, a negative in-phase ( Im) a signal, a positive quadrature (Op) signal, and a negative quadrature (Om) signal to mix the mixer input signal with the LO and 2LO signals to produce a corresponding plurality of mixed waves The signals are output, and the mixed output signals are sequentially output. 一種正交混波器，其包含：一輸入級，其具有四個輸入，該四個輸入之每一者經組態以接收一正的同相(Ip)信號、一負的同相(Im)信號、一正的正交(Op)信號、及一負的正交(Om)信號之相對應一者；四個開關單元，其每一者對應於該四個輸入之一個別者，該等開關單元之每一者包括一具有一或多個電晶體及一控制端子之開關，該等開關單元之每一者進一步包括一具有一參考電阻 之線性化電路、具有一或多個電晶體之複製開關元件電路、及一電耦接至該開關之該控制端子之開關控制輸出，該線性化電路提供一複製控制信號至該複製開關元件電路，以控制該複製開關元件電路以維持跨越該複製開關元件電路之壓降在對應於跨越該參考電阻之壓降之一位準，該開關控制輸出回應於在該開關控制輸出上之該複製控制信號從而促進該開關之線性操作；及一輸出級，其耦接至該四個開關單元且依序提供對應於該四個輸入之經混波輸出信號。 A quadrature mixer comprising: an input stage having four inputs, each of the four inputs configured to receive a positive in-phase (Ip) signal, a negative in-phase (Im) signal a positive orthogonal (Op) signal, and a negative orthogonal (Om) signal corresponding to one; four switching units, each of which corresponds to one of the four inputs, the switches Each of the units includes a switch having one or more transistors and a control terminal, each of the switch units further including a reference resistor a linearization circuit, a replica switching element circuit having one or more transistors, and a switch control output electrically coupled to the control terminal of the switch, the linearization circuit providing a copy control signal to the replica switching element circuit Controlling the replica switching element circuit to maintain a voltage drop across the replica switching element circuit at a level corresponding to a voltage drop across the reference resistor, the switch control output responsive to the copy control at the switch control output The signal thereby facilitates linear operation of the switch; and an output stage coupled to the four switch units and sequentially providing a mixed output signal corresponding to the four inputs.
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