TWI447886B

TWI447886B - Multiple patterning method

Info

Publication number: TWI447886B
Application number: TW100103128A
Authority: TW
Inventors: Shih Hung Chen; Hang Ting Lue
Original assignee: Macronix Int Co Ltd
Priority date: 2011-01-27
Filing date: 2011-01-27
Publication date: 2014-08-01
Also published as: TW201232741A

Description

多重圖案化之方法Multiple patterning method

本發明是有關於積體電路之製造，且特別是有關於藉由接受所形成之線材料以協助製造積體電路之多重圖案化方法。This invention relates to the fabrication of integrated circuits, and more particularly to multiple patterning methods that assist in fabricating integrated circuits by accepting the formed line material.

積體電路通常被廣泛用於不同的電氣裝置，例如記憶體晶片。目前對於積體電路尺寸上的微縮減少是極度盼望的，如此一來可增加個別元件的密度，進而增強積體電路的功能。在積體電路上的最小間距(在相同型態之二相鄰結構的相同點之間的距離，例如：二相鄰閘極導體)通常被用來當成電路密度的代表度量。Integrated circuits are commonly used in a variety of electrical devices, such as memory chips. At present, it is highly desirable for the reduction of the size of the integrated circuit to increase the density of individual components, thereby enhancing the function of the integrated circuit. The minimum spacing on the integrated circuit (the distance between the same points of the adjacent structures of the same type, such as two adjacent gate conductors) is typically used as a representative measure of circuit density.

增加電路密度通常受限於黃光微影設備的解析度。黃光微影設備之一給定部所能製作的最小尺寸特徵和空間係和此黃光微影設備的解析度能力相關。Increasing the circuit density is usually limited by the resolution of the yellow lithography device. The minimum size feature and space system that can be produced by a given portion of the yellow light lithography device is related to the resolution capability of the yellow lithography device.

黃光微影設備之給定部所能製造的最小特徵寬度和最小空間寬度之總合係為此設備可製造的最小間距。最小特徵寬度通常可大約為最小空間的數倍，因此由黃光微影設備之給定部所製造的最小間距係大約二倍於黃光微影設備可製造出的最小特徵。The sum of the minimum feature width and the minimum space width that can be made by a given portion of the yellow lithography apparatus is the minimum spacing that can be made for this device. The minimum feature width is typically about a multiple of the minimum space, so the minimum spacing produced by a given portion of the yellow lithography apparatus is about twice the smallest feature that can be fabricated by a yellow lithography apparatus.

用來減少小於微影製造最小間距的積體電路裝置之間距的一個方法是通過二倍或四倍圖案化的使用，在此通常稱為多重圖案化。通過此方法，一單一光罩被用來在基板上製作一系列的平行線材料。接著，可用不同方法將每一平行線材料轉變為多重平行線材料。這些各種不同的方法通常是使用一系列的沉積和蝕刻步驟來執行。這些方法係已於Xie、Peng、以及Smith、Bruce W等人於2009年SPIE的Optical Microlithography XXII會議所發表的“用於32nm以下的更高等級間距部之分析”中作討論。於下列實施例中所討論的一方法係使用自我對準間隙壁(self aligned sidewall spacer)來製作二或四個平行線材料，其每一線材料係由原本的光罩來製作。One method for reducing the spacing between integrated circuit devices that are smaller than the minimum spacing of lithography fabrication is through the use of double or quadruple patterning, commonly referred to herein as multiple patterning. In this way, a single reticle is used to make a series of parallel line materials on the substrate. Next, each parallel line material can be converted into multiple parallel line materials in different ways. These various different methods are typically performed using a series of deposition and etching steps. These methods are discussed in Xie, Peng, and by Smith and Bruce W et al., "Analysis of Higher Gradient Parts Below 32 nm", published at the SPIE Optical Microlithography XXII conference in 2009. One method discussed in the following examples uses two self-aligning spacers to make two or four parallel line materials, each of which is made from an original reticle.

本發明係根據部分藉由將間距減少至次微影尺寸(sub lithographic dimension)的問題之確認為基礎。這就是說，即使位於線材料之間的間距可能是次微影尺寸，然而一般要接受這些線所要通過的一接收元件，例如一垂直栓塞(plug)，可能不是完全符合次微影尺寸。用以定義栓塞的光罩是微影的尺寸，並且，對於允許光罩對準誤差增加了對於接受區所要求的尺寸。The present invention is based on the recognition of a problem in part by reducing the pitch to a sub lithographic dimension. That is to say, even though the spacing between the line materials may be sub-lithographic, it is generally acceptable to accept a receiving element through which the wires are to pass, such as a vertical plug, which may not be fully compliant with the sub-lithographic size. The reticle used to define the plug is the size of the lithography and, for allowing the reticle alignment error, increases the size required for the receiving area.

根據本發明之一實施例之一積體電路記憶體，包括一組線，此組線中的每一條線具有複數個在一第一區中平行X方向線部分物以及複數個在一第二區中平行Y方向線部分物。X方向線部分物之長度係實質上長於Y方向線部分物之長度。X方向和Y方向線部分物各自具有第一和第二間距，第二間距係為第一間距的3倍。接觸區係於Y方向線部分物。在一些實施例中，這些線係為字元線或位元線。According to one embodiment of the present invention, an integrated circuit memory includes a set of lines, each of the set of lines having a plurality of parallel X-directional line portions in a first region and a plurality of second and second Part of the parallel Y direction line in the area. The length of the X-directional line portion is substantially longer than the length of the Y-directional line portion. The X-direction and Y-direction line portions each have a first and a second pitch, and the second pitch is three times the first pitch. The contact area is a part of the Y direction line. In some embodiments, these lines are word lines or bit lines.

在黃光微影積體電路製程步驟中，用於製作線多重圖案化方法之一實施例實施如下。為一組第一線材料選擇一組線圖案。在一基板上形成該組第一線材料。此組第一線材料中的每一第一線材料定義出具有一X方向部分物和一Y方向部分物之一圖案。第一線材料之X方向部分物的長度係實質上長於第一線材料之Y方向部分物的長度。為此些X方向部分物和Y方向部分物選擇複數個第一間距和第二間距，第二間距係大於第一間距。X方向部分物係為平行的，並且Y方向部分物係為平行的。形成平行於每一第一線材料之至少二個第二線材料，以製作出包括複數個平行X方向線部分物和複數個平行Y方向線部分物的複數個字元線。Y方向線部分物之第二線材料包括複數個底端區。複數個附加特徵物(supplemental features)形成於此些底端區之至少部分處。在一些實施例中，第二間距係至少為第一間距的四倍，而在其他實施例中，第二間距係至少為第一間距的八倍。在一些實施例中，形成附加特徵物係包括形成擴大的接觸區(contact pickup area)。In the yellow light micro-integration circuit processing step, an embodiment for fabricating a line multiple patterning method is implemented as follows. A set of line patterns is selected for a set of first line materials. The set of first line materials is formed on a substrate. Each of the first line materials of the set of first line materials defines a pattern having one of an X-direction portion and a Y-direction portion. The length of the X-direction portion of the first wire material is substantially longer than the length of the Y-direction portion of the first wire material. For the X-direction portion and the Y-direction portion, a plurality of first pitches and second pitches are selected, and the second pitch is greater than the first pitch. The X-direction partial systems are parallel, and the Y-direction partial systems are parallel. At least two second line materials parallel to each of the first line materials are formed to form a plurality of word lines including a plurality of parallel X direction line portions and a plurality of parallel Y direction line portions. The second line material of the Y direction line portion includes a plurality of bottom end regions. A plurality of supplementary features are formed at at least a portion of the bottom end regions. In some embodiments, the second pitch is at least four times the first pitch, while in other embodiments, the second pitch is at least eight times the first pitch. In some embodiments, forming additional features includes forming an enlarged contact pickup area.

本發明之其他方面、特徵、以及優點可從圖式中檢閱，詳細的說明和申請專利範圍請參考下文。Other aspects, features, and advantages of the present invention can be reviewed from the drawings. For detailed description and patent claims, refer to the following.

在此提供本發明一詳細說明之實施例，請參考第1圖至第33圖。在此所說明的製程步驟和結構並非用來製造一積體電路的完整製程。本發明可和本領域常用的、或是日後所發展出的其他不同積體電路製造技巧作連結實施。An embodiment of a detailed description of the invention is provided herein, please refer to Figures 1 through 33. The process steps and structures described herein are not a complete process for fabricating an integrated circuit. The present invention can be implemented in conjunction with other different integrated circuit fabrication techniques that are commonly used in the art or that have been developed in the future.

下列說明係為特殊結構實施例和方法之參考。在此所揭露的實施例和方法並非用以限定本發明，本發明可用其他特徵、元件、方法、以及實施例來實施。本發明較佳實施例之說明並非用以限定本發明的專利申請範圍所定義之範圍。本領域具有一般知識者應可識別下述說明的不同變化。在不同實施例和範例中的相似元件一般相似的參考數字來論述。The following description is a reference to specific structural examples and methods. The embodiments and methods disclosed herein are not intended to limit the invention, and the invention may be embodied in other features, elements, methods, and embodiments. The description of the preferred embodiments of the invention is not intended to limit the scope of the scope of the invention. Those of ordinary skill in the art should be able to recognize the various changes described below. Similar elements in different embodiments and examples are generally discussed with reference numerals.

第1-8圖以簡化方式繪示合併本發明之一四倍圖案化製程的第一實施例。1-8 illustrate, in a simplified manner, a first embodiment incorporating a four-fold patterning process of the present invention.

第1圖係為由相對應形狀之光罩所製造於一基板14上的一組巢狀環形(nested ring-like)第一線材料12之一組件10。第一線材料12具有複數個平行X方向部分物16，以及複數個平行Y方向部分物18。位於X方向部分物16之間的間距20係小於位於Y方向部分物18之間的間距22。間距20較佳地是不超過約25%的間距22，且更佳的是不超過約15%的間距22。複數個X方向部分物16的長度24係實質上大於複數個Y方向部分物18的長度26，所超過的長度一般是以數量級(orders of magnitude)來論。然而，為了繪圖參考，X方向部分物16的長度24並未按照實際尺寸，而是大幅縮減。在此實施例中，每一X方向部分物16的寬度28可例如大約是30 nm，以及每一Y方向部分物18的寬度30可例如大約是110 nm。由於間距22遠大於間距20，故而此Y方向部分物18的額外寬度是可被容納的。1 is an assembly 10 of a set of nested ring-like first wire materials 12 fabricated on a substrate 14 by correspondingly shaped reticle. The first line material 12 has a plurality of parallel X-direction portions 16, and a plurality of parallel Y-direction portions 18. The spacing 20 between the X-direction portions 16 is less than the spacing 22 between the Y-direction portions 18. The spacing 20 is preferably no more than about 25% of the spacing 22, and more preferably no more than about 15% of the spacing 22. The length 24 of the plurality of X-direction portions 16 is substantially greater than the length 26 of the plurality of Y-direction portions 18, the length of which is generally in terms of orders of magnitude. However, for drawing reference, the length 24 of the X-direction portion 16 is not substantially reduced in size, but is greatly reduced. In this embodiment, the width 28 of each X-direction portion 16 can be, for example, approximately 30 nm, and the width 30 of each Y-direction portion 18 can be, for example, approximately 110 nm. Since the spacing 22 is much larger than the spacing 20, the additional width of the Y-direction portion 18 can be accommodated.

第2圖繪示第1圖的第一線材料12的X方向部分物16和Y方向部分物18的每一邊上的間隔物32(spacer)之製造。間隔物32係表示為一組第二線材料32。相較於第一線材料12之密度，此有效的二倍線密度之間距是縮減的。在接下來的製程步驟中，移除第一線材料12的X方向部分物16和Y方向部分物18，僅留下第二線材料，如間隔物32。Fig. 2 is a view showing the manufacture of a spacer 32 on each side of the X-direction portion 16 and the Y-direction portion 18 of the first line material 12 of Fig. 1. Spacer 32 is represented as a set of second wire materials 32. This effective double line density spacing is reduced compared to the density of the first line material 12. In the next process step, the X-direction portion 16 and the Y-direction portion 18 of the first wire material 12 are removed leaving only the second wire material, such as the spacers 32.

第3圖繪示第2圖之第二線材料32的每一邊上的間隔物34之製造，其具有縮減的間距，且為第1圖之線密度的四倍。如同部分物16和部分物18，在接下來的製程步驟中移除第二線材料32，僅留下間隔物34當作第三線材料34。Figure 3 illustrates the fabrication of spacers 34 on each side of the second line of material 32 of Figure 2, which has a reduced pitch and is four times the line density of Figure 1. As with the portion 16 and the portion 18, the second wire material 32 is removed in the next processing step, leaving only the spacer 34 as the third wire material 34.

第4圖繪示使用具有第3圖結構之一光罩36的俯視圖。光罩36係被用以光罩分離第3圖之間隔物34的部分Y方向部分物38。在此實施例所示的第5圖中，X方向部分物40並未使用光罩36作修正。使用光罩36可移除間隔物34的部分的Y方向部分物38。第6圖係繪示移除後之結果，其製作出沿著Y方向部分物38的底端區42。Fig. 4 is a plan view showing the use of a reticle 36 having the structure of Fig. 3. The mask 36 is used to separate the partial Y-direction portion 38 of the spacer 34 of FIG. 3 by the mask. In the fifth diagram shown in this embodiment, the X-direction portion 40 is not corrected using the photomask 36. The Y-direction portion 38 of the portion of the spacer 34 can be removed using the reticle 36. Figure 6 is a graph showing the result of the removal, which produces the bottom end region 42 of the portion 38 along the Y direction.

第7圖為使用具有第6圖結構之一光罩44的一俯視圖，以形成附加特徵物。在此實施例中，附加特徵物(supplemental feature)包括被施加在Y方向部分物38之底端區42的複數個接觸墊，以及複數個電路內連線(circuit interconnect line)。第8圖繪示使用光罩44的結果，和其後之製程步驟，例如曝光和蝕刻步驟，以製作附加特徵物和電路內連線48，其中附加特徵物，特別是位於沿著Y方向部份物38的底端區42的接觸墊46。對黃光微影尺寸化的墊件(pad)和對準容許誤差而言，Y方向部分物38之間距較佳地是必須足夠的，而由於這些因素的關係，X方向部分物40之間距則是不受限制，因此可以是次微影的。Figure 7 is a top plan view of a reticle 44 having a structure of Figure 6 to form additional features. In this embodiment, the supplementary feature includes a plurality of contact pads applied to the bottom end region 42 of the Y-direction portion 38, and a plurality of circuit interconnect lines. Figure 8 illustrates the results of the use of the reticle 44, and subsequent processing steps, such as exposure and etching steps, to create additional features and circuit interconnects 48, wherein additional features, particularly located along the Y-direction The contact pad 46 of the bottom end region 42 of the portion 38. For the pad and alignment tolerance of the yellow lithography size, the distance between the Y-direction portions 38 is preferably sufficient, and due to these factors, the distance between the X-direction portions 40 is Unrestricted, so it can be sub-lithography.

在和X方向部分物40之間距相比時，位於Y方向部分物38的底端區42之間所增加的間距是重要的，這是因為此增加的間距允許以其他方式形成一般使用黃光微影尺寸化的接觸墊46或較大的接觸墊，以提供電性通道至次黃光微影尺寸化和空間化的第三線材料34的X方向部分物40。第三線材料34一般係為字元線或位元線，因此使得X方向部分物40和Y方向部分物38通常分別為X方向字元/位元線部分物40和Y方向字元/位元線部分38。藉由提供位於線材料34最內部的X方向部分物40足夠的空間，電路內連線48可如第8圖所示，設置於最內部之X方向部分物之間。在其他實施例中，電路內連線48可被設置於線材料34最外部的X方向部分物40的外圍。電路內連線48可以是黃光微影尺寸化之線或是次黃光微影尺寸化之線。The increased spacing between the bottom end regions 42 of the Y-direction portions 38 is important when compared to the spacing between the X-direction portions 40, since this increased spacing allows for other forms of general use of yellow lithography. The sized contact pads 46 or larger contact pads provide an X-direction portion 40 of the third wire material 34 that is electrically and channelized to the secondary yellow lithography. The third line material 34 is typically a word line or a bit line, such that the X-direction portion 40 and the Y-direction portion 38 are typically X-direction characters/bit line portions 40 and Y-direction characters/bits, respectively. Line portion 38. By providing a sufficient space for the X-direction portion 40 located at the innermost portion of the wire material 34, the circuit interconnection 48 can be disposed between the innermost X-direction portions as shown in FIG. In other embodiments, the circuit interconnects 48 may be disposed on the periphery of the X-direction portion 40 that is the outermost portion of the wire material 34. The circuit interconnect 48 can be a line of yellow lithography or a line of sub-yellow lithography.

第9-16圖以簡化方式繪示類似第1-8圖的四倍圖案化製程的第二實施例。因此，此第二實施例於此將不再作詳細的說明，而主要的區隔如下所述。巢狀環形線材料12之組件10係為L型部分物52之外形。因此，一對L型部分物52可製作出巢狀環形線材料。第12圖的光罩54係被尺寸化以覆蓋第13圖中的Y方向部分物38以及X方向部分物40，使得鄰接間隔物34不會藉由第11圖所示的底端元件56而彼此電性連接。Figures 9-16 illustrate a second embodiment of a four-fold patterning process similar to Figures 1-8 in a simplified manner. Therefore, this second embodiment will not be described in detail herein, and the main divisions are as follows. The assembly 10 of the nested loop wire material 12 is shaped as an L-shaped portion 52. Therefore, a pair of L-shaped portions 52 can be made into a nested loop wire material. The mask 54 of Fig. 12 is sized to cover the Y-direction portion 38 and the X-direction portion 40 in Fig. 13 such that the adjacent spacers 34 are not passed through the bottom end member 56 shown in Fig. 11. Electrically connected to each other.

第17A-17C圖繪示巢狀環形線材料12的三個附加實施例之結構10，其中巢狀環形線材料12具有X方向部分物16和Y方向部分物18。第17A圖係繪示具有兩U型部分物相對設置之第一線材料12的一開環形狀(open ring configuration)之示意圖，且兩U型部分物之間係沿著Y方向部分物18具有間隙(gaps)19。17A-17C illustrate a structure 10 of three additional embodiments of a nested loop wire material 12 having a X-direction portion 16 and a Y-direction portion 18. Figure 17A is a schematic view showing an open ring configuration of the first wire material 12 having two U-shaped portions disposed oppositely, and the two U-shaped portions have a portion 18 along the Y-direction. Gap (19).

第17B圖係繪示具有兩L型部分物相對設置之第一線材料12的另一開環形狀之示意圖，且兩L型部分物之間沿著Y方向部分物18亦具有間隙(gaps)19。然而，Y方向部分物18是位在兩相鄰X方向部分物16的一對端(alternating ends)。X方向部分物16具有第一端15和第二端17。在此實施例中，巢狀環形線材料12外環上的Y方向部分物18是位在X方向部分物16的第一端15，而巢狀環形線材料12內環上的Y方向部分物18是位在X方向部分物16的第二端17。Figure 17B is a schematic view showing another open-loop shape of the first wire material 12 having two L-shaped portions disposed oppositely, and the portion 18 of the L-shaped portion also has a gap (gaps) along the Y-direction. 19. However, the Y-direction portion 18 is an alternating end located in two adjacent X-direction portions 16. The X-direction portion 16 has a first end 15 and a second end 17. In this embodiment, the Y-direction portion 18 on the outer ring of the nested loop wire material 12 is the first end 15 of the X-direction portion 16 and the Y-direction portion of the nested loop wire material 12 on the inner ring. 18 is the second end 17 of the portion 16 in the X direction.

第17C圖係繪示第17B圖之開環形狀的變形，其中同樣的環形線材料12的Y方向部分物18分別位於X方向部分物16的第一端15和第二端17。因此所產生的兩間隙21分別是在Y方向部分物18和兩相對X方向部分物16的第一端15和第二端17之間。在此實施例中，環形線材料12的外環包括第一、二X方向部分物16.1和16.2，以及第一、二Y方向部分物18.1和18.2。第一Y方向部分物18.1是位於第一X方向部分物16.1的第一端15，第二Y方向部分物18.2是位於第二X方向部分物16.2的第二端17。環形線材料12的內環包括第三、四X方向部分物16.3和16.4，以及第三、四Y方向部分物18.3和18.4。第三Y方向部分物18.3是位於第三X方向部分物16.3的第二端17，第四Y方向部分物18.4是位於第四X方向部分物16.4的第一端15。Fig. 17C is a diagram showing the deformation of the open-loop shape of Fig. 17B in which the Y-direction portions 18 of the same annular wire material 12 are respectively located at the first end 15 and the second end 17 of the X-direction portion 16. The two gaps 21 thus produced are between the first end 15 and the second end 17 of the Y-direction portion 18 and the two opposite X-direction portions 16, respectively. In this embodiment, the outer ring of the loop wire material 12 includes first and second X-direction portions 16.1 and 16.2, and first and second Y-direction portions 18.1 and 18.2. The first Y-direction portion 18.1 is the first end 15 of the first X-direction portion 16.1, and the second Y-direction portion 18.2 is the second end 17 of the second X-direction portion 16.2. The inner ring of the loop wire material 12 includes third and fourth X-direction portions 16.3 and 16.4, and third and fourth Y-direction portions 18.3 and 18.4. The third Y-direction portion 18.3 is the second end 17 of the third X-direction portion 16.3, and the fourth Y-direction portion 18.4 is the first end 15 of the fourth X-direction portion 16.4.

第18圖係為簡化流程圖，其繪示本發明之多重圖案化方法中所實施的基礎步驟。於開始的步驟60，一組平行線圖案，一般是巢狀環形圖案，平行第一線材料12的組件10係被選擇。第一線材料12具有實質上長於平行Y方向部分物18的平行X方向部分物16，例如是100倍或1000倍的長度。接著在步驟62，X方向部分物16和Y方向部分物18的第一間距20和第二間距22係被選擇。被選擇的間距中，第二間距22係大於第一間距20，例如是4-8倍。在步驟64，形成平行第一線材料12的組件10以覆蓋一基板14。二第二線材料32形成於步驟66。第二線材料32平行於第一線材料12。於步驟68形成二個第三線材料34平行於每一第二線材料32。以同樣的作法製作出平行X方向部分物40和平行Y方向部分物38當作第三線材料。第二線材料34的Y方向部分物38包括底端區42。於步驟70製作出附加特徵物，例如是位於底端區42的擴大接觸墊46以及電路內連線48。Figure 18 is a simplified flow diagram illustrating the basic steps performed in the multiple patterning method of the present invention. In the initial step 60, a set of parallel line patterns, generally nested annular patterns, are selected for the assembly 10 of parallel first line material 12. The first wire material 12 has a parallel X-direction portion 16 that is substantially longer than the parallel Y-direction portion 18, for example 100 or 1000 times longer. Next at step 62, the first pitch 20 and the second pitch 22 of the X-direction portion 16 and the Y-direction portion 18 are selected. Of the selected pitches, the second pitch 22 is greater than the first pitch 20, for example 4-8 times. At step 64, an assembly 10 of parallel first line material 12 is formed to cover a substrate 14. Two second wire materials 32 are formed in step 66. The second wire material 32 is parallel to the first wire material 12. At step 68, two third line materials 34 are formed parallel to each of the second line materials 32. In the same manner, a parallel X-direction portion 40 and a parallel Y-direction portion 38 are formed as the third line material. The Y-direction portion 38 of the second wire material 34 includes a bottom end region 42. Additional features are created in step 70, such as enlarged contact pads 46 at the bottom end region 42 and electrical interconnects 48.

第19-32圖繪示一使用能帶工程SONOS四倍字元線(BE-SONOS WL quadruple)自我對準間隔物圖案化(self-aligned spacer patterning)實施例的製程流程圖，BE-SONOS係為電荷捕捉記憶胞。第19圖繪示一基板76，基板76包括第一層至第八層78-92，以及形成於第一層78上的一光阻跡線94。在此實施例中，第一層78、第三層82、和第六層88係為複晶矽，而第二層80和第四層84係為二氧化矽。第五層86為矽化鎢。第八層92為矽。第七層90係為一五層之組合，係為BE-SONOS的電荷捕捉結構，其具有可替換的二氧化矽層和氮化矽層，其中二氧化矽層係為從此結構上方數來第一層、第三層、和第五層。由於第一層78、第二層80、和第三層82可在圖案化製程中完全地移除，因此係為犧牲層。其他材料和材料的設置亦可被使用。19-32 illustrate a process flow diagram of an embodiment of a self-aligned spacer patterning using a band-engineered SONOS WL quadruple, BE-SONOS Capturing memory cells for charge. FIG. 19 illustrates a substrate 76 including first to eighth layers 78-92, and a photoresist trace 94 formed on the first layer 78. In this embodiment, the first layer 78, the third layer 82, and the sixth layer 88 are polycrystalline germanium, and the second layer 80 and the fourth layer 84 are cerium oxide. The fifth layer 86 is tungsten telluride. The eighth layer 92 is 矽. The seventh layer 90 series is a combination of five layers, which is a charge trapping structure of BE-SONOS, which has a replaceable ruthenium dioxide layer and a tantalum nitride layer, wherein the ruthenium dioxide layer is from the top of the structure One, third, and fifth layers. Since the first layer 78, the second layer 80, and the third layer 82 can be completely removed in the patterning process, they are sacrificial layers. Other materials and material settings can also be used.

光阻跡線94係被用於蝕刻第一層78，以製作對應第1圖的第一線材料12的結構96。第21圖繪示沉積覆蓋於第20圖結構的一氮化矽層98。第22圖繪示對氮化矽層98作非等向性蝕刻，以移除覆蓋結構96和第二層80的氮化矽層98的部分。以此作法留下間隙壁100於結構96的每個邊上，此間隙壁100係對應於第2圖的間隔物32。第23圖繪示蝕刻結構96並留下間隙壁100的結果。第24圖繪示於第23圖的結構上沉積一層複晶矽層102。第25圖中，位於間隙壁100和第二層80上的部分複晶矽層102係被移除，留下複晶矽間隙壁104於氮化矽間隙壁100的每個邊上。Photoresist trace 94 is used to etch first layer 78 to form structure 96 corresponding to first line material 12 of FIG. Figure 21 illustrates the deposition of a tantalum nitride layer 98 overlying the structure of Figure 20. FIG. 22 illustrates an anisotropic etch of the tantalum nitride layer 98 to remove portions of the tantalum nitride layer 98 overlying the structure 96 and the second layer 80. In this manner, the spacers 100 are left on each side of the structure 96, which corresponds to the spacers 32 of FIG. FIG. 23 illustrates the result of etching the structure 96 and leaving the spacers 100. Figure 24 illustrates the deposition of a layer of polysilicon layer 102 on the structure of Figure 23. In Fig. 25, portions of the germanium layer 102 on the spacers 100 and the second layer 80 are removed, leaving the germanium spacers 104 on each side of the tantalum nitride spacers 100.

第26圖中，一光阻遮罩106係用於覆蓋第25圖未被移除的結構的一部分。光阻遮罩106可被視為相反於第4圖之光罩36。第27圖繪示移除未被光阻遮罩106保護的複晶矽間隙壁104並且接著移除光阻遮罩106之結果。第28圖繪示蝕刻氮化矽間隙壁100以及未被間隙壁104覆蓋的第二層80的部分；以此方法留下位於第三層82上的複晶矽/二氧化矽堆疊件108。堆疊件108包括上層之複晶矽部分物107以及下層之二氧化矽部分物109。對位於第20圖結構右手邊的二結構96以及位於第28圖結構右手邊上的複晶矽/二氧化矽堆疊件108作比較，可以發現垂直結構的數目係為從2個到8個，增加了四倍。In Fig. 26, a photoresist mask 106 is used to cover a portion of the structure that has not been removed in Fig. 25. The photoresist mask 106 can be considered to be opposite to the reticle 36 of FIG. FIG. 27 illustrates the result of removing the germanium spacers 104 that are not protected by the photoresist mask 106 and then removing the photoresist mask 106. FIG. 28 illustrates a portion of the etched tantalum nitride spacer 100 and the second layer 80 that is not covered by the spacers 104; in this way, the polysilicon/cerium oxide stack 108 on the third layer 82 is left. The stack 108 includes an upper layer of the germanium layer portion 107 and a lower layer of the hafnium oxide portion 109. Comparing the two structures 96 on the right hand side of the structure of Fig. 20 with the polysilicon/cerium oxide stack 108 on the right hand side of the structure of Fig. 28, it can be found that the number of vertical structures is from 2 to 8. Four times more.

第29圖繪示位於第28圖結構上的一光阻遮罩110，光阻遮罩110對應於第7圖之光罩44。第30圖繪示蝕刻第29圖結構中未被堆疊件108或光阻遮罩110覆蓋的第三層82的部分。上層之複晶矽部分物107係被移除，而留下堆疊件112。堆疊件112包括一上層之二氧化矽部分物113和一下層之複晶矽部分物114。在第30圖中，光阻遮罩110已被移除。第31圖繪示氧化層蝕刻的結果，此蝕刻移除了上層之氧化層部分物113以及第四層84(二氧化矽)中未被複晶矽部分物114覆蓋的部分。此蝕刻步驟製作出堆疊件116。堆疊件116包括複晶矽部分物114以及二氧化矽部分物118。FIG. 29 illustrates a photoresist mask 110 on the structure of FIG. 28, and the photoresist mask 110 corresponds to the mask 44 of FIG. FIG. 30 illustrates a portion of the third layer 82 that is not covered by the stack 108 or the photoresist mask 110 in the structure of the etched FIG. The upper layer of the germanium wafer portion 107 is removed leaving the stack 112. The stack 112 includes an upper layer of ruthenium oxide portion 113 and a lower layer of ruthenium layer portion 114. In Fig. 30, the photoresist mask 110 has been removed. Fig. 31 is a view showing the result of the oxide layer etching which removes the portion of the upper oxide layer 113 and the portion of the fourth layer 84 (cerium oxide) which is not covered by the polysilicon portion 114. This etching step produces a stack 116. The stack 116 includes a polysilicon portion 114 and a hafnium oxide portion 118.

第32圖繪示蝕刻未被堆疊件116覆蓋的第五層86、第六層88、以及第七層90部分，以及移除複晶矽部分物114、和移除部分二氧化矽部分物118，留下一列具有相對應矽化鎢和複晶矽的被蝕刻元件122、124之記憶胞120的結果，其中，字元線124的組成列係位於電荷儲存區128之上。在此實施例中，記憶胞120形成一NAND串。在此實施例中的蝕刻步驟也製作出以相同於字元線124方向延伸的一串選擇線130。在整個第七層90被蝕刻之後，部分的二氧化矽部分物118可被保留。這是因為第四層84的厚度一般是遠大於第七層90的厚度。Figure 32 illustrates the etching of the fifth layer 86, the sixth layer 88, and the seventh layer 90 portion that are not covered by the stack 116, as well as removing the polysilicon portion 114, and removing portions of the ceria portion 118. The result of leaving a column of memory cells 120 having etched elements 122, 124 corresponding to tungsten and polysilicon, wherein the constituent lines of word lines 124 are above charge storage region 128. In this embodiment, memory cell 120 forms a NAND string. The etching step in this embodiment also produces a series of select lines 130 that extend in the same direction as the word line 124. After the entire seventh layer 90 is etched, a portion of the ceria portion 118 can be retained. This is because the thickness of the fourth layer 84 is generally much greater than the thickness of the seventh layer 90.

第33圖係為繪示在一字元線區132中緊密設置的X方向字元線部分物40以及較寬鬆設置的Y方向字元線部分物38之一方塊圖。通常在一記憶體電路中會有上千條的字元線124。在此實施例中，提供二不同接觸區134鄰接耦合至字元線區132。接觸墊46係位於沿著較寬鬆設置(較大的間距)的Y方向字元線部分物38的接觸區134內。一周邊電路驅動區136係位於二接觸區134之間並和二接觸區134耦合。其中，設置型態是(1)位於一字元線區132中的多條字元線；(2)字元線區132，且假設一或多個接觸區134包含沿Y方向字元向部分物38之接觸墊46；(3)一或多個組合的周邊電路驅動區136接觸區134，此設置型態給高密度記憶體提供了一個在實際設置上有效的積體電路佈局(layout)。Figure 33 is a block diagram showing the X-direction word line portion 40 and the loosely disposed Y-direction word line portion 38 which are closely arranged in a word line region 132. There are typically thousands of word lines 124 in a memory circuit. In this embodiment, two different contact regions 134 are provided adjacent to the word line region 132. The contact pads 46 are located within the contact regions 134 of the Y-direction wordline portions 38 along the looser arrangement (larger pitch). A peripheral circuit drive region 136 is located between the two contact regions 134 and coupled to the two contact regions 134. Wherein, the setting type is (1) a plurality of word lines located in a word line area 132; (2) a word line area 132, and it is assumed that one or more contact areas 134 include a character portion along the Y direction Contact pad 46 of object 38; (3) one or more combined peripheral circuit drive region 136 contact region 134, this arrangement provides high-density memory with an integrated circuit layout that is effective in practical settings. .

上述任一及所有專利、專利申請案以及已印刷的公開文件的揭露內容在此以引用方式全數併入。The disclosure of any and all of the above patents, patent applications, and published publications is hereby incorporated by reference in its entirety.

綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10．．．組件10. . . Component

12．．．第一線材料12. . . First line material

14．．．基板14. . . Substrate

16、40．．．X方向部分物16, 40. . . X direction part

18、38．．．Y方向部分物18, 38. . . Y direction part

20、22．．．間距20, 22. . . spacing

24、26．．．長度24, 26. . . length

28、30．．．寬度28, 30. . . width

32．．．第二線材料(間隔物)32. . . Second line material (spacer)

34．．．第三線材料(間隔物)34. . . Third line material (spacer)

36、44、54．．．光罩36, 44, 54. . . Mask

38、40、124．．．字元線38, 40, 124. . . Word line

42．．．底端區42. . . Bottom end zone

46．．．接觸墊46. . . Contact pad

48．．．電路內連線48. . . In-circuit connection

55．．．位置55. . . position

56．．．底端元件56. . . Bottom element

60、62、64、66、68、70．．．步驟60, 62, 64, 66, 68, 70. . . step

78、82、88、102．．．複晶矽78, 82, 88, 102. . . Polycrystalline germanium

80、84．．．二氧化矽80, 84. . . Cerium oxide

86．．．矽化鎢86. . . Tungsten

90．．．BE-SONOS電荷捕捉結構90. . . BE-SONOS charge trapping structure

92．．．矽92. . .矽

94．．．光阻跡線94. . . Photoresist trace

96．．．結構96. . . structure

98．．．氮化矽層98. . . Tantalum nitride layer

100．．．間隙壁100. . . Clearance wall

104．．．複晶矽間隙壁104. . . Complex crystal spacer

106、110．．．光阻遮罩106, 110. . . Photoresist mask

107、114．．．複晶矽部分物107, 114. . . Part of the crystal

108、112、116．．．堆疊件108, 112, 116. . . Stack

109、113、118．．．二氧化矽部分物109, 113, 118. . . Ceria partial

120．．．記憶胞120. . . Memory cell

122．．．被蝕刻元件122. . . Etched component

126、130．．．選擇線126, 130. . . Selection line

128．．．電荷儲存區128. . . Charge storage area

132．．．字元線區132. . . Character line area

134．．．接觸區134. . . Contact area

136．．．周邊電路驅動區136. . . Peripheral circuit drive area

第1-8圖以簡化方式繪示一四倍圖案化製程之第一實施例。Figures 1-8 illustrate a first embodiment of a four-fold patterning process in a simplified manner.

第1圖繪示對應光罩形狀之一基板內巢狀環形(nested ring-like)線材料之俯視圖。線材料具有平行X方向部分物以及平行Y方向部分物，位於X方向部分物之間的間距小於位於Y方向部分物之間的間距。FIG. 1 is a plan view showing a nested ring-like line material in a substrate corresponding to the shape of the reticle. The wire material has a parallel X-direction portion and a parallel Y-direction portion, and a pitch between the X-direction portions is smaller than a pitch between the Y-direction portions.

第2圖繪示第1圖線材料的每一邊上之間隔物之製作，藉由間距的縮減從而使線密度二倍化。Figure 2 illustrates the fabrication of spacers on each side of the first line of material, which is doubled by the reduction in pitch.

第3圖繪示第2圖線材料的每一邊上之間隔物之製作，藉由間距的縮減從而使第1圖之線密度四倍化。Figure 3 shows the fabrication of spacers on each side of the second line of material, and the line density of Figure 1 is quadrupled by the reduction in pitch.

第4圖繪示用於第3圖結構之一光罩之俯視圖。Fig. 4 is a plan view showing a reticle for use in the structure of Fig. 3.

第5圖繪示覆蓋部分Y方向部分物之第3圖結構以第4圖光罩作對準之圖。Fig. 5 is a view showing the structure of Fig. 3 covering a portion of the Y-direction portion, which is aligned with the mask of Fig. 4.

第6圖繪示移除第4圖光罩覆蓋的部分Y方向部分物所製作出線材料之底端區之結果圖。Fig. 6 is a view showing the result of removing the bottom end region of the line material produced by removing a portion of the Y-direction portion covered by the mask of Fig. 4.

第7圖繪示用於第6圖結構之一光罩俯視圖，其用以製作附加特徵物。Figure 7 is a plan view of a reticle for use in the structure of Figure 6, for making additional features.

第8圖繪示使用第7圖光罩以及後續製程步驟之結果圖，特別是位於沿Y方向部分物之底端區的接觸墊和位元線或字元線，而後續製程步驟例如是顯影和蝕刻以製作附加特徵物。Figure 8 is a diagram showing the result of using the mask of Figure 7 and subsequent processing steps, particularly the contact pads and bit lines or word lines located in the bottom end region of the portion along the Y direction, and subsequent processing steps such as development And etching to make additional features.

第9-16圖以簡化方式繪示類似第1-8圖的一四倍圖案化製程之一第二實施例，然而其巢狀環形線材料係為L型部分物之形式。Figures 9-16 illustrate, in a simplified manner, a second embodiment of a four-fold patterning process similar to Figures 1-8, however, the nested loop line material is in the form of an L-shaped portion.

第17A-17C圖繪示巢狀環形線材料的三組附加實施例。Figures 17A-17C illustrate three additional sets of embodiments of nested loop wire materials.

第18圖一簡化流程圖，此流程圖顯示參考上述討論的第1-17圖之本發明之多重圖案化方法所實行的基本步驟。Figure 18 is a simplified flow diagram showing the basic steps performed by the multiple patterning method of the present invention with reference to Figures 1-17 discussed above.

第19-32圖繪示使用BESONOS WL四倍圖案化之一實施例之製程流程。Figures 19-32 illustrate a process flow for an embodiment using BESONOS WL quadruple patterning.

第33圖繪示字元線區、接觸區、以及周邊電路驅動區之間的關係方塊圖。Figure 33 is a block diagram showing the relationship between the word line area, the contact area, and the peripheral circuit driving area.

38、40．．．字元線38, 40. . . Word line

46．．．接觸墊46. . . Contact pad

48．．．電路內連線48. . . In-circuit connection

Claims

一種積體電路記憶體，包括：一組線，該組線中之每一條線具有在一第一區中複數個平行X方向線部分物，以及在一第二區中複數個平行Y方向線部分物，該第二區係和該第一區相互分隔開；該些X方向線部分物的長度實質上長於該些Y方向線部分物的長度；該些X方向線部分物和該些Y方向線部分物分別具有複數個第一間距和第二間距，且該第二間距係大於該第一間距；以及位於該些Y方向線部分物的複數個接觸區，其中該些Y方向線部分物以及該些X方向線部分物定義出一組巢狀環形平行線(nested ring-like parallel lines)，該組巢狀環形平行線包括：具有複數個相對L型部分物之複數條第一和第二環形平行線，且該些L型部分物係沿著該些Y方向線部分物具有數個間隙，該些第一和第二環形平行線係彼此相鄰；具有第一端和第二端之該些X方向線部分物；該些第一環形平行線之該些Y方向線部分物係位於該些X方向線部分物之第一端；和該些第二環形平行線之該些Y方向線部分物係位於該些X方向線部分物之第二端。 An integrated circuit memory comprising: a set of lines, each of the set of lines having a plurality of parallel X-directional line portions in a first region, and a plurality of parallel Y-directional lines in a second region a portion, the second region and the first region are spaced apart from each other; the lengths of the X-directional line portions are substantially longer than the lengths of the Y-directional line portions; the X-directional line portions and the portions The Y-directional line portions respectively have a plurality of first pitches and second pitches, and the second pitch is greater than the first pitch; and a plurality of contact regions located in the Y-directional line portions, wherein the Y-directional lines The portion and the X-directional line portions define a set of nested ring-like parallel lines, the set of nested annular parallel lines comprising: a plurality of first plurality of relative L-shaped portions And the second annular parallel line, and the L-shaped partial portions have a plurality of gaps along the Y-directional line portions, the first and second annular parallel lines are adjacent to each other; having the first end and the first The X-directional line parts of the two ends; the first rings The Y-directional line portions of the parallel lines are located at the first ends of the X-directional line portions; and the Y-directional line portions of the second annular parallel lines are located in the X-directional line portions Second end.

一種積體電路記憶體，包括：一組線，該組線中之每一條線具有在一第一區中複數個平行X方向線部分物，以及在一第二區中複數個平行Y 方向線部分物，該第二區係和該第一區相互分隔開；該些X方向線部分物的長度實質上長於該些Y方向線部分物的長度；該些X方向線部分物和該些Y方向線部分物分別具有複數個第一間距和第二間距，且該第二間距係大於該第一間距；以及位於該些Y方向線部分物的複數個接觸區，其中該些Y方向線部分物以及該些X方向線部分物定義出一組巢狀環形平行線(nested ring-like parallel lines)，其中該組巢狀環形平行線包括；具有複數個相對L型部分物之複數條第一和第二環形平行線，且該些L型部分物係沿著該些Y方向線部分物具有數個間隙，該些第一和第二環形平行線係彼此相鄰；該些第一環形平行線包括複數個第一和第二X方向線部分物以及第一和第二Y方向線部分物，每該第一和第二X方向線部分物具有第一端和第二端，該第一Y方向線部分物係位於該第一X方向線部分物之第一端，該第二Y方向線部分物係位於該第二X方向線部分物之第二端；以及該些第二環形平行線包括複數個第三和第四X方向線部分物以及第三和第四Y方向線部分物，每該第三和第四X方向線部分物具有第一端和第二端，該第三Y方向線部分物係位於該第三X方向線部分物之第二端，該第四Y方向線部分物係位於該第四X方向線部分物之第一端。 An integrated circuit memory comprising: a set of lines, each of the set of lines having a plurality of parallel X-directional line portions in a first region, and a plurality of parallel Ys in a second region a direction line portion, the second region and the first region are separated from each other; the lengths of the X-directional line portions are substantially longer than the lengths of the Y-directional line portions; The Y-directional line portions respectively have a plurality of first pitches and second pitches, and the second pitch is greater than the first pitch; and a plurality of contact regions located in the Y-directional line portions, wherein the Y The direction line portion and the X-directional line portions define a set of nested ring-like parallel lines, wherein the set of nested annular parallel lines includes; a plurality of relative L-shaped portions; a first and a second annular parallel line, and the L-shaped partial portions have a plurality of gaps along the Y-directional line portions, the first and second annular parallel lines are adjacent to each other; An annular parallel line includes a plurality of first and second X-directional line portions and first and second Y-directional line portions, each of the first and second X-directional line portions having a first end and a second end The first Y direction line part is located in the first X direction line part a first end of the object, the second Y-directional line portion is located at a second end of the second X-directional line portion; and the second annular parallel lines comprise a plurality of third and fourth X-directional line portions And third and fourth Y-directional line portions, each of the third and fourth X-directional line portions having a first end and a second end, the third Y-directional line portion being located in the third X-directional line portion The second end of the object, the fourth Y-directional line portion is located at the first end of the fourth X-directional line portion.

如申請專利範圍第1或2項所述之記憶體，其中該些線包括複數個字元線或複數個位元線。 The memory of claim 1 or 2, wherein The lines include a plurality of word lines or a plurality of bit lines.

如申請專利範圍第1或2項所述之記憶體，其中該些線係以微影方式形成，並且該第一間距具有一子微影尺寸。 The memory of claim 1 or 2, wherein the lines are formed in a lithographic manner, and the first pitch has a sub-diaphragm size.

如申請專利範圍第1或2項所述之記憶體，其中該些線係以微影方式形成，並且該些接觸區具有微影尺寸。 The memory of claim 1 or 2, wherein the lines are formed in a lithographic manner, and the contact regions have a lithographic size.

一種積體電路記憶體，包括：一組線，該組線中之每一條線具有在一第一區中複數個平行X方向線部分物，以及在一第二區中複數個平行Y方向線部分物，該第二區係和該第一區相互分隔開；該些X方向線部分物的長度實質上長於該些Y方向線部分物的長度；該些X方向線部分物和該些Y方向線部分物分別具有複數個第一間距和第二間距，且該第二間距係大於該第一間距，其中該第二間距係至少為該第一間距之6倍；以及位於該些Y方向線部分物的複數個接觸區。 An integrated circuit memory comprising: a set of lines, each of the set of lines having a plurality of parallel X-directional line portions in a first region, and a plurality of parallel Y-directional lines in a second region a portion, the second region and the first region are spaced apart from each other; the lengths of the X-directional line portions are substantially longer than the lengths of the Y-directional line portions; the X-directional line portions and the portions The Y-directional line portions respectively have a plurality of first and second pitches, and the second pitch is greater than the first pitch, wherein the second pitch is at least 6 times the first pitch; and located at the Y A plurality of contact areas of the direction line portion.

如申請專利範圍第6項所述之記憶體，其中該些Y方向線部分物以及該些X方向線部分物定義出一組巢狀環形平行線(nested ring-like parallel lines)。 The memory of claim 6, wherein the Y-directional line portions and the X-directional line portions define a set of nested ring-like parallel lines.

如申請專利範圍第7項所述之記憶體，其中該組巢狀環形平行線包括具有複數個相對U型部分物之複數條第一和第二環形平行線，且該些U型部分物係沿著該些Y方向線部分物之至少一些而具有數個間隙。 The memory of claim 7, wherein the set of nested annular parallel lines comprises a plurality of first and second annular parallel lines having a plurality of relatively U-shaped portions, and the U-shaped partial lines are There are several gaps along at least some of the Y-directional line portions.

如申請專利範圍第8項所述之記憶體，其中該些間隙係位於沿著該些Y方向線部分物之至少一些的中央處。 The memory of claim 8, wherein the gaps are located at a center along at least some of the Y-directional line portions.

如申請專利範圍第8項所述之記憶體，其中該些間隙各位於沿著每該Y方向線部分物之中央處。 The memory of claim 8, wherein the gaps are located at a center of each of the portions along the Y-direction line.

如申請專利範圍第6項所述之記憶體，其中該些線係以微影方式形成，並且該些接觸區具有微影尺寸。 The memory of claim 6, wherein the lines are formed in a lithographic manner, and the contact regions have a lithographic size.

一種在黃光微影積體電路製程步驟中用來製作積體電路記憶體的多重圖案化方法，包括：為一組第一線材料選擇一組線圖案；在一基板上形成該組第一線材料，該組第一線材料中的每一第一線材料定義出具有一X方向部分物和一Y方向部分物之一圖案，該些第一線材料之該X方向部分物的長度係實質上長於該些第一線材料之該些Y方向部分物的長度；為該些X方向部分物和該些Y方向部分物選擇複數個第一間距和第二間距，該第二間距係大於該第一間距，該些X方向部分物係為平行，並且該些Y方向部分物係為平行；形成平行於每一第一線材料之至少二個第二線材料，以製作出包括複數個平行X方向線部分物和複數個平行Y方向線部分物的複數個字元線，該些Y方向線部分物之第二線材料包括複數個底端區；以及形成複數個附加特徵物(supplemental features)於至少部分的該些底端區。 A multiple patterning method for fabricating integrated circuit memory in a yellow light microintegration circuit processing step, comprising: selecting a set of line patterns for a set of first line materials; forming the first line of material on a substrate Each of the first line materials of the set of first line materials defines a pattern having a portion of an X-direction portion and a Y-direction portion, the length of the X-direction portion of the first line material being substantially a length of the Y-direction portion of the first line material; a plurality of first and second pitches for the X-direction portion and the Y-direction portions, the second pitch being greater than the first a spacing, the X-direction portions are parallel, and the Y-direction portions are parallel; forming at least two second-line materials parallel to each of the first line materials to produce a plurality of parallel X a plurality of word lines of the direction line portion and the plurality of parallel Y direction line portions, the second line material of the Y direction line portion includes a plurality of bottom end regions; and forming a plurality of supplementary features At least in part The bottom end areas.

如申請專利範圍第12項所述之方法，其中該些線包括複數個字元線或複數個位元線。 The method of claim 12, wherein the lines comprise a plurality of word lines or a plurality of bit lines.

如申請專利範圍第12項所述之方法，其中該至少二個第二線材料之形成步驟更包括：形成二第二線材料平行於每一第一線材料；以及形成二第三線材料平行於每一第二線材料以製作該些線。 The method of claim 12, wherein the forming of the at least two second wire materials further comprises: forming two second wire materials parallel to each of the first wire materials; and forming the second third wire material parallel to Each second line of material is used to make the lines.

如申請專利範圍第12項所述之方法，其中該些平行線圖案選擇步驟包括為一組巢狀環形平行第一線材料選擇一組巢狀環形平行線圖案。 The method of claim 12, wherein the parallel line pattern selection step comprises selecting a set of nested annular parallel line patterns for a set of nested annular parallel first line materials.

如申請專利範圍第12項所述之方法，更包括移除至少部分的Y方向線部分物以製作該底端區。 The method of claim 12, further comprising removing at least a portion of the Y-directional line portion to form the bottom end region.

如申請專利範圍第12項所述之方法，其中該些第一線材料中之一者定義下列至少一者：一連續矩形、具有沿著該些Y方向部分物中之一者之一間隙(gap)的一矩形、具有同時(both)沿著該些Y方向部分物之一間隙的一矩形、以及具有僅僅一Y方向部分物的一矩形。 The method of claim 12, wherein one of the first line materials defines at least one of: a continuous rectangle having a gap along one of the Y-direction portions ( A rectangle of a gap, a rectangle having a gap along a portion of the Y-direction portions, and a rectangle having only a Y-direction portion.

如申請專利範圍第12項所述之方法，其中該些X方向線部分物之該些長度係至少該些Y方向線部分物之該些長度的30倍。 The method of claim 12, wherein the lengths of the X-directional line portions are at least 30 times the lengths of the Y-directional line portions.

如申請專利範圍第12項所述之方法，其中該第二間距係至少為該第一間距的四倍。 The method of claim 12, wherein the second spacing is at least four times the first spacing.

如申請專利範圍第12項所述之方法，其中該第二間距係至少為該第一間距的八倍。 The method of claim 12, wherein the second spacing is at least eight times the first spacing.

如申請專利範圍第12項所述之方法，其中該些附加特徵物形成步驟包括形成複數個擴大的接觸區。 The method of claim 12, wherein the The additional feature forming step includes forming a plurality of enlarged contact regions.

如申請專利範圍第16項所述之方法，更包括在移除步驟後形成一導線材料。 The method of claim 16, further comprising forming a wire material after the removing step.

如申請專利範圍第22項所述之方法，其中複數個第一導線材料和複數個第二導線材料係形成於由該些第二線材料所圍成之一區域內。 The method of claim 22, wherein the plurality of first wire materials and the plurality of second wire materials are formed in a region surrounded by the second wire materials.

如申請專利範圍第22項所述之方法，其中複數個第一導線材料和複數個第二導線材料係形成於由該些第二線材料所圍成之一區域之外部和複數個相對邊上。 The method of claim 22, wherein the plurality of first wire materials and the plurality of second wire materials are formed on an outer portion and a plurality of opposite sides of a region surrounded by the second wire materials .

如申請專利範圍第22項所述之方法，其中該導線材料包括一電路內連線(circuit interconnect line)。 The method of claim 22, wherein the wire material comprises a circuit interconnect line.

如申請專利範圍第12項所述之方法，其中該複加特徵物之形成步驟於該些底端區形成複數個接觸區。 The method of claim 12, wherein the step of forming the complex feature forms a plurality of contact regions in the bottom regions.

一種在黃光微影積體電路製程步驟中用來製作線的多重圖案化方法，包括：為一組平行第一線材料選擇一組平行線圖案；在一基板上形成該組平行第一線材料，該組平行第一線材料的每一第一線材料定義出具有一X方向部分物和一Y方向部分物之一圖案，該些第一線材料之該X方向部分物的長度係至少為該第一線材料之該些Y方向部分物的長度的30倍；為該些X方向部分物和該些Y方向部分物選擇複數個第一間距和第二間距，該第二間距係至少為該第一間距的3倍，該些X方向部分物係為平行的，並且該些Y方向部分物係為平行的；形成平行於每一第一線材料之至少二個第二線材料，以製作出包括複數個平行X方向字元/位元線部分物和複數個平行Y方向字元/位元線部分物的複數個字元/位元線，該些Y方向字元/位元線部分物包括複數個底端區；於該些底端區形成複數個擴大的接觸區；以及形成一導線材料。 A multiple patterning method for fabricating lines in a yellow light lithography circuit process step, comprising: selecting a set of parallel line patterns for a set of parallel first line materials; forming the set of parallel first line materials on a substrate, Each of the first line materials of the set of parallel first line materials defines a pattern having a portion of an X-direction portion and a Y-direction portion, the length of the X-direction portion of the first line material being at least The length of the Y-direction portion of the first line material is 30 times; the plurality of first and second pitches are selected for the X-direction portion and the Y-direction portions, and the second spacing is at least 3 times the first pitch, the X-direction partial systems are parallel, and the Y-direction partial systems are parallel; Forming at least two second line materials parallel to each of the first line materials to produce a plurality of parallel X-direction characters/bit line portions and a plurality of parallel Y-direction characters/bit line portions a plurality of characters/bit lines, the Y-direction character/bit line portion including a plurality of bottom end regions; forming a plurality of enlarged contact regions in the bottom end regions; and forming a wire material.

如申請專利範圍第27項所述之方法，其中該導線材料包括形成複數個第一導電線材料和複數個第二導電線材料於(1)被至少二第二線材料所圍成的一區域內，或是於(2)被該至少二第二線材料所圍成的一區域之外部和複數個相對邊上。 The method of claim 27, wherein the wire material comprises a plurality of first conductive wire materials and a plurality of second conductive wire materials (1) surrounded by at least two second wire materials. Or, (2) an outer portion and a plurality of opposite sides of a region surrounded by the at least two second-line materials.