TWI443665B

TWI443665B - Over-erased verification and repair methods for flash memory

Info

Publication number: TWI443665B
Application number: TW99141864A
Authority: TW
Inventors: Chung Meng Huang; Im-Cheol Ha
Original assignee: Winbond Electronics Corp
Priority date: 2010-12-02
Filing date: 2010-12-02
Publication date: 2014-07-01
Also published as: TW201225090A

Description

反或閘型快閃記憶體與其過抹除驗證與修復方法 Reverse or gate type flash memory and its over-wipe verification and repair method

本發明係有關於一種反或閘型快閃記憶體(NOR type stack flash)與其過抹除(over-erased)驗證與修復方法 The invention relates to an anti-gate type flash (NOR type stack flash) and an over-erased verification and repair method thereof

反或閘型快閃記憶體的設計包括一抹除(erase)操作，用以將所有記憶單元的內容清成同樣值。然而，在抹除操作下，可能會發生有些記憶單元被過抹除(over-erased)，導致該些記憶單元內的電晶體(如MOS)之臨界電壓(threshold voltage)過低，容易產生漏電流(leakage)。 The design of the inverse or gate type flash memory includes an erase operation to clear the contents of all memory cells to the same value. However, under the erase operation, some memory cells may be over-erased, causing the threshold voltage of the transistors (such as MOS) in the memory cells to be too low, which is easy to cause leakage. Current (leakage).

為了解決上述漏電流問題，需要對上述過抹除問題作出相應處理。 In order to solve the above leakage current problem, it is necessary to deal with the above-mentioned over-wiping problem.

本發明揭露一種反或閘型快閃記憶體與其過抹除驗證與修復方法。該方法對該反或閘型快閃記憶體上一扇區逐行個別施行一過抹除行驗證，並對無法通過該過抹除行驗證的行進行一過抹除行修復。此外，該方法更對無法藉由該過抹除行修復通過該過抹除行驗證的行逐位元個別施行一過抹除位元驗證，並對無法通過該過抹除位元驗證的位元進行一過抹除位元修復。 The invention discloses an anti-gate type flash memory and an over-wipe verification and repair method thereof. The method performs an erase line verification on a sector of the inverse or gate type flash memory, and performs an erase line repair on the line that cannot be verified by the erase line. In addition, the method performs an over-erasing bit verification on a row-by-bit individual that cannot be verified by the over-erase row by the over-erase row, and the bit that cannot be verified by the over-erased bit. The element performs an erase erase bit repair.

為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖示，詳細說明如下。 The above described objects, features, and advantages of the invention will be apparent from the description and appended claims appended claims

第1圖圖解反或閘型快閃記憶體(NOR type stack flash)內一記憶單元陣列(對應一扇區(sector))的一種實施方式，標號為100。在抹除(erase)操作中，可能會有過抹除(over-erased)問題發生。舉例說明之，以第一行的記憶單元(資料線BL1所連結的該等記憶單元)為例，若抹除過程中，發現第一行的某些記憶單元較不易抹除，則會持續對第一行內所有的記憶單元進行抹除，直至第一行上所有記憶單元都確時被抹除為止。然而，這樣的操作縱然可以將不易抹除的記憶單元也確實抹除，卻可能會導致第一行內的其它記憶單元被過抹除(over-erased)。過抹除的一種現象是：該記憶單元之電晶體(如MOS)的臨界電壓(threshold voltage)會被壓得很低，導致漏電流。 Figure 1 illustrates an embodiment of a memory cell array (corresponding to a sector) in a NOR type stack flash. The number is 100. In an erase operation, there may be over-erased problems. For example, taking the memory unit of the first row (the memory cells connected by the data line BL1) as an example, if some memory cells in the first row are less easily erased during the erasing process, the pair will continue to be All memory cells in the first row are erased until all memory cells on the first row are erased. However, such an operation may erase the memory cells that are not easily erased, but may cause other memory cells in the first row to be over-erased. One phenomenon of over-wiping is that the threshold voltage of the transistor (such as MOS) of the memory cell is suppressed to be low, resulting in leakage current.

關於上述過抹除問題，本案提出適當的解決方法，其中涉及「過抹除行驗證」、「過抹除行修復」、「過抹除位元驗證」以及「過抹除位元修復」技術。以下分別敘述之。 Regarding the above-mentioned erasure problem, the case proposes an appropriate solution, which involves "over erasing line verification", "over erasing line repair", "over erasing bit verification" and "over erasing bit repair" technology. . The following is described separately.

關於「過抹除行驗證」，其驗證對象是一整行的記憶單元。此技術所得到的驗證結果是該行是否有任何記憶單元有過抹除問題。必須注意的是，過抹除行驗證並不一定能精確指出該行是哪一記憶單元出了問題。所述過抹除行驗證技術可由本技術領域所發展的任何以「行(column)」為驗證單位的過抹除驗證技術實現。 Regarding "over-wipe verification", the verification object is a whole line of memory cells. The verification result obtained by this technique is whether there is any erasing problem in the memory cell of the line. It must be noted that over-wipe verification does not necessarily indicate exactly which memory unit the line is having. The over-erase verification technique can be implemented by any over-wipe verification technique developed in the art using "column" as a verification unit.

關於「過抹除行修復」，是對一整行的記憶單元統一作一次過抹除修復操作，且非對該行的記憶單元個別作修復。所述過抹除行修復技術可由本技術領域所發展的任何以「行(column)」為修復單位的過抹除修復技術實現。 Regarding "over erasing line repair", an entire erasing memory unit is uniformly erased and repaired, and the memory unit of the line is not individually repaired. The over-erasing repair technique can be implemented by any over-wiping repair technique developed in the art using "column" as a repair unit.

關於「過抹除位元驗證」，其驗證對象為單一個記憶單元(位元)或單一組記憶單元(位元組)，所得到的驗證結果是該位元/位元組之記憶單元是否有過抹除問題。所述過抹除位元驗證技術可由本技術領域所發展的任何以「位元(bit)」或「位元組(byte)」為驗證單位的過抹除驗證技術實現。以下為了方便討論，皆以「位元」討論之。需要聲明的是，以下關於「位元」的討論，都更包括「位元組」的例子。 Regarding "over-wipe bit verification", the verification object is a single memory. The unit (bit) or a single group of memory units (bytes), the result of the verification is whether the memory unit of the bit/byte has been erased. The over-erasing bit verification technique can be implemented by any over-wiping verification technique developed in the art by using "bit" or "byte" as a verification unit. The following are discussed in terms of "bits" for the convenience of discussion. It should be noted that the following discussion of "bits" includes examples of "bytes".

關於「過抹除位元修復」，是對單一個記憶單元(位元)或單一組記憶單元(位元組)作過抹除修復操作。所述過抹除位元修復技術可由本技術領域所發展的任何以「位元(bit)」或「位元組(byte)」為修復單位的過抹除修復技術實現。同樣地，以下為了方便討論，皆以「位元」討論之。需要聲明的是，以下關於「位元」的討論，都更包括「位元組」的例子。 Regarding "over erasing bit repair", a single memory unit (bit) or a single group of memory cells (bytes) is erased and repaired. The over-erasing bit repair technique can be implemented by any over-wiping repair technique developed in the art by using "bit" or "byte" as a repair unit. Similarly, the following is discussed in terms of "bits" for the convenience of discussion. It should be noted that the following discussion of "bits" includes examples of "bytes".

此外，關於上述「過抹除行修復」與「過抹除位元修復」，其目的皆包括提升所修復之該行記憶體單元或該記憶體單元內的電晶體(如MOS)之臨界電壓，以避免漏電流發生。關於上述提升電晶體臨界電壓之技術，通常稱為「軟編程(soft program或稱post program)」。對整行記憶單元統一操作者稱為「行軟編程」，可用於所述「過抹除行修復」中。對各個位元操作者稱為「位元軟編程」，可用於所述「過抹除位元修復」中。 In addition, regarding the above-mentioned "over erasing line repair" and "over erasing bit repair", the purpose thereof is to increase the threshold voltage of the repaired memory unit or the transistor (such as MOS) in the memory unit. To avoid leakage currents. The above technique for raising the threshold voltage of a transistor is generally called "soft program or post program". The unified operator of the entire line of memory units is called "line soft programming" and can be used in the "over erasing line repair". It is called "bit soft programming" for each bit operator, and can be used in the "over erasing bit repair".

此段敘述本案所揭露之反或閘型快閃記憶體過抹除驗證與修復方法的一種實施方式。該方法對一反或閘型快閃記憶體上一扇區(sector，可對應前述記憶單元陣列100)逐行(for each column)個別施行上述「過抹除行驗證」，並對無法通過「過抹除行驗證」的行進行上述「過抹除行修復」。此外，該方法更對無法藉由該「過抹除行修復」通過該「過抹除行驗證」的行逐位元(for each bit or byte)個別施行上述「過抹除位元驗證」，並對無法通過該「過抹除位元驗證」的位元進行上述「過抹除位元修復」。此驗證與修復方法，無須如傳統技術般，為了確保扇區內的每一個記憶單元都無過抹除問題，而對扇區內的每一個記憶單元都作驗證動作。事實上，本案之驗證與修復方法是先以「行」為驗證與修復單位處理過抹除問題，只有無法由「過抹除行修復」補救的行，才需要對其中每個位元進行過抹除驗證與修復。本案所揭露之方法可以較短的時間以及較少的操作完成一個扇區的過抹除驗證與修復。 This paragraph describes an embodiment of the inverse or gate type flash memory over-wipe verification and repair method disclosed in the present application. The method is directed to a sector (sector corresponding to the foregoing memory cell array 100) on a reverse or gate type flash memory. For each column, the above-mentioned "over-wipe verification" is performed individually, and the above-mentioned "over-wipe line repair" is performed on a line that cannot be verified by "erasing the line". In addition, the method further performs the above-mentioned "over-wipe bit verification" by using the "over-wipe-line repair" line by bit-by-bit (for each bit or byte). The above "over erasing bit repair" is performed on the bit that cannot pass the "erasing bit verification". This verification and repair method does not need to be a verification operation for each memory unit in the sector in order to ensure that each memory cell in the sector has no erasing problem as in the conventional technology. In fact, the verification and repair method of this case is to use the "line" as the verification and repair unit to deal with the erasing problem. Only the line that cannot be remedied by the "erasing line" is required to perform each bit. Wipe verification and repair. The method disclosed in this case can complete the erasure verification and repair of one sector in a shorter time and with less operation.

以第1圖所揭露之記憶單元矩陣100為例，本案所揭露技術自其中選擇一行記憶單元-例如，位元線BL1所連結的第一行記憶單元-作為一「測試行」的初始設定。接著，對該「測試行(第一行)」執行上述「過抹除行驗證」。再來，判斷該「測試行(第一行)」是否通過上述「過抹除行驗證」。若該「測試行(第一行)」通過該「過抹除行驗證」，則自該扇區(記憶單元陣列100)選擇未驗證過的行-例如，位元線BL2所連結的第二行記憶單元-更新「測試行」，並回到上述對「測試行」執行「過抹除行驗證」的步驟，以切換成對第二行之記憶單元作「過抹除行驗證」。或者，若前述判斷顯示該「測試行(第一行)」並未通過「過抹除行驗證」，則對該「測試行(第一行)」進行「過抹除行修復」。若該「測試行(第一行)」無法藉由該「過抹除行修復」通過「過抹除行驗證」，則對該「測試行(第一行)」的複數個位元個別施行上述「過抹除位元驗證」，並對無法通過該「過抹除位元驗證」的位元進行上述「過抹除位元修復」；此外，若「該測試行(第一行)」中沒有位元無法藉由該「過抹除位元修復」通過「過抹除位元驗證」，則自該扇區(記憶單元陣列100)選擇未驗證過的行-例如，位元線BL2所連結的第二行記憶單元-更新「測試行」，並回到上述對「測試行」執行「過抹除行驗證」的步驟，以切換成對第二行之記憶單元作「過抹除行驗證」。某些實施方式更考慮該「測試行(第一行)」中有位元無法藉由該「過抹除位元修復」通過「過抹除位元驗證」的狀況，其中，會發出「失敗信息」顯示所執行之反或閘型快閃記憶體過抹除驗證與修復方法失敗。 Taking the memory cell matrix 100 disclosed in FIG. 1 as an example, the technique disclosed in the present invention selects a row of memory cells, for example, the first row of memory cells connected by the bit line BL1, as an initial setting of a "test row". Next, the above "test line verification" is performed on the "test line (first line)". Then, it is judged whether or not the "test line (first line)" passes the above "over erasing line verification". If the "test line (first line)" passes the "erasing line verification", an unverified line is selected from the sector (memory cell array 100) - for example, the second line connected by the bit line BL2 Line Memory Unit - Update the "Test Line" and return to the above "Test Line" to perform the "Erase Line Verification" step to switch to the "Secondary Line Verification" of the memory unit of the second line. Or, if the above judgment indicates that the "test line (first line)" has not passed the "erasing line verification", the "test line (first line)" is "erased" Line repair." If the "test line (first line)" cannot pass the "erasing line verification" by "over erasing line repair", then the multiple bits of the "test line (first line)" are executed individually. The above "Erase erase bit verification" and the above "over erase bit repair" for the bit that cannot pass the "Erase erase bit verification"; in addition, if "The test line (first line)" No bit in the cell cannot be unverified from the sector (memory cell array 100) by "over erasing bit repair" by "erase erasing bit" - for example, bit line BL2 Connected second row memory unit - update "test line" and return to the above "test line" to perform "over erase line verification" step to switch to "erasing" the second line of memory cells Line verification." In some implementations, it is considered that a bit in the "test line (first line)" cannot pass the "erasing bit-repair" condition by the "erasing bit-repair", in which a "failure" is issued. The message "displays" the inverse or gate type flash memory over-erasing verification and repair method failed.

第2圖以流程圖揭露本發明反或閘型快閃記憶體過抹除驗證與修復方法的一種實施方式，其中針對一扇區之過抹除驗證與修復作說明。 FIG. 2 is a flow chart showing an embodiment of the method for verifying and repairing the anti-gate type flash memory over erasing of the present invention, wherein the erasing verification and repair of a sector are explained.

步驟S202用於對「測試行」作初始設定(如前述，自記憶單元陣列100中選擇一行作為「測試行」)、並且將「行測試迴圈數」歸零。步驟S204對該「測試行」執行「過抹除行驗證」。步驟S206判斷該「測試行」是否通過「過抹除行驗證」。若步驟S206判定該「測試行」無法通過「過抹除行驗證」，則流程進入「過抹除行修復」(包括圖2步驟S208、S212、S214、S204與S206所組成的迴圈)。 Step S202 is for initial setting of the "test line" (as described above, selecting one line from the memory cell array 100 as a "test line"), and zeroing the "line test loop number". Step S204 performs "erasing line verification" on the "test line". Step S206 determines whether the "test line" passes the "erasing line verification". If it is determined in step S206 that the "test line" cannot pass the "erasing line verification", the flow proceeds to "over erasing line repair" (including the loop formed by steps S208, S212, S214, S204 and S206 of Fig. 2).

此段討論所述「過抹除行修復」。首先，執行步驟S208，判斷「行測試迴圈數」是否達一第一上限(可由使用者依照需求設定)。在步驟S208判斷「行測試迴圈數」未達該第一上限的狀況下，執行步驟S212，對該「測試行」進行「行軟編程」。接著，執行步驟S214，將「行測試迴圈數」加1。再來，回到步驟S204，對經「行軟編程」處理過的「測試行」再次施行「過抹除行驗證」，並以步驟S206判斷目前的「測試行」是否通過「過抹除行驗證」。若步驟S206顯示經「行軟編程」處理過的「測試行」已可通過「過抹除行驗證」，則執行步驟S216，判斷該扇區內是否還有未驗證過的行，並執行步驟S218，自未驗證過的行中擇一更新「測試行」、並歸零「行測試迴圈數」。接著，流程會回到步驟S204，以對更新過的「測試行」另外施行「過抹除行驗證」以及後續動作。然而，若經「行軟編程」作用之「測試行」仍無法通過「過抹除行驗證」(由步驟S206判斷)，則如圖2流程圖所示，步驟S208再次被執行，判斷目前的「行測試迴圈數」是否達到該第一上限，以決定施行步驟S212、或轉而施行步驟S210。關於步驟S210，是在步驟S208判斷該「行測試迴圈數」達該第一上限後實施。若步驟S208判斷出該「行測試迴圈數」達到該第一上限，所揭露的方法會判定該「測試行」無法藉由「過抹除行修復」通過「過抹除行驗證」。流程進入步驟S210，對該「測試行」逐位元作「過抹除位元驗證」，並對無法通過「過抹除位元驗證」的位元進行「過抹除位元修正」。某些實施方式更如圖2流程，於步驟S210後更執行一步驟S220，判斷該「測試行」所有位元可否全數成功通過「過抹除位元驗證」。若皆可成功，則流程進入步驟S216。若無法全數成功，則發出失敗信息，顯示所施行之反或閘型快閃記憶體過抹除驗證與修復方法失敗。 This paragraph discusses the "over erasing line repair". First, step S208 is performed, Determine whether the "number of line test loops" reaches a first upper limit (can be set by the user according to requirements). If it is determined in step S208 that the "number of line test loops" has not reached the first upper limit, step S212 is executed to perform "line soft programming" on the "test line". Next, in step S214, "the number of line test loops" is incremented by one. Then, returning to step S204, the "test line" processed by "line soft programming" is again subjected to "erasing line verification", and in step S206, it is determined whether the current "test line" passes the "erasing line". verification". If the step S206 shows that the "test line" processed by "line soft programming" can pass the "erasing line verification", step S216 is executed to determine whether there are any unverified lines in the sector, and steps are performed. S218: Select one of the unverified lines to update the "test line" and return to the "line test loop number". Then, the flow returns to step S204 to perform "over-wipe verification" and subsequent actions on the updated "test line". However, if the "test line" functioned by "soft programming" cannot pass the "erasing line verification" (determined by step S206), as shown in the flowchart of FIG. 2, step S208 is executed again to judge the current Whether or not the "line test loop number" reaches the first upper limit is determined to execute step S212 or to execute step S210. In step S210, it is determined in step S208 that the "row test loop number" reaches the first upper limit. If it is determined in step S208 that the "number of line test loops" reaches the first upper limit, the disclosed method determines that the "test line" cannot pass "erasing line verification" by "over erasing line repair". The flow proceeds to step S210, the "test line" bit by bit is "over erased bit verification", and the "over erase bit correction" is performed for the bit that cannot be "erased by the erased bit". Some embodiments are further illustrated in FIG. 2, and after step S210, a step S220 is further performed to determine whether all the bits of the "test row" can be successfully passed. Erase bit verification." If all can be successful, the flow proceeds to step S216. If it is not successful, a failure message is sent indicating that the reverse or gate flash memory over-validation verification and repair method failed.

此段對照第1圖之記憶單元陣列，說明第2圖步驟S220-以「位元」為對象的過抹除驗證與修復-的一種實施方式。假設目前「測試行」為「第一行(與位元線BL1相連的該行記憶單元)」。若該「測試行(第一行)」需要更以「位元」為對象進行過抹除驗證與修復，可自該「測試行(第一行)」中選擇一位元(例如，由字元線WL1所控制的該記憶單元，即第一行第一列之記憶單元)作為一「測試位元」的初始設定，並對該「測試位元(第一行第一列之記憶單元)」作「過抹除位元驗證」，且判斷該「測試位元(第一行第一列之記憶單元)」是否通過該「過抹除位元驗證」。若該「測試位元(第一行第一列之記憶單元)」通過該「過抹除位元驗證」，則自「該測試行(第一行)」選擇一個未驗證過的位元-例如，由字元線WL2所控制的該記憶單元，即第一行第二列之記憶單元-更新「測試位元」，並回到上述對「測試位元」執行「過抹除位元驗證」的步驟，以切換成對第一行第二列之記憶單元作「過抹除位元驗證」。或者，若該「測試位元(第一行第一列之記憶單元)」並未能通過該「過抹除位元驗證」，則對該「測試位元(第一行第一列之記憶單元)」進行「過抹除位元修復」。倘若該「測試位元(第一行第一列之記憶單元)」無法藉由該「過抹除位元修復」通過「過抹除位元驗證」，則發出失敗信息顯示所施行之反或閘型快閃記憶體過抹除驗證與修復方法失敗。 This section compares the memory cell array of FIG. 1 with an embodiment of step S220 of FIG. 2 - over-wipe verification and repair with "bits" as the object. Assume that the current "test line" is "the first line (the line of memory cells connected to the bit line BL1)". If the "test line (first line)" needs to be erased and verified with "bit" as the object, select one element from the "test line (first line)" (for example, by word) The memory unit controlled by the line WL1, that is, the memory unit of the first row and the first column) is used as an initial setting of a "test bit", and the "test bit (the memory unit of the first row and the first column) "Over erase level verification" and determine whether the "test bit (memory unit in the first row of the first row)" passes the "erased by bit erase". If the "test bit (memory unit in the first row and first column)" passes the "erased by bit erase", then an unverified bit is selected from "the test line (first line)" - For example, the memory unit controlled by the word line WL2, that is, the memory unit of the first row and the second column - updates the "test bit" and returns to the above-mentioned "test bit" to perform "erasing bit verification" The step of switching to the memory cell of the first row and the second column is "over erase bit verification". Or, if the "test bit (memory unit in the first column of the first row)" fails to pass the "erased by bit erase", then the "test bit" (memory of the first row and the first column) Unit)" performs "Erase erase bit repair". If the "test bit (memory unit in the first row of the first row)" cannot pass the "erase erase bit verification" by the "erase erase bit repair", a failure message is displayed indicating that the execution is reversed or The gate flash memory over erase verification and repair method failed.

第3圖以一流程圖揭露以「位元」為對象之過抹除驗證與修復的一種實施方式。流程300可用來實現第2圖之步驟S220。 Fig. 3 discloses an embodiment of the erasure verification and repair using "bits" as a flowchart. Flow 300 can be used to implement step S220 of Figure 2.

步驟S302用於對「測試位元」作初始設定(如前述，自目前「測試行」中選擇一位元作為「測試位元」)、並且將「位元測試迴圈數」歸零。步驟S304對該「測試位元」執行「過抹除位元驗證」。步驟S306判斷該「測試位元」是否通過該「過抹除位元驗證」。若步驟S306判定該「測試位元」無法通過該「過抹除位元驗證」，則流程進入「過抹除位元修復」(包括圖3步驟S308、S310、S312、S304與S306所組成的迴圈)。 Step S302 is used to initially set the "test bit" (as described above, select one bit from the current "test line" as the "test bit"), and zero the "bit test loop". In step S304, "erasing bit verification" is performed on the "test bit". Step S306 determines whether the "test bit" passes the "erasing bit verification". If it is determined in step S306 that the "test bit" cannot pass the "erasing bit verification", the flow proceeds to "over erasing bit repair" (including steps S308, S310, S312, S304 and S306 of FIG. 3). Loop).

此段討論所述「過抹除位元修復」。首先，執行步驟S308，判斷「位元測試迴圈數」是否達一第二上限(可由使用者依照需求設定)。在「位元測試迴圈數」未達該第二上限的狀況下，執行步驟S310，對該「測試位元」進行「位元軟編程」。接著，執行步驟S312，將「位元測試迴圈數」加1。再來，回到步驟S304，對經「位元軟編程」處理過的「測試位元」再次施行「過抹除位元驗證」，並以步驟S306判斷目前的「測試位元」是否通過「過抹除位元驗證」。若步驟S306顯示經「位元軟編程」處理過的「測試位元」已可通過「過抹除位元驗證」，則執行步驟S314，判斷目前「測試行」內是否還有未驗證過的位元，並執行步驟S316，自未驗證過的位元中擇一更新「測試位元」、並歸零「位元測試迴圈數」。接著，流程會回到步驟S304，以對更新過的「測試位元」另外施行「過抹除位元驗證」以及後續動作。然而，若經「位元軟編程」作用之「測試位元」仍無法通過「過抹除位元驗證」(由步驟S306判斷)，則如圖3流程圖所示，步驟S308再次被執行，判斷目前的「位元測試迴圈數」是否達到該第二上限。若「位元測試迴圈數」未達該第二上限，則施行步驟S310，繼續所述「過抹除位元修復」。若「位元測試迴圈數」已達該第二上限，則代表「測試位元」無法藉由「過抹除位元修復」通過「過抹除位元驗證」，所揭露方法將發佈失敗信息。 This paragraph discusses the "over erasing bit repair". First, step S308 is executed to determine whether the "bit test loop number" reaches a second upper limit (which can be set by the user according to requirements). In a case where the "bit test loop number" does not reach the second upper limit, step S310 is executed to perform "bit soft programming" on the "test bit". Next, in step S312, the "bit test loop number" is incremented by one. Then, returning to step S304, the "test bit" that has been processed by the "bit soft programming" is again subjected to "over erasing bit verification", and in step S306, it is determined whether the current "test bit" has passed " Over erase bit verification." If the "test bit" processed by the "bit soft programming" has passed the "erasing the bit verification", the step S314 is executed to determine whether there is still an unverified test in the "test line". The bit is executed, and step S316 is executed to update the "test bit" from the unverified bits and return to the "bit test loop number". Then, the process returns to step S304 to perform an "over-wipe bit verification" on the updated "test bit". And follow-up actions. However, if the "test bit" functioned by the "bit soft programming" cannot pass the "erasing of the erasing bit" (as determined by step S306), as shown in the flowchart of FIG. 3, step S308 is executed again. Determine whether the current "bit test loop number" reaches the second upper limit. If the "bit test loop number" does not reach the second upper limit, then step S310 is performed to continue the "over erase bit repair". If the "bit test loop number" has reached the second upper limit, it means that the "test bit" cannot be over-erased by the "erased bit" and the disclosed method will fail to be published. information.

第4圖圖解本案反或閘型快閃記憶體的一種實施方式。反或閘型快閃記憶體400包括至少一扇區(該扇區可為圖1所示之記憶體單元陣列100)以及一控制器402。控制器402可實施前述之過抹除驗證與修復技術，包括對該記憶單元陣列100逐行個別施行上述「過抹除行驗證」，並對無法通過該「過抹除行驗證」的行進行上述「過抹除行修復」，以及對於無法藉由「過抹除行修復」通過「過抹除行驗證」的行，逐位元個別施行上述「過抹除位元驗證」，並對無法通過該「過抹除位元驗證」的位元進行上述「過抹除位元修復」。 Figure 4 illustrates an embodiment of the inverse or gate type flash memory of the present invention. The inverse or gate type flash memory 400 includes at least one sector (which may be the memory cell array 100 shown in FIG. 1) and a controller 402. The controller 402 can implement the above-described over-wipe verification and repair technology, including performing the above-mentioned "over-wipe verification" on the memory cell array 100 line by line, and performing the line that cannot pass the "erasing line verification". The above "over erasing line repair", and for the line that cannot be verified by "erasing line erasure", the above-mentioned "over erasing bit verification" is performed individually on a bit-by-bit basis, and The above "over erasing bit repair" is performed by the bit of the "erasing bit verification".

此外，該控制器402也可用於實現前述其他種過抹除驗證與修復技術。 In addition, the controller 402 can also be used to implement the aforementioned other over-erasing verification and repair techniques.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟悉此項技藝者，在不脫離本發明之精神和範圍內，當可做些許更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧記憶體單元陣列 100‧‧‧Memory Cell Array

400‧‧‧反或閘型快閃記憶體 400‧‧‧Anti-gate type flash memory

402‧‧‧控制器 402‧‧‧ Controller

BL1…BLM‧‧‧位元線 BL1...BLM‧‧‧ bit line

S202…S220‧‧‧扇區之過抹除驗證與修復的多個步驟 Multiple steps of S202...S220‧‧‧ sector erasure verification and repair

S302…S316‧‧‧關於步驟S220-以目前「測試行」之「位元」為對象的過抹除驗證與修復-的一種實施方式之多個步驟 S302...S316‧‧‧Steps S220 - Multiple steps of an embodiment of over-wipe verification and repair for the "bits" of the current "test line"

WL1…WLN‧‧‧字元線 WL1...WLN‧‧‧ character line

第1圖圖解反或閘型快閃記憶體(NOR type stack flash)內一記憶單元陣列的一種實施方式；第2圖以流程圖揭露本發明反或閘型快閃記憶體過抹除驗證與修復方法的一種實施方式，其中針對一扇區之過抹除驗證與修復作說明；第3圖以一流程圖揭露以「位元」為對象的過抹除驗證與修復的一種實施方式，所揭露的流程300可用來實現第2圖之步驟S220；以及第4圖圖解本案反或閘型快閃記憶體的一種實施方式。 1 is a diagram showing an embodiment of a memory cell array in a NOR type stack flash; FIG. 2 is a flow chart showing the inverse or gate type flash memory over-wipe verification of the present invention. An embodiment of the repair method, wherein the erasing verification and repair of a sector are explained; FIG. 3 is a flow chart exposing an implementation method of over-wiping verification and repair using "bit" as a target, The disclosed process 300 can be used to implement step S220 of FIG. 2; and FIG. 4 illustrates an embodiment of the inverse or gate type flash memory of the present invention.

S202…S220‧‧‧對一扇區施行過抹除驗證與修復的多個步驟 S202...S220‧‧‧Multiple steps for erasing verification and repair of a sector

Claims

一種反或閘型快閃記憶體過抹除驗證與修復方法，包括：對一反或閘型快閃記憶體上一扇區逐行個別施行一過抹除行驗證，並對無法通過該過抹除行驗證的行進行一過抹除行修復；以及對於無法藉由該過抹除行修復通過該過抹除行驗證的行，逐位元個別施行一過抹除位元驗證，並對無法通過該過抹除位元驗證的位元進行一過抹除位元修復。 An anti-gate type flash memory over-wipe verification and repair method, comprising: performing a wipe-by-line verification on a sector on a sector of a reverse or gate type flash memory, and failing to pass the Erasing the row of the row verification to perform an erase row repair; and for the row that cannot be verified by the erase erase row by the erase erase row, the bitwise individual performs an erase erase bit verification, and It is not possible to perform an erase erase bit repair by the bit that has been erased by the erased bit.

如申請專利範圍第1項所述之方法，其中更包括：自該扇區中選擇一行記憶單元，作為一測試行的初始設定；對該測試行執行該過抹除行驗證；判斷該測試行是否通過該過抹除行驗證；若該測試行通過該過抹除行驗證，則自該扇區選擇未驗證過的行更新該測試行，並回到上述對該測試行執行該過抹除行驗證的步驟；並且若該測試行未通過該過抹除行驗證，則對該測試行進行該過抹除行修復，其中：若該測試行無法藉由該過抹除行修復通過該過抹除行驗證，則對該測試行內的複數個位元個別施行該過抹除位元驗證，並對無法通過該過抹除位元驗證的位元進行該過抹除位元修復；以及若該測試行中沒有位元無法藉由該過抹除位元修復通過該過抹除位元驗證，則自該扇區選擇未驗證過的行更新該測試行，並回到上述對該測試行執行該過抹除行驗證的步驟。 The method of claim 1, further comprising: selecting a row of memory cells from the sector as an initial setting of a test line; performing the over-wipe verification on the test line; determining the test line Whether the verification is performed by the erase line; if the test line is verified by the erase line, the untested line is selected from the sector to update the test line, and the above-mentioned over-erasing is performed on the test line. The step of verifying the line; and if the test line does not pass the erase line verification, the line is repaired by the erase line, wherein: if the test line cannot be repaired by the erase line If the row verification is erased, the over-erasing bit verification is performed on the plurality of bits in the test row, and the over-erasing bit repair is performed on the bit that cannot be verified by the over-erased bit; If no bit in the test line cannot be verified by the over erase bit by the over erase bit, the unselected from the sector is selected. The past line updates the test line and returns to the step of performing the erase line verification on the test line.

如申請專利範圍第2項所述之方法，其中，若無法藉由上述過抹除行修復通過該過抹除行驗證的該測試行中有位元無法藉由該過抹除位元修復通過該過抹除位元驗證，則發出失敗信息顯示上述反或閘型快閃記憶體過抹除驗證與修復方法失敗。 The method of claim 2, wherein, if the over-erasing row cannot be repaired, the bit in the test row verified by the over-erasing row cannot be repaired by the over-erasing bit. The over-erasing bit verification verifies that the above-mentioned inverse or gate type flash memory over-erasing verification and repair method fails.

如申請專利範圍第3項所述之方法，其中更包括將一行測試迴圈數的初始值設定為零，並且於施行該過抹除行修復時執行以下步驟：判斷該行測試迴圈數是否達一第一上限；於該行測試迴圈數達該第一上限時，判定該測試行無法藉由該過抹除行修復通過該過抹除行驗證；以及於該行測試迴圈數未達該第一上限時，對該測試行進行一行軟編程，且將該行測試迴圈數加1，並再次判斷該測試行是否通過該過抹除行驗證，其中：若該測試行得以藉由該行軟編程通過該過抹除行驗證，則自該扇區選擇未驗證過的行更新該測試行、並歸零該行測試迴圈數，以對更新過的該測試行另外施行該過抹除行驗證；並且若該測試行無法藉由該行軟編程通過該過抹除行驗證，則重新執行上述判斷該行測試迴圈數是否達該第一上限的步驟。 The method of claim 3, further comprising setting an initial value of the number of test loops to zero, and performing the following steps when performing the erase erase repair: determining whether the test loop number of the row is Up to a first upper limit; when the number of test loops reaches the first upper limit, it is determined that the test line cannot be verified by the over erase line by the over erase line; and the number of loops tested in the line is not When the first upper limit is reached, a soft programming is performed on the test line, and the number of test loops is increased by one, and it is determined again whether the test line passes the erase erase line verification, wherein: if the test line can be borrowed By the line soft programming, the over-erase row verification is performed, the untested row is selected from the sector to update the test row, and the row test loop number is zeroed to additionally perform the modified test row. After the line verification is performed; and if the test line cannot pass the erase line verification by the line soft programming, the step of determining whether the line test loop number reaches the first upper limit is re-executed.

如申請專利範圍第4項所述之方法，其中更包括：自無法藉由該過抹除行修復通過該過抹除行驗證的該測試行的該等位元中擇一，作為一測試位元的初始設定；對該測試位元作該過抹除位元驗證；判斷該測試位元是否通過該過抹除位元驗證；若該測試位元通過該過抹除位元驗證，則自該測試行選擇未驗證過的位元更新該測試位元，並回到上述對該測試位元執行該過抹除位元驗證的步驟；並且若該測試位元未通過該過抹除位元驗證，則對該測試位元進行該過抹除位元修復，其中：若該測試位元無法藉由該過抹除位元修復通過該過抹除位元驗證，則發出失敗信息顯示上述反或閘型快閃記憶體過抹除驗證與修復方法失敗。 The method of claim 4, further comprising: the verification that the over-erasing line cannot be verified by the over-erasing line Selecting one of the bits of the test line as an initial setting of a test bit; performing the over-erasing bit verification on the test bit; determining whether the test bit is verified by the over-erased bit; The test bit is verified by the over-erased bit, and the untested bit is selected from the test row to update the test bit, and the step of performing the over-erasing bit verification on the test bit is returned. And if the test bit is not verified by the erased bit, the over-pad repair is performed on the test bit, wherein: if the test bit cannot be repaired by the over-erased bit The over-erasing bit verification verifies that the above-mentioned inverse or gate type flash memory over-erasing verification and repair method fails.

如申請專利範圍第5項所述之方法，其中更包括於判定該測試行無法藉由該過抹除行修復通過該過抹除行驗證時將一位元測試迴圈數的初始值設定為零，並且於施行該過抹除位元修復時執行以下步驟：判斷該位元測試迴圈數是否達一第二上限；於該位元測試迴圈數達該第二上限時，判定該測試位元無法藉由該過抹除位元修復通過該過抹除行驗證；以及於該位元測試迴圈數未達該第二上限時，對該測試位元進行一位元軟編程，且將該位元測試迴圈數加1，並再次判斷該測試位元是否通過該過抹除行驗證，其中：若該測試位元得以藉由該位元軟編程通過該過抹除位元驗證，則自該測試行選擇未驗證過的位元更新該測試位元、並歸零該位元測試迴圈數，並回到上述對該測試位元執行該過抹除位元驗證的步驟；並且若該測試位元無法藉由該位元軟編程通過該過抹除位元驗證，則回到上述判斷該位元測試迴圈數是否達該第二上限的步驟。 The method of claim 5, further comprising determining that the test line cannot set the initial value of the one-bit test loop number to be verified by the over-erase line repair by the over-erasing line verification. Zero, and performing the following step of erasing the bit repair: determining whether the number of loops of the bit test reaches a second upper limit; determining the test when the number of loops of the bit test reaches the second upper limit The bit cannot be verified by the over-erasing row by the over-erasing bit; and when the bit-testing loop does not reach the second upper limit, the test bit is subjected to one-bit soft programming, and Adding the number of loops of the bit test to 1 and judging whether the test bit is verified by the erase line, wherein: if the test bit is soft-programmed by the bit, the erased bit is verified by the bit And selecting, from the test line, the unverified bit to update the test bit, and returning to the bit test loop number, and returning to the step of performing the erase erase bit verification on the test bit; and If the test bit cannot be verified by the bit erase bit by the bit soft programming, return to the step of determining whether the bit test loop number reaches the second upper limit.

一種反或閘型快閃記憶體，包括：至少一扇區，包括一記憶單元陣列；一控制器，用以對該扇區之該記憶單元陣列逐行個別施行一過抹除行驗證，並對無法通過該過抹除行驗證的行進行一過抹除行修復，以及對於無法藉由該過抹除行修復通過該過抹除行驗證的行，逐位元個別施行一過抹除位元驗證，並對無法通過該過抹除位元驗證的位元進行一過抹除位元修復。 An anti-gate type flash memory, comprising: at least one sector, comprising a memory cell array; and a controller for performing an erase line verification on the memory cell array of the sector row by row, and Performing an erase line repair on the line that cannot be verified by the erase line, and performing an erase bit on the bit by bit for the line that cannot be verified by the erase line by the erase line. Meta-verification, and an erasing bit repair for a bit that cannot be verified by the erased bit.