TWI442474B - Methods for forming conformal oxide layers on semiconductor devices - Google Patents

Description

用於在半導體裝置上形成共形氧化層的方法Method for forming a conformal oxide layer on a semiconductor device

本發明實施例大體而言係有關於半導體製造，並且更明確地說，係有關於半導體裝置或其零組件的氧化以形成共形氧化物層。Embodiments of the present invention are generally related to semiconductor fabrication and, more specifically, to oxidation of a semiconductor device or its components to form a conformal oxide layer.

半導體裝置在其若干製造階段需形成薄氧化物層。例如，在電晶體中，一薄閘極氧化物層可形成為一閘極堆疊結構的一部分，包含側壁，如會在後方詳加描述者。此外，在某些應用中，例如在快閃記憶體薄膜堆疊的製造中，可在整個閘極堆疊周圍形成薄氧化物層，例如，藉由將該堆疊暴露在氧化製程中。此類氧化製程習知上係以熱方法執行或利用電漿執行。Semiconductor devices require the formation of a thin oxide layer during several stages of their fabrication. For example, in a transistor, a thin gate oxide layer can be formed as part of a gate stack structure, including sidewalls, as will be described later. Moreover, in certain applications, such as in the fabrication of flash memory film stacks, a thin oxide layer can be formed around the entire gate stack, for example, by exposing the stack to an oxidation process. Such oxidation processes are conventionally performed by thermal methods or by using plasma.

形成氧化物層，例如，該閘極氧化物層或該閘極堆疊氧化層，的熱製程在過去所使用的較大特徵結構尺寸半導體裝置的製造中成效相當好。不幸地，隨著特徵結構尺寸大幅度縮小並且在下世代的先進技術中使用不同氧化物，熱氧化製程所需的高晶圓或基材溫度會因為矽晶圓內的摻質(井摻雜及接合面)在較高溫度下(例如高於約700℃)擴散而造成問題。此種摻質輪廓及其他特徵結構的失真可導致不良的裝置效能或失效。The thermal process of forming an oxide layer, such as the gate oxide layer or the gate stack oxide layer, works well in the fabrication of larger feature size semiconductor devices used in the past. Unfortunately, as feature sizes shrink dramatically and different oxides are used in next-generation advanced technologies, the high wafer or substrate temperature required for thermal oxidation processes can be due to dopants in the germanium wafer (well doping and The joint surface) diffuses at higher temperatures (e.g., above about 700 ° C) causing problems. Distortion of such dopant profiles and other features can result in poor device performance or failure.

用來形成氧化物層的電漿製程擁有類似問題。例如，在高腔室壓力下(例如100毫托耳)，形成期間污染物有匯聚在該閘極氧化物層內的傾向，造成閘極氧化物結構的嚴重缺陷，例如懸鍵(dangling bonds)或移動電荷，而在低腔室壓力下(例如數十毫托耳)，增加的電漿離子能量造成離子轟擊傷害和其它擴散問題。例如，習知氧化製程常造成稱為鳥嘴的缺陷。鳥嘴係指氧化物層從相鄰層之間介面處的側邊擴散進入薄膜堆疊結構的層內，環繞該等相鄰層的角落。所造成的缺陷具有類似鳥嘴的輪廓。該氧化層侵入該記憶單元(例如在快閃記憶體應用中)的主動區會縮小該記憶單元的主動寬度，因此不預期縮小該單元的有效寬度，並降低該快閃記憶體裝置的效能。The plasma process used to form the oxide layer has similar problems. For example, at high chamber pressures (eg, 100 mTorr), there is a tendency for contaminants to converge within the gate oxide layer during formation, causing serious defects in the gate oxide structure, such as dangling bonds or The charge is moved, and at low chamber pressures (eg, tens of milliTorr), the increased plasma ion energy causes ion bombardment damage and other diffusion problems. For example, conventional oxidation processes often cause defects known as bird's beak. A bird's beak refers to an oxide layer that diffuses from the side at the interface between adjacent layers into the layer of the film stack structure, surrounding the corners of the adjacent layers. The resulting defect has a contour similar to a bird's beak. The active region of the oxide layer invading the memory cell (e.g., in a flash memory application) reduces the active width of the memory cell, and thus is not expected to reduce the effective width of the cell and reduce the performance of the flash memory device.

現行低溫電漿製程的另一限制在於氧化似乎優先在與該晶圓或基材面平行的表面上發生，也就是說，結構的頂部和底部，例如藉由堆疊材料層所形成的閘極以及形成在該等閘極之間的溝槽。咸信這是緣於與該晶圓垂直的氧離子和自由基流通量。無論成因為何，該等堆疊側壁上發生有限的氧化，在該等閘極堆疊上產生薄到令人無法接受的側壁層和極差的共形性。因此，需要一種改善的在半導體基材上形成氧化物層的方法。Another limitation of current low temperature plasma processes is that oxidation appears to occur preferentially on surfaces parallel to the wafer or substrate surface, that is, the top and bottom of the structure, such as the gate formed by stacking layers of material, and A trench is formed between the gates. This is due to the oxygen ion and free radical flux perpendicular to the wafer. No matter what happens, there is limited oxidation on the stacking sidewalls, resulting in thin to unacceptable sidewall layers and poor conformality on the gate stacks. Therefore, there is a need for an improved method of forming an oxide layer on a semiconductor substrate.

本發明之一態樣係有關於一種處理形成在一半導體基材上的氧化物層的方法。根據一或多個實施例，該方法包含將此種基材置於一電漿反應室內一基材支撐件上。在一或多個實施例中使用的腔室包含一離子產生區。該方法也可包含通入或流入一製程氣體進入該腔室，其中，在該離子產生區內，一電漿係經產生在該腔室的離子產生區內，並用來在該基材上形成一氧化物層。根據一或多個實施例形成的電漿可含氧或一氧物種。在一或多個實施例中，該氧化物層係在該基材主動冷卻期間由該電漿形成。在此實施例中，主動冷卻該基材增加某些電漿內所含氧物種之黏滯係數。One aspect of the invention pertains to a method of treating an oxide layer formed on a semiconductor substrate. In accordance with one or more embodiments, the method includes placing such a substrate on a substrate support within a plasma reaction chamber. The chamber used in one or more embodiments includes an ion generating region. The method may also include introducing or flowing a process gas into the chamber, wherein in the ion generating region, a plasma is generated in the ion generating region of the chamber and used to form on the substrate. An oxide layer. The plasma formed in accordance with one or more embodiments may contain oxygen or an oxygen species. In one or more embodiments, the oxide layer is formed from the plasma during active cooling of the substrate. In this embodiment, actively cooling the substrate increases the viscosity coefficient of the oxygen species contained in certain plasmas.

根據一或多個實施例，該基材係經冷卻至低於約100℃的溫度。在一具體實施例中，該基材係經冷卻至範圍在約-50℃至約100℃內的溫度。在一更具體的實施例中，該基材係經冷卻至範圍在約-25℃至75℃內的溫度，並且在一甚至更具體的實施例中，該基材係經冷卻至範圍在約0℃至約50℃內的溫度。According to one or more embodiments, the substrate is cooled to a temperature below about 100 °C. In a specific embodiment, the substrate is cooled to a temperature ranging from about -50 ° C to about 100 ° C. In a more specific embodiment, the substrate is cooled to a temperature ranging from about -25 ° C to 75 ° C, and in an even more specific embodiment, the substrate is cooled to a range of about Temperature from 0 ° C to about 50 ° C.

如在此所使用者，“主動冷卻”一詞表示在該基材鄰近流通一冷卻流體。在一實施例中，利用一靜電夾盤(ESC)在該基材鄰近流通一冷卻流體。在另一實施例中，供應一對流氣體至該腔室並在該基材鄰近流通。As used herein, the term "active cooling" means the circulation of a cooling fluid adjacent to the substrate. In one embodiment, an electrostatic chuck (ESC) is used to circulate a cooling fluid adjacent the substrate. In another embodiment, a pair of flow gases are supplied to the chamber and circulated adjacent the substrate.

根據一或多個實施例，該基材係藉由使一冷卻劑流經該基材支撐件來主動冷卻。在一具體實施例中，該冷卻劑係在該基材和基材支撐件間循環。該基材也可，例如，透過接觸該基材表面來冷卻，其中，在一具體實施例中，其含有複數個冷卻導管。在一更具體的實施例中，該基材支撐件使用一系列通道來供應一冷卻劑至該等冷卻導管。適用於此種實施例的冷卻劑包含氦氣，其他惰性氣體及其組合物。According to one or more embodiments, the substrate is actively cooled by flowing a coolant through the substrate support. In a specific embodiment, the coolant circulates between the substrate and the substrate support. The substrate can also be cooled, for example, by contact with the surface of the substrate, wherein, in one embodiment, it contains a plurality of cooling conduits. In a more specific embodiment, the substrate support uses a series of channels to supply a coolant to the cooling conduits. Coolants suitable for use in such embodiments include helium, other inert gases, and combinations thereof.

一或多個其他實施例藉由流通一對流氣體進入該反應室內來主動冷卻該基材。在一具體實施例中，一氦氣係經流入該反應室內以主動冷卻該基材。在一更具體的實施例中，對流氣體係以範圍從約500sccm至約3000sccm的流速流入該反應室。在一或多個實施例中使用的對流氣體包含氦氣，並且也可包含一或多種其他惰性氣體。One or more other embodiments actively cool the substrate by flowing a pair of flowing gases into the reaction chamber. In one embodiment, an inert gas stream is passed into the reaction chamber to actively cool the substrate. In a more specific embodiment, the convection gas system flows into the reaction chamber at a flow rate ranging from about 500 sccm to about 3000 sccm. The convective gas used in one or more embodiments comprises helium and may also comprise one or more other inert gases.

前面已相當廣泛概述本發明之某些特徵結構。熟知技藝者應領會所揭示的具體實施例可輕易用做調整或設計落在本發明範圍內之其他結構或製程的基礎。熟知技藝者也應理解此種等效結構並不背離在附屬申請專利範圍中提出之本發明精神及範圍。Certain features of the present invention have been fairly broadly outlined above. Those skilled in the art will appreciate that the specific embodiments disclosed may be readily utilized as a basis for adapting or designing other structures or processes that fall within the scope of the invention. It is also understood by those skilled in the art that such equivalent constructions are not to be

本發明實施例提供藉由氧化半導體基材形成共形氧化物層的方法。下述具體實施例係關於利用低溫氧化法形成的氧化物層描述。Embodiments of the present invention provide methods of forming a conformal oxide layer by oxidizing a semiconductor substrate. The following specific examples are directed to oxide layer formations formed using low temperature oxidation processes.

如在此所使用者，低溫氧化表示在低於約700℃的溫度下之氧化。習知電漿氧化因為傳送至該基材的電漿功率而在高於100℃的溫度下發生。在高於100℃的溫度下，氧離子流通量支配該氧化製程，因此僅有半數的氧化流通量抵達垂直側壁，與抵達寬度為50奈米之結構的水平壁(也可稱為頂和底表面或閘極和溝槽)的氧化流通量相比。據此，當共形性係定義為一側壁上的成長及一頂或底表面上的成長之比例時，在大於25埃的厚度下，習知電漿氧化僅達到50%的共形性。As used herein, low temperature oxidation means oxidation at temperatures below about 700 °C. Conventional plasma oxidation occurs at temperatures above 100 ° C due to the plasma power delivered to the substrate. At temperatures above 100 ° C, the oxygen ion flux dominates the oxidation process, so only half of the oxidation flux reaches the vertical sidewalls and reaches the horizontal wall of the structure with a width of 50 nm (also known as top and bottom) The surface or gate and groove are compared to the amount of oxidation flow. Accordingly, when the conformality is defined as the growth on one side wall and the growth ratio on a top or bottom surface, conventional plasma oxidation achieves only 50% conformality at thicknesses greater than 25 angstroms.

已發現在電漿氧化期間主動冷卻基材至約-50℃至100℃範圍內的溫度，例如在約-25℃至75℃的具體範圍內，並且更具體地在約0℃至50℃範圍內，可改善利用矽結構之低溫氧化所形成的薄膜之共形性。更明確地說，厚度低於約100奈米的較小特徵結構之薄膜共形性顯著改善。共形性係定義為形成在一結構側壁上的薄膜厚度對形成在一結構的水平表面，包含頂及底表面，上之薄膜厚度間的比例。根據本發明之一或多個實施例，可達到至少約75%的共形性，並且更明確地說至少約80%，並且在具體實施例中至少約90%。在一或多個實施例中，藉由以上述方法處理，咸信該較低溫度增加該氧物種對一結構側壁的黏滯係數。It has been found that the substrate is actively cooled during plasma oxidation to a temperature in the range of from about -50 ° C to 100 ° C, such as in the specific range of from about -25 ° C to 75 ° C, and more specifically in the range of from about 0 ° C to 50 ° C. Within this, the conformality of the film formed by low temperature oxidation of the ruthenium structure can be improved. More specifically, film conformality of smaller features having a thickness of less than about 100 nanometers is significantly improved. The conformality is defined as the ratio of the thickness of the film formed on the sidewalls of a structure to the thickness of the film formed on the horizontal surface of a structure, including the top and bottom surfaces. According to one or more embodiments of the invention, a conformality of at least about 75% can be achieved, and more specifically at least about 80%, and in particular embodiments at least about 90%. In one or more embodiments, by treating in the manner described above, the lower temperature increases the viscosity coefficient of the oxygen species to the sidewalls of a structure.

本發明實施例可在適當配備的電漿反應器內執行，例如可從加州聖塔克拉拉的應用材料公司取得之去耦電漿氮化(DPN)反應器。也可使用其他適合的電漿反應器，包含但不限於，輻射狀排列槽形天線電漿設備及中空陰極電漿設備。第1圖示出適於執行根據本發明實施例之氧化物形成製程的例示電漿反應器。該反應器可透過由連續波(CW)功率產生器驅動的感應耦合電漿電源應用器提供低離子能量電漿及高離子能量電漿。Embodiments of the invention may be practiced in a suitably equipped plasma reactor, such as a decoupled plasma nitriding (DPN) reactor available from Applied Materials, Inc. of Santa Clara, California. Other suitable plasma reactors can also be used, including, but not limited to, radial array trough antenna plasma equipment and hollow cathode plasma equipment. FIG. 1 illustrates an exemplary plasma reactor suitable for performing an oxide formation process in accordance with an embodiment of the present invention. The reactor provides low ion energy plasma and high ion energy plasma through an inductively coupled plasma power application driven by a continuous wave (CW) power generator.

第1圖所示反應器11包含一腔室10，其具有一圓柱狀側壁12及一頂板14，其可以是圓頂狀(如圖中所示者)、平板狀、或其他幾何形狀。一電漿電源應用器包含一線圈天線16，設置在該頂板14上方並透過一第一阻抗匹配網絡18耦合至一功率源。該功率源包含一RF功率產生器20和一閘極22在該產生器20的輸出處。The reactor 11 shown in Fig. 1 includes a chamber 10 having a cylindrical side wall 12 and a top plate 14, which may be dome shaped (as shown), flat, or other geometric shape. A plasma power supply application includes a coil antenna 16 disposed above the top plate 14 and coupled to a power source through a first impedance matching network 18. The power source includes an RF power generator 20 and a gate 22 at the output of the generator 20.

該反應器也包含一基材支撐座26，其可以是一靜電夾盤或其他適合的基材支撐件，以抓持一半導體基材27，例如200毫米或300毫米半導體晶圓或諸如此類者。通常，擁有一加熱設備，例如一加熱器34在該基材支撐座26頂表面下方。該加熱器34可以是單或多區域加熱器，例如具有徑向內部及外部加熱元件34a和34b的雙徑向區域加熱器，如第1圖所示者。The reactor also includes a substrate support 26, which may be an electrostatic chuck or other suitable substrate support for grasping a semiconductor substrate 27, such as a 200 mm or 300 mm semiconductor wafer or the like. Typically, a heating device is provided, such as a heater 34 below the top surface of the substrate support 26. The heater 34 can be a single or multi-zone heater, such as a dual radial zone heater having radially inner and outer heating elements 34a and 34b, as shown in FIG.

此外，該反應器包含一氣體注入系統28及與該腔室10的內部空間連結的真空幫浦30。該氣體注入系統28係由一氣源供應，其可包含氧氣瓶32、氫氣瓶62或惰氣瓶70。可包含其他製程氣源，例如水蒸氣源和惰性氣體源(未示出)。在一或多個實施例中，可使用多於一個氣源。流量控制閥66、64和68分別與該氧氣瓶32、該氫氣瓶62和該惰氣瓶70連結，並且可用來在處理期間選擇性提供製程氣體或製程氣體混合物至該腔室10的內部空間。也可提供供應例如氮氣、氣體混合物、或諸如此類者之額外氣體的其他氣源(未示出)。可利用該真空幫浦30的節流閥38來控制該腔室10內的壓力。In addition, the reactor includes a gas injection system 28 and a vacuum pump 30 coupled to the interior space of the chamber 10. The gas injection system 28 is supplied from a source of gas, which may include an oxygen cylinder 32, a hydrogen cylinder 62, or an inert gas cylinder 70. Other process gas sources may be included, such as a water vapor source and an inert gas source (not shown). In one or more embodiments, more than one gas source can be used. Flow control valves 66, 64 and 68 are coupled to the oxygen cylinder 32, the hydrogen cylinder 62 and the inert gas cylinder 70, respectively, and are operable to selectively provide a process gas or process gas mixture to the interior of the chamber 10 during processing. . Other sources of gas (not shown) that supply additional gases such as nitrogen, gas mixtures, or the like may also be provided. The throttle valve 38 of the vacuum pump 30 can be utilized to control the pressure within the chamber 10.

可藉由控制其輸出與該閘極22連結的脈衝產生器36的工作週期來控制該閘極22處的脈衝RF功率輸出之工作週期。電漿係在一離子產生區39內產生，其對應該頂板14下方被該線圈天線16圍繞的空間。因為電漿係在該腔室10之上半部區域與該基材27有一段距離處產生，該電漿遂被稱為類遠端電漿(例如，該電漿具備遠端電漿形成的優勢，但係在與該基材27相同的腔室10內形成)。The duty cycle of the pulsed RF power output at the gate 22 can be controlled by controlling the duty cycle of the pulse generator 36 whose output is coupled to the gate 22. The plasma is generated in an ion generating region 39 which corresponds to the space below the top plate 14 surrounded by the coil antenna 16. Since the plasma is generated at a distance from the substrate 27 in the upper half of the chamber 10, the plasma is referred to as a far-end plasma (for example, the plasma is formed by a distal plasma) Advantages, but formed in the same chamber 10 as the substrate 27.

操作時，可用該電漿反應器來執行根據本發明實施例之氧化製程，以沈積高品質氧化物層，其在形成於一基材上的氧化物堆疊之側壁上具有增量的氧化物層。In operation, the plasma reactor can be used to perform an oxidation process in accordance with an embodiment of the present invention to deposit a high quality oxide layer having an incremental oxide layer on the sidewalls of the oxide stack formed on a substrate. .

例如，第2A-B圖示出含有形成在半導體基材202上之薄膜堆疊240的半導體結構200之製造階段。在一或多個實施例中，該基材202可包含多個薄膜堆疊240，其在該等堆疊之間形成溝槽250。在此所述用來製造該半導體結構200的製程可在，例如，上面關於第1圖所述之反應器11內執行。For example, FIGS. 2A-B illustrate a stage of fabrication of a semiconductor structure 200 comprising a thin film stack 240 formed on a semiconductor substrate 202. In one or more embodiments, the substrate 202 can include a plurality of thin film stacks 240 that form trenches 250 between the stacks. The process for fabricating the semiconductor structure 200 described herein can be performed, for example, in the reactor 11 described above with respect to FIG.

基材202具有一薄膜堆疊240沈積在其上。該薄膜堆疊240將被氧化。該基材202一般對應於第1圖的基材27，並且通常係支撐在該電漿反應器11的腔室10內該基材支撐座26上。該基材202可擁有各種尺寸，例如直徑200毫米或300毫米的晶圓，以及矩形或方形面板。在某些實施例中，該薄膜堆疊240可形成在該基材202 上，然後提供給該腔室10進行該氧化製程。例如，可在與一群集工具連結的一或多個製程腔室內製造該薄膜堆疊240，其也擁有該電漿反應器11連結至其上。一適合的群集工具之範例是可從加州聖塔克拉拉的應用材料公司取得之閘極堆疊CENTURA®。Substrate 202 has a thin film stack 240 deposited thereon. The film stack 240 will be oxidized. The substrate 202 generally corresponds to the substrate 27 of FIG. 1 and is typically supported on the substrate support 26 within the chamber 10 of the plasma reactor 11. The substrate 202 can be of various sizes, such as wafers having a diameter of 200 mm or 300 mm, as well as rectangular or square panels. In some embodiments, the film stack 240 can be formed on the substrate 202 The upper chamber is then supplied to the chamber 10 for the oxidation process. For example, the film stack 240 can be fabricated in one or more process chambers coupled to a cluster tool, which also has the plasma reactor 11 attached thereto. An example of a suitable clustering tool is the gate stack CENTURA® available from Applied Materials, Inc. of Santa Clara, California.

該基材202可包含一材料，例如結晶矽(例如，矽<100>或矽<111>)、氧化矽、應變矽、鍺化矽、摻雜或未摻雜的多晶矽、摻雜或未摻雜的矽晶圓、圖案化或未圖案化的晶圓、絕緣層上矽(SOI)、摻雜碳的氧化矽、氮化矽、摻雜的矽、鍺、砷化鎵、玻璃、藍寶石、或諸如此類。The substrate 202 can comprise a material such as crystalline germanium (eg, germanium <100> or germanium <111>), germanium oxide, strained germanium, germanium telluride, doped or undoped poly germanium, doped or undoped. Miscellaneous germanium wafers, patterned or unpatterned wafers, germanium on insulator (SOI), carbon-doped germanium oxide, tantalum nitride, doped germanium, germanium, gallium arsenide, glass, sapphire, Or something like that.

會了解該薄膜堆疊240並不受限於上述特定材料。因此，該薄膜堆疊240可以是欲氧化的任何種材料堆疊。例如，在某些實施例中，例如在快閃記憶體應用中，該堆疊240可以是一快閃記憶單元的閘極堆疊，其含有穿隧氧化物層204、浮置閘極層206、單或多層介電層，其含有多晶矽間介電層(IPD)210(該IPD之一非限制性範例係一多層ONO層，其含有一氧化物層212、一氮化物層214、以及一氧化物層216，在第2A-B圖中例示性示出)、以及一控制閘極層220。該等氧化物層204、212、216通常含矽和氧，例如氧化矽(SiO₂ )、氧氮化矽(SiON)、或諸如此類者。該氮化物層通常含矽及氮，例如氮化矽(SiN)、或諸如此類者。在某些實施例中，也可用一含有SiO₂ /Al₂ O₃ /SiO₂ 的多層來做為該IPD層210。該浮置閘極層206和該控制閘極層220通常含有一導電材料，例如多晶矽、金屬、或諸如此類者。預期在其他應用中的薄膜堆疊可根據在此提供的教示有利地氧化，例如動態隨機存取記憶體(DRAM)金屬電極/多晶矽閘極堆疊、用於非揮發性記憶體(NVM)的電荷擷取快閃記憶體(CTF)、或諸如此類者。該DRAM金屬電極通常是鎢(W)，具有氮化鈦(TiN)或氮化鎢(WN)之中間層在該等鎢及多晶矽層之間。用於非揮發性記憶體(NVM)的電荷擷取快閃記憶體(CTF)使用SiO₂ /SiN/Al₂ O₃ 閘極堆疊，具有氮化鉭(TaN)或氮化鈦(TiN)的金屬電極，其也可從閘極蝕刻後的側壁氧化受益。在某些實施例中，該製程氣體可包含水蒸氣，並且在一或多個具體實施例中，該水蒸氣可與氫氣及/或氧氣的至少一者混合。做為另一種選擇或合併使用，該水蒸氣可與至少一種惰性氣體混合，例如氦氣(He)、氬氣(Ar)、氪氣(Kr)、氖氣(Ne)、或諸如此類者。It will be appreciated that the film stack 240 is not limited to the particular materials described above. Thus, the film stack 240 can be any type of material stack to be oxidized. For example, in some embodiments, such as in a flash memory application, the stack 240 can be a gate stack of a flash memory cell that includes a tunnel oxide layer 204, a floating gate layer 206, a single Or a multilayer dielectric layer comprising a polysilicon dielectric layer (IPD) 210 (one non-limiting example of the IPD is a multilayer ONO layer comprising an oxide layer 212, a nitride layer 214, and an oxidation The layer 216 is exemplarily shown in FIGS. 2A-B) and a control gate layer 220. Such silicon oxide layer is 204,212,216 and usually contain oxygen, for example, silicon oxide (SiO _2), silicon oxynitride (SiON), or the like person. The nitride layer typically contains hafnium and nitrogen, such as tantalum nitride (SiN), or the like. In some embodiments, a plurality of layers containing SiO ₂ /Al ₂ O ₃ /SiO ₂ may also be used as the IPD layer 210. The floating gate layer 206 and the control gate layer 220 typically comprise a conductive material such as polysilicon, metal, or the like. Film stacks in other applications are expected to be advantageously oxidized according to the teachings provided herein, such as dynamic random access memory (DRAM) metal electrodes/polysilicon gate stacks, charge for non-volatile memory (NVM). Take a flash memory (CTF), or the like. The DRAM metal electrode is typically tungsten (W) with an intermediate layer of titanium nitride (TiN) or tungsten nitride (WN) between the tungsten and polysilicon layers. Charge-extracted flash memory (CTF) for non-volatile memory (NVM) uses a SiO ₂ /SiN/Al ₂ O ₃ gate stack with tantalum nitride (TaN) or titanium nitride (TiN) Metal electrodes, which also benefit from sidewall oxidation after gate etching. In certain embodiments, the process gas can comprise water vapor, and in one or more embodiments, the water vapor can be mixed with at least one of hydrogen and/or oxygen. Alternatively or in combination, the water vapor may be mixed with at least one inert gas such as helium (He), argon (Ar), helium (Kr), helium (Ne), or the like.

在某些實施例中，可提供總流速約100-2000sccm之間，或約400sccm，的製程氣體(或氣體混合物)。例如，在提供氧氣(O₂ )和氫氣(H₂ )兩者的實施例中，可提供總流速約100-2000sccm之間的氧氣(O₂ )和氫氣(H₂ )，或約400sccm，在上述百分比範圍內。在提供水蒸氣的實施例中，可通入流速約5-1000sccm之間的水蒸氣，連同一或多種惰性載氣，例如氦氣、氬氣、氪氣、氖氣或其他適合惰性氣體。可依需要供應該等惰性氣體，以提供約100-2000sccm之間的總流速，並提供擁有多至約50%水蒸氣的製程氣體混合物。惰性氣體添加也可與H₂ /O₂ 混合物並用，以避免離子化氧氣及/或氦氣的再結合。激發的雙原子分子通常傾向在電漿內與自身再結合，因此添加惰性氣體(例如氬氣、氦氣、氪氣、氖氣、或諸如此類)可促進較高氧化速率。In certain embodiments, a process gas (or gas mixture) having a total flow rate between about 100 and 2000 sccm, or about 400 sccm, can be provided. For example, in an embodiment providing oxygen (O ₂₎ and hydrogen (H ₂₎ of the two, it may be provided an oxygen (O ₂₎ and hydrogen (H ₂₎ of between about 100-2000sccm total flow rate, or about 400 sccm, in Within the above percentage range. In embodiments in which water vapor is provided, water vapor having a flow rate between about 5 and 1000 seem can be passed through one or more inert carrier gases, such as helium, argon, helium, neon or other suitable inert gases. The inert gases may be supplied as needed to provide a total flow rate between about 100 and 2000 sccm and provide a process gas mixture having up to about 50% water vapor. Inert gas addition can also be combined with the H ₂ /O ₂ mixture to avoid recombination of ionized oxygen and/or helium. Excited diatomic molecules generally tend to recombine with themselves within the plasma, so the addition of an inert gas (such as argon, helium, neon, xenon, or the like) can promote higher oxidation rates.

一電漿係在該腔室10內從該等製程氣體產生，以在該薄膜堆疊240上形成一氧化物層230。該電漿係形成在第1圖所示腔室10的離子產生區39內，利用感應耦合來自設置在該頂板14上方的線圈天線16之RF能量，因此有利地提供低離子能量(例如就脈衝電漿而言低於約5eV，並且就CW電漿而言低於15eV)。該電漿的低離子能量限制離子轟擊傷害，並促進該薄膜堆疊240的側壁之氧化，同時限制氧氣在其各層之間擴散，藉此減少鳥嘴。A plasma is generated in the chamber 10 from the process gases to form an oxide layer 230 on the thin film stack 240. The plasma is formed in the ion generating region 39 of the chamber 10 shown in Fig. 1 by inductive coupling of RF energy from the coil antenna 16 disposed above the top plate 14, thereby advantageously providing low ion energy (e.g., pulsed) It is less than about 5 eV for plasma and less than 15 eV for CW plasma. The low ion energy of the plasma limits ion bombardment damage and promotes oxidation of the sidewalls of the film stack 240 while limiting the diffusion of oxygen between its layers, thereby reducing the bird's beak.

在某些實施例中，可以適當頻率提供約25至5000瓦的功率至該線圈天線16，以形成電漿(例如，在MHz或GHz範圍內，或約13.56MHz或更大)。可以連續波或脈衝模式提供該功率。在一或多個實施例中，係以工作週期介於約2至70%之間的脈衝模式提供該功率。In some embodiments, about 25 to 5000 watts of power can be supplied to the coil antenna 16 at a suitable frequency to form a plasma (eg, in the MHz or GHz range, or about 13.56 MHz or greater). This power can be provided in continuous wave or pulse mode. In one or more embodiments, the power is provided in a pulsed mode with a duty cycle between about 2 and 70%.

例如，在某些實施例中，該電漿可在連續的“開啟”時間期間產生，而容許該電漿的離子能量在連續的“關閉”區間期間衰變。該“關閉”區間隔離連續的“開啟”區間，而該“開啟”及“關閉”區間界定出一可控制的工作週期。該工作週期將該基材表面處的離子動能限制在低於一預定臨界能量下。在某些實施例中，該預定臨界能量係在或低於約5eV。For example, in certain embodiments, the plasma can be generated during a continuous "on" time while allowing the ion energy of the plasma to decay during successive "off" intervals. The "off" interval isolates a continuous "on" interval, and the "on" and "off" intervals define a controllable duty cycle. This duty cycle limits the ion kinetic energy at the surface of the substrate below a predetermined critical energy. In certain embodiments, the predetermined critical energy is at or below about 5 eV.

例如，在該脈衝RF功率的“開啟”時間期間，該電漿能量增加，而在該“關閉”時間期間則降低。在短暫的“開啟”時間期間，該電漿係在大約對應於該線圈天線16所圈起的空間之該離子產生區39內產生。該離子產生區39係在該基材27上方一段顯著距離LD處。在該“開啟”時間期間於該離子產生區39內靠近該頂板14產生的電漿在該“關閉”時間以一平均速度VD朝該基材27飄移。在每一個“關閉”時間期間，最快速的電子擴散至該等腔室壁，容許該電漿冷卻。能量最高的電子以比該電漿離子飄移速度VD快許多的速度擴散至該等腔室壁。因此，在該“關閉”時間，該電漿離子能量在該等離子抵達該基材27之前顯著降低。在下一次“開啟”時間期間，更多電漿產生在該離子產生區39，並且整個週期重複。因此，抵達該基材27的電漿離子之能量顯著降低。在較低的腔室壓力範圍下，也就是說約10毫托耳和以下，該脈衝RF情況的電漿能量與該連續RF情況相比大幅降低。For example, during the "on" time of the pulsed RF power, the plasma energy increases and decreases during the "off" time. During a brief "on" time, the plasma is generated in the ion generating region 39 corresponding to the space enclosed by the coil antenna 16. The ion generating zone 39 is at a significant distance LD above the substrate 27. The plasma generated in the ion generating zone 39 near the top plate 14 during the "on" time drifts toward the substrate 27 at an average speed VD during the "off" time. During each "off" time, the fastest electrons diffuse to the walls of the chamber, allowing the plasma to cool. The most energetic electrons diffuse to the walls of the chamber at a much faster rate than the plasma ion drift velocity VD. Thus, at this "off" time, the plasma ion energy is significantly reduced before the plasma reaches the substrate 27. During the next "on" time, more plasma is produced in the ion generating zone 39 and the entire cycle repeats. Therefore, the energy of the plasma ions reaching the substrate 27 is significantly reduced. At lower chamber pressure ranges, that is, about 10 mTorr and below, the plasma energy of the pulsed RF case is substantially reduced compared to the continuous RF case.

該脈衝RF功率波形的“關閉”時間及該離子產生區39和該基材27之間的距離LD兩者均應足以容許產生在該離子產生區39的電漿失去足夠大量的能量，因此其在抵達該基材27時造成很少或無離子轟擊傷害或缺陷。明確地說，該“關閉”時間係由約2和20kHz之間，或約10kHz，的脈衝頻率以及約5%和20%之間的“開啟”工作週期界定。因此，在某些實施例中，該“開啟”區間可持續約5微秒至約50微秒範圍內的時間，或約20微秒，而該“關閉”區間可持續約50微秒至約95微秒範圍內的時間，或約80微秒。The "off" time of the pulsed RF power waveform and the distance LD between the ion generating region 39 and the substrate 27 should be sufficient to allow the plasma generated in the ion generating region 39 to lose a sufficient amount of energy, thus Little or no ion bombardment damage or defects are caused upon arrival at the substrate 27. In particular, the "off" time is defined by a pulse frequency between about 2 and 20 kHz, or about 10 kHz, and an "on" duty cycle between about 5% and 20%. Thus, in some embodiments, the "on" interval may last from about 5 microseconds to about 50 microseconds, or about 20 microseconds, while the "off" interval may last from about 50 microseconds to about Time in the range of 95 microseconds, or about 80 microseconds.

在某些實施例中，該離子產生區至基材距離LD係大於約2公分，或者在約2公分至約20公分範圍內。該離子產生區至基材距離LD可與該等電漿離子在該脈衝RF功率波形的單一個“關閉”時間期間行進的距離(VD乘以該“關閉”時間)約相同(或更大)。In certain embodiments, the ion generating zone to substrate distance LD is greater than about 2 centimeters, or ranges from about 2 centimeters to about 20 centimeters. The ion generating zone to substrate distance LD can be about the same (or greater) than the distance traveled by the plasma ions during a single "off" time of the pulsed RF power waveform (VD multiplied by the "off" time) .

在連續波和脈衝模式兩者中，該電漿有利地在該腔室內平衡氧氣和氫氣離子的共生，並且與該基材之間距離夠近以利用對於離子能量的控制來限制該等離子活性的流失，以避免離子轟擊造成的傷害或擴散傷害(例如鳥嘴)。In both continuous wave and pulsed modes, the plasma advantageously balances the symbiosis of oxygen and hydrogen ions within the chamber and is close enough to the substrate to limit the activity of the plasma with control of ion energy. Loss to avoid damage or spread damage caused by ion bombardment (such as a bird's beak).

所產生的電漿可在一低壓製程中形成，藉以減少污染導致的缺陷之可能性。例如，在某些實施例中，可將該腔室10保持在約1-500毫托耳之間的壓力下。此外，可藉由使用類遠端電漿源及，選擇性地，藉由如上所述般脈衝該電漿電源來限制或避免在如此低的腔室壓力水準下所能期待的轟擊導致的缺陷。The resulting plasma can be formed in a low pressure process to reduce the likelihood of defects caused by contamination. For example, in certain embodiments, the chamber 10 can be maintained at a pressure of between about 1-500 mTorr. In addition, defects caused by bombardment at such low chamber pressure levels can be limited or avoided by using a remote-like plasma source and, optionally, by pulsing the plasma power source as described above. .

根據一或多個實施例，該氧化物層230可形成至從約5埃至約50埃範圍內的厚度。該製程可提供每分鐘約7埃至約50埃範圍內的氧化物薄膜成長速率，或每分鐘至少約25埃。在此揭示之本發明製程在較低熱預算下提供上述之氧化物成長速率提升，因而藉由與習知氧化製程相比減少該基材對於該製程的暴露時間而更加限制擴散效應。在某些實施例中，該製程可擁有從約5秒至約300秒範圍內的持續時間。In accordance with one or more embodiments, the oxide layer 230 can be formed to a thickness ranging from about 5 angstroms to about 50 angstroms. The process can provide an oxide film growth rate in the range of from about 7 angstroms to about 50 angstroms per minute, or at least about 25 angstroms per minute. The process of the present invention disclosed herein provides for the above-described increase in oxide growth rate at a lower thermal budget, thereby further limiting the diffusion effect by reducing the exposure time of the substrate to the process as compared to conventional oxidation processes. In certain embodiments, the process can have a duration ranging from about 5 seconds to about 300 seconds.

可在該薄膜堆疊240上將該氧化物層230形成至一預期厚度。隨後可依需要進一步處理該基材202以完成在其上製造的結構。The oxide layer 230 can be formed to a desired thickness on the film stack 240. The substrate 202 can then be further processed as needed to complete the structure fabricated thereon.

如上所述，已發現在電漿氧化期間主動冷卻該基材至約-50℃至100℃範圍內的溫度，例如在約-25℃至75℃的具體範圍內，並且更具體地在約0℃至50℃範圍內，能改善利用矽結構的低溫氧化所形成的薄膜之共形性。可用若干方法完成冷卻。As noted above, it has been discovered that the substrate is actively cooled during plasma oxidation to a temperature in the range of from about -50 ° C to 100 ° C, such as within a specific range of from about -25 ° C to 75 ° C, and more specifically at about 0 In the range of °C to 50 °C, the conformality of the film formed by low-temperature oxidation of the ruthenium structure can be improved. Cooling can be accomplished in a number of ways.

根據一第一實施例，該支撐座26可包含靜電夾盤(ESC)，其以一冷卻氣體冷卻或接觸該基材背側，或該基材與該支撐座26接觸的一側，以在低溫氧化期間維持該基材溫度。第3圖示出一ESC 325之一範例實施例。參考第1圖的反應器11，該ESC 325在該腔室10內支撐一半導體基材27。該ESC 325可包含具有孔330穿透其間的底座。在所示實施例中，一靜電組件333包含一絕緣體335，其封住一電極350。該靜電組件333包含一上表面340，以容納並支撐一基材。具有一電壓供應導線360的電氣連接器355係經電氣連接至該電極350。該電壓供應導線360沿伸通過該ESC 325的基座之孔330，並在一電氣接觸365終止，其電氣接合一電壓供應終端370。使用時，將該靜電夾盤325固定在一製程腔室380內的支撐件375上。應了解該ESC 325可與第1圖所示之反應器11並用。在第3圖所示實施例中，該製程腔室380(其對應第1圖的腔室10)可包含一製程氣體入口382(其對應第1圖的氣體注入系統28)，其連結一製程氣源302(其對應第1圖的氧氣瓶32、氫氣瓶62或惰氣瓶70)至該腔室380。第3圖的製程腔室380更包含連接至一排氣系統301的排氣出口384。According to a first embodiment, the support base 26 may include an electrostatic chuck (ESC) that cools or contacts the back side of the substrate with a cooling gas, or the side of the substrate that is in contact with the support base 26 to The substrate temperature is maintained during low temperature oxidation. FIG. 3 shows an exemplary embodiment of an ESC 325. Referring to reactor 11 of FIG. 1, the ESC 325 supports a semiconductor substrate 27 within the chamber 10. The ESC 325 can include a base having a bore 330 therethrough. In the illustrated embodiment, an electrostatic component 333 includes an insulator 335 that encloses an electrode 350. The electrostatic assembly 333 includes an upper surface 340 for receiving and supporting a substrate. An electrical connector 355 having a voltage supply lead 360 is electrically connected to the electrode 350. The voltage supply lead 360 extends along an aperture 330 extending through the base of the ESC 325 and terminates at an electrical contact 365 that electrically engages a voltage supply terminal 370. In use, the electrostatic chuck 325 is secured to a support member 375 within a process chamber 380. It will be appreciated that the ESC 325 can be used in conjunction with the reactor 11 shown in Figure 1. In the embodiment shown in FIG. 3, the process chamber 380 (which corresponds to the chamber 10 of FIG. 1) may include a process gas inlet 382 (which corresponds to the gas injection system 28 of FIG. 1) coupled to a process A gas source 302 (which corresponds to the oxygen cylinder 32, the hydrogen cylinder 62 or the inert gas cylinder 70 of Fig. 1) is supplied to the chamber 380. The process chamber 380 of FIG. 3 further includes an exhaust outlet 384 that is coupled to an exhaust system 301.

在第3圖實施例中，一基材345係經抓持在該ESC 325上，並且從該冷卻劑源或冷卻器300供應冷卻劑至位於該絕緣體335上表面340內的冷卻導管305，其也包含冷卻導管或溝渠。在一或多個實施例中，該冷卻劑包含一傳導氣體，例如氦氣、氬氣以及週期表第8族中的大部分惰性元素。抓持在該ESC 325上的基材345覆蓋並密封該等冷卻導管305，避免該冷卻劑外漏。該等冷卻導管305內的冷卻劑從該基材345除熱，並在處理期間將該基材345保持在固定溫度下。In the embodiment of FIG. 3, a substrate 345 is grasped on the ESC 325, and a coolant is supplied from the coolant source or cooler 300 to a cooling conduit 305 located in the upper surface 340 of the insulator 335. Also included are cooling ducts or ditches. In one or more embodiments, the coolant comprises a conducting gas such as helium, argon, and most of the inert elements of Group 8 of the Periodic Table. Substrate 345 gripping the ESC 325 covers and seals the cooling conduits 305 to prevent leakage of the coolant. The coolant within the cooling conduits 305 removes heat from the substrate 345 and maintains the substrate 345 at a fixed temperature during processing.

在一或多個實施例中，該等冷卻導管305係利用一系列通道連結至該冷卻劑源300，其可延伸通過整個絕緣體和電極。該等冷卻導管可經隔開、按一定尺寸製作及分散，而使保持在其中的冷卻劑可實質上冷卻整個基材345。In one or more embodiments, the cooling conduits 305 are coupled to the coolant source 300 by a series of passages that extend through the entire insulator and electrode. The cooling conduits can be spaced apart, sized, and dispersed such that the coolant held therein can substantially cool the entire substrate 345.

在一或多個實施例中，可使用電漿脈衝技術來最小化肇因於傳輸至該基材的電漿功率之基材加熱。根據該等實施例，在電漿氧化期間可使用電漿脈衝技術來將該基材保持在約-50℃至100℃範圍內的溫度下，例如在約-25℃至75℃的具體範圍內，並且更具體地在約0℃至50℃範圍內。In one or more embodiments, plasma pulse techniques can be used to minimize substrate heating due to plasma power delivered to the substrate. According to such embodiments, the plasma pulse technique can be used during plasma oxidation to maintain the substrate at a temperature in the range of from about -50 ° C to 100 ° C, such as in the specific range of from about -25 ° C to 75 ° C. And more specifically in the range of about 0 ° C to 50 ° C.

可以若干適合方法來實現電漿脈衝。在一實施例中，可開關循環該電漿以將該基材保持在此間所述溫度範圍內。在另一實施例中，該電漿可以是範圍從約2kHz至約50kHz的kHz頻率脈衝電漿。Plasma pulses can be implemented in a number of suitable ways. In one embodiment, the plasma can be cycled to maintain the substrate within the temperature range therebetween. In another embodiment, the plasma can be a pulsed plasma of kHz frequency ranging from about 2 kHz to about 50 kHz.

使用開關循環該電漿之電漿脈衝技術的實施例包含藉由脈衝或時間調變該RF電漿電源訊號來調整平均電漿電子溫度及化學。此技術也稱為RP電漿電源調變，並獨立於該RF電漿電源水準控制電子溫度，因為在脈衝之間的功率關閉時間期間，電子溫度以比電漿密度快許多的速率降低。RF電漿電源調變包含實體上連續或依照一預定順序開啟及關閉該電漿產生。在一或多個實施例中，RF電漿電源調變包含開啟和關閉產生該離子產生區和該電漿的功率源。An embodiment of a plasma pulse technique that uses a switch to cycle the plasma includes adjusting the average plasma electron temperature and chemistry by pulse or time modulating the RF plasma power signal. This technique, also known as RP plasma power modulation, controls the electronic temperature independently of the RF plasma power level because during the power off time between pulses, the electron temperature decreases at a much faster rate than the plasma density. The RF plasma power modulation includes physically opening or closing the plasma generation continuously or in a predetermined sequence. In one or more embodiments, RF plasma power modulation includes turning on and off a power source that produces the ion generating region and the plasma.

根據一或多個實施例，該電漿脈衝技術包含在一第一頻率及一第二頻率之間替換該RF功率源的頻率。在一或多個實施例中，也可以該第一及/或第二頻率供應不同量的功率。在使用此電漿脈衝法來維持或冷卻該基材溫度至-50℃和100℃之間的一或多個實施例中包含將一基材置於一電漿反應器的一腔室內，並通入含氫氣、氧氣或惰氣的氣體至該腔室內。之後以一第一頻率供應功率至該反應器以在該腔室內產生一第一電漿。然後以一第二頻率供應功率以在該腔室內產生一第二電漿。此類實施例也可供應頻率與該第一及第二頻率不同的功率。在一或多個實施例中，以該第一或第二頻率供應的功率量可不同，並且可關於該等頻率的一或兩者週期性增加或減少或保持固定。也可控制以該第一或第二頻率供應的功率量之改變率以調節或降低該基材的溫度。In accordance with one or more embodiments, the plasma pulse technique includes replacing a frequency of the RF power source between a first frequency and a second frequency. In one or more embodiments, the first and/or second frequencies may also be supplied with different amounts of power. In one or more embodiments using the plasma pulse method to maintain or cool the substrate temperature to between -50 ° C and 100 ° C, a substrate is placed in a chamber of a plasma reactor, and A gas containing hydrogen, oxygen or inert gas is introduced into the chamber. Power is then supplied to the reactor at a first frequency to produce a first plasma within the chamber. Power is then supplied at a second frequency to produce a second plasma within the chamber. Such embodiments may also supply power at a different frequency than the first and second frequencies. In one or more embodiments, the amount of power supplied at the first or second frequency may be different and may be periodically increased or decreased or maintained fixed with respect to one or both of the frequencies. The rate of change in the amount of power supplied at the first or second frequency can also be controlled to adjust or lower the temperature of the substrate.

在另一實施例中，可透過氣體對流將該基材溫度保持在或冷卻至-50℃和100℃之間，藉由流通一冷卻或對流氣體至該反應腔室內。在一或多個實施例中，一冷卻氣體可流經該基材頂部而非該基材背側。在此類實施例中，可調整該腔室以提供另一個氣體入口，使該冷卻氣體流入該腔室內以冷卻該基材。在一或多個實施例中，可設置該入口以使該冷卻氣體可毗鄰該基材表面流動。在一或多個實施例中，該冷卻氣體係一惰性氣體，其係從一冷卻氣源供應至該腔室。在一或多個實施例中，該惰性氣體係一種傳導氣體，例如氦氣、氬氣及週期表第8族內的其他惰性元素。In another embodiment, the substrate temperature can be maintained or cooled to between -50 ° C and 100 ° C by gas convection by circulating a cooling or convection gas into the reaction chamber. In one or more embodiments, a cooling gas can flow through the top of the substrate rather than the back side of the substrate. In such embodiments, the chamber can be adjusted to provide another gas inlet that flows into the chamber to cool the substrate. In one or more embodiments, the inlet can be configured to allow the cooling gas to flow adjacent the surface of the substrate. In one or more embodiments, the cooling gas system is an inert gas that is supplied to the chamber from a source of cooling gas. In one or more embodiments, the inert gas system is a conducting gas such as helium, argon, and other inert elements within Group 8 of the Periodic Table.

第4圖示出第1圖之反應器11，更包含與該腔室10的內部空間連結的冷卻氣體輸送系統29。該冷卻氣體輸送系統29係由一冷卻氣源82供應，並流通一冷卻氣體至該腔室10內。在一或多個實施例中，該冷卻氣源可包含一氦氣瓶。在一具體實施例中，該冷卻氣源可包含一惰氣混合氣體瓶。冷卻流量控制閥80係經連結至該冷卻氣源82。在第4圖所示實施例中，該冷卻氣體係經供應至該腔室並以所示方向毗鄰該基材流動，以冷卻該基材溫度。Fig. 4 shows the reactor 11 of Fig. 1 and further includes a cooling gas delivery system 29 coupled to the internal space of the chamber 10. The cooling gas delivery system 29 is supplied by a cooling gas source 82 and circulates a cooling gas into the chamber 10. In one or more embodiments, the source of cooling gas may comprise a helium cylinder. In a specific embodiment, the source of cooling gas may comprise an inert gas mixture gas bottle. Cooling flow control valve 80 is coupled to the cooling gas source 82. In the embodiment illustrated in Figure 4, the cooling gas system is supplied to the chamber and flows adjacent the substrate in the direction indicated to cool the substrate temperature.

根據本發明之一或多個實施例，可使用若干方法在一堆疊中形成氧化物層，例如閘極氧化物堆疊。第5圖示出利用兩個閘極堆疊241、242和一基材203之間的空間形成的溝槽250，如第2A-B圖所示者。該等閘極堆疊241、242可如上面參考第2A-B圖及/或薄膜堆疊240所示般形成。該基材203也可包含在此參考第2A-B圖所述之材料。在第5圖中，一氧化物層231係經形成在該基材203上該等閘極堆疊241、242及該溝槽250上方。該氧化物層係在一電漿反應器內形成，例如關於第1圖所述之反應器11，利用不包含冷卻該基材的習知處理技術。In accordance with one or more embodiments of the present invention, oxide layers, such as gate oxide stacks, may be formed in a stack using several methods. Figure 5 shows a trench 250 formed using the space between two gate stacks 241, 242 and a substrate 203, as shown in Figures 2A-B. The gate stacks 241, 242 can be formed as described above with reference to Figures 2A-B and/or film stack 240. The substrate 203 can also comprise the materials described herein with reference to Figures 2A-B. In FIG. 5, an oxide layer 231 is formed over the gate stacks 241, 242 and the trenches 250 on the substrate 203. The oxide layer is formed in a plasma reactor, such as the reactor 11 described with respect to Figure 1, using conventional processing techniques that do not include cooling the substrate.

發明人判定藉由將該基材保持在約-50℃至100℃範圍內，可改善利用低溫氧化法形成的薄膜或氧化物層的共形性。在一或多個實施例中，可改善共形性而使該等側壁上和該溝槽上的二氧化矽層厚度之間的比例高於至少75%。The inventors have determined that the conformality of the film or oxide layer formed by the low temperature oxidation method can be improved by maintaining the substrate in the range of about -50 ° C to 100 ° C. In one or more embodiments, the conformality can be improved such that the ratio between the thickness of the ceria layer on the sidewalls and the trench is greater than at least 75%.

第5圖示出利用根據先前技藝之電漿氧化製程形成的氧化物層231。第5圖具體示出閘極長度為65奈米並且間隔為65奈米之淺溝槽隔離或“STI”結構的底部溝槽。第5圖的氧化物層231係經沈積在形成在兩個薄膜堆疊之間的溝槽250內，例如第2B圖所示之薄膜堆疊240。該溝槽250係由兩個側壁251、252界定。半導體結構200通常包含多個例如第2B圖所示之薄膜堆疊，具有溝槽250在薄膜堆疊之間。形成在第5圖所示溝槽250內的氧化物層231在該溝槽250底部處的厚度大於在該等側壁251、252處。第5圖的矽結構係藉由利用快速熱氧化法成長厚度75埃的通道氧化物，然後成長厚度1200埃的摻雜的多晶矽層形成。利用低壓化學氣相沈積或“LPCVD”製程在該多晶層上形成厚度50埃的高溫氧化物或“HTO”層以及最終一厚度400埃的氮化矽層。所形成結構的高度大約是340-380奈米。該閘極長度和間距是65奈米。Figure 5 shows an oxide layer 231 formed using a plasma oxidation process according to the prior art. Figure 5 specifically shows a shallow trench isolation or "STI" structure bottom trench with a gate length of 65 nanometers and a spacing of 65 nanometers. The oxide layer 231 of Fig. 5 is deposited in a trench 250 formed between two thin film stacks, such as the thin film stack 240 shown in Fig. 2B. The trench 250 is defined by two sidewalls 251, 252. The semiconductor structure 200 typically includes a plurality of thin film stacks, such as shown in FIG. 2B, having trenches 250 between the thin film stacks. The thickness of the oxide layer 231 formed in the trench 250 shown in FIG. 5 is greater at the bottom of the trench 250 than at the sidewalls 251, 252. The tantalum structure of Fig. 5 is formed by growing a channel oxide having a thickness of 75 Å by rapid thermal oxidation and then growing a doped polysilicon layer having a thickness of 1200 Å. A high temperature oxide or "HTO" layer having a thickness of 50 angstroms and a final layer of tantalum nitride having a thickness of 400 angstroms are formed on the polycrystalline layer by a low pressure chemical vapor deposition or "LPCVD" process. The height of the resulting structure is approximately 340-380 nm. The gate length and spacing are 65 nm.

該氧化物層231在該等側壁251、252處的厚度係介於1.9奈米和2.1奈米之間。形成在該基材203上該溝槽250底表面處的氧化物層231的厚度約為3.2奈米。該氧化物層231的共形性，也就是該等側壁251、252處該氧化物層231的厚度對於該基材203上的厚度之間的比例係在從約0.59至0.66之範圍內。The thickness of the oxide layer 231 at the sidewalls 251, 252 is between 1.9 nm and 2.1 nm. The thickness of the oxide layer 231 formed on the bottom surface of the trench 250 on the substrate 203 is about 3.2 nm. The conformality of the oxide layer 231, that is, the ratio of the thickness of the oxide layer 231 at the sidewalls 251, 252 to the thickness on the substrate 203 is in the range of from about 0.59 to 0.66.

第6A圖示出形成在與第5圖所用者相同類型的基材及結構上的氧化物層232，但是，形成該氧化物層232的方法包含利用一ESC冷卻或保持該基材203的溫度，如此間所述者。該基材203係置放在一腔室內一ESC上，如此說明書內他處所述般，並且在一電漿氧化製程期間，該基材203背側或該基材與該ESC接觸的一側係利用氦氣冷卻。在第6A圖所示實施例中，該氧化物層232係藉由室溫電漿氧化製程利用約2000瓦的電源及含有80%氫氣並且總流速為200sccm的製程氣體形成。用於該ESC內的氦冷卻氣體係經設定在4t時間，並且該基材係經冷卻至從約30℃至約50℃範圍內的溫度。Fig. 6A shows an oxide layer 232 formed on the same type of substrate and structure as those used in Fig. 5, but the method of forming the oxide layer 232 includes cooling or maintaining the temperature of the substrate 203 using an ESC. , so described. The substrate 203 is placed in an ESC on a chamber, as described elsewhere in the specification, and the back side of the substrate 203 or the side of the substrate in contact with the ESC during a plasma oxidation process It is cooled by helium. In the embodiment illustrated in Figure 6A, the oxide layer 232 is formed by a room temperature plasma oxidation process using a power supply of about 2000 watts and a process gas containing 80% hydrogen and a total flow rate of 200 seem. The helium cooling gas system used in the ESC was set at 4 t time and the substrate was cooled to a temperature ranging from about 30 °C to about 50 °C.

所形成的氧化物層232在該等側壁251、252處的厚度係介於2.5奈米和2.7奈米之間。該氧化物層232在該溝槽250底表面處的厚度是2.7奈米。該氧化物層232的共形性係介於0.93和1.0之間。The thickness of the formed oxide layer 232 at the sidewalls 251, 252 is between 2.5 nm and 2.7 nm. The thickness of the oxide layer 232 at the bottom surface of the trench 250 is 2.7 nm. The conformality of the oxide layer 232 is between 0.93 and 1.0.

參見第6B圖，利用此間所述之電漿脈衝法在與第5圖所用者相同類型的基材及結構上形成一氧化物層233，以保持或冷卻該基材溫度。如此間他處所述般，RF電漿電源訊號係藉由循環供應至該反應器的功率來脈衝。利用一巨脈衝製程根據如下配方實體開關該電漿功率：開啟4次持續25秒以及關閉4次持續120秒。運用使用2000瓦的功率源之RT去耦電漿氧化或“DPO”腔室來形成該氧化物層。用來形成該氧化物層的製程氣體包含80%的氫氣，並且係以約200sccm的流速流入該腔室內。該基材溫度係經冷卻至從約20℃和約-30℃範圍內的溫度。Referring to Figure 6B, an oxide layer 233 is formed on the same type of substrate and structure as used in Figure 5 by means of the plasma pulse method described herein to maintain or cool the substrate temperature. As described elsewhere, the RF plasma power signal is pulsed by circulating the power supplied to the reactor. The plasma power is switched according to the following recipe entity using a giant pulse process: 4 turns on for 25 seconds and off 4 times for 120 seconds. The oxide layer is formed using an RT decoupling plasma oxidation or "DPO" chamber using a 2000 watt power source. The process gas used to form the oxide layer contained 80% hydrogen and flowed into the chamber at a flow rate of about 200 sccm. The substrate temperature is cooled to a temperature ranging from about 20 ° C to about -30 ° C.

所形成的氧化物層233在該等側壁251、252處的厚度是2.8奈米。該氧化物層233在該溝槽250底表面處的厚度是3.1奈米，產生0.90的共形性。如上面結果清楚示出者，發現在電漿氧化期間將該基材溫度保持在或冷卻至約-50℃和100℃範圍內的溫度可產生一共形的氧化物層。The thickness of the formed oxide layer 233 at the sidewalls 251, 252 is 2.8 nm. The thickness of the oxide layer 233 at the bottom surface of the trench 250 was 3.1 nm, yielding a conformality of 0.90. As is clear from the above results, it has been found that maintaining the substrate temperature at or cooling to a temperature in the range of about -50 ° C and 100 ° C during plasma oxidation produces a conformal oxide layer.

遍及本說明書所提到的“一個實施例”、“某些實施例”、“一或多個實施例”或“一實施例”表示結合該實施例所描述之一特定特徵、結構、材料、或特性係包含在本發明之至少一實施例中。因此，遍及本說明書各處之例如“在一或多個實施例中”、“在某些實施例中”、“在一實施例中”或“在一個實施例中”等句子的出現並不必定指涉本發明之相同實施例。此外，該特定特徵、結構、材料、或特性可在一或多個實施例中以任何適當方式組合。不應將上述方法的描述順序視為限制性，並且該等方法可不依照順序或以有減省或添加的方式使用所述操作。References to "an embodiment", "an embodiment", "one or more embodiments" or "an embodiment" or "an" Or a feature is included in at least one embodiment of the invention. Thus, the appearance of sentences such as "in one or more embodiments", "in some embodiments", "in an embodiment" or "in one embodiment" throughout the specification is not The same embodiment of the invention must be referred to. In addition, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. The order of description of the above methods should not be considered as limiting, and the methods may be used in a non-sequential or in a reduced or added manner.

應了解上面描述旨在說明，而非限制。在審視上面說明後，對熟知技藝者而言，許多其他實施例會是顯而易見的。因此，本發明之範圍應參考附屬申請專利範圍，連同此等申請專利範圍賦予等效物之完整範圍做判定。It should be understood that the above description is intended to be illustrative, not limiting. Many other embodiments will be apparent to those skilled in the art after reviewing the description. Therefore, the scope of the invention should be determined by reference to the scope of the appended claims.

10、380．．．腔室10,380. . . Chamber

11．．．反應器11. . . reactor

12．．．側壁12. . . Side wall

14．．．頂板14. . . roof

16．．．線圈天線16. . . Coil antenna

18．．．第一阻抗匹配網絡18. . . First impedance matching network

20．．．RF功率產生器20. . . RF power generator

22．．．閘極twenty two. . . Gate

26．．．基材支撐座26. . . Substrate support

27、202、345．．．半導體基材27, 202, 345. . . Semiconductor substrate

28．．．氣體注入系統28. . . Gas injection system

29．．．冷卻氣體輸送系統29. . . Cooling gas delivery system

30．．．真空幫浦30. . . Vacuum pump

32．．．氧氣瓶32. . . oxygen cylinder

34．．．加熱器34. . . Heater

34a、34b．．．加熱元件34a, 34b. . . Heating element

36．．．脈衝產生器36. . . Pulse generator

38．．．節流閥38. . . Throttle valve

39．．．離子產生區39. . . Ion generating zone

62．．．氫氣瓶62. . . Hydrogen bottle

64、66、68．．．流量控制閥64, 66, 68. . . Flow control valve

70．．．惰氣瓶70. . . Inert gas cylinder

80．．．冷卻流量控制閥80. . . Cooling flow control valve

82．．．冷卻氣源82. . . Cooling gas source

200．．．半導體結構200. . . Semiconductor structure

204．．．穿隧氧化物層204. . . Tunneling oxide layer

206．．．浮置閘極層206. . . Floating gate layer

210．．．多晶矽間介電層210. . . Polycrystalline dielectric layer

212、216、230、231、232、233．．．氧化物層212, 216, 230, 231, 232, 233. . . Oxide layer

214．．．氮化物層214. . . Nitride layer

220．．．控制閘極層220. . . Control gate layer

240．．．薄膜堆疊240. . . Film stacking

241、242．．．閘極堆疊241, 242. . . Gate stack

250．．．溝槽250. . . Trench

251、252．．．側壁251, 252. . . Side wall

300．．．冷卻劑源300. . . Coolant source

301．．．排氣系統301. . . Exhaust system

302．．．製程氣源302. . . Process gas source

305．．．冷卻導管305. . . Cooling duct

325．．．靜電夾盤325. . . Electrostatic chuck

330．．．孔330. . . hole

333．．．靜電組件333. . . Electrostatic assembly

335．．．絕緣體335. . . Insulator

340．．．上表面340. . . Upper surface

350．．．電極350. . . electrode

355．．．電氣連接器355. . . Electrical connector

360．．．電壓供應導線360. . . Voltage supply wire

365．．．電氣接觸365. . . Electrical contact

370．．．電壓供應終端370. . . Voltage supply terminal

375．．．支撐件375. . . supporting item

382．．．製程氣體入口382. . . Process gas inlet

384．．．排氣出口384. . . Exhaust outlet

因此可以詳細瞭解上述本發明之特徵結構的方式，即對本發明更明確的描述，簡短地在前面概述過，可藉由參考實施例來得到，其中某些在附圖中示出。但應注意的是，附圖僅示出本發明之一般實施例，因此不應視為係對其範圍之限制，因為本發明可允許其他等效實施例。The manner in which the above-described features of the present invention are described in detail, that is, the more detailed description of the present invention, which is briefly described above, may be obtained by reference to the embodiments, some of which are illustrated in the drawings. It is to be understood, however, that the appended claims

第1圖示出根據本發明之一實施例的電漿反應器；Figure 1 shows a plasma reactor in accordance with an embodiment of the present invention;

第2A-B圖示出根據本發明之一或多個實施例的半導體結構之製造階段；2A-B illustrate a stage of fabrication of a semiconductor structure in accordance with one or more embodiments of the present invention;

第3圖示出用於本發明之一實施例的靜電夾盤；Figure 3 shows an electrostatic chuck for use in an embodiment of the invention;

第4圖示出包含一對流氣源的電漿反應器腔室；Figure 4 shows a plasma reactor chamber containing a pair of flow gas sources;

第5圖示出利用先前技藝之電漿氧化製程形成的氧化物層；以及Figure 5 illustrates an oxide layer formed using a prior art plasma oxidation process;

第6A-6B圖示出利用根據本發明之一或多個實施例之電漿氧化製程形成的氧化物層。6A-6B illustrate an oxide layer formed using a plasma oxidation process in accordance with one or more embodiments of the present invention.

10．．．腔室10. . . Chamber

11．．．反應器11. . . reactor

12．．．側壁12. . . Side wall

14．．．頂板14. . . roof

16．．．線圈天線16. . . Coil antenna

18．．．第一阻抗匹配網絡18. . . First impedance matching network

20．．．RF功率產生器20. . . RF power generator

22．．．閘極twenty two. . . Gate

26．．．基材支撐座26. . . Substrate support

27．．．半導體基材27. . . Semiconductor substrate

28．．．氣體注入系統28. . . Gas injection system

29．．．冷卻氣體輸送系統29. . . Cooling gas delivery system

30．．．真空幫浦30. . . Vacuum pump

32．．．氧氣瓶32. . . oxygen cylinder

34．．．加熱器34. . . Heater

34a、34b．．．加熱元件34a, 34b. . . Heating element

36．．．脈衝產生器36. . . Pulse generator

38．．．節流閥38. . . Throttle valve

39．．．離子產生區39. . . Ion generating zone

62．．．氫氣瓶62. . . Hydrogen bottle

64、66、68．．．流量控制閥64, 66, 68. . . Flow control valve

70．．．惰氣瓶70. . . Inert gas cylinder

80．．．冷卻流量控制閥80. . . Cooling flow control valve

82．．．冷卻氣源82. . . Cooling gas source

Claims (14)

一種在一半導體基材上處理一氧化物層的方法，其包含：將一欲氧化的基材置於具有一離子產生區的一電漿反應腔室內之一基材支撐件上；通入一製程氣體至該腔室內；以及在該電漿反應腔室的離子產生區內產生一電漿，以在該基材上形成一氧化物層，該離子產生區在該基材上方上升之距離係大於約2公分，該氧化物層具有一水平表面厚度及一側壁厚度，同時主動冷卻該基材至約-50℃至100℃範圍內的溫度。 A method for treating an oxide layer on a semiconductor substrate, comprising: placing a substrate to be oxidized on a substrate support member in a plasma reaction chamber having an ion generating region; Process gas into the chamber; and generating a plasma in the ion generating region of the plasma reaction chamber to form an oxide layer on the substrate, the ion generating region rising above the substrate Above about 2 cm, the oxide layer has a horizontal surface thickness and a sidewall thickness while actively cooling the substrate to a temperature in the range of from about -50 °C to 100 °C. 一種在一半導體基材上形成一氧化物層的方法，其包含：將一欲氧化的基材置於一電漿反應器之一腔室內之一基材支撐件上，該腔室具有一離子產生區；通入一製程氣體至該腔室內；以及在該腔室之該離子產生區內產生一電漿，其中該腔室之該離子產生區自該基材上升之距離係大於約2公分，以在該基材上形成一氧化物層，同時主動冷卻該基材至低於約100℃的溫度。 A method of forming an oxide layer on a semiconductor substrate, comprising: placing a substrate to be oxidized on a substrate support in a chamber of a plasma reactor, the chamber having an ion a generating zone; introducing a process gas into the chamber; and generating a plasma in the ion generating region of the chamber, wherein the ion generating region of the chamber rises from the substrate by more than about 2 cm To form an oxide layer on the substrate while actively cooling the substrate to a temperature below about 100 °C. 如申請專利範圍第1項所述之方法，其中該基材溫度在該氧化物層形成期間係經主動冷卻至約0℃至50℃範圍內的溫度。 The method of claim 1, wherein the substrate temperature is actively cooled to a temperature in the range of from about 0 °C to 50 °C during formation of the oxide layer. 如申請專利範圍第1項所述之方法，其中主動冷卻該基材溫度包含使一冷卻劑流動通過該基材支撐件。 The method of claim 1, wherein actively cooling the substrate temperature comprises flowing a coolant through the substrate support. 如申請專利範圍第4項所述之方法，其中該基材支撐件包含一表面，其具有複數個冷卻導管，並且主動冷卻該基材溫度包含使該基材與該基材支撐件的表面接觸。 The method of claim 4, wherein the substrate support comprises a surface having a plurality of cooling conduits, and actively cooling the substrate temperature comprises contacting the substrate with a surface of the substrate support . 如申請專利範圍第5項所述之方法，其中該基材支撐件更包含一系列通道，其供應一冷卻劑至該等冷卻導管。 The method of claim 5, wherein the substrate support further comprises a series of channels that supply a coolant to the cooling conduits. 如申請專利範圍第4項所述之方法，其中主動冷卻該基材溫度包含流動一對流氣體至該反應腔室內。 The method of claim 4, wherein actively cooling the substrate temperature comprises flowing a pair of flowing gases into the reaction chamber. 如申請專利範圍第7項所述之方法，其中該對流氣體包含氦氣。 The method of claim 7, wherein the convection gas comprises helium. 如申請專利範圍第7項所述之方法，其中該對流氣體包含約500sccm至約3000sccm範圍內的流速。 The method of claim 7, wherein the convective gas comprises a flow rate in the range of from about 500 sccm to about 3000 sccm. 如申請專利範圍第1或2項所述之方法，其中該電漿包含一氧物種，並且主動冷卻該基材增加該氧物種的黏滯係數。 The method of claim 1 or 2, wherein the plasma comprises an oxygen species, and actively cooling the substrate increases a viscosity coefficient of the oxygen species. 如申請專利範圍第1或2項所述之方法，其中主動冷卻該基材包含流動一對流氣體至該反應器。 The method of claim 1 or 2, wherein actively cooling the substrate comprises flowing a pair of flowing gases to the reactor. 如申請專利範圍第1或2項所述之方法，其中主動冷卻該基材包含在該基材和該基材支撐件之間循環一冷卻劑。 The method of claim 1 or 2, wherein actively cooling the substrate comprises circulating a coolant between the substrate and the substrate support. 如申請專利範圍第12項所述之方法，其中該冷卻劑包含氦氣。 The method of claim 12, wherein the coolant comprises helium. 如申請專利範圍第13項所述之方法，其中該冷卻劑更包含一第二惰氣。The method of claim 13, wherein the coolant further comprises a second inert gas.