TWI442405B

TWI442405B - Memory device with a current sink system for source side sensing and its sensing method

Info

Publication number: TWI442405B
Application number: TW98138891A
Authority: TW
Inventors: Chun Hsiung Hung; Han Sung Chen; Chung Kuang Chen
Original assignee: Macronix Int Co Ltd
Priority date: 2009-11-16
Filing date: 2009-11-16
Publication date: 2014-06-21
Also published as: TW201118881A

Description

具有用於源極端感測之汲入電流系統的記憶體裝置及其感測方法Memory device with inrush current system for source terminal sensing and sensing method thereof

本發明係關於記憶裝置的感測電路，特別是關於如此裝置的源極端感測電路。The present invention relates to sensing circuits for memory devices, and more particularly to source terminal sensing circuits for such devices.

現今存在許多利用電荷儲存記憶胞型態的非揮發記憶體，包括記憶胞儲存電荷於一場效電晶體的通道與閘極之間。所儲存的電荷數量影響了電晶體的臨界電壓，其可以被感測以指示資料。There are many non-volatile memories that use charge storage memory cell types, including memory cells that store charge between a channel and a gate of a potent transistor. The amount of charge stored affects the threshold voltage of the transistor, which can be sensed to indicate data.

一種型態的電荷儲存記憶胞被稱為浮動閘極記憶胞。在浮動閘極記憶胞中，電荷被儲存在一電性導電層介於場效電晶體的通道與閘極之間。臨界電壓的改變藉由施加一合適的電壓於此記憶胞自此電性導電層儲存或移除電荷。另一種型態的記憶胞被稱為電荷捕捉記憶胞，其使用一介電電荷捕捉層取代浮動閘極。One type of charge storage memory cell is called a floating gate memory cell. In the floating gate memory cell, the charge is stored between an electrically conductive layer between the channel and the gate of the field effect transistor. The change in the threshold voltage stores or removes charge from the electrically conductive layer by applying a suitable voltage to the memory cell. Another type of memory cell is called a charge trapping memory cell, which uses a dielectric charge trapping layer instead of a floating gate.

在讀取操作中，施加合適的電壓以自此記憶胞的汲極端誘發電流至源極端。此電流係取決於電晶體的臨界電壓，因此指示儲存於其中的資料。In a read operation, a suitable voltage is applied to induce current from the 汲 extreme of the memory cell to the source terminal. This current is dependent on the threshold voltage of the transistor and therefore indicates the data stored therein.

讀取一所選取記憶胞的資料係利用感測流入汲極端(“汲極端感測”)的電流或是感測自源極端(“源極端感測”)流出的電流來進行。Reading the data of a selected memory cell is performed by sensing the current flowing into the 汲 extreme ("汲 extreme sensing") or sensing the current flowing from the source terminal ("source extreme sensing").

在汲極端感測中，此所選取記憶胞的汲極終端連接之一資料線(如位元線)與一感測電路耦接。施加合適的電壓至此記憶胞以自資料線誘發一電流經過源極端至此記憶胞的汲極終端。此感測電路感測資料線由此記憶胞導入的電流，且將此感測的電流與一合適的參考值作比較以決定儲存於此記憶胞中的資料。可參閱，舉例而言，美國專利第7,295,471、6,272,043、7,339,846、6,731,452及6,771,543。汲極端感測的表現缺點可以包括相對慢的讀取速度及高功率消耗。In the 汲 extreme sensing, one of the data lines (such as the bit line) of the drain terminal of the selected memory cell is coupled to a sensing circuit. Applying a suitable voltage to the memory cell induces a current from the data line through the source terminal to the drain terminal of the memory cell. The sensing circuit senses the current drawn by the data line from the memory cell and compares the sensed current to a suitable reference value to determine the data stored in the memory cell. See, for example, U.S. Patent Nos. 7,295,471, 6,272,043, 7,339,846, 6,731,452, and 6,771,543. The performance disadvantages of extreme sensing can include relatively slow read speeds and high power consumption.

在源極端感測中，此所選取記憶胞的源極終端連接之一資料線與一感測電路耦接。施加合適的電壓至此記憶胞以誘發一讀取電流自此記憶胞的汲極終端經過源極終端而進入資料線。此感測電路在資料線感測讀取電流，且將此感測的電流與一合適的參考值作比較以決定儲存於此記憶胞中的資料。In source extreme sensing, one of the source terminals of the selected memory cell is coupled to a sensing circuit. A suitable voltage is applied to the memory cell to induce a read current from the drain terminal of the memory cell through the source terminal into the data line. The sensing circuit senses the read current at the data line and compares the sensed current to an appropriate reference value to determine the data stored in the memory cell.

此讀取電流可以使用此讀取電流在此感測電路的一感測放大器之感測節點來對一等效負載電容充電而被感測。感測輸入的電壓改變係與讀取電流相關，且因此指示儲存於此所選取記憶胞中的資料。The read current can be sensed using the sense current at a sense node of a sense amplifier of the sense circuit to charge an equivalent load capacitor. The voltage change of the sense input is related to the read current and thus to the data stored in the selected memory cell.

在源極端感測中，此感測放大器的感測輸入與此記憶胞的源極終端耦接。其結果是，會造成此源極端感測一特定的問題，此源極終端的電壓也會增加一個與讀取電流相關的一數量。在源極終端增加的電壓會減少汲極至源極的電壓且會增加此所選取記憶胞的主體效應。如此會減少由此記憶胞提供的讀取電流。In source extreme sensing, the sense input of the sense amplifier is coupled to the source terminal of the memory cell. As a result, this source extreme senses a particular problem, and the voltage at the source terminal also increases by an amount associated with the read current. The increased voltage at the source terminal reduces the drain-to-source voltage and increases the bulk effect of the selected memory cell. This will reduce the read current provided by this memory cell.

陣列中記憶胞的臨界電壓會隨著操作環境的變動及材料和製程的變動而產生變動。此變動會造成陣列間儲存相同資料時讀取電流的變動，包括因為源極電壓增加所導致的讀取電流改變的差值。因此，具有源極電壓增加的一數量與讀取電流相關，結果會是感測放大器之感測輸入的電壓或電流一個較廣的分佈，其增加了感測所需的時間及感測電路的複雜程度。The threshold voltage of the memory cells in the array varies with changes in the operating environment and changes in materials and processes. This change causes a change in the read current when the same data is stored between the arrays, including the difference in read current changes due to the increase in the source voltage. Therefore, an amount with a source voltage increase is related to the read current, and the result is a wider distribution of the sense input voltage or current of the sense amplifier, which increases the time required for sensing and the sensing circuit. Complexity.

因此，需要提供一種源極端感測電路，其可以解決在讀取時因為源極電壓變動所產生的問題，及操作此種電路的方法。Therefore, it is desirable to provide a source extreme sensing circuit that solves the problems caused by source voltage variations during reading and the method of operating such a circuit.

此處所描述之源極端感測技術根據自此記憶胞源極終端所讀取之電流與自該讀取電流所導入之汲入電流之間的差值來決定儲存於記憶胞中的資料值。此汲入電流係響應由一例如是參考胞所提供之一參考電流源的參考電流的大小而導入。The source extreme sensing technique described herein determines the value of the data stored in the memory cell based on the difference between the current read from the memory cell source terminal and the inrush current introduced from the read current. The inrush current is introduced in response to a magnitude of a reference current, such as a reference current source provided by the reference cell.

使用讀取電流與汲入電流之間的差值，而不是整個讀取電流，會減少在感測操作時記憶胞源極終端的電壓變動。如此則會在此陣列中的記憶胞之間進行源極端感測時減少讀取電流的變動。其結果是，於此陣列間記憶胞中的感測節點之電壓或電流分佈會變得較為緊縮。Using the difference between the read current and the inrush current, rather than the entire read current, reduces the voltage variation of the memory source terminal during the sensing operation. This reduces the variation in read current when source-to-source sensing is performed between memory cells in the array. As a result, the voltage or current distribution of the sensing nodes in the memory cells between the arrays becomes tighter.

此處所描述之記憶裝置包括一記憶陣列可自該記憶陣列中的一選取記憶胞之一源極端點提供一讀取電流至一資料線，一參考電流源可提供一參考電流，一與該資料線耦接的汲入電流源，該汲入電流源可響應該參考電流的一大小而自該資料線導入一汲入電流。此記憶裝置更包括感測放大電路包含一感測節點與該資料線耦接。該感測放大電路響應於該讀取電流與該汲入電流之間的一差值，而產生一用來指示儲存於該被選取記憶胞中的一資料值之一輸出信號。The memory device described herein includes a memory array for providing a read current to a data line from a source terminal of a selected memory cell in the memory array, a reference current source providing a reference current, and the data The line is coupled to the inrush current source, and the inrush current source is capable of introducing an inrush current from the data line in response to a magnitude of the reference current. The memory device further includes a sensing amplifier circuit including a sensing node coupled to the data line. The sense amplification circuit generates an output signal for indicating a data value stored in the selected memory cell in response to a difference between the read current and the inrush current.

此記憶裝置更包括電路用來設置該參考節點的一參考電壓，該參考電壓與該參考電流的該大小無關，其中該感測放大電路係響應於該參考節點與該感測節點的電壓之間的一差值而產生該輸出信號。在此情況下，到達參考電壓所需的時間比使用使用參考電流來對參考節點充電來得快，允許較高的操作速度。The memory device further includes a circuit for setting a reference voltage of the reference node, the reference voltage being independent of the magnitude of the reference current, wherein the sensing amplification circuit is responsive to a voltage between the reference node and the sensing node The difference is generated to produce the output signal. In this case, the time required to reach the reference voltage is faster than using the reference current to charge the reference node, allowing for a higher operating speed.

此處所描述之感測一記憶胞的方法包含施加一偏壓至該記憶胞以自該記憶胞的一源極終端誘發一讀取電流，自一參考電流源提供一參考電流，響應該參考電流的一大小而自該讀取電流導入一汲入電流，提供該讀取電流與該汲入電流之間的一差值至一感測節點，以及根據該差值決定儲存於該選取記憶胞中的一資料值。The method of sensing a memory cell as described herein includes applying a bias voltage to the memory cell to induce a read current from a source terminal of the memory cell, providing a reference current from a reference current source, responsive to the reference current And inputting a current from the read current, providing a difference between the read current and the inrush current to a sensing node, and determining to be stored in the selected memory cell according to the difference a data value.

本發明之目的，特徵，和實施例，會在下列實施方式的章節中搭配圖式被描述。The objects, features, and embodiments of the present invention will be described in the accompanying drawings.

本發明實施例搭配以下第1到14圖進行詳細描述。The embodiments of the present invention are described in detail with reference to the following figures 1 to 14.

第1圖顯示一傳統記憶裝置100之示意圖，在其中使用一源極端感測機制以自選取記憶胞110中讀取所儲存之資料。此裝置100包括一記憶胞陣列105，顯示於此例示圖中為一虛擬接地組態。此陣列105包含複數條字元線，其包含字元線120-1和120-2在一第一方向上延伸且與此陣列105中記憶胞的閘極終端耦接。這些字元線120-1和120-2與列解碼器/驅動器125電性溝通。1 shows a schematic diagram of a conventional memory device 100 in which a source extreme sensing mechanism is used to read stored data from selected memory cells 110. The device 100 includes a memory cell array 105, shown as a virtual ground configuration in this illustration. The array 105 includes a plurality of word lines including word lines 120-1 and 120-2 extending in a first direction and coupled to gate terminals of the memory cells in the array 105. These word lines 120-1 and 120-2 are in electrical communication with the column decoder/driver 125.

此陣列105也包含複數條位元線130-1和130-2在一第二方向上延伸且與此陣列105中記憶胞的源極和汲極終端耦接。這些位元線130-1和130-2與行解碼器/驅動器135電性溝通。The array 105 also includes a plurality of bit lines 130-1 and 130-2 extending in a second direction and coupled to the source and drain terminals of the memory cells in the array 105. These bit lines 130-1 and 130-2 are in electrical communication with the row decoder/driver 135.

記憶胞110是此陣列105中記憶胞的代表性記憶胞。字元線120-2與此記憶胞110中的閘極終端耦接。位元線130-2和130-3分別與此記憶胞110中的第一導電終端112和第二導電終端114耦接。此第一導電終端112和第二導電終端114，視流經此記憶胞110上電流方向分別作為記憶胞110的源極或汲極終端之一。Memory cell 110 is a representative memory cell of memory cells in this array 105. The word line 120-2 is coupled to the gate terminal of the memory cell 110. Bit lines 130-2 and 130-3 are coupled to first conductive terminal 112 and second conductive terminal 114 in memory cell 110, respectively. The first conductive terminal 112 and the second conductive terminal 114 respectively see a current direction flowing through the memory cell 110 as one of a source or a drain terminal of the memory cell 110.

在讀取或感測儲存於記憶胞110中的一資料時，列解碼器/驅動器125係響應位址信號140而施加讀取電壓V_WL 至字元線120-2。行解碼器/驅動器135係響應位址信號140而施加讀取電壓V_BL 至位元線130-2，且將位元線130-3耦接至感測電路160的一輸入線150。施加在字元線120-2和位元線130-2的讀取電壓自汲極終端112誘發一讀取電流I_CELL 至源極終端114且至位元線130-3。When reading or sensing a data stored in memory cell 110, column decoder/driver 125 applies read voltage V _WL to word line 120-2 in response to address signal 140. The row decoder/driver 135 applies the read voltage _VBL to the bit line 130-2 in response to the address signal 140 and couples the bit line 130-3 to an input line 150 of the sense circuit 160. The read voltage applied to word line 120-2 and bit line 130-2 induces a read current I _CELL from source terminal 112 to source terminal 114 and to bit line 130-3.

此位元線130-3上的讀取電流I_CELL 經由輸入線150提供至一感測放大器170的一感測輸入172。此讀取電流I_CELL 在感測放大器170的感測輸入172對等效電容器C_LOAD1 進行充電，導致感測電壓(CMI)在讀取操作持續期間以和讀取電流I_CELL 等比例方式改變。因此，在感測輸入172的讀取電壓假如此被選取記憶胞110是在一較低臨界狀態時會較此被選取記憶胞110是在一較高臨界狀態時更快地改變。The read current I _CELL on the bit line 130-3 is provided via input line 150 to a sense input 172 of a sense amplifier 170. This read current I _CELL charges the equivalent capacitor C _LOAD1 at the sense input 172 of the sense amplifier 170, causing the sense voltage (CMI) to change in a proportional manner to the read current I _CELL during the duration of the read operation. Thus, the read voltage at sense input 172 is thus changed faster when the selected memory cell 110 is in a lower critical state than when the selected memory cell 110 is in a higher critical state.

第2圖為在記憶胞110具有兩個狀態之一操作時感測輸入172的電壓改變與時間的關係簡要示意圖。曲線200顯示假如記憶胞110是在一較低臨界狀態時感測輸入172的電壓改變，而曲線210顯示假如記憶胞110是在一較高臨界狀態時感測輸入172的電壓改變。曲線200和210之間的差異會跟隨著用以區分此記憶胞是在一較低還是較高臨界狀態的感測邊界之感測區間改變。為了可靠地區分不同的臨界狀態，必須維持一個相對大的感測邊界。Figure 2 is a schematic diagram showing the relationship between the voltage change of the sense input 172 and time when the memory cell 110 has one of two states of operation. Curve 200 shows that if memory cell 110 is a voltage change in sense input 172 in a lower critical state, curve 210 shows a change in voltage of sense input 172 if memory cell 110 is in a higher critical state. The difference between curves 200 and 210 will follow a change in the sensing interval to distinguish whether the memory cell is a sensing boundary in a lower or higher critical state. In order to reliably distinguish between different critical states, a relatively large sensing boundary must be maintained.

重新參考第1圖，一參考電流源180提供一參考電流I_REF 至感測放大器170的一參考輸入174。此參考電流I_REF 在感測放大器170的參考輸入174對等效電容器C_LOAD2 進行充電，轉變參考電流I_REF 至一參考電壓(V_TREF )。第2圖中的曲線220顯示第二輸入174的電壓改變與時間的關係。Referring back to FIG. 1, a reference current source 180 provides a reference current I _REF to a reference input 174 of the sense amplifier 170. This reference current I _REF charges the equivalent capacitor C _LOAD2 at the reference input 174 of the sense amplifier 170, transitioning the reference current I _REF to a reference voltage (V _TREF ). Curve 220 in FIG. 2 shows the voltage change of the second input 174 as a function of time.

一個感測致能信號SEN施加至感測放大器170以定義此被選取記憶胞110讀取操作時的感測區間。此感測放大器170響應輸入172和174之間的電壓差而產生一輸出用來指示儲存於被選取記憶胞110中的資料值。A sense enable signal SEN is applied to the sense amplifier 170 to define the sensed interval when the selected memory cell 110 is read. The sense amplifier 170 produces an output in response to the voltage difference between the inputs 172 and 174 to indicate the value of the data stored in the selected memory cell 110.

因為感測輸入172與記憶胞110的源極終端114耦接，此源極終端114上的電壓也會增加一個與讀取電流I_CELL 相關的數量。此源極終端114上的電壓增加減少了汲極至源極電壓且增加了此記憶胞110的本體效應，其因此會降低讀取電流I_CELL 。Because the sense input 172 is coupled to the source terminal 114 of the memory cell 110, the voltage on the source terminal 114 also increases by a quantity associated with the read current I _CELL . The increase in voltage on this source terminal 114 reduces the drain-to-source voltage and increases the bulk effect of this memory cell 110, which in turn reduces the read current I _CELL .

因為操作的環境變動的關係，也會因為材料及製程條件變動的關係，此記憶胞的臨界電壓會在陣列105之間變動。此變動會造成陣列105間儲存相同資料時讀取電流I_CELL 的變動，包括因為源極電壓增加所導致的讀取電流I_CELL 改變的差值。因此，具有源極電壓增加的一數量與讀取電流I_CELL 相關，結果會是感測輸入172的電壓或電流一個較廣的分佈，其增加了感測所需的時間及複雜程度。Because of the environmental changes in the operation, the threshold voltage of the memory cell will vary between the arrays 105 due to changes in material and process conditions. This change causes a change in the read current I _CELL when the same data is stored between the arrays 105, including the difference in the change in the read current I _CELL due to the increase in the source voltage. Thus, an amount having a source voltage increase is related to the read current I _CELL , which results in a wider distribution of the voltage or current of the sense input 172 , which increases the time and complexity required for sensing.

第3圖顯示一積體電路300的簡要方塊示意圖，在其中包含本發明所描述之使用於一記憶陣列320中的記憶胞之一源極端感測機制的汲入電流電路310。3 is a schematic block diagram of an integrated circuit 300 incorporating the inrush current circuit 310 of one of the memory source cells used in a memory array 320 described herein.

列解碼器322與複數條沿著此記憶陣列320列方向上排列的字元線324耦接。行解碼器326與複數條沿著此記憶陣列320行方向上排列的位元線328耦接，以自此陣列320的記憶胞中讀取和程式化資料。在區塊330中的感測放大器及資料輸入結構在此範例中經由資料匯流排332與行解碼器326耦接。此記憶陣列320中的記憶胞可以串連地、平行地或是虛擬接地的方式排列。Column decoder 322 is coupled to a plurality of word lines 324 arranged along the column direction of memory array 320. Row decoder 326 is coupled to a plurality of bit lines 328 arranged along the row direction of memory array 320 to read and program data from the memory cells of array 320. The sense amplifier and data input structure in block 330 is coupled to row decoder 326 via data bus 332 in this example. The memory cells in the memory array 320 can be arranged in series, in parallel, or in a virtual ground.

會於以下更詳細地描述，汲入電流電路310與資料匯流排332耦接以在此陣列320中的記憶胞進行源極端感測時響應一參考電流I_REF 而導入一汲入電流I_SINK 。此汲入電流電路310也會提供一參考電壓V_TREF 至區塊330中的感測放大器之參考輸入在此陣列320中的記憶胞進行源極端感測時。As will be described in more detail below, the inrush current circuit 310 is coupled to the data bus 332 to introduce an inrush current I _SINK in response to a reference current I _REF when the memory cells in the array 320 are source sensed. The inrush current circuit 310 also provides a reference voltage V _TREF to the reference input of the sense amplifier in block 330 when the memory cells in the array 320 are source sensed.

在此例示實施例中，使用一參考陣列340中參考胞所產生的參考電流I_REF 經由行解碼器342與匯流排346提供給汲入電流電路310。替代地也可以使用其他的技術來產生參考電流I_REF 。舉例而言，參考電流I_REF 可以藉由根據超過一個以上的參考胞之參考電流。In the illustrated embodiment, the reference current I _REF generated by the reference cells in a reference array 340 is provided to the inrush current circuit 310 via the row decoder 342 and the bus bar 346. Alternatively, other techniques can be used to generate the reference current I _REF . For example, the reference current I _REF can be based on a reference current based on more than one reference cell.

列解碼器344與沿著此參考陣列340列方向上排列的字元線345耦接。行解碼器342與沿著此參考陣列340行方向上排列的位元線343耦接。在此例示實施例中，參考陣列340與記憶陣列320是分開的，且包括分別的列及行解碼器344、342。替代地，參考陣列340可以是在記憶陣列320中的一部分，且在陣列320、340中分享解碼器。Column decoder 344 is coupled to word line 345 arranged along the column direction of this reference array 340. Row decoder 342 is coupled to bit line 343 arranged along the row direction of this reference array 340. In this illustrative embodiment, reference array 340 is separate from memory array 320 and includes separate column and row decoders 344, 342. Alternatively, reference array 340 may be part of memory array 320 and share decoders in arrays 320, 340.

於此陣列320中一選取記憶胞進行源極端感測時，讀取電流I_CELL 與汲入電流I_SINK 之間的電流差提供至一感測節點，因此於此感測節點上設置一電流或電壓。方塊330中的感測放大器具有一感測輸入與此感測節點耦接，且會響應此感測節點上的電流或電壓而產生用來指示儲存於該選取記憶胞中的資料之一輸出信號。When a memory cell is selected for source-end sensing in the array 320, the current difference between the read current I _CELL and the inrush current I _SINK is supplied to a sensing node, so a current is set on the sensing node or Voltage. The sense amplifier in block 330 has a sense input coupled to the sense node and responsive to current or voltage on the sense node to generate an output signal indicative of one of the data stored in the selected memory cell .

因為感測放大器之感測輸入的電壓係根據讀取電流I_CELL 與汲入電流I_SINK 之間的電流差，而不是整個讀取電流I_CELL ，所選取記憶胞中源極終端的電壓變動會減少。如此則會在此陣列320中的記憶胞進行源極端感測時減少讀取電流I_CELL 的變動。其結果是，於此陣列間方塊330中的感測放大器之感測輸入的電壓或電流分佈會變得較為緊縮。Because the voltage of the sensing input of the sense amplifier is based on the current difference between the read current I _CELL and the inrush current I _SINK , rather than the entire read current I _CELL , the voltage variation of the source terminal in the selected memory cell will be cut back. This will reduce the variation of the read current I _CELL when the memory cells in the array 320 perform source-end sensing. As a result, the voltage or current distribution of the sense input of the sense amplifier in block 330 between the arrays becomes tighter.

位址係透過匯流排350提供至行解碼器326、342及列解碼器322、344。資料係由積體電路300上的輸入/輸出埠透過資料輸入線352傳送至方塊330之資料輸入結構。在此例示的實施例中，其他電路360也包括在此積體電路300內，例如通用目的處理器或特殊用途電路，或是由此記憶陣列所支援的組合模組以提供單晶片系統功能。資料係由方塊330中的感測放大器，透過資料輸出線354，傳送至積體電路300上的輸入/輸出埠或其他積體電路300內或外之資料目的地。The address is provided through bus bar 350 to row decoders 326, 342 and column decoders 322, 344. The data is transmitted from the input/output port on the integrated circuit 300 through the data input line 352 to the data input structure of block 330. In the illustrated embodiment, other circuits 360 are also included in the integrated circuit 300, such as a general purpose processor or special purpose circuit, or a combination module supported by the memory array to provide a single wafer system function. The data is transmitted by the sense amplifier in block 330 through data output line 354 to the input/output ports on integrated circuit 300 or to other data destinations within or outside of integrated circuit 300.

此積體電路300包含控制器369以讀取、程式化和抹除記憶陣列320與參考陣列340中的記憶胞。此控制器369，在此範例中為一偏壓調整狀態機構，控制由區塊368中產生的偏壓調整供應電壓或提供至區塊368中的讀取、程式化或抹除電壓。此控制器369的應用可以使用，業界所熟知的技術，如特殊目的邏輯電路來實施。在另一實施例中，該控制器369包含一通用目的處理器，其可以實施在相同積體電路上，其執行一電腦程式以控制該裝置的操作。在另一實施例中，特殊目的邏輯電路和一通用目的處理器的組合可以被用來實施該控制器369。The integrated circuit 300 includes a controller 369 to read, program, and erase the memory cells in the memory array 320 and the reference array 340. The controller 369, in this example a bias adjustment state mechanism, controls the supply voltage being applied by the bias generated in block 368 or supplied to the read, program or erase voltage in block 368. The application of this controller 369 can be implemented using techniques well known in the art, such as special purpose logic circuits. In another embodiment, the controller 369 includes a general purpose processor that can be implemented on the same integrated circuit that executes a computer program to control the operation of the device. In another embodiment, a combination of special purpose logic circuitry and a general purpose processor can be used to implement the controller 369.

第4圖顯示此記憶陣列320中的一選取記憶胞進行源極端感測之一方法400流程圖。可以理解的是第4圖中的某些方塊可以被合併或是部份執行而不會影響了所欲達成的功效。4 is a flow chart showing a method 400 of selecting a memory cell for source extreme sensing in the memory array 320. It can be understood that some of the blocks in Figure 4 can be combined or partially executed without affecting the desired effect.

在方塊410，施加一讀取偏壓至該被選取之記憶胞以自該被選取之記憶胞的一源極終端誘發一讀取電流I_CELL 。At block 410, a read bias is applied to the selected memory cell to induce a read current I _CELL from a source terminal of the selected memory cell.

在方塊420，自一參考電流源提供一參考電流I_REF 。在第3圖的例示實施例中，此參考電流I_REF 是來自參考陣列340中的參考胞。參考電流I_REF 因此藉由施加合適的偏壓電壓至此參考胞以誘發一參考電流I_REF 而提供。At block 420, a reference current I _{REF is} provided from a reference current source. In the illustrated embodiment of FIG. 3, this reference current I _REF is from a reference cell in reference array 340. The reference current I _{REF is} thus provided by applying a suitable bias voltage to the reference cell to induce a reference current I _REF .

在方塊430，汲入電流電路310響應該參考電流I_REF 的一大小而自該讀取電流I_CELL 導入一汲入電流I_SINK 。At block 430, the inrush current circuit 310 _receives an inrush current I _SINK from the read current I _{CELL in} response to a magnitude of the reference current I _REF .

在方塊440，提供該讀取電流I_CELL 與該汲入電流I_SINK 之間的一差值至一與方塊330中的感測放大器之感測輸入耦接的感測節點。At block 440, a difference between the read current I _CELL and the inrush current I _SINK is provided to a sense node coupled to the sense input of the sense amplifier in block 330.

在方塊450，根據讀取電流I_CELL 與該汲入電流I_SINK 之間的該差值決定儲存於該被選取記憶胞中的一資料值。At block 450, a data value stored in the selected memory cell is determined based on the difference between the read current I _CELL and the inrush current I _SINK .

第5圖顯示汲入電流電路310在此記憶陣列320中的一被選取記憶胞510進行源極端感測時的一簡要示意圖。FIG. 5 shows a simplified schematic diagram of the inrush current circuit 310 when a selected memory cell 510 in the memory array 320 performs source terminal sensing.

如第5圖中所示，字元線324a與所選取記憶胞510的閘極耦接。位元線328a與汲極終端511耦接，而位元線328b與源極終端512耦接。於源極端感測時，行解碼器326將位元線328b與資料線332a耦接。As shown in FIG. 5, word line 324a is coupled to the gate of selected memory cell 510. Bit line 328a is coupled to drain terminal 511, and bit line 328b is coupled to source terminal 512. During source extreme sensing, row decoder 326 couples bit line 328b to data line 332a.

在此例示中，汲入電流電路310接收資料線332a上由參考陣列340的參考胞560所提供之參考電流I_REF 。如之前所討論過的，替代地也可以使用其他技術來提供參考電流I_REF 。位元線343a與參考胞560的汲極終端561耦接，而位元線343b與源極終端562耦接。於源極端感測時，行解碼器342將位元線343b與資料線346a耦接。In this illustration, the inrush current circuit 310 receives the reference current I _REF provided by the reference cell 560 of the reference array 340 on the data line 332a. As previously discussed, other techniques may alternatively be used to provide the reference current I _REF . The bit line 343a is coupled to the drain terminal 561 of the reference cell 560, and the bit line 343b is coupled to the source terminal 562. The row decoder 342 couples the bit line 343b to the data line 346a during source extreme sensing.

此汲入電流電路310包括汲入電流源520與資料線332a耦接。汲入電流源520自讀取電流I_CELL 導入該汲入電流I_SINK 。此汲入電流I_SINK 具有一大小其為參考電流I_REF 大小的一函數關係。在此處所描述的實施例中，汲入電流源520係利用一電流鏡，且因此具有一大小其直接正比於參考電流I_REF 的大小。舉例而言，汲入電流I_SINK 的一大小可以大致與參考電流I_REF 大小相當。或是替代地使用其他的技術來實施汲入電流源520。舉例而言，汲入電流I_SINK 的一大小可以與參考電流I_REF 大小成反比。The inrush current circuit 310 includes a sink current source 520 coupled to the data line 332a. The inrush current source 520 introduces the inrush current I _SINK from the read current I _CELL . This inrush current I _SINK has a magnitude which is a function of the magnitude of the reference current I _REF . In the embodiment described herein, the inrush current source 520 utilizes a current mirror and thus has a magnitude that is directly proportional to the magnitude of the reference current I _REF . For example, a magnitude of the inrush current I _SINK can be approximately equal to the magnitude of the reference current I _REF . Alternatively, other techniques may be used to implement the inrush current source 520. For example, a magnitude of the inrush current I _SINK can be inversely proportional to the magnitude of the reference current I _REF .

此汲入電流電路310也具有一輸出522提供一參考電壓V_TREF 以偏壓參考節點595。此參考節點595與感測放大器570的參考電壓TREF輸入574耦接。The inrush current circuit 310 also has an output 522 that provides a reference voltage V _TREF to bias the reference node 595. This reference node 595 is coupled to the reference voltage TREF input 574 of the sense amplifier 570.

感測電流I_SENSE ，其為讀取電流I_CELL 與該汲入電流I_SINK 之間的一差值，提供至一感測節點590。此感測節點590與感測放大器570的感測輸入CMI 572耦接。A sense current I _SENSE , which is a difference between the read current I _CELL and the inrush current I _SINK , is provided to a sense node 590 . This sense node 590 is coupled to the sense input CMI 572 of the sense amplifier 570.

此感測電流I_SENSE 係由將等效負載電容C_load1 充電而轉換成感測節點590的一電壓。感測放大器570係響應感測節點590耦接至感測輸入CMI 572的電壓，與參考節點595耦接至的參考輸入574電壓，之間的差值，而產生用來指示儲存於該選取記憶胞510中的臨界狀態之一輸出信號576。This sense current I _SENSE is converted into a voltage of the sense node 590 by charging the equivalent load capacitance C _load1 . The sense amplifier 570 is generated in response to the difference between the voltage sensed by the sense node 590 coupled to the sense input CMI 572 and the reference input 574 voltage coupled to the reference node 595, and is generated to indicate storage in the selected memory. One of the critical states in cell 510 outputs a signal 576.

因為感測放大器570的感測輸入CMI 572之電壓係與讀取電流I_CELL 和該汲入電流I_SINK 之間的差值而不是整個汲入電流I_SINK 相關，所選取記憶胞510中源極終端512的電壓變動會減少。如此則會在此陣列320中的記憶胞進行源極端感測時減少讀取電流I_CELL 的變動。其結果是，於感測放大器的感測輸入572之電壓分佈會變得較為緊縮。Because the voltage of the sense input CMI 572 of the sense amplifier 570 is related to the difference between the read current I _CELL and the inrush current I _SINK rather than the entire inrush current I _SINK , the source of the selected memory cell 510 The voltage variation of terminal 512 is reduced. This will reduce the variation of the read current I _CELL when the memory cells in the array 320 perform source-end sensing. As a result, the voltage distribution at the sense input 572 of the sense amplifier can become tighter.

此外，使用汲入電流電路310來偏壓參考節點595，而不是使用參考電流I_REF 來將等效負載電容C_load2 充電，允許較高的操作速度。In addition, the inrush current circuit 310 is used to bias the reference node 595 instead of using the reference current I _REF to charge the equivalent load capacitance C _load2 , allowing for higher operating speeds.

當使用參考電流I_REF 來對參考節點595充電時，到達一參考電壓所需的時間與此參考胞的臨界電壓相關聯。因此，感測操作必須在參考節點取得參考電壓值的一段時間之後才進行。使用汲入電流電路310來偏壓參考節點595，到達參考電壓所需的時間比使用使用參考電流I_REF 來對參考節點595充電來得快。When the reference current I _{REF is} used to charge the reference node 595, the time required to reach a reference voltage is associated with the threshold voltage of this reference cell. Therefore, the sensing operation must be performed after the reference node has obtained the reference voltage value for a period of time. Using the inrush current circuit 310 to bias the reference node 595, the time required to reach the reference voltage is faster than using the reference current I _REF to charge the reference node 595.

第6圖顯示操作第5圖中所示的結構以使用此處所描述之源極端感測技術來感測儲存在此所選取記憶胞510中的資料值之一時序圖。可以理解的是，第6圖中的時序圖是經過簡化的且並未等比例繪示。Figure 6 shows a timing diagram for operating the structure shown in Figure 5 to sense one of the data values stored in the selected memory cell 510 using the source extreme sensing techniques described herein. It will be understood that the timing diagrams in Figure 6 are simplified and not shown to scale.

在時間T1，列解碼器322響應地址信號而施加一讀取偏壓V_WL-READ 至與該被選取之記憶胞510閘極耦接的字元線324a，行解碼器326響應地址信號而施加一讀取偏壓V_BL-READ 至與該被選取之記憶胞510汲極終端511耦接的位元線328a，及將位元線328b與資料線332a耦接。施加至字元線324a及位元線328a的偏壓誘發一讀取電流I_CELL 自汲極終端511至源極終端512，且進入位元線328b與資料線332a。At time T1, column decoder 322 applies a read bias voltage V _WL-READ to word line 324a coupled to the selected memory cell 510 gate in response to the address signal, and row decoder 326 applies the address signal in response thereto. A read bias voltage _VBL-READ is coupled to the bit line 328a coupled to the selected memory cell 510 drain terminal 511, and the bit line 328b is coupled to the data line 332a. The bias applied to word line 324a and bit line 328a induces a read current I _CELL from drain terminal 511 to source terminal 512 and into bit line 328b and data line 332a.

列解碼器344響應地址信號而施加一讀取偏壓V_WL-REF 至與該被選取之參考胞560閘極耦接的字元線345a，行解碼器342響應地址信號而施加一讀取偏壓V_BL-REF 至與該被選取之參考胞560汲極終端561耦接的位元線343a，及將位元線343b與資料線346a耦接。施加至字元線345a及位元線343a的電壓誘發一參考電流I_REF 自汲極終端561至源極終端562，至位元線343b而進入字元線346a，及進入汲入電流電路310。Column decoder 344 applies a read bias voltage V _WL-REF to word line 345a coupled to the selected reference cell 560 gate in response to the address signal, and row decoder 342 applies a read bias in response to the address signal. The voltage V _BL-REF is coupled to the bit line 343a coupled to the selected reference cell 560 drain terminal 561, and the bit line 343b is coupled to the data line 346a. The voltage applied to word line 345a and bit line 343a induces a reference current I _REF from drain terminal 561 to source terminal 562, to bit line 343b to word line 346a, and into inrush current circuit 310.

汲入電流電路310中的汲入電流源520與資料線332a耦接。汲入電流源520響應該參考電流I_REF 的一大小而自該讀取電流I_CELL 導入一汲入電流I_SINK 。The inrush current source 520 in the inrush current circuit 310 is coupled to the data line 332a. The inrush current source 520 _receives an inrush current I _SINK from the read current I _{CELL in} response to a magnitude of the reference current I _REF .

感測電流I_SENSE ，其為該讀取電流I_CELL 與該汲入電流I_SINK 之間的一差值，提供至感測節點590。感測節點590與感測放大器570的感測輸入CMI 572耦接。A sense current I _SENSE , which is a difference between the read current I _CELL and the inrush current I _SINK , is provided to the sense node 590 . Sensing node 590 is coupled to sense input CMI 572 of sense amplifier 570.

此感測電流I_SENSE 係由將等效負載電容C_load1 充電而轉換成感測節點590的一電壓。因此，感測節點590與感測輸入CMI 572上的電壓會較快改變假如此被選取記憶胞510是在一較低臨界狀態時會較此被選取記憶胞510是在一較高臨界狀態時。在第6圖中，感測輸入CMI 572上的電壓是沿著曲線600假如此被選取記憶胞510是在一較低臨界狀態時，而會沿著曲線610假如此被選取記憶胞510是在一較高臨界狀態時。雖然在第6圖中僅顯示兩條曲線，但是可以明瞭的是在多重位元操作時會有超過兩條以上的曲線。This sense current I _SENSE is converted into a voltage of the sense node 590 by charging the equivalent load capacitance C _load1 . Therefore, the voltage on the sense node 590 and the sense input CMI 572 will change faster. Thus, when the selected memory cell 510 is in a lower critical state, the selected memory cell 510 is in a higher critical state. . In Fig. 6, the voltage on the sense input CMI 572 is along the curve 600. Thus, the selected memory cell 510 is in a lower critical state, and along the curve 610, the selected memory cell 510 is When a higher critical state. Although only two curves are shown in Fig. 6, it can be understood that there are more than two curves in the multi-bit operation.

在時間T2，感測放大器570為了響應與感測輸入CMI 572耦接的感測節點590，及與參考輸入574耦接的參考節點上的參考電壓V_TREF 兩者之間的電壓差，會產生用來指示該選取記憶胞510中的臨界狀態。在第6圖中，V_OUT 是一第一電壓620假如此被選取記憶胞510是在一較低臨界狀態時，而是一第二電壓630假如此被選取記憶胞510是在一較高臨界狀態時。At time T2, the sense amplifier 570 generates a voltage difference between the sense node 590 coupled to the sense input CMI 572 and the reference voltage V _TREF on the reference node coupled to the reference input 574. Used to indicate the critical state in the selected memory cell 510. In Fig. 6, V _OUT is a first voltage 620. Thus, when the selected memory cell 510 is in a lower critical state, a second voltage 630 is thus selected. The selected memory cell 510 is at a higher threshold. When the status is.

在此例示實施例中，此感測操作決定此記憶胞510是在兩種狀態之一。更一般的說，此處所描述的感測操作可以用在多位元記憶胞被程式化至超過兩種臨界電壓狀態時。舉例而言，在多重位元的實施例中，可以使用複數個參考電流或參考電壓。In this illustrative embodiment, this sensing operation determines that the memory cell 510 is in one of two states. More generally, the sensing operations described herein can be used when multi-bit memory cells are programmed to exceed two threshold voltage states. For example, in a multi-bit embodiment, a plurality of reference currents or reference voltages can be used.

第7圖顯示汲入電流電路310第一實施例的示意圖。此汲入電流電路310包括一運算放大器700用來偏壓參考電壓V_TREF 的參考節點595。此運算放大器700具有一第一輸入702與地耦接及具有一第二輸入704與參考節點595耦接。其結果是，在參考節點595的參考電壓V_TREF 由運算放大器700對地偏壓，且參考電壓V_TREF 與參考電流I_REF 無關。在此例示實施例中，參考電壓V_TREF 是地。替代地，其他的偏壓或技術也可以用來偏壓參考節點595。FIG. 7 shows a schematic diagram of a first embodiment of the inrush current circuit 310. The inrush current circuit 310 includes a reference node 595 that the operational amplifier 700 uses to bias the reference voltage V _TREF . The operational amplifier 700 has a first input 702 coupled to ground and a second input 704 coupled to a reference node 595. As a result, the reference voltage V _TREF at reference node 595 is biased to ground by operational amplifier 700, and reference voltage V _{TREF is} independent of reference current I _REF . In this illustrative embodiment, the reference voltage V _TREF is ground. Alternatively, other biasing or techniques can be used to bias reference node 595.

供應電壓V_DD 和負磊電路703提供偏壓電壓至運算放大器700。The supply voltage V _DD and the negative deflection circuit 703 provide a bias voltage to the operational amplifier 700.

在此例示實施例中的汲入電流源520係利用連接成電流鏡安排的電晶體710和720構成。電晶體710具有一第一導通終端與資料線346a及參考節點595連接以接收由參考胞560所提供的參考電流I_REF 。電晶體720具有一第一導通終端與感測節點590連接以響應該參考電流I_REF 的一大小而自該讀取電流I_CELL 導入一汲入電流I_SINK 。The inrush current source 520 in this exemplary embodiment is constructed using transistors 710 and 720 connected in a current mirror arrangement. The transistor 710 has a first conductive terminal coupled to the data line 346a and the reference node 595 to receive the reference current I _REF provided by the reference cell 560. The transistor 720 has a first conductive terminal connected to the sensing node 590 to introduce an inrush current I _SINK from the read current I _CELL in response to a magnitude of the reference current I _REF .

電晶體710和720的第二導通終端共同連接至運算放大器700的輸出。電晶體710和720的閘極共同連接至一設置電晶體730。於進行感測操作之前，設置信號732開啟設置電晶體730以偏壓電晶體710和720的閘極至一合適的偏壓電壓。在此例示實施例中，電晶體710和720的閘極被偏壓至地。替代地，也可以使用其他的偏壓。The second conductive terminals of transistors 710 and 720 are commonly connected to the output of operational amplifier 700. The gates of transistors 710 and 720 are commonly connected to a set transistor 730. Prior to performing the sensing operation, set signal 732 turns on set transistor 730 to bias the gates of transistors 710 and 720 to a suitable bias voltage. In this exemplary embodiment, the gates of transistors 710 and 720 are biased to ground. Alternatively, other bias voltages can be used.

在第7圖中也顯示放電電晶體750和760與資料線346a及感測節點590耦接。放電電晶體750和760的閘極共同耦接至一放電信號755以將參考節點595及感測節點590在進行感測操作之前接地。Also shown in FIG. 7 are discharge transistors 750 and 760 coupled to data line 346a and sense node 590. The gates of the discharge transistors 750 and 760 are commonly coupled to a discharge signal 755 to ground the reference node 595 and the sense node 590 prior to performing the sensing operation.

如第8圖所示的示意圖中，電晶體710可以連接至汲入電流電路310中的一電流鏡安排之中的每一個電晶體720-0到720-n。電晶體720-0到720-n係響應通過電晶體710之該參考電流I_REF 的一大小而自區塊330中的n+1個感測放大器每一個之各自的感測輸入CMI0到CMIn導入汲入電流I_SINK1 到I_SINKn 。第8圖中也顯示，運算放大器700提供參考電壓V_TREF 至區塊330中的n+1個感測放大器每一個的參考輸入。替代地，其他的組態也可以用來感測放大器的參考輸入，以自感測輸入導入汲入電流及提供參考電流。As shown in the diagram of FIG. 8, the transistor 710 can be connected to each of the transistors 720-0 to 720-n in a current mirror arrangement in the current circuit 310. The transistors 720-0 to 720-n are introduced from the respective sensing inputs CMI0 to CMIn of each of the n+1 sense amplifiers in the block 330 in response to a magnitude of the reference current I _REF through the transistor 710. Inrush current I _SINK1 to I _SINKn . Also shown in FIG. 8, operational amplifier 700 provides a reference voltage V _TREF to a reference input for each of the n+1 sense amplifiers in block 330. Alternatively, other configurations can be used to sense the reference input of the amplifier to introduce the inrush current and provide a reference current from the sense input.

第9圖顯示汲入電流電路310第二實施例的示意圖。在第9圖中省略了第7圖中的設置電晶體730，且電晶體710為二極體連接方式。FIG. 9 shows a schematic diagram of a second embodiment of the inrush current circuit 310. The setting transistor 730 in Fig. 7 is omitted in Fig. 9, and the transistor 710 is in a diode connection mode.

第10圖顯示汲入電流電路310第三實施例的示意圖。在第10圖中，與二極體連接的電晶體1010a和1010b安排成串連以導入參考電流I_REF 。電晶體1020a和1020b的閘極各自與二極體連接方式的電晶體1010a和1010b耦接，響應該參考電流I_REF 的一大小而自電晶體1020a和1020b導入汲入電流I_SINK 。Figure 10 shows a schematic diagram of a third embodiment of the inrush current circuit 310. In Fig. 10, the transistors 1010a and 1010b connected to the diode are arranged in series to introduce a reference current I _REF . The gates of the transistors 1020a and 1020b are each coupled to the diode-connected transistors 1010a and 1010b, and the inrush current I _{SINK is} introduced from the transistors 1020a and 1020b in response to a magnitude of the reference current I _REF .

第11圖顯示汲入電流電路310第四實施例的示意圖。串連安排的電晶體1110a和1110b導入由參考胞提供的參考電流I_REF 。電晶體1110a的閘極與一合適的偏壓電壓V_Bias 1130耦接，且電晶體1110b的閘極與由運算放大器700提供參考電壓V_TREF 耦接。電晶體1120a和1120b的閘極各自與電晶體1110a和1110b的閘極耦接。響應該參考電流I_REF 的一大小串連安排的電晶體1120a和1120b導入汲入電流I_SINK 。Figure 11 shows a schematic diagram of a fourth embodiment of the inrush current circuit 310. The serially arranged transistors 1110a and 1110b are introduced into a reference current I _REF provided by the reference cell. The gate of transistor 1110a is coupled to a suitable bias voltage V _Bias 1130, and the gate of transistor 1110b is coupled to a reference voltage V _TREF provided by operational amplifier 700. The gates of the transistors 1120a and 1120b are each coupled to the gates of the transistors 1110a and 1110b. The transistors 1120a and 1120b arranged in series in response to the magnitude of the reference current I _REF are introduced into the inrush current I _SINK .

第12圖顯示汲入電流電路310第五實施例的示意圖。在第12圖中，運算放大器700的第一輸入702係使用放電電晶體1200選擇性地與一偏壓電壓(在此例中為地)耦接。Figure 12 shows a schematic diagram of a fifth embodiment of the inrush current circuit 310. In FIG. 12, first input 702 of operational amplifier 700 is selectively coupled to a bias voltage (in this example, ground) using discharge transistor 1200.

第13圖顯示汲入電流電路310第六實施例的示意圖。在第13圖中，省略了第7圖中的設置電晶體730，且電晶體710的閘極係直接與地耦接。Figure 13 shows a schematic diagram of a sixth embodiment of the inrush current circuit 310. In Fig. 13, the setting transistor 730 in Fig. 7 is omitted, and the gate of the transistor 710 is directly coupled to the ground.

第14圖顯示汲入電流電路310第七實施例的示意圖。在第14圖中，電晶體710使用設置電晶體1400選擇性地變成二極體連接方式。於執行感測操作之前，設置信號1402開啟電晶體1400以偏壓電晶體710和720的閘極至參考電壓V_TREF 。於執行感測操作時，設置信號1402關閉電晶體1400，如此電晶體710和720的閘極在感測操作時是浮接的。Figure 14 shows a schematic diagram of a seventh embodiment of the inrush current circuit 310. In Fig. 14, the transistor 710 is selectively turned into a diode connection using the set transistor 1400. Prior to performing the sensing operation, the set signal 1402 turns on the transistor 1400 to bias the gates of the transistors 710 and 720 to the reference voltage V _TREF . When the sensing operation is performed, the set signal 1402 turns off the transistor 1400 such that the gates of the transistors 710 and 720 are floating during the sensing operation.

雖然本發明係已參照實施例來加以描述，然本發明創作並未受限於其詳細描述內容。替換方式及修改樣式係已於先前描述中所建議，且其他替換方式及修改樣式將為熟習此項技藝之人士所思及。特別是，所有具有實質上相同於本發明之構件結合而達成與本發明實質上相同結果者，皆不脫離本發明之精神範疇。因此，所有此等替換方式及修改樣式係意欲落在本發明於隨附申請專利範圍及其均等物所界定的範疇之中。Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

100．．．記憶裝置100. . . Memory device

105．．．記憶胞陣列105. . . Memory cell array

110．．．選取記憶胞110. . . Memory cell

112、511．．．汲極終端112, 511. . . Bungee terminal

114、512．．．源極終端114, 512. . . Source terminal

120-1、120-2．．．字元線120-1, 120-2. . . Word line

125．．．列解碼器/驅動器125. . . Column decoder/driver

130-1、130-2、130-3、130-4．．．位元線130-1, 130-2, 130-3, 130-4. . . Bit line

135．．．行解碼器/驅動器135. . . Row decoder/driver

140．．．位址140. . . Address

150．．．輸入線150. . . Input line

160．．．感測電路160. . . Sense circuit

170．．．感測放大器170. . . Sense amplifier

172．．．感測輸入172. . . Sensing input

174．．．參考輸入174. . . Reference input

176．．．感測輸出176. . . Sensing output

180．．．參考電流源180. . . Reference current source

300．．．積體電路300. . . Integrated circuit

310、520．．．汲入電流電路310, 520. . . Inrush current circuit

320．．．記憶陣列320. . . Memory array

324．．．字元線324. . . Word line

322、344．．．列解碼器322, 344. . . Column decoder

328．．．位元線328. . . Bit line

332．．．資料匯流排332. . . Data bus

326、342．．．行解碼器326, 342. . . Row decoder

330．．．感測放大器/資料輸入結構330. . . Sense amplifier / data input structure

340．．．參考陣列340. . . Reference array

343．．．參考位元線343. . . Reference bit line

345．．．參考字元線345. . . Reference character line

346、350．．．匯流排346, 350. . . Busbar

352．．．資料輸入線352. . . Data input line

354．．．資料輸出線354. . . Data output line

360．．．其他電路360. . . Other circuit

368．．．調整偏壓供應電壓368. . . Adjust bias supply voltage

369．．．控制器369. . . Controller

510．．．選取記憶胞510. . . Memory cell

560．．．參考胞560. . . Reference cell

561．．．參考胞之汲極終端561. . . Reference cell

562．．．參考胞之源極終端562. . . Reference source terminal

570．．．感測放大器570. . . Sense amplifier

572．．．感測輸入572. . . Sensing input

574．．．參考電壓574. . . Reference voltage

576．．．感測輸出576. . . Sensing output

590．．．感測節點590. . . Sensing node

595．．．參考節點595. . . Reference node

700．．．運算放大器700. . . Operational Amplifier

703．．．負磊703. . . Negative barrow

710、720、1010、1020、1110、1120．．．電晶體710, 720, 1010, 1020, 1110, 1120. . . Transistor

730、1400．．．設置電晶體730, 1400. . . Setting the transistor

732、1402．．．設置信號732, 1402. . . Setting signal

750、760．．．放電電晶體750, 760. . . Discharge transistor

755．．．放電信號755. . . Discharge signal

本發明係由申請專利範圍所界定。這些和其它目的，特徵，和實施例，會在下列實施方式的章節中搭配圖式被描述，其中：The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:

第1圖顯示使用源極端感測機制的傳統記憶裝置之示意圖。Figure 1 shows a schematic diagram of a conventional memory device using a source extreme sensing mechanism.

第2圖為感測放大器之感測輸入的電壓改變與時間之關係圖。Figure 2 is a graph of voltage change versus time for the sense input of the sense amplifier.

第3圖顯示一積體電路的簡要方塊示意圖，在其中包含本發明所描述之使用於一記憶陣列中的記憶胞之一源極端感測機制的汲入電流電路。Figure 3 shows a schematic block diagram of an integrated circuit incorporating the inrush current circuit of one of the source-source sensing mechanisms of the memory cells described in the present invention.

第4圖顯示此記憶陣列中的一選取記憶胞進行源極端感測之一方法流程圖。Figure 4 shows a flow chart of one of the methods for selecting source cells for source-end sensing in this memory array.

第5圖顯示汲入電流電路在此記憶陣列中的一選取記憶胞進行源極端感測時的一簡要示意圖。Figure 5 shows a simplified schematic diagram of the inrush current circuit for source-to-source sensing of a selected memory cell in the memory array.

第6圖顯示操作第5圖中所示的結構之時序圖。Fig. 6 is a timing chart showing the operation of the structure shown in Fig. 5.

第7圖顯示汲入電流電路第一實施例的示意圖。Figure 7 shows a schematic diagram of a first embodiment of a current sinking circuit.

第8圖顯示第7圖實施例中的汲入電流電路與此記憶陣列耦接的方塊示意圖。Figure 8 is a block diagram showing the intrusion current circuit of the embodiment of Figure 7 coupled to the memory array.

第9圖顯示汲入電流電路第二實施例的示意圖。Figure 9 shows a schematic diagram of a second embodiment of the inrush current circuit.

第10圖顯示汲入電流電路第三實施例的示意圖。Fig. 10 is a view showing a third embodiment of the inrush current circuit.

第11圖顯示汲入電流電路第四實施例的示意圖。Fig. 11 is a view showing a fourth embodiment of the inrush current circuit.

第12圖顯示汲入電流電路第五實施例的示意圖。Fig. 12 is a view showing a fifth embodiment of the inrush current circuit.

第13圖顯示汲入電流電路第六實施例的示意圖。Fig. 13 is a view showing a sixth embodiment of the inrush current circuit.

第14圖顯示汲入電流電路第七實施例的示意圖。Fig. 14 is a view showing a seventh embodiment of the inrush current circuit.

300‧‧‧積體電路300‧‧‧ integrated circuit

310‧‧‧汲入電流電路310‧‧‧Inrush current circuit

320‧‧‧記憶陣列320‧‧‧ memory array

324‧‧‧字元線324‧‧‧ character line

322、344‧‧‧列解碼器322, 344‧‧‧ column decoder

328‧‧‧位元線328‧‧‧ bit line

332‧‧‧資料匯流排332‧‧‧ data bus

326、342‧‧‧行解碼器326, 342‧‧ ‧ row decoder

330‧‧‧感測放大器/資料輸入結構330‧‧‧Sense Amplifier/Data Entry Structure

340‧‧‧參考陣列340‧‧‧reference array

343‧‧‧參考位元線343‧‧‧Reference bit line

345‧‧‧參考字元線345‧‧‧Reference word line

346、350‧‧‧匯流排346, 350‧‧ ‧ busbar

352‧‧‧資料輸入線352‧‧‧ data input line

354‧‧‧資料輸出線354‧‧‧ data output line

360‧‧‧其他電路360‧‧‧Other circuits

368‧‧‧調整偏壓供應電壓368‧‧‧Adjust the bias supply voltage

369‧‧‧控制器369‧‧‧ Controller

Claims

一種記憶裝置，包含：一記憶陣列，可自該記憶陣列中的一選取記憶胞提供一讀取電流至一資料線；一參考電流源，可提供一供判定該被選取記憶胞中之資料值的參考電流；一與該資料線耦接的汲入電流源，該汲入電流源可響應該參考電流的大小而自該資料線導入一汲入電流；以及一感測放大電路，其包含一耦接至該資料線的感測節點，且該感測放大電路響應於該讀取電流與該汲入電流之間的差值，而產生一用來指示儲存於該被選取記憶胞中的資料值之輸出信號。 A memory device comprising: a memory array, wherein a read current is supplied from a selected memory cell in the memory array to a data line; and a reference current source is provided to determine a data value in the selected memory cell a reference current; a sinking current source coupled to the data line, the inrush current source is capable of introducing a sink current from the data line in response to the magnitude of the reference current; and a sense amplifier circuit including a And a sensing node coupled to the data line, and the sensing and amplifying circuit generates a data for indicating the data stored in the selected memory cell in response to a difference between the read current and the inrush current The output signal of the value.

如申請專利範圍第1項所述之裝置，其中該感測放大電路包含一參考節點，該感測放大電路響應於該參考節點的電流或電壓與該感測節點的電流或電壓之間的一差值，而產生該輸出信號。 The device of claim 1, wherein the sense amplifier circuit comprises a reference node, the sense amplifier circuit is responsive to a current or voltage of the reference node and a current or voltage of the sense node The difference is generated to produce the output signal.

如申請專利範圍第2項所述之裝置，更包含電路用來設定該參考節點的一參考電壓，該參考電壓與該參考電流的大小無關。 The device of claim 2, further comprising a circuit for setting a reference voltage of the reference node, the reference voltage being independent of the magnitude of the reference current.

如申請專利範圍第3項所述之裝置，其中該用來設定該參考節點上的該參考電壓之電路包含一運算放大器，該運算放大器具有一第一輸入與地耦接且具有一第二輸入與該參考節點耦接。 The device of claim 3, wherein the circuit for setting the reference voltage on the reference node comprises an operational amplifier having a first input coupled to ground and having a second input Coupled with the reference node.

如申請專利範圍第1項所述之裝置，其中該參考電流源包含一參考胞。 The device of claim 1, wherein the reference current source comprises a reference cell.

如申請專利範圍第1項所述之裝置，其中該汲入電流源包括一電流鏡，其與該資料線及該參考電流源耦接，該電流鏡能接收該參考電流，且能響應於所接收之該參考電流大小而自該資料線導入該汲入電流。 The device of claim 1, wherein the inrush current source comprises a current mirror coupled to the data line and the reference current source, the current mirror capable of receiving the reference current and responsive to the The inrush current is introduced from the data line by the magnitude of the reference current received.

如申請專利範圍第6項所述之裝置，其中該電流鏡包含：一第一電晶體，與該參考電流源耦接，且安排為以接收該參考電流；以及一第二電晶體，與該資料線及該第一電晶體耦接，該第二電晶體能響應於該第一電晶體所接收之該參考電流大小而自該資料線導入該汲入電流。 The device of claim 6, wherein the current mirror comprises: a first transistor coupled to the reference current source and arranged to receive the reference current; and a second transistor, The data line is coupled to the first transistor, and the second transistor can introduce the inrush current from the data line in response to the magnitude of the reference current received by the first transistor.

如申請專利範圍第7項所述之裝置，其中各該第一電晶體及第二電晶體包含一控制終端及第一和第二導通終端，該第一電晶體的該控制終端與該第二電晶體的該控制終端耦接，該第一電晶體的該第一導通終端與該參考電流源耦接，且該第二電晶體的該第一導通終端與該資料線耦接。 The device of claim 7, wherein each of the first transistor and the second transistor comprises a control terminal and first and second conductive terminals, the control terminal of the first transistor and the second The first terminal of the first transistor is coupled to the reference current source, and the first conductive terminal of the second transistor is coupled to the data line.

如申請專利範圍第8項所述之裝置，其中該第一電晶體及第二電晶體的該些控制終端與一偏壓電壓耦接。 The device of claim 8, wherein the control terminals of the first transistor and the second transistor are coupled to a bias voltage.

如申請專利範圍第8項所述之裝置，其中該第一電晶體的該第一導通終端與該第一電晶體及第二電晶體的該些控制終端耦接。 The device of claim 8, wherein the first conductive terminal of the first transistor is coupled to the control terminals of the first transistor and the second transistor.

如申請專利範圍第8項所述之裝置，其中該第一電晶體的該第二導通終端與該第二電晶體的該第二導通終端耦接。 The device of claim 8, wherein the second conductive terminal of the first transistor is coupled to the second conductive terminal of the second transistor.

如申請專利範圍第8項所述之裝置，更包含第三電晶體及第四電晶體，各包含一控制終端及第一和第二導通終端，該第三電晶體的該控制終端與該第四電晶體的該控制終端耦接，該第三電晶體的該第一導通終端與該第一電晶體的該第二導通終端耦接，且該第四電晶體的該第一導通終端與該第二電晶體的該第二導通終端耦接。 The device of claim 8, further comprising a third transistor and a fourth transistor, each comprising a control terminal and first and second conductive terminals, the control terminal of the third transistor and the first The first conductive terminal of the fourth transistor is coupled to the second conductive terminal of the first transistor, and the first conductive terminal of the fourth transistor is coupled to the control terminal of the fourth transistor. The second conductive terminal of the second transistor is coupled.

如申請專利範圍第12項所述之裝置，其中：該第一電晶體及第二電晶體的該些控制終端與該第一電晶體的該第一導通終端耦接；以及該第三電晶體及第四電晶體的該些控制終端與該第三電晶體的該第一導通終端耦接。 The device of claim 12, wherein: the control terminals of the first transistor and the second transistor are coupled to the first conductive terminal of the first transistor; and the third transistor And the control terminals of the fourth transistor are coupled to the first conductive terminal of the third transistor.

如申請專利範圍第12項所述之裝置，其中：該第一電晶體及第二電晶體的該些控制終端與一參考電壓耦接；以及該第三電晶體及第四電晶體的該些控制終端與該第一電晶體的該第一導通終端耦接。 The device of claim 12, wherein: the control terminals of the first transistor and the second transistor are coupled to a reference voltage; and the third transistor and the fourth transistor The control terminal is coupled to the first conductive terminal of the first transistor.

一種感測一記憶胞的方法，該方法包含：施加一偏壓至該記憶胞以自該記憶胞誘發一讀取電流；自一參考電流源提供判定該記憶胞中之資料值的一參考電流；響應該參考電流的大小而自該讀取電流導入一汲入電流；提供該讀取電流與該汲入電流之間的一差值至一感測節點；以及根據該差值決定儲存於該記憶胞中的一資料值。 A method of sensing a memory cell, the method comprising: applying a bias voltage to the memory cell to induce a read current from the memory cell; providing a reference current for determining a data value in the memory cell from a reference current source Transmitting an input current from the read current in response to the magnitude of the reference current; providing a difference between the read current and the inrush current to a sensing node; and determining to store the difference according to the difference A data value in a memory cell.

如申請專利範圍第15項所述之方法，更包含：一根據該讀取電流與該汲入電流之間的該差值而設定該感測節點上之電壓的步驟，以及一偏壓一參考節點至一參考電壓的步驟，且其中該決定儲存於該記憶胞中的該資料值的步驟包含一根據該感測節點的該電壓與該參考節點的該參考電壓的一差值來決定所儲存的該資料值的步驟。 The method of claim 15, further comprising: a step of setting a voltage on the sensing node according to the difference between the read current and the inrush current, and a bias-reference a step of deriving a reference voltage, and wherein the step of determining the data value stored in the memory cell comprises determining a stored value based on a difference between the voltage of the sensing node and the reference voltage of the reference node The steps of the data value.

如申請專利範圍第16項所述之方法，其中該決定儲存於該記憶胞中的該資料值的步驟更包含：耦接該感測節點至一感測放大器的一第一輸入；耦接該參考節點至該感測放大器的一第二輸入；以及根據該第一輸入與該第二輸入之間的一電壓差值來產生該感測放大器的一輸出信號，該輸出信號指示儲存於該記憶胞中的該資料值。 The method of claim 16, wherein the step of determining the data value stored in the memory cell further comprises: coupling the sensing node to a first input of a sense amplifier; coupling the Referring a node to a second input of the sense amplifier; and generating an output signal of the sense amplifier according to a voltage difference between the first input and the second input, the output signal indicating being stored in the memory The value of this data in the cell.

如申請專利範圍第16項所述之方法，其中該參考電壓與該參考電流的大小無關。 The method of claim 16, wherein the reference voltage is independent of the magnitude of the reference current.

如申請專利範圍第15項所述之方法，其中該提供該參考電流的步驟包含施加一偏壓至一參考胞以自該參考胞中誘發該參考電流。 The method of claim 15, wherein the step of providing the reference current comprises applying a bias voltage to a reference cell to induce the reference current from the reference cell.

如申請專利範圍第15項所述之方法，其中該響應該參考電流的大小而自該讀取電流導入一汲入電流的步驟包含將一電流鏡與該參考電流源耦接，且該電流鏡可接收該參考電流，且可響應所接收之該參考電流大小而自該讀取電流導入該汲入電流。 The method of claim 15, wherein the step of introducing a current from the read current in response to the magnitude of the reference current comprises coupling a current mirror to the reference current source, and the current mirror The reference current can be received and the inrush current can be directed from the read current in response to the received reference current magnitude.