TWI441450B - Filler circuit cell - Google Patents
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Description
本發明是關於一種填充電路單元，尤指一種搭配接低與接高電路的填充電路單元。The invention relates to a filling circuit unit, in particular to a filling circuit unit with a low-connecting and high-connecting circuit.
在現今的數位積體電路設計流程中，為了符合高度自動化的需求，通常會採用標準單元庫(standard cell library)來完成所需的佈局設計。由於標準單元庫中已具備各種常用的單元型態(cell type)，例如AND、OR、NOT等基本邏輯閘電路，客戶可依據設計的架構套用標準單元庫中現有的單元型態來迅速拼出所需的設計。In today's digital integrated circuit design flow, in order to meet the requirements of high automation, the standard cell library is usually used to complete the required layout design. Since the standard cell library already has various commonly used cell types, such as AND, OR, NOT and other basic logic gate circuits, the customer can quickly spell out the existing cell types in the standard cell library according to the designed architecture. The design required.
為了符合製程的需求，每個設計單元在經由自動化工具拼湊出來時通常會呈現一矩型的形狀，使輸入/輸出端(I/O)可順利排列在完成的設計單元的周邊。在大部分情況下，由許多單元拼湊出的一個完整設計都無法呈現出完美的矩型，且會留有一些空隙。為了填補這些空隙，常見的作法是以填充電路單元(filler circuit cell)來填滿單元與單元之間或輸入/輸出端之間的間隙，以滿足設計規則檢查(design rule check)等設計上的需求。一般填充電路單元主要區分為空心圖案類型及電容類型等兩大類。其中空心圖案類的填充電路單元本身並無電路設計，其主要是用來填滿上述單元之間的空隙，使整個製程不至因圖案密度不完整而產生不一致(non-uniformity)。電容類型的填充電路單元則是提供一種穩定電壓的作用，使輸入/輸出端及單元之間不至因電源端的突波(switching surge)而影響整個運作。In order to meet the needs of the process, each design unit usually presents a rectangular shape when assembled by automated tools, so that the input/output (I/O) can be smoothly arranged around the completed design unit. In most cases, a complete design that is pieced together by many units will not present a perfect rectangular shape with some gaps. In order to fill these gaps, it is common practice to fill the gap between the cell and the cell or the input/output port with a filler circuit cell to satisfy the design rule check design. demand. Generally, the filling circuit unit is mainly divided into two categories: a hollow pattern type and a capacitor type. The filling circuit unit of the hollow pattern type has no circuit design itself, and is mainly used for filling the gap between the above units, so that the entire process is not caused by non-uniformity due to incomplete pattern density. The capacitor type filling circuit unit provides a stable voltage function, so that the input/output terminal and the unit do not affect the entire operation due to a switching surge at the power supply terminal.
請參照第1圖，第1圖為習知以MOS電晶體來實現電容類型填充電路單元之電路示意圖。如第1圖所示，習知填充電路單元主要包含一NMOS電晶體12、一PMOS電晶體14以及二電壓源(Vdd/Vss)分別連接至NMOS電晶體12與PMOS電晶體14。其中，NMOS電晶體12包含一閘極16、一源極18與一汲極18，且閘極16是直接連接至電壓源Vdd，而源極18與汲極18則是連接至另一電壓源Vss。PMOS電晶體14同樣一閘極20、一源極22與一汲極22，且閘極20是直接連接至電壓源Vss，而源極22與汲極22則是連接至電壓源Vdd。Please refer to FIG. 1 , which is a schematic diagram of a circuit for implementing a capacitor type filling circuit unit by using a MOS transistor. As shown in FIG. 1, the conventional filling circuit unit mainly includes an NMOS transistor 12, a PMOS transistor 14, and two voltage sources (Vdd/Vss) connected to the NMOS transistor 12 and the PMOS transistor 14, respectively. The NMOS transistor 12 includes a gate 16, a source 18 and a drain 18, and the gate 16 is directly connected to the voltage source Vdd, and the source 18 and the drain 18 are connected to another voltage source. Vss. The PMOS transistor 14 is also a gate 20, a source 22 and a drain 22, and the gate 20 is directly connected to the voltage source Vss, and the source 22 and the drain 22 are connected to the voltage source Vdd.
上述習知之填充電路單元雖可用來填滿單元之間的空隙，但由於填充電路單元中NMOS電晶體12的閘極16與PMOS電晶體14的閘極20是直接連接至電壓源Vss或Vdd，當一脈衝波形干擾(glitch)產生時，突發的偏壓會使集中的電流直接導入電晶體通道表面的閘介電層/反轉層並損毀整個電晶體。The above-mentioned conventional filling circuit unit can be used to fill the gap between the cells, but since the gate 16 of the NMOS transistor 12 and the gate 20 of the PMOS transistor 14 in the filling circuit unit are directly connected to the voltage source Vss or Vdd, When a pulsed glitch is generated, the sudden bias causes the concentrated current to be directed into the gate dielectric/inversion layer on the surface of the transistor channel and destroys the entire transistor.
因此本發明的主要目的是提供一種改良的填充電路單元以解決上述習知問題。It is therefore a primary object of the present invention to provide an improved fill circuit unit to solve the above-mentioned conventional problems.
本發明較佳實施例是揭露一種填充電路單元，包含有一去耦合電容、一接低(tie low)電路與一接高(tie high)電路。其中去耦合電容包含一第一N型金氧半導體(NMOS)電晶體與一第一P型金氧半導體(PMOS)電晶體，且第一NMOS電晶體之源極/汲極是連接一第二電源，而第一PMOS電晶體之源極/汲極是連接一第一電源。接低電路是設於第一PMOS電晶體及第二電源之間，其包含一第二NMOS電晶體與一第二PMOS電晶體，而接高電路則設於第一NMOS電晶體及該第一電源之間，其包含一第三NMOS電晶體與一第三PMOS電晶體。A preferred embodiment of the invention discloses a padding circuit unit including a decoupling capacitor, a tie low circuit and a tie high circuit. The decoupling capacitor comprises a first N-type metal oxide semiconductor (NMOS) transistor and a first P-type metal oxide semiconductor (PMOS) transistor, and the source/drain of the first NMOS transistor is connected to a second The power source, and the source/drain of the first PMOS transistor is connected to a first power source. The low circuit is disposed between the first PMOS transistor and the second power source, and includes a second NMOS transistor and a second PMOS transistor, and the high circuit is disposed on the first NMOS transistor and the first Between the power sources, it includes a third NMOS transistor and a third PMOS transistor.
本發明另一實施例是揭露一種填充電路單元，包含一去耦合電容以及一穩壓單元。其中去耦合電容包含一第一MOS電晶體，且第一MOS電晶體之源極/汲極係連接一第一電源。穩壓單元則包含一第二MOS電晶體與一第三MOS電晶體。Another embodiment of the present invention discloses a padding circuit unit including a decoupling capacitor and a voltage stabilizing unit. The decoupling capacitor comprises a first MOS transistor, and the source/drain of the first MOS transistor is connected to a first power source. The voltage stabilizing unit comprises a second MOS transistor and a third MOS transistor.
請參照第2圖，第2圖為本發明較佳實施例之一填充電路單元之電路示意圖。如圖中所示，本發明之填充電路單元主要包含一去耦合電容32以及一穩壓單元34連接去耦合電容32。其中，去耦合電容32包含一電晶體，例如一PMOS電晶體36。PMOS電晶體36包含一閘極38、一源極40與一汲極40。穩壓單元34則包含一NMOS電晶體42與一PMOS電晶體44。NMOS電晶體42包含一閘極46、一源極48與一汲極48，PMOS電晶體44包含一閘極50、一源極52與一汲極52。Please refer to FIG. 2, which is a circuit diagram of a filling circuit unit according to a preferred embodiment of the present invention. As shown in the figure, the filling circuit unit of the present invention mainly comprises a decoupling capacitor 32 and a voltage stabilizing unit 34 connected to the decoupling capacitor 32. The decoupling capacitor 32 includes a transistor, such as a PMOS transistor 36. The PMOS transistor 36 includes a gate 38, a source 40 and a drain 40. The voltage stabilizing unit 34 includes an NMOS transistor 42 and a PMOS transistor 44. The NMOS transistor 42 includes a gate 46, a source 48 and a drain 48. The PMOS transistor 44 includes a gate 50, a source 52 and a drain 52.
在本實施例中，穩壓單元34中PMOS電晶體44的一源極/汲極52是直接連接一電壓源Vdd，閘極50與另一源極/汲極52則是一起連接至NMOS電晶體42的閘極46。NMOS電晶體42的其中一個源極/汲極48是連接至去耦合電容32中PMOS電晶體36的閘極38，另一個源極/汲極48則是連接至另一電壓源Vss。PMOS電晶體36的兩個源極/汲極40均同時連接至電壓源Vdd。In this embodiment, a source/drain 52 of the PMOS transistor 44 in the voltage stabilizing unit 34 is directly connected to a voltage source Vdd, and the gate 50 and the other source/drain 52 are connected to the NMOS battery. Gate 46 of crystal 42. One of the source/drain 48 of the NMOS transistor 42 is connected to the gate 38 of the PMOS transistor 36 in the decoupling capacitor 32, and the other source/drain 48 is connected to another voltage source Vss. Both source/drain 40 of PMOS transistor 36 are simultaneously connected to voltage source Vdd.
需注意的是，本實施例的去耦合電容32雖以PMOS電晶體36為例，但不侷限於此，又可採用NMOS電晶體來實施，此設計也屬本發明所涵蓋的範圍。舉例來說，當去耦合電容32是由NMOS電晶體所組成時，第2圖所示之穩壓單元34中的NMOS電晶體42及PMOS電晶體44的位置則可互相調換，例如改由PMOS電晶體44的其中一個源極/汲極52來控制去耦合電容32的閘極38開關，而另一源極/汲極52則是連接至電壓源Vdd。此架構也屬本發明所涵蓋的範圍。It should be noted that the decoupling capacitor 32 of the present embodiment is exemplified by the PMOS transistor 36, but is not limited thereto, and may be implemented by using an NMOS transistor. This design is also within the scope of the present invention. For example, when the decoupling capacitor 32 is composed of an NMOS transistor, the positions of the NMOS transistor 42 and the PMOS transistor 44 in the voltage stabilizing unit 34 shown in FIG. 2 can be interchanged, for example, by PMOS. One of the source/drain 52 of the transistor 44 controls the gate 38 of the decoupling capacitor 32 to switch, while the other source/drain 52 is connected to the voltage source Vdd. This architecture is also within the scope of the present invention.
另外，依照上述設計，穩壓單元34主要設於兩個電壓源與去耦合電容32之間，其一端是直接連接至電壓源Vdd，另一端則是控制PMOS電晶體36的閘極38開關，並藉此提供填充電路單元一穩定的電壓。換句話說，由於PMOS電晶體36的閘極38並非直接電連接至電壓源Vdd，而是藉由穩壓單元34中的兩個電晶體達到一緩衝，因此當一脈衝干擾產生時，過高的偏壓不至直接衝擊到PMOS電晶體36的閘介電層/反轉層而使PMOS電晶體36能避免受到損害。In addition, according to the above design, the voltage stabilizing unit 34 is mainly disposed between the two voltage sources and the decoupling capacitor 32, one end of which is directly connected to the voltage source Vdd, and the other end is a gate 38 switch for controlling the PMOS transistor 36. And thereby providing a stable voltage for the filling circuit unit. In other words, since the gate 38 of the PMOS transistor 36 is not directly electrically connected to the voltage source Vdd, but is buffered by the two transistors in the voltage stabilizing unit 34, when a pulse interference occurs, it is too high. The bias voltage does not directly impinge on the gate dielectric/inversion layer of PMOS transistor 36 to protect PMOS transistor 36 from damage.
請參照第3圖，第3圖為本發明另一實施例之一填充電路單元之電路示意圖。如圖中所示，填充電路單元主要包含一去耦合電容62、二電壓源Vss與Vdd、以及一接低(tielow)電路64與一接高(tie high)電路66分別設於電壓源與去耦合電容62之間。其中，去耦合電容62包含一PMOS電晶體68與一NMOS電晶體70，PMOS電晶體68包含一閘極72、一源極74與一汲極74，NMOS電晶體70包含一閘極76、一源極78與一汲極78。Please refer to FIG. 3, which is a circuit diagram of a filling circuit unit according to another embodiment of the present invention. As shown in the figure, the filling circuit unit mainly comprises a decoupling capacitor 62, two voltage sources Vss and Vdd, and a tielow circuit 64 and a tie high circuit 66 respectively disposed at the voltage source and Between the coupling capacitors 62. The decoupling capacitor 62 includes a PMOS transistor 68 and an NMOS transistor 70. The PMOS transistor 68 includes a gate 72, a source 74 and a drain 74. The NMOS transistor 70 includes a gate 76 and a gate. Source 78 and a drain 78.
接低電路64包含一NMOS電晶體80與一PMOS電晶體82。其中NMOS電晶體80包含一閘極84、一源極86與一汲極86，PMOS電晶體82包含一閘極88、一源極90與一汲極90。在本實施例中，接低電路64中PMOS電晶體82的其中一個源極/汲極90是直接電連接至電壓源Vdd，PMOS電晶體82的閘極88與另一源極/汲極90則是一同連接至NMOS電晶體80的閘極84並控制NMOS電晶體80的開關。NMOS電晶體80的其中一個源極/汲極86是直接連接至去耦合電容62中的PMOS電晶體68閘極72，使PMOS電晶體68永遠處於開啟的狀態，NMOS電晶體80的另一源極/汲極86則是連接另一電壓源Vss。整體而言，接低電路64主要設在兩個電壓源與去耦合電容62中之PMOS電晶體68之間並作為一緩衝電路，使PMOS電晶體68的閘極72電位維持在一低電位的狀態且不至在脈衝產生時直接受到脈衝的衝擊而毀損。The low circuit 64 includes an NMOS transistor 80 and a PMOS transistor 82. The NMOS transistor 80 includes a gate 84, a source 86 and a drain 86. The PMOS transistor 82 includes a gate 88, a source 90 and a drain 90. In the present embodiment, one of the source/drain electrodes 90 of the PMOS transistor 82 in the low circuit 64 is directly electrically connected to the voltage source Vdd, the gate 88 of the PMOS transistor 82 and the other source/drain 90 Then, it is connected to the gate 84 of the NMOS transistor 80 and controls the switching of the NMOS transistor 80. One of the source/drain electrodes 86 of the NMOS transistor 80 is directly connected to the PMOS transistor 68 gate 72 in the decoupling capacitor 62, leaving the PMOS transistor 68 in an on state, another source of the NMOS transistor 80. The pole/drain 86 is connected to another voltage source Vss. In general, the low circuit 64 is mainly disposed between the two voltage sources and the PMOS transistor 68 of the decoupling capacitor 62 and serves as a buffer circuit to maintain the potential of the gate 72 of the PMOS transistor 68 at a low potential. The state is not damaged by the impact of the pulse directly when the pulse is generated.
接高電路66同樣包含一NMOS電晶體92與一PMOS電晶體94，其中NMOS電晶體92包含一閘極96、一源極98與一汲極98，而PMOS電晶體94包含一閘極100、一源極102與一汲極102。類似於接低電路64的連接方式，接高電路66中NMOS電晶體92的其中一個源極/汲極98是直接連接至電壓源Vss，閘極96與另一源極/汲極98則是一起連接至PMOS電晶體94的閘極100並控制PMOS電晶體94的開啟。PMOS電晶體94的其中一個源極/汲極102是直接連接至去耦合電容62中的NMOS電晶體70之閘極76，使NMOS電晶體70永遠處於開啟的狀態，而另一源極/汲極102則是連接另一電壓源Vdd。整體而言，接高電路66是設在兩個電壓源與去耦合電容62中之NMOS電晶體70之間並作為一緩衝電路，使NMOS電晶體70的閘極76維持在一高電位的狀態且不至直接受到脈衝的衝擊而毀損。The splicing circuit 66 also includes an NMOS transistor 92 and a PMOS transistor 94. The NMOS transistor 92 includes a gate 96, a source 98 and a drain 98, and the PMOS transistor 94 includes a gate 100. A source 102 and a drain 102. Similar to the connection mode of the low circuit 64, one of the source/drain electrodes 98 of the NMOS transistor 92 in the high circuit 66 is directly connected to the voltage source Vss, and the gate 96 and the other source/drain 98 are Together, it is connected to the gate 100 of the PMOS transistor 94 and controls the turn-on of the PMOS transistor 94. One of the source/drain 102 of the PMOS transistor 94 is directly connected to the gate 76 of the NMOS transistor 70 in the decoupling capacitor 62, so that the NMOS transistor 70 is always on, and the other source/汲The pole 102 is connected to another voltage source Vdd. In general, the junction circuit 66 is disposed between the two voltage sources and the NMOS transistor 70 of the decoupling capacitor 62 and acts as a buffer circuit to maintain the gate 76 of the NMOS transistor 70 at a high potential. It is not damaged directly by the impact of the pulse.
請參照第4圖，第4圖為第3圖中填充電路單元之結構示意圖。如第4圖所示，填充電路單元包含一組去耦合電容62，一接低電路64連接去耦合電容62的PMOS電晶體68以及一接高電路66連接去耦合電容62中的NMOS電晶體70。其中，由PMOS電晶體68所組成的去耦合電容62是設於一N型井104中，其包含：一閘極72、一源極74與一汲極74設於閘極72兩側的N型井104中、一N+摻雜區106設於源極/汲極74鄰近的N型井104中作為N型井104的電接觸端、以及複數個淺溝隔108離隔開N+摻雜區106、PMOS電晶體68以及相鄰的電晶體。PMOS電晶體68的源極74與汲極74與N+摻雜區106(即N型井104)均同時連接至電壓源Vdd。Please refer to FIG. 4, which is a schematic structural view of the filling circuit unit in FIG. As shown in FIG. 4, the padding circuit unit includes a set of decoupling capacitors 62, a PMOS transistor 68 connected to the decoupling capacitor 62 connected to the low circuit 64, and a NMOS transistor 70 connected to the decoupling capacitor 62. . The decoupling capacitor 62 composed of the PMOS transistor 68 is disposed in an N-type well 104, and includes: a gate 72, a source 74, and a drain 74 disposed on both sides of the gate 72. In the well 104, an N+ doped region 106 is disposed in the N-well 104 adjacent to the source/drain 74 as an electrical contact of the N-well 104, and a plurality of shallow trenches 108 are spaced apart from the N+ doped region 106. , PMOS transistor 68 and adjacent transistors. The source 74 of the PMOS transistor 68 and the drain 74 and the N+ doped region 106 (i.e., the N-well 104) are both connected to the voltage source Vdd.
接低電路64包含一NMOS電晶體80與一PMOS電晶體82。其中NMOS電晶體80是設於一P型基底110中，其包含：一閘極84、一源極86與一汲極86設於閘極84兩側的P型基底110內、一P+摻雜區112另設於源極/汲極86鄰近的P型基底110中作為P型基底110的電接觸端、以及複數個淺溝隔離108隔開P+摻雜區112、NMOS電晶體80以及相鄰的其他電晶體與摻雜區。NMOS電晶體80的其中一個源極/汲極86與P+摻雜區112(即P型基底110)是直接連接至一電壓源VSS，另一源極/汲極86則是連接至PMOS電晶體68的閘極72。The low circuit 64 includes an NMOS transistor 80 and a PMOS transistor 82. The NMOS transistor 80 is disposed in a P-type substrate 110 and includes a gate 84, a source 86 and a drain 86 disposed in the P-type substrate 110 on both sides of the gate 84, and a P+ doping. The region 112 is further disposed in the P-type substrate 110 adjacent to the source/drain 86 as an electrical contact end of the P-type substrate 110, and a plurality of shallow trench isolations 108 separate the P+ doped region 112, the NMOS transistor 80, and adjacent Other transistors and doped regions. One of the source/drain electrodes 86 and the P+ doping region 112 (ie, the P-type substrate 110) of the NMOS transistor 80 is directly connected to a voltage source VSS, and the other source/drain 86 is connected to the PMOS transistor. Gate 72 of 68.
接低電路64的PMOS電晶體82是設於一N型井114中，其包含：一閘極88、一源極90與一汲極90設於閘極88兩側的N型井114中、一N+摻雜區116另設於源極/汲極90鄰近的N型井114中作為N型井114的電接觸端、以及複數個淺溝隔離108隔開N+摻雜區116、PMOS電晶體82以及相鄰的電晶體與摻雜區。PMOS電晶體82的其中一個源極/汲極90與N+摻雜區116(即N型井114)一同連接至電壓源Vdd，閘極88與另一源極/汲極90則是連接至NMOS電晶體80的閘極84。The PMOS transistor 82 of the low circuit 64 is disposed in an N-type well 114, and includes a gate 88, a source 90 and a drain 90 disposed in the N-well 114 on both sides of the gate 88. An N+ doped region 116 is further disposed in the N-well 114 adjacent to the source/drain 90 as an electrical contact of the N-well 114, and a plurality of shallow trench isolations 108 separate the N+ doped region 116, PMOS transistor 82 and adjacent transistors and doped regions. One of the source/drain electrodes 90 of the PMOS transistor 82 is connected to the voltage source Vdd together with the N+ doping region 116 (ie, the N-well 114), and the gate 88 and the other source/drain 90 are connected to the NMOS. Gate 84 of transistor 80.
由NMOS電晶體70所組成的去耦合電容62是設於一P型基底110中，其包含：一閘極76、一源極78與一汲極78設於閘極76兩側的P型基底110中、一P+摻雜區118設於源極/汲極78鄰近的P型基底110中作為P型基底110的電接觸端、以及複數個淺溝隔離108隔開P+摻雜區118、NMOS電晶體70以及相鄰的電晶體與摻雜區。NMOS電晶體70的源極/汲極78與P+摻雜區118(即P型基底)一同連接至一電壓源Vss。The decoupling capacitor 62 composed of the NMOS transistor 70 is disposed in a P-type substrate 110 and includes a gate 76, a source 78 and a drain 78 disposed on both sides of the gate 76. 110, a P+ doped region 118 is disposed in the P-type substrate 110 adjacent to the source/drain 78 as an electrical contact end of the P-type substrate 110, and a plurality of shallow trench isolations 108 separate the P+ doped region 118, NMOS The transistor 70 and adjacent transistors and doped regions. The source/drain 78 of the NMOS transistor 70 is coupled to a voltage source Vss along with a P+ doped region 118 (i.e., a P-type substrate).
接高電路66包含一NMOS電晶體92與一PMOS電晶體94。其中PMOS電晶體94是設於一N型井120中，其包含：一閘極100、一源極102與一汲極102設於閘極100兩側的N型井120中、一N+摻雜區122另設於源極/汲極102鄰近的N型井120中作為N型井120的電接觸端、以及複數個淺溝隔離108隔開N+摻雜區122、PMOS電晶體94以及相鄰的電晶體與摻雜區。PMOS電晶體94的其中一個源極/汲極102與N+摻雜區122(即N型井120)是直接連接至電壓源Vdd，另一源極/汲極102則是連接至NMOS電晶體70的閘極76。The junction circuit 66 includes an NMOS transistor 92 and a PMOS transistor 94. The PMOS transistor 94 is disposed in an N-type well 120, and includes a gate 100, a source 102, and a drain 102 disposed in the N-well 120 on both sides of the gate 100, and an N+ doping. The region 122 is further disposed in the N-well 120 adjacent to the source/drain 102 as an electrical contact of the N-well 120, and a plurality of shallow trench isolations 108 separate the N+ doped region 122, the PMOS transistor 94, and adjacent The transistor and the doped region. One of the source/drain 102 and the N+ doping region 122 (ie, the N-well 120) of the PMOS transistor 94 is directly connected to the voltage source Vdd, and the other source/drain 102 is connected to the NMOS transistor 70. The gate 76.
接高電路66的NMOS電晶體92是設於一P型基底110中，其包含：一閘極96、一源極98與一汲極98設於閘極96兩側的P型基底110內、一P+摻雜區124另設於源極/汲極98鄰近的P型基底110中作為P型基底110的電接觸終、以及複數個淺溝隔離108隔開P+摻雜區124、NMOS電晶體92以及相鄰的電晶體。NMOS電晶體92的其中一個源極/汲極98與P+摻雜區124(即P型基底110)是直接連接至電壓源Vss，閘極96與另一源極/汲極98則是連接至PMOS電晶體94的閘極100。The NMOS transistor 92 of the grounding circuit 66 is disposed in a P-type substrate 110, and includes a gate 96, a source 98 and a drain 98 disposed in the P-type substrate 110 on both sides of the gate 96. A P+ doped region 124 is further disposed in the P-type substrate 110 adjacent to the source/drain 98 as the electrical contact end of the P-type substrate 110, and a plurality of shallow trench isolations 108 separate the P+ doped region 124, the NMOS transistor 92 and adjacent transistors. One of the source/drain electrodes 98 and the P+ doping region 124 (i.e., the P-type substrate 110) of the NMOS transistor 92 is directly connected to the voltage source Vss, and the gate 96 and the other source/drain 98 are connected to Gate 100 of PMOS transistor 94.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
12．．．NMOS電晶體12. . . NMOS transistor
14．．．PMOS電晶體14. . . PMOS transistor
16．．．閘極16. . . Gate
18．．．源極/汲極18. . . Source/bungee
20．．．閘極20. . . Gate
22．．．源極/汲極twenty two. . . Source/bungee
32．．．去耦合電容32. . . Decoupling capacitor
34．．．穩壓單元34. . . Voltage regulator unit
36．．．PMOS電晶體36. . . PMOS transistor
38．．．閘極38. . . Gate
40．．．源極/汲極40. . . Source/bungee
42．．．NMOS電晶體42. . . NMOS transistor
44．．．PMOS電晶體44. . . PMOS transistor
46．．．閘極46. . . Gate
48．．．源極/汲極48. . . Source/bungee
50．．．閘極50. . . Gate
52．．．源極/汲極52. . . Source/bungee
62．．．去耦合電容62. . . Decoupling capacitor
64．．．接低電路64. . . Connect low circuit
66．．．接高電路66. . . High circuit
68．．．PMOS電晶體68. . . PMOS transistor
70．．．NMOS電晶體70. . . NMOS transistor
72．．．閘極72. . . Gate
74．．．源極/汲極74. . . Source/bungee
76．．．閘極76. . . Gate
78．．．源極/汲極78. . . Source/bungee
80．．．NMOS電晶體80. . . NMOS transistor
82．．．PMOS電晶體82. . . PMOS transistor
84．．．閘極84. . . Gate
86．．．源極/汲極86. . . Source/bungee
88．．．閘極88. . . Gate
90．．．源極/汲極90. . . Source/bungee
92．．．NMOS電晶體92. . . NMOS transistor
94．．．PMOS電晶體94. . . PMOS transistor
96．．．閘極96. . . Gate
98．．．源極/汲極98. . . Source/bungee
100．．．閘極100. . . Gate
102．．．源極/汲極102. . . Source/bungee
104．．．N型井104. . . N-type well
106．．．N+摻雜區106. . . N+ doped region
108．．．淺溝隔離108. . . Shallow trench isolation
110．．．P型基底110. . . P-type substrate
112．．．P+摻雜區112. . . P+ doped region
114．．．N型井114. . . N-type well
116．．．N+摻雜區116. . . N+ doped region
118．．．P+摻雜區118. . . P+ doped region
120．．．N型井120. . . N-type well
122．．．N+摻雜區122. . . N+ doped region
124．．．P+摻雜區124. . . P+ doped region
第1圖為習知一MOS電晶體電容類型的填充電路單元之電路示意圖。FIG. 1 is a schematic circuit diagram of a conventional MOS transistor capacitor type filling circuit unit.
第2圖為本發明較佳實施例之一填充電路單元之電路示意圖。2 is a circuit diagram of a filling circuit unit according to a preferred embodiment of the present invention.
第3圖為本發明另一實施例之一填充電路單元之電路示意圖。FIG. 3 is a schematic circuit diagram of a filling circuit unit according to another embodiment of the present invention.
第4圖為第3圖中填充電路單元之結構示意圖。Fig. 4 is a schematic view showing the structure of a filling circuit unit in Fig. 3.
62．．．去耦合電容62. . . Decoupling capacitor
64．．．接低電路64. . . Connect low circuit
66．．．接高電路66. . . High circuit
68．．．PMOS電晶體68. . . PMOS transistor
70．．．NMOS電晶體70. . . NMOS transistor
72．．．閘極72. . . Gate
74．．．源極/汲極74. . . Source/bungee
76．．．閘極76. . . Gate
78．．．源極/汲極78. . . Source/bungee
80．．．NMOS電晶體80. . . NMOS transistor
82．．．PMOS電晶體82. . . PMOS transistor
84．．．閘極84. . . Gate
86．．．源極/汲極86. . . Source/bungee
88．．．閘極88. . . Gate
90．．．源極/汲極90. . . Source/bungee
92．．．NMOS電晶體92. . . NMOS transistor
94．．．PMOS電晶體94. . . PMOS transistor
96．．．閘極96. . . Gate
98．．．源極/汲極98. . . Source/bungee
100．．．閘極100. . . Gate
102．．．源極/汲極102. . . Source/bungee
Claims (20)
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|---|---|---|---|
| TW98103485A TWI441450B (en) | 2009-02-04 | 2009-02-04 | Filler circuit cell |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98103485A TWI441450B (en) | 2009-02-04 | 2009-02-04 | Filler circuit cell |
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| Publication Number | Publication Date |
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| TW201031114A TW201031114A (en) | 2010-08-16 |
| TWI441450B true TWI441450B (en) | 2014-06-11 |
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| TW98103485A TWI441450B (en) | 2009-02-04 | 2009-02-04 | Filler circuit cell |
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