TWI441007B - Capacitor-free low drop-out voltage regulator and voltage regulating method thereof - Google Patents
Capacitor-free low drop-out voltage regulator and voltage regulating method thereof Download PDFInfo
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本發明是有關於一種穩壓器及其穩壓方法，且特別是有關於一種無需外掛穩壓電容之低壓降穩壓器及其穩壓方法。The invention relates to a voltage regulator and a voltage stabilization method thereof, and particularly relates to a low-dropout voltage regulator without an external voltage-stabilizing capacitor and a voltage stabilization method thereof.
為提供電子產品多功能的訴求，現今的電子裝置中常利用電源轉換器來做為產生操作電源的媒介。而在切換式電源轉換器中，需要一個高耐壓且大電流驅動能力的功率電晶體，並藉由功率電晶體的切換動作來進行電源轉換。由於功率電晶體通常具有大尺寸的特性，因此也相對具有較大的閘極寄生電容。因此，在習知的功率電晶體的閘極驅動器中，常利用所謂的低壓降穩壓器(Low Drop-Out Regulator,LDO Regulator)來供應足夠的電流以驅動功率電晶體。In order to provide the versatility of electronic products, power converters are often used in today's electronic devices as a medium for generating operating power. In the switching power converter, a power transistor with high withstand voltage and high current driving capability is required, and power conversion is performed by switching operation of the power transistor. Since power transistors generally have large size characteristics, they also have relatively large gate parasitic capacitance. Therefore, in the gate driver of a conventional power transistor, a so-called Low Drop-Out Regulator (LDO Regulator) is often used to supply a sufficient current to drive the power transistor.
圖1繪示為傳統低壓降穩壓器的示意圖。請參照圖1，傳統的低壓降穩壓器100包括一誤差放大器102、一功率電晶體MP、一分壓電阻RD1、一分壓電阻RD2以及一穩壓電容Cc。另外，低壓降穩壓器100的輸出端OUT耦接一負載104。其中穩壓電容Cc為一uF量級的電容，其耦接於低壓降穩壓器100的輸出端OUT與接地電壓之間。功率電晶體MP耦接於一輸入電壓與低壓降穩壓器100的輸出端OUT之間，功率電晶體MP的閘極則耦接誤差放大器102的輸出端。分壓電阻RD1、RD2串接於低壓降穩壓器100的輸出端OUT與接地電壓之間。另外，誤差放大器102的兩輸入端分別耦接一參考電壓Vref以及分壓電阻RD1、RD2的共同接點之間。Figure 1 is a schematic diagram of a conventional low dropout regulator. Referring to FIG. 1, the conventional low-dropout regulator 100 includes an error amplifier 102, a power transistor MP, a voltage dividing resistor RD1, a voltage dividing resistor RD2, and a voltage stabilizing capacitor Cc. In addition, the output terminal OUT of the low dropout regulator 100 is coupled to a load 104. The voltage stabilizing capacitor Cc is a capacitor of the order of uF, which is coupled between the output terminal OUT of the low dropout regulator 100 and the ground voltage. The power transistor MP is coupled between an input voltage and the output terminal OUT of the low-dropout regulator 100, and the gate of the power transistor MP is coupled to the output of the error amplifier 102. The voltage dividing resistors RD1, RD2 are connected in series between the output terminal OUT of the low dropout regulator 100 and the ground voltage. In addition, the two input ends of the error amplifier 102 are respectively coupled between a reference voltage Vref and a common contact of the voltage dividing resistors RD1, RD2.
誤差放大器102依據參考電壓Vref以及分壓電阻RD1、RD2所產生的分壓電壓Vf產生一誤差信號ER1以控制功率電晶體MP的導通狀態，進而藉由功率電晶體MP的導通狀態調整低壓降穩壓器100的輸出電壓Vout。在傳統的低壓降穩壓器100中，穩壓電容Cc雖可穩定輸出電壓，並提供相位補償的功能，但其具有增加成本以及必須多出一腳位以外接電容。近年來為了將穩壓器整合進晶片中，發展出無需穩壓電容的低壓降穩壓器。少了穩壓電容，雖然可藉由誤差放大器的架構來解決相位的問題，但是輸出電壓穩定性明顯不足，由於誤差放大器的頻寬有限，在快速且大量的負載電流變化下，誤差放大器無法及時作出修正，輸出電壓的時間暫態變化量與安定時間仍有很大的改善空間。The error amplifier 102 generates an error signal ER1 according to the reference voltage Vref and the divided voltage Vf generated by the voltage dividing resistors RD1 and RD2 to control the conduction state of the power transistor MP, thereby adjusting the low voltage stability by the conduction state of the power transistor MP. The output voltage Vout of the voltage regulator 100. In the conventional low-dropout regulator 100, the voltage stabilizing capacitor Cc stabilizes the output voltage and provides phase compensation, but it has an increased cost and must have an external capacitor. In recent years, in order to integrate the regulator into the chip, a low-dropout regulator that does not require a stabilizing capacitor has been developed. The voltage regulator capacitor is reduced. Although the phase error can be solved by the architecture of the error amplifier, the output voltage stability is obviously insufficient. Due to the limited bandwidth of the error amplifier, the error amplifier cannot be timely under the rapid and large load current variation. With the correction, there is still much room for improvement in the time transient change and the settling time of the output voltage.
本發明提供一種無需外掛穩壓電容之低壓降穩壓器及其穩壓方法，可改善輸出電壓的穩定性。The invention provides a low-dropout voltage regulator without an external voltage stabilizing capacitor and a voltage stabilizing method thereof, which can improve the stability of the output voltage.
本發明提出一種無需外掛穩壓電容之低壓降穩壓器(以下簡稱為低壓降穩壓器)，用以將一輸入電壓轉換為一輸出電壓，低壓降穩壓器包括一誤差放大器、一功率電晶體、一分壓單元以及一快速補償模組。其中誤差放大器依據一第一參考電壓以及一回授電壓產生一控制電壓。一功率電晶體之閘極耦接誤差放大器的輸出端，功率電晶體之源極耦接輸入電壓，依據控制電壓於汲極產生輸出電壓。分壓單元耦接於功率電晶體的汲極與接地電壓之間，分壓輸出電壓以產生回授電壓。快速補償模組耦接於功率電晶體之閘極與低壓降穩壓器的輸出端之間，反應輸出電壓之向下突波或向上突波而加強或降低功率電晶體的驅動輸出電流之能力。The invention provides a low-dropout regulator (hereinafter referred to as a low-dropout regulator) that does not require an external voltage stabilizing capacitor for converting an input voltage into an output voltage. The low-dropout regulator includes an error amplifier and a power. A transistor, a voltage dividing unit and a fast compensation module. The error amplifier generates a control voltage according to a first reference voltage and a feedback voltage. The gate of a power transistor is coupled to the output of the error amplifier, the source of the power transistor is coupled to the input voltage, and the output voltage is generated at the drain according to the control voltage. The voltage dividing unit is coupled between the drain of the power transistor and the ground voltage, and divides the output voltage to generate a feedback voltage. The fast compensation module is coupled between the gate of the power transistor and the output of the low-dropout regulator, and reacts to the downward glitch or upward glitch of the output voltage to enhance or reduce the driving output current of the power transistor. .
在本發明之一實施例中，上述之快速補償模組包括一向下突波補償單元以及一向上突波補償單元。其中向下突波補償單元耦接於功率電晶體之閘極與汲極之間，反應輸出電壓之向下突波而加強導通功率電晶體。向上突波補償單元耦接於功率電晶體之汲極與接地電壓之間，反應輸出電壓之向上突波而將功率電晶體之汲極耦接至接地電壓。In an embodiment of the invention, the fast compensation module includes a downward glitch compensation unit and an upward glitch compensation unit. The downward glitch compensation unit is coupled between the gate and the drain of the power transistor, and reacts to the downward spur of the output voltage to strengthen the power transistor. The upward surge compensation unit is coupled between the drain of the power transistor and the ground voltage, and reacts the upward surge of the output voltage to couple the drain of the power transistor to the ground voltage.
在本發明之一實施例中，上述之向下突波補償單元包括一第一放大器以及一第一高通濾波器。其中第一放大器之輸出端耦接功率電晶體之閘極。第一高通濾波器耦接於第一放大器之輸入端與功率電晶體之汲極之間。In an embodiment of the invention, the downward glitch compensation unit includes a first amplifier and a first high pass filter. The output of the first amplifier is coupled to the gate of the power transistor. The first high pass filter is coupled between the input of the first amplifier and the drain of the power transistor.
在本發明之一實施例中，上述之向下突波補償單元包括一第一放大器、一第一高通濾波器。其中第一電阻之一端耦接一電源電壓。第一電晶體之汲極耦接第一電阻的另一端，第一電晶體之閘極耦接一偏壓電壓。第二電阻耦接於第一電晶體之源極與接地電壓之間。第一電容，耦接於第一電晶體之源極與輸入電壓之間。In an embodiment of the invention, the downward glitch compensation unit includes a first amplifier and a first high pass filter. One of the first resistors is coupled to a power supply voltage. The first transistor is coupled to the other end of the first resistor, and the gate of the first transistor is coupled to a bias voltage. The second resistor is coupled between the source of the first transistor and the ground voltage. The first capacitor is coupled between the source of the first transistor and the input voltage.
在本發明之一實施例中，上述之向上突波補償單元包括一第一開關電晶體、一第二放大器以及一第二高通濾波器。其中第一開關電晶體耦接於功率電晶體之汲極與接地電壓之間。第二放大器之輸出端耦接第一開關電晶體之閘極。第二高通濾波器耦接於第二放大器之輸入端與功率電晶體之汲極之間。In an embodiment of the invention, the upward glancing compensation unit includes a first switching transistor, a second amplifier, and a second high pass filter. The first switching transistor is coupled between the drain of the power transistor and the ground voltage. The output of the second amplifier is coupled to the gate of the first switching transistor. The second high pass filter is coupled between the input of the second amplifier and the drain of the power transistor.
在本發明之一實施例中，上述之向上突波補償單元包括一第三電阻、一第二電晶體、一第四電阻以及一第二電容。其中第三電阻之一端耦接接地電壓。第二電晶體之汲極耦接第三電阻的另一端，第一電晶體之閘極耦接一偏壓電壓。第四電阻耦接於第二電晶體之源極與接地電壓之間。第二電容，耦接於第二電晶體之源極與輸入電壓之間。In an embodiment of the invention, the upward surge compensation unit includes a third resistor, a second transistor, a fourth resistor, and a second capacitor. One of the third resistors is coupled to the ground voltage. The drain of the second transistor is coupled to the other end of the third resistor, and the gate of the first transistor is coupled to a bias voltage. The fourth resistor is coupled between the source of the second transistor and the ground voltage. The second capacitor is coupled between the source of the second transistor and the input voltage.
本發明亦提出一種無需外掛穩壓電容之低壓降穩壓器(以下簡稱為低壓降穩壓器)的穩壓方法，其中低壓降穩壓器包括一功率電晶體與一開關電晶體，功率電晶體耦接於一輸入電壓與低壓降穩壓器的輸出端之間，開關電晶體耦接於低壓降穩壓器的輸出端與一接地電壓之間。低壓降穩壓器的穩壓方法包括下列步驟。偵測低壓降穩壓器的一輸出電壓是否出現向下突波或向上突波。當輸出電壓出現向下突波時，透過一第一快速回授路徑加強導通功率電晶體，以拉高輸出電壓。當輸出電壓出現向上突波時，透過一第二快速回授路徑開啟開關電晶體，以拉低輸出電壓。The invention also provides a voltage stabilization method for a low-dropout regulator (hereinafter referred to as a low-dropout regulator) that does not require an external voltage-stabilizing capacitor, wherein the low-dropout regulator includes a power transistor and a switching transistor, and the power is electrically The crystal is coupled between an input voltage and an output of the low-dropout regulator, and the switching transistor is coupled between the output of the low-dropout regulator and a ground voltage. The voltage regulation method of the low dropout regulator includes the following steps. Detects whether an output voltage of the low-dropout regulator has a downward glitch or an upward glitch. When the output voltage has a downward spur, the power transistor is boosted through a first fast feedback path to pull up the output voltage. When an upward glitch occurs in the output voltage, the switching transistor is turned on through a second fast feedback path to pull down the output voltage.
在本發明之一實施例中，若輸出電壓未出現向下突波與向上突波時，依據輸出電壓與一參考電壓調整功率電晶體的導通狀態。In an embodiment of the invention, if the output voltage does not show a downward glitch and an upward glitch, the conduction state of the power transistor is adjusted according to the output voltage and a reference voltage.
基於上述，本發明藉由偵測並反應輸出電壓的向下突波或向上突波致能第一快速回授路徑或第二快速回授路徑，以快速地對輸出電壓進行補償，而增加輸出電壓的穩定性。Based on the above, the present invention enables the first fast feedback path or the second fast feedback path by detecting and reacting the downward glitch or the upward spur of the output voltage to quickly compensate the output voltage and increase the output. Voltage stability.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖2繪示為本發明一實施例之無需外掛穩壓電容之低壓降穩壓器的示意圖。請參照圖2，無需外掛穩壓電容之低壓降穩壓器200(以下簡稱為低壓降穩壓器200)用以將一輸入電壓Vin轉換為一輸出電壓Vout，其包括一誤差放大器202、一功率電晶體M1、一分壓單元204以及一快速補償模組206。其中誤差放大器202的兩輸入端分別耦接一參考電壓Vref以及一回授電壓Vfb，誤差放大器202的輸出端耦接至功率電晶體M1的閘極，其中參考電壓Vref可例如為能隙參考電壓。功率電晶體M1的源極與汲極分別耦接至輸入電壓Vin與低壓降穩壓器200的輸出端。快速補償模組206耦接於功率電晶體M1之閘極與低壓降穩壓器200的輸出端之間。在本實施例中，功率電晶體M1以一PMOS電晶體來實現，然並不以此為限，其亦可例如為一NMOS電晶體。分壓單元204則耦接功率電晶體M1的汲極與接地電壓之間，以分壓低壓降穩壓器200輸出端的輸出電壓Vout而產生回授電壓Vfb。2 is a schematic diagram of a low dropout voltage regulator that does not require an external voltage stabilizing capacitor according to an embodiment of the invention. Referring to FIG. 2, a low dropout regulator 200 (hereinafter referred to as a low dropout regulator 200) that does not require an external voltage stabilizing capacitor is used to convert an input voltage Vin into an output voltage Vout, which includes an error amplifier 202, a The power transistor M1, a voltage dividing unit 204, and a fast compensation module 206. The two input terminals of the error amplifier 202 are respectively coupled to a reference voltage Vref and a feedback voltage Vfb. The output of the error amplifier 202 is coupled to the gate of the power transistor M1, wherein the reference voltage Vref can be, for example, a bandgap reference voltage. . The source and the drain of the power transistor M1 are respectively coupled to the input voltage Vin and the output of the low dropout regulator 200. The fast compensation module 206 is coupled between the gate of the power transistor M1 and the output of the low dropout regulator 200. In this embodiment, the power transistor M1 is implemented by a PMOS transistor. However, it is not limited thereto, and may be, for example, an NMOS transistor. The voltage dividing unit 204 is coupled between the drain of the power transistor M1 and the ground voltage to generate a feedback voltage Vfb by dividing the output voltage Vout of the output of the low voltage drop regulator 200.
如圖2所示，當低壓降穩壓器200的輸出電壓Vout未出現向上突波或向下突波的情形時，誤差放大器202依據參考電壓Vref以及分壓單元204所產生的回授電壓Vfb產生一控制電壓Vcon以控制功率電晶體M1的導通狀態，進而於低壓降穩壓器200的輸出端輸出穩定的輸出電壓Vout。As shown in FIG. 2, when the output voltage Vout of the low dropout regulator 200 does not show an upward glitch or a downward glitch, the error amplifier 202 is based on the reference voltage Vref and the feedback voltage Vfb generated by the voltage dividing unit 204. A control voltage Vcon is generated to control the on state of the power transistor M1, and a stable output voltage Vout is outputted at the output of the low dropout regulator 200.
當低壓降穩壓器200輸出端上的負載208將於瞬間抽取大量的電流或突然停止抽取電流時，將使得低壓降穩壓器200的輸出端出現向上突波或向下突波，而使輸出電壓Vout急速上升或下降。此時，快速補償模組206便反應輸出電壓Vout的急速上升或下降來加強導通功率電晶體M1或將低壓降穩壓器200的輸出端耦接至接地電壓，以快速地拉高或降低低壓降穩壓器200的輸出電壓Vout，進而快速地穩定低壓降穩壓器200的輸出電壓Vout。When the load 208 at the output of the low dropout regulator 200 will draw a large amount of current instantaneously or abruptly stop drawing current, the output of the low dropout regulator 200 will have an upward glitch or a downward spur, The output voltage Vout rises or falls rapidly. At this time, the fast compensation module 206 reacts to the rapid rise or fall of the output voltage Vout to strengthen the conduction power transistor M1 or couple the output terminal of the low-dropout regulator 200 to the ground voltage to quickly pull up or lower the low voltage. The output voltage Vout of the regulator 200 is lowered, thereby rapidly stabilizing the output voltage Vout of the low dropout regulator 200.
也就是說，功率電晶體M1在正常操作時(亦即輸出電壓Vout未出現向上突波或向下突波的情形時)也是導通的，而當輸出電壓Vout出現向上突波或向下突波時，快速補償模組206進行補償時的閘極電壓會快速增大或縮減低壓降穩壓器所輸出的驅動電流，以有效快速地穩定低壓降穩壓器200的輸出電壓Vout。That is to say, the power transistor M1 is also turned on during normal operation (that is, when the output voltage Vout does not show an upward glitch or a downward glitch), and when the output voltage Vout appears an upward glitch or a downward glitch When the fast compensation module 206 performs compensation, the gate voltage rapidly increases or decreases the driving current output by the low-dropout regulator to effectively and quickly stabilize the output voltage Vout of the low-dropout regulator 200.
圖3繪示為本發明另一實施例之無需外掛穩壓電容之低壓降穩壓器的示意圖。請參照圖3，進一步來說，上述之分壓單元204可例如以本實施例之電阻RA與電阻RB來實現，電阻RA與電阻RB串接於無需外掛穩壓電容之低壓降穩壓器300(以下簡稱為低壓降穩壓器300)的輸出端與接地電壓之間，用以對輸出電壓Vout進行電阻分壓，而產生回授電壓Vfb至誤差放大器202的輸入端。另外，快速補償模組206可包括一向下突波補償單元302以及一向上突波補償單元304。其中向下突波補償單元302耦接於功率電晶體M1之閘極與汲極之間，向上突波補償單元304則耦接於功率電晶體M1之汲極與接地電壓之間。向下突波補償單元302用以反應輸出電壓Vout的向下突波而加強導通功率電晶體M1，以拉高輸出電壓Vout。向上突波補償單元304則反應輸出電壓Vout的向上突波而將功率電晶體M1之汲極耦接至接地電壓，以拉低輸出電壓Vout。3 is a schematic diagram of a low-dropout voltage regulator that does not require an external voltage stabilizing capacitor according to another embodiment of the present invention. Referring to FIG. 3, further, the voltage dividing unit 204 can be implemented, for example, by the resistor RA and the resistor RB of the embodiment. The resistor RA and the resistor RB are connected in series to the low-dropout regulator 300 that does not require an external voltage stabilizing capacitor. (hereinafter referred to as low-dropout regulator 300) between the output terminal and the ground voltage for voltage division of the output voltage Vout, and generating a feedback voltage Vfb to the input terminal of the error amplifier 202. In addition, the fast compensation module 206 can include a downward glitch compensation unit 302 and an upward glitch compensation unit 304. The downward glitch compensation unit 302 is coupled between the gate and the drain of the power transistor M1, and the up rush compensation unit 304 is coupled between the drain of the power transistor M1 and the ground voltage. The downward surge compensation unit 302 is configured to react the downward surge of the output voltage Vout to strengthen the power transistor M1 to pull up the output voltage Vout. The upward surge compensation unit 304 reacts the upper spur of the output voltage Vout to couple the drain of the power transistor M1 to the ground voltage to pull down the output voltage Vout.
在本實施例中，低壓降穩壓器300的向下突波補償單元302包括一第一放大器302A以及一第一高通濾波器302B。其中第一放大器302A之輸出端耦接功率電晶體M1之閘極，第一高通濾波器302B耦接於第一放大器302A之輸入端與功率電晶體M1的汲極之間。In the present embodiment, the downsampling compensation unit 302 of the low dropout regulator 300 includes a first amplifier 302A and a first high pass filter 302B. The output of the first amplifier 302A is coupled to the gate of the power transistor M1. The first high-pass filter 302B is coupled between the input terminal of the first amplifier 302A and the drain of the power transistor M1.
另外，向上突波補償單元304則包括一開關電晶體M2、一第二放大器304A以及一第二高通濾波器304B。其中開關電晶體M2耦接於功率電晶體M1的汲極與接地電壓之間。第二放大器304A之輸出端耦接開關電晶體M2的閘極。第二高通濾波器304B則耦接於第二放大器304A的輸入端與功率電晶體M1的汲極之間。其中第一放大器302A以及第二放大器304A可例如以N型電晶體與P型電晶體所組成的共閘極放大器來實施，然不以此為限。In addition, the upward surge compensation unit 304 includes a switching transistor M2, a second amplifier 304A, and a second high pass filter 304B. The switching transistor M2 is coupled between the drain of the power transistor M1 and the ground voltage. The output of the second amplifier 304A is coupled to the gate of the switching transistor M2. The second high pass filter 304B is coupled between the input terminal of the second amplifier 304A and the drain of the power transistor M1. The first amplifier 302A and the second amplifier 304A can be implemented, for example, by a common gate amplifier composed of an N-type transistor and a P-type transistor, but not limited thereto.
在本實施例中，上述的第一快速回授路徑為第一放大器302A與第一高通濾波器302B所構成，而第二快速回授路徑則為第二放大器304A與第二高通濾波器304B所構成。當低壓降穩壓器300的輸出電壓Vout發生高頻的變動時，低壓降穩壓器300的主要回授路徑將為第一快速回授路徑與第二快速回授路徑。其中當輸出電壓Vout出現向下突波情形時，輸出電壓Vout的負脈衝電壓將被第一放大器302A放大，進而加強導通功率電晶體M1，使功率電晶體M1得以提供補償電流IC1至負載208，而減緩輸出電壓Vout下降的情形。類似地，當輸出電壓Vout出現向上突波情形時，輸出電壓Vout的正脈衝電壓將被第二放大器304A放大，進而導通開關電晶體M2，使多餘的補償電流IC1可透過開關電晶體M2流向接地電壓，而減緩輸出電壓Vout上升的情形。In this embodiment, the first fast feedback path is formed by the first amplifier 302A and the first high-pass filter 302B, and the second fast feedback path is the second amplifier 304A and the second high-pass filter 304B. Composition. When the output voltage Vout of the low dropout regulator 300 fluctuates at a high frequency, the main feedback path of the low dropout regulator 300 will be the first fast feedback path and the second fast feedback path. When the output voltage Vout is in a downward spur condition, the negative pulse voltage of the output voltage Vout is amplified by the first amplifier 302A, thereby enhancing the conduction power transistor M1, so that the power transistor M1 can provide the compensation current IC1 to the load 208. And slow down the output voltage Vout. Similarly, when the output voltage Vout appears in an upward spur condition, the positive pulse voltage of the output voltage Vout will be amplified by the second amplifier 304A, thereby turning on the switching transistor M2, so that the excess compensation current IC1 can flow to the ground through the switching transistor M2. Voltage, which slows down the output voltage Vout.
另外，當低壓降穩壓器300的輸出電壓Vout為低頻的變動時，低壓降穩壓器300的主要回授路徑將為誤差放大器202與分壓單元204所構成。誤差放大器202將低壓降穩壓器300的輸出電壓Vout修正至正確的輸出準位，而不經由第一放大器302A、第一高通濾波器302B、第二放大器304A與第二高通濾波器304B所構成的第一、二快速回授路徑進行回授補償。In addition, when the output voltage Vout of the low dropout regulator 300 is a low frequency variation, the main feedback path of the low dropout regulator 300 will be the error amplifier 202 and the voltage dividing unit 204. The error amplifier 202 corrects the output voltage Vout of the low dropout regulator 300 to the correct output level without being formed by the first amplifier 302A, the first high pass filter 302B, the second amplifier 304A, and the second high pass filter 304B. The first and second fast feedback paths are used for feedback compensation.
如上所述，利用第一放大器302A、第一高通濾波器302B、第二放大器304A、第二高通濾波器304B以及開關電晶體M2來實現快速補償模組206，可使快速補償模組206在輸出電壓Vout未出現向上突波或向下突波時不被致能，而不增加額外的功率消耗。此外，藉由第一放大器302A與第二放大器304A可放大輸出電壓Vout的振幅變動，在輸出電壓Vout產生微小的變化時即進行電壓補償，因而可提高電壓補償的靈敏度，大幅地提升電壓補償的效率。As described above, the fast compensation module 206 is implemented by using the first amplifier 302A, the first high pass filter 302B, the second amplifier 304A, the second high pass filter 304B, and the switching transistor M2, so that the fast compensation module 206 can be outputted. The voltage Vout is not enabled when there is no upward or downward spurt, and no additional power consumption is added. Further, the amplitude fluctuation of the output voltage Vout can be amplified by the first amplifier 302A and the second amplifier 304A, and the voltage compensation can be performed when the output voltage Vout is slightly changed. Therefore, the sensitivity of the voltage compensation can be improved, and the voltage compensation can be greatly improved. effectiveness.
詳細來說，第一快速回授路徑與第二快速回授路徑的實施方式可分別如圖4A與圖4B所示。在圖4A中，第一放大器302A包括一第一電晶體Q1以及一第一電阻R1，而第一高通濾波器302B包括一第二電阻R2以及一第一電容C1。其中第一電阻R1耦接於一電源電壓VDD與功率電晶體M1的閘極之間。第一電晶體Q1的閘極耦接一偏壓電壓Vb，其汲極則耦接功率電晶體M1的閘極。第二電阻R2耦接於第一電晶體Q1之源極與接地電壓之間。第一電容C1則耦接於第一電晶體Q1之源極與輸出電壓Vout之間。In detail, the implementation manners of the first fast feedback path and the second fast feedback path may be as shown in FIG. 4A and FIG. 4B, respectively. In FIG. 4A, the first amplifier 302A includes a first transistor Q1 and a first resistor R1, and the first high-pass filter 302B includes a second resistor R2 and a first capacitor C1. The first resistor R1 is coupled between a power supply voltage VDD and a gate of the power transistor M1. The gate of the first transistor Q1 is coupled to a bias voltage Vb, and the drain of the first transistor Q1 is coupled to the gate of the power transistor M1. The second resistor R2 is coupled between the source of the first transistor Q1 and the ground voltage. The first capacitor C1 is coupled between the source of the first transistor Q1 and the output voltage Vout.
在本實施例中，第一電晶體Q1以及第一電阻R1為共閘極放大器的結構，當輸出電壓Vout出現向下突波的情形時，下降的輸出電壓Vout將透過第一高通濾波器302B拉低第一電晶體Q1的源極電位，進而使第一電晶體Q1導通，而產生一大電流I1。此時功率電晶體M1的閘極電壓VM1如下列所示：In this embodiment, the first transistor Q1 and the first resistor R1 are structures of a common gate amplifier. When the output voltage Vout appears to be a downward surge, the falling output voltage Vout will pass through the first high pass filter 302B. Pulling down the source potential of the first transistor Q1, thereby turning on the first transistor Q1, and generating a large current I1. At this time, the gate voltage VM1 of the power transistor M1 is as follows:
VM1=VDD-I1×R1 (1)VM1=VDD-I1×R1 (1)
由式(1)可知，電流I1流經第一電阻R1將使得功率電晶體M1的閘極電壓VM1被拉低。如此便能加強導通功率電晶體M1，對負載208灌注補償電流IC1，進而拉高輸出電壓Vout。As can be seen from equation (1), the flow of current I1 through the first resistor R1 causes the gate voltage VM1 of the power transistor M1 to be pulled low. In this way, the power transistor M1 can be reinforced, and the load current 208 is filled with the compensation current IC1, thereby increasing the output voltage Vout.
另外，在圖4B中，第二放大器302B包括一第二電晶體Q2以及一第四電阻R4，而第二高通濾波器304B包括一第三電阻R3以及一第二電容C2。其中第四電阻R4耦接於接地電壓與開關電晶體M2的閘極之間。第二電晶體Q2的閘極耦接偏壓電壓Vb，其汲極則耦接開關電晶體M2的閘極。第三電阻R3耦接於第一電晶體Q1之源極與接地電壓之間。第二電容C2則耦接於第一電晶體Q1之源極與輸出電壓Vout之間。In addition, in FIG. 4B, the second amplifier 302B includes a second transistor Q2 and a fourth resistor R4, and the second high-pass filter 304B includes a third resistor R3 and a second capacitor C2. The fourth resistor R4 is coupled between the ground voltage and the gate of the switching transistor M2. The gate of the second transistor Q2 is coupled to the bias voltage Vb, and the drain of the second transistor Q2 is coupled to the gate of the switching transistor M2. The third resistor R3 is coupled between the source of the first transistor Q1 and the ground voltage. The second capacitor C2 is coupled between the source of the first transistor Q1 and the output voltage Vout.
類似地，在本實施例中，第二電晶體Q2以及第四電阻R4亦為共閘極放大器的結構，當輸出電壓Vout出現向上突波的情形時，上升的輸出電壓Vout將透過高通濾波器304B拉高第二電晶體Q2的源極電位，進而使第二電晶體Q2導通，而產生一大電流I2。此時開關電晶體M2的閘極電壓VM2如下列所示：Similarly, in the embodiment, the second transistor Q2 and the fourth resistor R4 are also structures of a common gate amplifier. When the output voltage Vout is in an upward glitch, the rising output voltage Vout will pass through the high-pass filter. 304B pulls up the source potential of the second transistor Q2, thereby turning on the second transistor Q2 to generate a large current I2. At this time, the gate voltage VM2 of the switching transistor M2 is as follows:
VM2=I2×R4 (2)VM2=I2×R4 (2)
由式(2)可知，電流I2流經第四電阻R4將使得開關電晶體M2的閘極電壓VM2被拉高。如此便能開啟開關電晶體M2，而使多餘的補償電流IC1可透過開關電晶體M2流向接地電壓，進而拉低輸出電壓Vout。As can be seen from equation (2), the flow of current I2 through the fourth resistor R4 causes the gate voltage VM2 of the switching transistor M2 to be pulled high. In this way, the switching transistor M2 can be turned on, so that the excess compensation current IC1 can flow to the grounding voltage through the switching transistor M2, thereby pulling down the output voltage Vout.
圖5繪示為本發明一實施例之無需外掛穩壓電容之低壓降穩壓器的穩壓方法流程圖。請參照圖5，歸納上述無需外掛穩壓電容之低壓降穩壓器(以下簡稱為低壓降穩壓器)的穩壓方法可包括下列步驟。首先，偵測低壓降穩壓器的輸出電壓是否出現向下突波或向上突波。(步驟S502)。若輸出電壓出現向下突波的情形時，透過一第一快速回授路徑加強導通功率電晶體，以拉高輸出電壓(步驟S504)。而若輸出電壓出現向上突波的情形時，則透過一第二快速回授路徑開啟開關電晶體，以拉低輸出電壓。(步驟S506)。另外，若低壓降穩壓器的輸出電壓既無出現向下突波也無出現向上突波的情形時，則依據輸出電壓以及一參考電壓控制功率電晶體的導通狀態，以將輸出電壓調整至正確的電壓準位。(步驟S508)。FIG. 5 is a flow chart of a voltage stabilizing method for a low dropout regulator that does not require an external voltage stabilizing capacitor according to an embodiment of the invention. Referring to FIG. 5, the voltage stabilizing method of the low-dropout regulator (hereinafter referred to as a low-dropout regulator) that does not require an external voltage stabilizing capacitor may be included in the following steps. First, detect if the output voltage of the low-dropout regulator has a downward glitch or an upward glitch. (Step S502). If the output voltage has a downward glitch, the power transistor is boosted through a first fast feedback path to pull up the output voltage (step S504). If the output voltage has an upward glitch, the switching transistor is turned on through a second fast feedback path to pull down the output voltage. (Step S506). In addition, if the output voltage of the low-dropout regulator has neither a downward glitch nor an upward glitch, the power-on state of the power transistor is controlled according to the output voltage and a reference voltage to adjust the output voltage to The correct voltage level. (Step S508).
綜上所述，本發明藉由快速補償模組偵測輸出電壓的向下突波與向上突波，並反應輸出電壓的向下突波或向上突波致能第一快速回授路徑或第二快速回授路徑，以將輸出電壓拉高或降低，避免輸出電壓變化持續擴大，並縮短穩定輸出電壓的時間。In summary, the present invention detects the downward glitch and the upward glitch of the output voltage by the fast compensation module, and reacts to the downward glitch or the upward spur of the output voltage to enable the first fast feedback path or the first A fast feedback path to pull the output voltage high or low, to avoid the output voltage change continues to expand, and to shorten the time to stabilize the output voltage.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100．．．傳統低壓降穩壓器100. . . Traditional low dropout regulator
200、300．．．無需外掛穩壓電容之低壓降穩壓器200, 300. . . Low-dropout regulator without external voltage regulator
102、202．．．誤差放大器102, 202. . . Error amplifier
204．．．分壓單元204. . . Partition unit
206．．．快速補償模組206. . . Fast compensation module
104、208．．．負載104, 208. . . load
302．．．向下突波補償單元302. . . Downward surge compensation unit
304．．．向上突波補償單元304. . . Upward surge compensation unit
302A、304A．．．放大器302A, 304A. . . Amplifier
302B、304B．．．第一高通濾波器302B, 304B. . . First high pass filter
ER1．．．誤差信號ER1. . . Error signal
M1、MP‧‧‧功率電晶體M1, MP‧‧‧ power transistor
M2‧‧‧開關電晶體M2‧‧‧Switching transistor
OUT‧‧‧輸出端OUT‧‧‧ output
Vin‧‧‧輸入電壓Vin‧‧‧Input voltage
Vout‧‧‧輸出電壓Vout‧‧‧ output voltage
Vref‧‧‧參考電壓Vref‧‧‧reference voltage
Vfb‧‧‧回授電壓Vfb‧‧‧ feedback voltage
Vf‧‧‧分壓電壓Vf‧‧ ‧ voltage divider
Vcon‧‧‧控制電壓Vcon‧‧‧ control voltage
R1~R4、RA、RB、RD1、RD2‧‧‧電阻R1~R4, RA, RB, RD1, RD2‧‧‧ resistance
Q1‧‧‧電晶體Q1‧‧‧Optoelectronics
C1~C2‧‧‧電容C1~C2‧‧‧ capacitor
Cc‧‧‧穩壓電容Cc‧‧‧Stabilized capacitor
IC1‧‧‧補償電流IC1‧‧‧Compensation current
VDD‧‧‧電源電壓VDD‧‧‧Power supply voltage
Vb‧‧‧偏壓電壓Vb‧‧‧ bias voltage
I1、I2‧‧‧電流I1, I2‧‧‧ current
S502~S508‧‧‧低壓降穩壓器的穩壓方法步驟S502~S508‧‧‧Steps for voltage regulation of low-dropout regulator
圖1繪示為本發明一實施例之傳統低壓降穩壓器的示意圖。1 is a schematic diagram of a conventional low dropout regulator according to an embodiment of the invention.
圖2繪示為本發明一實施例之無需外掛穩壓電容之低壓降穩壓器的示意圖。2 is a schematic diagram of a low dropout voltage regulator that does not require an external voltage stabilizing capacitor according to an embodiment of the invention.
圖3繪示為本發明另一實施例之無需外掛穩壓電容之低壓降穩壓器的示意圖。3 is a schematic diagram of a low-dropout voltage regulator that does not require an external voltage stabilizing capacitor according to another embodiment of the present invention.
圖4A繪示為本發明一實施例之第一放大器與第一高通濾波器的電路圖。4A is a circuit diagram of a first amplifier and a first high pass filter according to an embodiment of the invention.
圖4B繪示為本發明一實施例之第二放大器與第二高通濾波器的電路圖。4B is a circuit diagram of a second amplifier and a second high pass filter according to an embodiment of the invention.
圖5繪示為本發明一實施例之無需外掛穩壓電容之低壓降穩壓器的穩壓方法流程圖。FIG. 5 is a flow chart of a voltage stabilizing method for a low dropout regulator that does not require an external voltage stabilizing capacitor according to an embodiment of the invention.
200．．．無須外掛穩壓電容之低壓降穩壓器200. . . Low-dropout regulator without external voltage regulator
202．．．誤差放大器202. . . Error amplifier
204．．．分壓單元204. . . Partition unit
206．．．快速補償模組206. . . Fast compensation module
208．．．負載208. . . load
M1．．．功率電晶體M1. . . Power transistor
Vin．．．輸入電壓Vin. . . Input voltage
Vout．．．輸出電壓Vout. . . The output voltage
Vref．．．參考電壓Vref. . . Reference voltage
Vfb．．．回授電壓Vfb. . . Feedback voltage
Vcon．．．控制電壓Vcon. . . Control voltage
Claims (6)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100123649A TWI441007B (en) | 2011-07-05 | 2011-07-05 | Capacitor-free low drop-out voltage regulator and voltage regulating method thereof |
| CN2011101951068A CN102868299A (en) | 2011-07-05 | 2011-07-07 | Low-voltage-drop voltage stabilizer without externally-hung voltage stabilizing capacitor and voltage stabilizing method thereof |
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| TW100123649A TWI441007B (en) | 2011-07-05 | 2011-07-05 | Capacitor-free low drop-out voltage regulator and voltage regulating method thereof |
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| TW201303545A TW201303545A (en) | 2013-01-16 |
| TWI441007B true TWI441007B (en) | 2014-06-11 |
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| TW100123649A TWI441007B (en) | 2011-07-05 | 2011-07-05 | Capacitor-free low drop-out voltage regulator and voltage regulating method thereof |
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| TW (1) | TWI441007B (en) |
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| KR101800560B1 (en) * | 2013-09-26 | 2017-11-22 | 인텔 코포레이션 | Low dropout voltage regulator integrated with digital power gate driver |
| CN104615181B (en) | 2013-11-05 | 2016-06-22 | 智原科技股份有限公司 | Voltage regulator arrangement and correlation technique |
| JP6244194B2 (en) * | 2013-12-13 | 2017-12-06 | エスアイアイ・セミコンダクタ株式会社 | Voltage regulator |
| CN104393760B (en) * | 2014-11-27 | 2016-11-09 | 中国兵器工业集团第二一四研究所苏州研发中心 | The positive negative output low voltage difference with short-circuit protection function adjusts circuit |
| TWI539437B (en) * | 2015-01-08 | 2016-06-21 | 矽創電子股份有限公司 | Voltage converting device and related display system |
| CN104503531A (en) * | 2015-01-14 | 2015-04-08 | 北京华强智连微电子有限责任公司 | Low dropout regulator circuit of transient response enhancing on-chip capacitor |
| CN104898752B (en) * | 2015-06-26 | 2017-03-15 | 中国兵器工业集团第二一四研究所苏州研发中心 | A kind of fast transient response without capacitor type LDO |
| CN106200741B (en) * | 2016-07-27 | 2017-12-22 | 豪威科技(上海)有限公司 | The heavy load circuit of electric current and low pressure difference linear voltage regulator |
| CN108616260B (en) * | 2018-04-02 | 2022-05-10 | 广州慧智微电子股份有限公司 | Power supply circuit of power amplifier |
| CN109149962B (en) * | 2018-09-03 | 2020-09-08 | 中国商用飞机有限责任公司北京民用飞机技术研究中心 | Method and device for compensating stability of direct current power supply system based on voltage reference signal |
| TWI799129B (en) * | 2022-02-09 | 2023-04-11 | 瑞昱半導體股份有限公司 | Voltage regulation integrated circuit |
| CN115437445B (en) * | 2022-10-20 | 2023-12-15 | 群联电子股份有限公司 | Voltage stabilizing circuit module, memory storage device and voltage control method |
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| JP2003243516A (en) * | 2002-02-14 | 2003-08-29 | Toshiba Corp | Semiconductor integrated circuit device |
| US7502719B2 (en) * | 2007-01-25 | 2009-03-10 | Monolithic Power Systems, Inc. | Method and apparatus for overshoot and undershoot errors correction in analog low dropout regulators |
| CN101339443B (en) * | 2008-08-08 | 2011-02-16 | 武汉大学 | Broad output current scope low pressure difference linear manostat |
| CN101369161A (en) * | 2008-10-14 | 2009-02-18 | 复旦大学 | Low-voltage difference linear voltage stabilizer without off-chip compensation capacitor |
| CN101419479B (en) * | 2008-12-10 | 2012-05-23 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
| KR101530085B1 (en) * | 2008-12-24 | 2015-06-18 | 테세라 어드밴스드 테크놀로지스, 인크. | Low-Dropout Voltage regulator, and operating method of the regulator |
| CN101727120B (en) * | 2009-11-26 | 2011-09-07 | 四川和芯微电子股份有限公司 | Linear voltage regulator circuit for rapidly responding to load change without plug-in capacitor |
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Also Published As
| Publication number | Publication date |
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| TW201303545A (en) | 2013-01-16 |
| CN102868299A (en) | 2013-01-09 |
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