TWI431666B - A method of forming a semiconductor structure - Google Patents
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本發明係關於包括半導體結晶材料之製作或結構，且特別是關於可形成於包括一半導體結晶材料之一平坦化表面上的經改善之磊晶成長情形或結構。This invention relates to the fabrication or construction of semiconductor crystalline materials, and in particular to improved epitaxial growth conditions or structures that can be formed on a planarized surface comprising a semiconductor crystalline material.
利用貫穿差排(threading dislocation)而進行基板圖案化之相關技術仍受到幾何學的限制，即結晶物內的差排行為(dislocation)並不會停止。當藉由圖案化基板以形成更小之成長區域時將使得一自由邊(free edge)更接近另一自由邊，因而可降低貫穿差排的密度。於過去技術中，基板的圖案化以及磊晶側向成長(epitaxial lateral overgrowth，ELO)等技術的結合已證明了可大量地降低氮化鍺裝置(gallium nitride device)內的缺陷密度(defect densities)，從而製作至出壽命更長之雷射二極體(laser diodes)。上述製程大體消除了於磊晶側向成長區域內的缺陷於但高度地劣化了剩餘之晶種窗(seed window)，因而需要微影與磊晶等步驟之重作(repetition)以消除所有缺陷。於一相似方法中，懸空磊晶(pendeo-epitaxy)技術大體消除了於鄰近基板之磊晶區域內的所有缺陷，但其仍需要一次的微影步驟與兩次的磊晶成長步驟。再者，上述兩項技術需要更為提升的的氮化鍺側向成長速度，其於目前所有之異質磊晶系統(heteroepitaxial systems)中尚未得到驗證。The related art of patterning a substrate by threading dislocation is still limited by geometry, that is, the dislocation behavior within the crystal does not stop. When the substrate is patterned to form a smaller growth region, a free edge is brought closer to the other free edge, thereby reducing the density of the through-difference. In the prior art, the combination of substrate patterning and epitaxial lateral overgrowth (ELO) techniques has demonstrated that the defect densities in the gallium nitride device can be greatly reduced. In order to produce laser diodes with a longer life. The above process substantially eliminates defects in the lateral growth region of the epitaxial crystal but highly degrades the remaining seed window, thus requiring a repetition of steps such as lithography and epitaxy to eliminate all defects. . In a similar method, the pendeo-epitaxy technique substantially eliminates all defects in the epitaxial regions of adjacent substrates, but it still requires one lithography step and two epitaxial growth steps. Furthermore, the above two techniques require a much higher lateral growth rate of tantalum nitride, which has not been verified in all current heteroepitaxial systems.
稱為”磊晶頸縮”之另一已知技術則為Langdo等人揭示於”High Quality Ge on Si by Epitaxial Necking”,Applied Physics Letters,Vol. 76,No. 25,April 2000.之文獻所相關的位於矽上之鍺的異質結構(Ge-on-Si heterostructure)之製作中。上述方法提供了藉由利用選擇性磊晶成長(selective epitaxial growth)與缺陷結晶學(defect crystallography)的結合之一簡化情形，以使得缺陷僅抵達位於圖案化罩幕內之開口的側壁，而上述方法不會依靠側向成長速率的增加。更明確地，於(111)<110>鑽石立方滑移系統(diamond cubic slip system)中，錯配差排(misfit dislocations)係沿著(100)成長平面之<110>方向而延伸，而貫穿片段(threading segments)係自(111)平面並依照<110>方向而產生。於位於(111)平面上沿著<110>方向之貫穿片段於相對於下方的矽(100)基板表面之45度角而延伸。因此，當位於圖案化罩幕層內的孔洞之深寬比(aspect ratio)大於1時，貫穿片段會為罩幕層的側壁所阻擋，使得直接形成於矽之上形成低缺陷之上方鍺突出物(Ge nodules)。磊晶頸縮的重要限制之一係為其所施行之區域的尺寸。一般來說，如下文中的更深入討論中所述，於尺寸內之側向尺寸需要相對較小，以使得上述差排可於側壁處終止。Another known technique known as "eductive necking" is disclosed by Langdo et al. in "High Quality Ge on Si by Epitaxial Necking", Applied Physics Letters, Vol. 76, No. 25, April 2000. Related to the creation of a heterostructure (Ge-on-Si heterostructure) located on the top of the raft. The above method provides a simplification by utilizing one of a combination of selective epitaxial growth and defect crystallography such that the defect only reaches the sidewall of the opening in the patterned mask, The method does not rely on an increase in the rate of lateral growth. More specifically, in the (111) <110> diamond cubic slip system, the misfit dislocations extend along the <110> direction of the (100) growth plane. The threading segments are generated from the (111) plane and in accordance with the <110> direction. The through-segment along the <110> direction on the (111) plane extends at an angle of 45 degrees with respect to the underlying 矽 (100) substrate surface. Therefore, when the aspect ratio of the holes in the patterned mask layer is greater than 1, the through segments are blocked by the sidewalls of the mask layer, so that the upper defects are formed directly on the top of the crucible to form a low defect. (Ge nodules). One of the important limitations of epitaxial necking is the size of the area in which it is applied. In general, as described in more in-depth discussion below, the lateral dimensions within the dimensions need to be relatively small so that the above-described difference can be terminated at the sidewalls.
如此，便需要一種用於製作半導體異質結構(semiconductor heterostructure)之多功能且有效的方法方法，其可抑制位於不同晶格不匹配材料系統(lattic-mismatched materials systems)中的差排缺陷。且亦需要一種利用具有較低差排缺陷程度之整合型晶格不匹配材料之半導體裝置，以改善其功能性與表現。Thus, there is a need for a versatile and efficient method for fabricating semiconductor heterostructures that inhibits poor row defects in different lattice-mismatched materials systems. There is also a need for a semiconductor device that utilizes an integrated lattice mismatch material having a lower level of defect defects to improve its functionality and performance.
有鑑於此，本發明提供了用於藉由採用深寬比捕捉(aspect ration trapping，ART)與磊晶側向成長(epitaxial lateral overgrowth，ELO)等技術於包括如晶格不匹配材料之基板上所形成如太陽能電池之裝置的方法與結構。In view of this, the present invention provides for use on a substrate including a lattice mismatched material by using techniques such as aspect trajection (ART) and epitaxial lateral overgrowth (ELO). A method and structure for forming a device such as a solar cell.
依據本發明之一實施例，本發明提供了一種半導體結構之形成方法。該方法包括形成一第一開口於設置於包括一第一半導體材料之一基板上之一罩幕層內。於該第一開口內形成包括晶格不匹配於該第一半導體材料之一第二半導體材料之一第一膜層。該第一膜層具有足夠延伸至高於該罩幕層之一頂面之一厚度。形成包括該第二半導體材料之一第二膜層於該第一膜層之上以及至少該罩幕層之一部之上。該第一膜層之垂直成長速率係高於該第一膜層之一側向成長速率，而該第二膜層之一側向成長速率係高於該第二膜層之一垂直成長速率。In accordance with an embodiment of the present invention, the present invention provides a method of forming a semiconductor structure. The method includes forming a first opening in a mask layer disposed on a substrate comprising a first semiconductor material. Forming a first film layer including one of the second semiconductor materials having a lattice mismatch with one of the first semiconductor materials is formed in the first opening. The first film layer has a thickness sufficient to extend above one of the top faces of the mask layer. Forming a second film layer comprising one of the second semiconductor materials over the first film layer and at least over a portion of the mask layer. The vertical growth rate of the first film layer is higher than a lateral growth rate of the first film layer, and one of the second film layers has a lateral growth rate higher than a vertical growth rate of the second film layer.
上述方法可包括一或多個下述特徵。於形成該第一膜層之前，可於該罩幕層內形成一第二開口，以及於形成該第二膜層之前，可形成該第一膜層於該第二開口內。於該第二膜層之可形成包括該第二半導體材料之一第三膜層。該第三膜層可接合於該第一開口與該第二開口之間。The above methods may include one or more of the following features. Before forming the first film layer, a second opening may be formed in the mask layer, and the first film layer may be formed in the second opening before the second film layer is formed. A third film layer including one of the second semiconductor materials may be formed on the second film layer. The third film layer is engageable between the first opening and the second opening.
於該第一膜層內之差排缺陷可於該第一開口內而捕捉。該第一膜層之該垂直成長速率可藉由於形成該第一膜層時摻雜該第一膜層而增加。該第一膜層之該垂直成長速率可藉由於形成該第一膜層時摻雜該第一膜層而增加。該第一膜層之該側向成長速率可於形成該第一膜層時藉由調整用於該第一膜層之一頂面上形成晶面之成長參數而降低。降低該第二膜層之該垂直成長速率可包括於形成該第二膜層時摻雜該第二膜層。A gap defect in the first film layer can be captured in the first opening. The vertical growth rate of the first film layer can be increased by doping the first film layer when the first film layer is formed. The vertical growth rate of the first film layer can be increased by doping the first film layer when the first film layer is formed. The lateral growth rate of the first film layer can be reduced by adjusting a growth parameter for forming a crystal face on a top surface of the first film layer when the first film layer is formed. Reducing the vertical growth rate of the second film layer can include doping the second film layer when the second film layer is formed.
降低該第二膜層之該垂直成長速率可包括於形成該第二膜層時摻雜該第二膜層以於該第二膜層內形成第一型之晶面並抑制於該第二膜層內一第二型之晶面的形成。於形成該第二膜層時摻雜該第二膜層可增加該第二膜層之側向成長速率。於形成該第三膜層時摻雜該第三膜層可促進該第三膜層之接合。於形成該第三膜層時摻雜該第三膜層可促進該第一開口與該第二開口之間的該第三膜層之接合。摻雜該第三膜層減緩了該第三膜層內之晶面成長且降低了於第三膜層內之堆疊錯誤的形成。該第二半導體材料可包括鍺。該第二半導體材料可包括p型摻質。形成至少該第一、第二或第三膜層可包括磊晶成長。形成該第一膜層可包括使用四氯化鍺作為一前趨物。上述方法可更包括於形成該第三膜層後移除該第三膜層之一頂部以移除缺陷。上述方法可更包括於該頂部移除之後形成一光學裝置於該第三膜層之上。該第一膜層之一頂部可定義了非平行於該基板之一頂面之一晶面。該第三膜層可自我平坦化。該第三膜層可藉由主要地於一(100)方向上成長該第三膜層而自我平坦化。Decreasing the vertical growth rate of the second film layer may include doping the second film layer when the second film layer is formed to form a first type crystal face in the second film layer and suppressing the second film The formation of a second type of crystal plane in the layer. Doping the second film layer while forming the second film layer increases the lateral growth rate of the second film layer. Doping the third film layer when forming the third film layer promotes bonding of the third film layer. Doping the third film layer when the third film layer is formed may promote bonding of the third film layer between the first opening and the second opening. Doping the third film layer slows the growth of the crystal plane in the third film layer and reduces the formation of stacking errors in the third film layer. The second semiconductor material can include germanium. The second semiconductor material can include a p-type dopant. Forming at least the first, second or third film layer may comprise epitaxial growth. Forming the first film layer can include using hafnium tetrachloride as a precursor. The above method may further include removing a top of one of the third film layers after forming the third film layer to remove defects. The above method may further comprise forming an optical device over the third film layer after the top removal. One of the tops of the first film layer may define a crystal face that is non-parallel to one of the top faces of the substrate. The third film layer can be self-planarized. The third film layer can be self-planarized by growing the third film layer mainly in a (100) direction.
上述形成方法可更包括形成一第四膜層於該第三膜層之頂部，該第四膜層包括一第三半導體材料。於該第四膜層之頂部形成一第五膜層，該第五膜層包括一第四半導體材料。可接合該第五膜層與一握持晶圓且移除該基板。該第三半導體材料與該第四半導體材料分別可包括III-V族材料。該基板可包括矽。該握持晶圓可包括金屬。該第三半導體材料之能隙可高於該第四半導體材料之能隙。該半導體結構可包括一多重接面光電電池。The above forming method may further include forming a fourth film layer on top of the third film layer, the fourth film layer including a third semiconductor material. Forming a fifth film layer on top of the fourth film layer, the fifth film layer comprising a fourth semiconductor material. The fifth film layer can be bonded to a holding wafer and the substrate can be removed. The third semiconductor material and the fourth semiconductor material may each comprise a III-V material. The substrate can include a crucible. The grip wafer can include a metal. The energy gap of the third semiconductor material may be higher than the energy gap of the fourth semiconductor material. The semiconductor structure can include a multi-junction photovoltaic cell.
依據本發明之另一實施例，本發明提供了一種半導體結構之形成方法，包括形成具有一寬度w1 之一開口於設置於一基板上之一罩幕層之內，該基底包括一第一半導體材料。於該開口內形成包括晶格不匹配於該第一半導體材料之一第二半導體材料之一第一膜層，該第一膜層垂直延伸至高於該罩幕層之一頂面且側向延伸至大於該寬度w1 之一寬度w2 。移除該第一膜層之一部，而該第一膜層之一剩餘部具有高於鄰近於該開口該基板之一第一區上之一厚度t1 。形成包括該第二半導體材料之一第二膜層於該第一膜層上，該第二膜層側向延伸至大於該寬度w2 之一寬度w3 。移除該第二膜層之一部，該第二膜層之一剩餘部具具有高於鄰近於該開口該基板之一第二區上之一厚度t2 。According to another embodiment of the present invention, the present invention provides a method of forming a semiconductor structure, comprising forming a mask having a width w 1 opening in a mask layer disposed on a substrate, the substrate including a first semiconductors. Forming, in the opening, a first film layer including a second semiconductor material having a lattice mismatch with one of the first semiconductor materials, the first film layer extending vertically to a top surface of the mask layer and extending laterally is greater than the width w to the width of one of 1 w 2. One portion of the first film layer is removed, and a remaining portion of the first film layer has a thickness t 1 that is higher than a first region of the substrate adjacent to the opening. The second one includes forming a second layer of semiconductor material on the first layer, the second layer extending laterally to more than one of the width w 2 width w 3. Removing one of the second film layers, the remaining portion of the second film layer having a thickness t 2 that is higher than a second region of the substrate adjacent to the opening.
上述方法可更包括一或多個下述特徵。於多個實施例中，t1 小於t2 。移除該第一膜層之該部可包括至少蝕刻或化學機械研磨其中之一。形成該第一膜層與移除該第一膜層之該部之步驟可於不同機台中所實施。形成該第一膜層與移除該第一膜層之該部之步驟可於同一機台中所實施。於該第二半導體材料內之差排缺陷係於該開口內所捕捉。高於該基板之該表面之該第一膜層之一部可大體不具有差排缺陷。該第二半導體材料之一垂直成長速率可大於該第二半導體材料之一側向成長速率。The above method may further include one or more of the following features. In various embodiments, t 1 is less than t 2 . Removing the portion of the first film layer can include at least one of etching or chemical mechanical polishing. The step of forming the first film layer and removing the portion of the first film layer can be carried out in different machines. The step of forming the first film layer and removing the portion of the first film layer can be carried out in the same machine. A gap defect in the second semiconductor material is captured within the opening. One portion of the first film layer above the surface of the substrate may have substantially no poor row defects. One of the second semiconductor materials may have a vertical growth rate that is greater than a lateral growth rate of the second semiconductor material.
該開口之一側壁可包括一介電材料。形成至少該第一材料與該第二材料之一可採用磊晶成長。上述方法可更包括採用四氯化鍺作為一前趨物以形成該第一膜層，於形成該第二膜層之後移除該第二膜層之一部，及/或於該第二膜層上形成一光電裝置。該第一膜層之一頂部可定義了不平行於該基板之一頂面之一晶面。該第二膜層可自我平坦化。該第二膜層可藉由主要地依照(100)方向成長該第二膜層而自我平坦化。One of the side walls of the opening may include a dielectric material. Forming at least one of the first material and the second material may employ epitaxial growth. The above method may further comprise using hafnium tetrachloride as a precursor to form the first film layer, removing one of the second film layers after forming the second film layer, and/or the second film An optoelectronic device is formed on the layer. The top of one of the first layers may define a crystal plane that is not parallel to one of the top surfaces of the substrate. The second film layer can be self-planarized. The second film layer can be self-planarized by growing the second film layer primarily in the (100) direction.
上述形成方法更包括形成一第三膜層於該第二膜層之頂部，該第三膜層包括一第三半導體材料。可形成一第四膜層於該第三膜層之頂部，該第四膜層包括一第四半導體材料。可接合該第四膜層與一握持晶圓以及移除該基板。該第三半導體材料與該第四半導體材料可包括III-V族材料，該基板可包括矽，以及該握持晶圓可包括金屬。該第三半導體材料之能隙可高於該第四半導體材料之能隙。上述半導體結構可包括一多重接面光電電池。The forming method further includes forming a third film layer on top of the second film layer, the third film layer including a third semiconductor material. A fourth film layer can be formed on top of the third film layer, the fourth film layer including a fourth semiconductor material. The fourth film layer can be bonded to a holding wafer and the substrate can be removed. The third semiconductor material and the fourth semiconductor material may comprise a III-V material, the substrate may comprise germanium, and the holding wafer may comprise a metal. The energy gap of the third semiconductor material may be higher than the energy gap of the fourth semiconductor material. The semiconductor structure described above can include a multi-junction photovoltaic cell.
一般來說，依據本發明之又一目的，本發明之實施例可包括一種膜層之形成方法。該方法包括了於設置一基板上之一罩幕層內形成一第一開口。於該第一開口內形成包括立方半導體材料之第一膜層。於該第一膜層之上形成亦包括該第一半導體材料之一第二膜層。該第一膜層之一垂直成長速率高於該第一膜層之一側向成長速率及該第二膜層之側向成長速率係高於該第二膜層之一垂直成長速率。In general, in accordance with yet another aspect of the present invention, embodiments of the present invention can include a method of forming a film layer. The method includes forming a first opening in a mask layer disposed on a substrate. A first film layer comprising a cubic semiconductor material is formed in the first opening. Forming a second film layer of the first semiconductor material also over the first film layer. One of the first film layers has a vertical growth rate higher than a lateral growth rate of the first film layer and a lateral growth rate of the second film layer is higher than a vertical growth rate of the second film layer.
上述方法之實施例可更包括於形成該第一膜層之前，形成一第二開口於該罩幕層內。於形成該第二膜層之前，可於該第二開口內形成一第一膜層。該第二膜層可接合於該第一開口與該第二開口之間。該罩幕層可包括一介電材料。位於該基板內之該第一開口可包括(110)晶面而該基板可包括矽。上述方法可更包括於該第一開口內捕捉該第一膜層內之差排缺陷。該第二膜層之垂直成長速率的減少以及該第二膜層之該側向成長速率之增加可包括改變成長條件。成長條件可包括0.1大氣壓與750℃。Embodiments of the above method may further include forming a second opening in the mask layer before forming the first film layer. A first film layer may be formed in the second opening before the second film layer is formed. The second film layer is engageable between the first opening and the second opening. The mask layer can include a dielectric material. The first opening in the substrate may include a (110) crystal face and the substrate may include a crucible. The above method may further comprise capturing a difference in the first film layer in the first opening. The reduction in the vertical growth rate of the second film layer and the increase in the lateral growth rate of the second film layer can include changing the growth conditions. Growth conditions can include 0.1 atmospheres and 750 °C.
上述立方半導體材料可包括鍺、砷化鎵、磷化銦或其他III-V族材料。該立方半導體材料可經過摻雜。於該第一膜層內之缺陷可於該開口內被捕捉。可於該第二膜層內形成一裝置。該裝置可為一光電裝置。該第二膜層之一頂部可經過蝕刻。該第一膜層之一頂部可定義一晶面非平行於該基板之一頂面。該第二膜層可自我平坦化。該第二膜層可藉由主要地依照(100)方向成長該第二膜層而自我平坦化。The above cubic semiconductor material may include germanium, gallium arsenide, indium phosphide or other III-V materials. The cubic semiconductor material can be doped. Defects within the first film layer can be captured within the opening. A device can be formed in the second film layer. The device can be an optoelectronic device. The top of one of the second layers can be etched. A top surface of one of the first film layers may define a crystal face that is non-parallel to a top surface of the substrate. The second film layer can be self-planarized. The second film layer can be self-planarized by growing the second film layer primarily in the (100) direction.
上述方法更包括形成一第三膜層於該第二膜層之頂部，該第三膜層包括一第三半導體材料。可形成一第四膜層於該第三膜層之頂部，該第四膜層包括一第四半導體材料。可接合該第四膜層與一握持晶圓以及可移除該基板。該第三半導體材料與該第四半導體材料可包括III-V族材料，該基板可包括矽，而該握持晶圓可包括金屬。該第三半導體材料之能隙可高於該第四半導體材料之能隙。上述結構可包括一多重接面光電電池。The method further includes forming a third film layer on top of the second film layer, the third film layer including a third semiconductor material. A fourth film layer can be formed on top of the third film layer, the fourth film layer including a fourth semiconductor material. The fourth film layer can be bonded to a holding wafer and the substrate can be removed. The third semiconductor material and the fourth semiconductor material may comprise a III-V material, the substrate may comprise germanium, and the holding wafer may comprise a metal. The energy gap of the third semiconductor material may be higher than the energy gap of the fourth semiconductor material. The above structure may comprise a multi-junction photovoltaic cell.
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附第圖式，作詳細說明如下：The above described objects, features and advantages of the present invention will become more apparent and understood.
於2008年6月26日申請之編號第12/147,027號以及標題為”Multi-Junction Solar Cell”之美國專利申請案中描述了包括剝離(lift-off)技術之基本的深寬比捕捉(aspect ratio trapping，ART)製程。於2008年7月25日申請之編號第12/180,254號以及標題為”Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication”之美國專利申請案中則描述了採用ART技術以形成太陽能電池(solar cells)。A basic aspect ratio capture including lift-off technique is described in U.S. Patent Application Serial No. 12/147,027, filed on Jun. 26, 2008, and entitled, the "Multi-Junction Solar Cell" Ratio trapping, ART) process. The use of ART technology to form a U.S. Patent Application Serial No. 12/180,254, filed on Jul. 25, 2008, and entitled to the "Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication" Solar cells.
如第1圖所示，本發明之一實施例之半導體結構係應用了磊晶側向成長(epitaxial lateral overgrowth，ELO)技術，而ELO係藉由雜質的使用以控制之。其可藉由使用晶面控制(control of faceting)以於晶圓上施行磊晶側向成長。晶面(faceting)則可藉由如改變材料內之雜質程度、改變成長溫度、改變成長壓力、改變前趨物氣體流率及/或改變前趨物之化學物組成而得到控制。晶面之較佳控制係具有兩個目的：(i)為了於一既定垂直成長中增加磊晶側向成長內之側向成長，以及(ii)為了降低於接合(coalescence)時之堆疊錯誤(stacking faults)或差排(dislocations)情形。於一實施例中，位於具(100)晶面之矽晶圓上且形成於具(110)晶面之溝槽內的鍺的晶面可藉由習知晶面表現而得到控制。以上相同技術亦可應用至其他材料或晶格方向的應用。第1圖中所示之半導體結構之實施例顯示於採用深寬比捕捉(ART)與磊晶側向成長(ELO)等技術的結合中之晶面控制應用，但上述技術亦可僅應用磊晶側向成長中。As shown in Fig. 1, the semiconductor structure of one embodiment of the present invention employs an epitaxial lateral overgrowth (ELO) technique, and the ELO is controlled by the use of impurities. It can be subjected to epitaxial lateral growth on the wafer by using a control of faceting. Faceting can be controlled by, for example, varying the degree of impurities in the material, changing the growth temperature, changing the growth pressure, changing the precursor gas flow rate, and/or changing the chemical composition of the precursor. The preferred control of the crystal face has two purposes: (i) to increase lateral growth within the epitaxial lateral growth for a given vertical growth, and (ii) to reduce stacking errors during coalescence ( Stacking faults) or dislocations. In one embodiment, the crystal plane of the germanium on the germanium wafer having the (100) crystal plane and formed in the trench having the (110) crystal plane can be controlled by the conventional crystal plane representation. The same techniques described above can also be applied to other materials or lattice orientation applications. The embodiment of the semiconductor structure shown in FIG. 1 is shown in a crystal plane control application using a combination of aspect ratio capture (ART) and epitaxial lateral growth (ELO) techniques, but the above technique may also only apply Lei. The crystal grows laterally.
於一實施例中，第1圖所示半導體結構的製作如下：首先提供包括一第一半導體材料之一基板100，例如為一矽晶圓且其可具有如(100)之晶面。接著於基板100上形成一罩幕層102，罩幕層102可包括由介電材料所組成之一絕緣物(insulator)。接著藉由如微影技術與蝕刻方法等程序，於罩幕層102形成至少一開口，在此顯示為位於罩幕層102且相分隔之兩個開口104，而各開口104則露出了位於下方之基板100之一部以及罩幕層102之一側壁。接著施行如磊晶成長之程序以於各開口104內形成包括晶格不匹配於基板100所包括之第一半導體材料之一第二半導體材料之一第一膜層106，上述第二半導體材料例如為鍺且可包括p型摻質。所形成之第一膜層106具有足夠延伸至高於罩幕層106之一頂面之一厚度，故第一膜層106可填滿各開口104並形成於鄰近各開口104之罩幕層102之一部之上。接著施行如磊晶成長之程序，以於第一膜層106與罩幕層102之一部上形成包括上述第二半導體材料之一第二膜層108，而分別形成各開口104上方之第一膜層106上之第二膜層108則可於位於此些開口104之間接合，進而形成了如第1圖所示之半導體結構。In one embodiment, the semiconductor structure shown in FIG. 1 is fabricated as follows: First, a substrate 100 including a first semiconductor material, such as a germanium wafer, and which may have a crystal face such as (100), is provided. A mask layer 102 is then formed on the substrate 100. The mask layer 102 can include an insulator composed of a dielectric material. At least one opening is then formed in the mask layer 102 by a process such as lithography and etching, as shown here as two openings 104 located in the mask layer 102 and separated, and each opening 104 is exposed below One of the substrate 100 and one side wall of the mask layer 102. Then, a process such as epitaxial growth is performed to form a first film layer 106 including a second semiconductor material having a lattice mismatch with one of the first semiconductor materials included in the substrate 100, such as the second semiconductor material, for example, in each of the openings 104. It can also include p-type dopants. The first film layer 106 is formed to extend sufficiently to a thickness higher than one of the top surfaces of the mask layer 106, so that the first film layer 106 can fill the openings 104 and be formed in the mask layer 102 adjacent to the openings 104. Above one. Then, a process such as epitaxial growth is performed to form a second film layer 108 including one of the second semiconductor materials on one of the first film layer 106 and the mask layer 102, and respectively form a first layer above each of the openings 104. The second film layer 108 on the film layer 106 can be joined between the openings 104 to form a semiconductor structure as shown in FIG.
於一實施例中，第一膜層106係採用磊晶成長程序所形成，例如是為應用深寬比捕捉(ART)技術之磊晶成長程序所形成，故第一膜層106之垂直成長速率係高於其側向成長速率，於第一膜層106內之差排缺陷103可於各第一開口104內而捕捉。第一膜層106之垂直成長速率可藉由於形成第一膜層時摻雜第一膜層而增加，而第一膜層106之側向成長速率則可於形成第一膜層106時藉由摻雜第一膜層106或調整於第一膜層之一頂面上形成晶面之成長參數而降低。第一膜層106之頂面具有非平行於基板100之晶面。In one embodiment, the first film layer 106 is formed by an epitaxial growth process, for example, an epitaxial growth process for applying an aspect ratio capture (ART) technique, so the vertical growth rate of the first film layer 106 Above the lateral growth rate, the differential defect 103 in the first film layer 106 can be captured within each of the first openings 104. The vertical growth rate of the first film layer 106 can be increased by doping the first film layer when the first film layer is formed, and the lateral growth rate of the first film layer 106 can be formed by forming the first film layer 106. The doping of the first film layer 106 or the growth parameters of the crystal face formed on one of the top surfaces of the first film layer is reduced. The top surface of the first film layer 106 has a crystal plane that is non-parallel to the substrate 100.
於一實施例中，第二膜層108係採用磊晶成長程序所形成，例如是為應用如磊晶側向成長(ELO)技術之磊晶成長程序所形成，故第二膜層108之一側向成長速率係高於其垂直成長速率。第二膜層108之垂直成長速率可藉由於形成第二膜層108時摻雜該第二膜層而降低，以於第二膜層108內形成第一型之晶面並抑制一第二型之晶面的形成。於形成第二膜層108時摻雜之亦可增加第二膜層之側向成長速率並可促進其於此些開口104之間的膜層接合情形。另外，摻雜第二膜層108亦減緩了該第二膜層內之晶面成長且降低了於第二膜層內之堆疊錯誤的形成。另外，於第二膜層108形成之後可部份移除其頂部以移除可能產生之缺陷。或者，於另一實施例中，第二膜層108可於成長之後而自我平坦化，例如是藉由主要按照<100>方向上的成長而達成自我平坦化的目的。In one embodiment, the second film layer 108 is formed by an epitaxial growth process, for example, by an epitaxial growth process using an epitaxial lateral growth (ELO) technique, such that one of the second film layers 108 The lateral growth rate is higher than its vertical growth rate. The vertical growth rate of the second film layer 108 can be reduced by doping the second film layer 108 when the second film layer 108 is formed, so as to form a first type crystal face in the second film layer 108 and suppress a second type. The formation of the crystal face. Doping during formation of the second film layer 108 may also increase the lateral growth rate of the second film layer and may promote film bonding between the openings 104. In addition, doping the second film layer 108 also slows the growth of the crystal plane in the second film layer and reduces the formation of stacking errors in the second film layer. Additionally, the top portion of the second film layer 108 may be partially removed after it is formed to remove possible defects. Alternatively, in another embodiment, the second film layer 108 may be self-planarized after growth, for example, by self-flattening mainly by growth in the <100> direction.
如第2圖所示，本發明之另一實施例中之半導體結構係則應用了具有膜層之重複移除與再成長之磊晶側向成長。磊晶側向成長係為用於成長不匹配磊晶(mismatched epitaxy)之技術。最大側向成長寬度則為薄膜之最大允許厚度所限制。最大側向成長寬度可藉由重複地薄化與再成長此薄膜而增加。上述之薄化與再成長等步驟可於不同機台內施行，或可於相同機台內施行。第2圖中所示之半導體結構伴隨著深寬比捕捉(ART)或磊晶側向成長(ELO)等技術之使用所形成。As shown in FIG. 2, the semiconductor structure in another embodiment of the present invention applies epitaxial lateral growth with repeated removal and re-growth of the film layer. The epitaxial lateral growth is a technique for growing mismatched epitaxy. The maximum lateral growth width is limited by the maximum allowable thickness of the film. The maximum lateral growth width can be increased by repeatedly thinning and re-growing the film. The above steps of thinning and re-growth can be performed in different machines or can be performed in the same machine. The semiconductor structure shown in Fig. 2 is formed by the use of techniques such as aspect ratio capture (ART) or epitaxial lateral growth (ELO).
於第2圖所示之半導體結構的製作中，首先提供包括一第一半導體材料之一基板200，例如為一矽晶圓且其可具有如(100)之晶面。接著於基板200上形成一罩幕層202，罩幕層202可包括由如氧化物之介電材料所組成之一絕緣物(insulator)。接著藉由如微影技術與蝕刻方法等程序，於罩幕層202形成一開口，在此顯示為位於罩幕層202之開口204，而此開口204具有一寬度W1 並露出了位於下方之基板200之一部以及罩幕層202之一側壁。接著於開口204內形成包括晶格不匹配於基板200所包括之第一半導體材料之一第二半導體材料之一第一膜層206。所形成之第一膜層206垂直延伸至高於罩幕層202之頂面且側向延伸於罩幕層202上至大於開口204寬度W1 之一寬度W2 ，故第一膜層206可填滿開口204並形成於鄰近開口204之罩幕層202之一部之上。接著藉由如蝕刻或化學機械研磨之程序以移除第一膜層206之一部，而殘留於罩幕層202上之第一膜層206之剩餘部則具有高於鄰近開口204之一厚度t1 。接著於第一膜層206與罩幕層202之一部上形成包括上述第二半導體材料之一第二膜層208，並接著移除第二膜層208之一部以於罩幕層202上留下覆蓋第一膜層206及其鄰近之罩幕層202之第二膜層208的剩餘部，進而形成了如第2圖所示之半導體結構。在此，第二膜層208的剩餘部具有寬於位於罩幕層202上第一膜層206部份之寬度W2 之一寬度W3 以及高於鄰近開口204之基板200之一厚度t2 ，其係高於第一膜層206高於開口204部分之厚度t1 。In the fabrication of the semiconductor structure shown in FIG. 2, a substrate 200 comprising a first semiconductor material, such as a germanium wafer, and which may have a crystal face such as (100), is first provided. A mask layer 202 is then formed on the substrate 200. The mask layer 202 can include an insulator composed of a dielectric material such as an oxide. The lithography techniques followed by an etching method or the like and a program, in the mask layer 202 is formed an opening located on this screen mask layer 202 of the opening 204, and this opening 204 having a width W 1 of the exposed and positioned below the One of the substrate 200 and one side wall of the mask layer 202. A first film layer 206 comprising a second semiconductor material that is lattice mismatched to one of the first semiconductor materials included in the substrate 200 is then formed in the opening 204. The first film layer 206 is formed to extend vertically above the top surface of the mask layer 202 and laterally extending over the mask layer 202 to a width W 2 greater than the width W 1 of the opening 204. Therefore, the first film layer 206 can be filled. The opening 204 is formed and formed over a portion of the mask layer 202 adjacent the opening 204. The portion of the first film layer 206 is then removed by a process such as etching or chemical mechanical polishing, and the remaining portion of the first film layer 206 remaining on the mask layer 202 has a thickness higher than one of the adjacent openings 204. t 1 . Forming a second film layer 208 comprising one of the second semiconductor materials on a portion of the first film layer 206 and the mask layer 202, and then removing a portion of the second film layer 208 over the mask layer 202 The remaining portion of the second film layer 208 covering the first film layer 206 and its adjacent mask layer 202 is left to form a semiconductor structure as shown in FIG. Here, the remaining portion of the second film layer 208 has a width W 3 that is wider than a width W 2 of the portion of the first film layer 206 on the mask layer 202 and a thickness t 2 of the substrate 200 that is higher than the adjacent opening 204. It is higher than the thickness t 1 of the first film layer 206 higher than the portion of the opening 204.
於一實施例中，第一膜層206係採用磊晶成長程序所形成，例如是為應用深寬比捕捉(ART)技術之磊晶成長程序所形成，故第一膜層206之垂直成長速率係高於其側向成長速率，於第一膜層206內之差排缺陷203可於開口204內而捕捉。第一膜層206之垂直成長速率可藉由於形成第一膜層時摻雜第一膜層而增加，而第一膜層206之側向成長速率則可於形成第一膜層206時藉由摻雜第一膜層206或調整於第一膜層之一頂面上形成晶面之成長參數而降低。在此，第一膜層206之頂面具有非平行於基板200之晶面。In one embodiment, the first film layer 206 is formed by an epitaxial growth process, for example, an epitaxial growth process for applying an aspect ratio capture (ART) technique, so the vertical growth rate of the first film layer 206 Above the lateral growth rate, the difference 203 in the first film layer 206 can be captured within the opening 204. The vertical growth rate of the first film layer 206 can be increased by doping the first film layer when the first film layer is formed, and the lateral growth rate of the first film layer 206 can be formed by forming the first film layer 206. The doping of the first film layer 206 or the growth parameter of the crystal face formed on one of the top surfaces of the first film layer is reduced. Here, the top surface of the first film layer 206 has a crystal plane that is not parallel to the substrate 200.
於一實施例中，第二膜層208係採用磊晶成長程序所形成，例如是為應用如磊晶側向成長(ELO)技術之磊晶成長程序所形成，故第二膜層208之一側向成長速率係高於其垂直成長速率。第二膜層208之垂直成長速率可藉由於形成第二膜層208時摻雜該第二膜層而降低，以於第二膜層208內形成第一型之晶面並抑制一第二型之晶面的形成。另外，摻雜第二膜層208亦減緩了該第二膜層內之晶面成長且降低了於第二膜層內之堆疊錯誤的形成。另外，於第二膜層208形成之後可部份移除其頂部以移除可能產生之缺陷。或者，於另一實施例中，第二膜層208可於成長之後而自我平坦化，例如是藉由主要按照<100>方向上的成長而達成自我平坦化的目的。In one embodiment, the second film layer 208 is formed by an epitaxial growth process, such as an epitaxial growth process using an epitaxial lateral growth (ELO) technique, such as one of the second film layers 208. The lateral growth rate is higher than its vertical growth rate. The vertical growth rate of the second film layer 208 can be reduced by doping the second film layer 208 when the second film layer 208 is formed, so as to form a first type crystal face in the second film layer 208 and suppress a second type. The formation of the crystal face. In addition, doping the second film layer 208 also slows the growth of the crystal plane in the second film layer and reduces the formation of stacking errors in the second film layer. Additionally, the top portion of the second film layer 208 may be partially removed after it is formed to remove possible defects. Alternatively, in another embodiment, the second film layer 208 may be self-planarized after growth, for example, by self-flattening mainly by growth in the <100> direction.
於一實施例中，第一膜層206的形成與部分移除可於不同機台或於同一機台中實施。由於第一膜層206之第二半導體材料內的差排缺陷203可於開口204內所捕捉，因此高於罩幕層202之表面之第一膜層206之一部可大體不具有差排缺陷。而於第一膜層206形成時，可採用四氯化鍺作為前趨物。In one embodiment, the formation and partial removal of the first film layer 206 can be performed in different machines or in the same machine. Since the differential defect 203 in the second semiconductor material of the first film layer 206 can be captured in the opening 204, one portion of the first film layer 206 higher than the surface of the mask layer 202 can have substantially no differential defect. . When the first film layer 206 is formed, hafnium tetrachloride can be used as a precursor.
如第3圖所示，本發明之其他實施例提供用於立方半導體材料(cubic semiconductor materials)之有效磊晶側向成長。GaN與其他III-N族半導體皆具有六方結晶(hexagonal crystal)結構。目前尚未發現有利於如鍺(Ge)之立方半導體材料或用於如砷化鍺(GaAs)或磷化銦(InP)之III-V族材料之水平成長速率(GR水平 )與垂直成長速率(GR垂直 )間之高比率(GR水平 /GR垂直 )的條件。上述情形使得磊晶側向成長變的較為困難。可能的解決方案之一係為選擇性地控制垂直與水平成長速率。於一實施例中，可採用具(110)晶面之基板，例如為具(110)晶面之矽基板300。可沈積一絕緣物302於上述基板之上並圖案化之，以於其內形成開口304，而開口304則部分露出矽基板300之(110)晶面之一部。可於如垂直與水平方向皆可施行之參數條件下於為開口304所露出之部分矽基板300之(110)晶面上成長鍺或III-V族立方材料。接著，將上述參數切換至於<110>方向上幾乎無成長但是於如<111>方向之垂直於<110>方向之方向上有顯著成長之參數條件，進而形成了如第3圖中所示之鍺或III-V族立方材料之膜層306，其填滿開口304且部分覆蓋於鄰近開口304之絕緣物302上並具有高於絕緣物302之特定厚度，膜層306內之差排缺陷308可於開口304內所捕捉，因此高於絕緣物302之表面之膜層306的鍺或III-V族立方材料將大體不具有差排缺陷。請參照Noborisaka等人於Applied Physics Letters 86 213102(2005)以及Noborisaka等人於Applied Physics Letters 87 093109(2005)等文獻之揭示情形。在此之關鍵係採用具(110)晶面之基板。如此便實際上允許了由高GR垂直 /GR水平 改變至高GR水平 /GR 垂直，如此較有利於磊晶側向成長的實施。As shown in FIG. 3, other embodiments of the present invention provide for effective epitaxial lateral growth for cubic semiconductor materials. Both GaN and other III-N semiconductors have a hexagonal crystal structure. No horizontal growth rate (GR level ) and vertical growth rate for cubic semiconductor materials such as germanium (Ge) or III-V materials such as germanium arsenide (GaAs) or indium phosphide (InP) have been found ( high ratio (GR horizontal / GR vertical) perpendicular to the conditions between the GR). The above situation makes it difficult to grow the epitaxial lateral direction. One of the possible solutions is to selectively control the vertical and horizontal growth rates. In one embodiment, a substrate having a (110) crystal plane, such as a germanium substrate 300 having a (110) crystal plane, may be employed. An insulator 302 may be deposited over the substrate and patterned to form an opening 304 therein, and the opening 304 partially exposes a portion of the (110) crystal plane of the germanium substrate 300. The germanium or III-V cubic material may be grown on the (110) crystal plane of the portion of the germanium substrate 300 exposed by the opening 304 under parameters such as vertical and horizontal. Then, the above parameters are switched to a parameter condition that has almost no growth in the <110> direction but has a significant growth in the direction perpendicular to the <110> direction of the <111> direction, thereby forming a condition as shown in FIG. A film layer 306 of tantalum or group III-V cubic material fills the opening 304 and partially overlies the insulator 302 adjacent the opening 304 and has a specific thickness above the insulator 302, a defect 308 within the film layer 306 It can be captured within the opening 304, so that the tantalum or III-V cubic material of the film layer 306 above the surface of the insulator 302 will generally have no differential discharge defects. Please refer to the disclosures of Noborisaka et al. in Applied Physics Letters 86 213102 (2005) and Noborisaka et al. in Applied Physics Letters 87 093109 (2005). The key here is to use a substrate with a (110) crystal plane. This actually allows for a change from a high GR vertical /GR level to a high GR level / GR vertical, which is more advantageous for the implementation of epitaxial lateral growth.
如第4圖所示，本發明之實施例包括了使用深寬比捕捉與磊晶側向成長等技術所形成之太陽能電池，其係為一多重接面太陽能光電電池。第4圖顯示了應用鍺材料之的深寬比捕捉與磊晶側向成長製程以替代習知多重接面形態中所使用之鍺基板。於習知形態中，可於一鍺晶圓(未顯示)上成長具p/n接面之GaAs膜層以及具p//n接面之InGaP膜層(皆未顯示)。InGaP膜層之p/n接面具有高能隙(1.8eV)且可收集高能量之光線，而GaAs之p/n接面(1.4eV)則具有一中階能隙且可收集中能量之光線。於上述習知形態中，最低能量之光線則藉由形成於鍺晶圓之頂面上一鍺的p/n接面所收集。As shown in FIG. 4, an embodiment of the present invention includes a solar cell formed using techniques such as aspect ratio capture and epitaxial lateral growth, which is a multi-junction solar photovoltaic cell. Figure 4 shows the aspect ratio capture and epitaxial lateral growth process applied to the germanium material to replace the germanium substrate used in the conventional multiple junction morphology. In a conventional form, a GaAs film layer having a p/n junction and an InGaP film layer having a p//n junction (both not shown) can be grown on a single wafer (not shown). The p/n junction of the InGaP film has a high energy gap (1.8eV) and collects high-energy light, while the p/n junction of GaAs (1.4eV) has a medium-order energy gap and collects light in the middle energy. . In the above conventional form, the lowest energy light is collected by a p/n junction formed on the top surface of the germanium wafer.
請參照第4圖，本發明之一實施例中使用深寬比捕捉與磊晶側向成長等技術所形成之太陽能電池的製作如下：首先提供一複合基板430，其包括了如第1-2圖所示之半導體結構。在此，複合基板430包括由第一半導體材料所構成之一基板400，位於基板400上圖案化之罩幕層402以及位於圖案化之罩幕層402上與部分之罩幕層402內之之半導體層404。於一實施例中，基板400可包括如矽之第一半導體材料，而基板400上圖案化之罩幕層402內則形成有數個開口403，此些開口403分別露出基板400之一部。因此，半導體層404可採用前述實施例中所揭示之深寬比捕捉與磊晶側向成長等技術而成長形成於罩幕層402之表面與開口403內且實體接觸基板400。在此，半導體層404可包括如鍺之半導體材料，其晶格不匹配於基板400所包括之如矽之第一半導體材料。Referring to FIG. 4, a solar cell formed by using techniques such as aspect ratio capture and epitaxial lateral growth in an embodiment of the present invention is as follows: First, a composite substrate 430 is provided, which includes The semiconductor structure shown in the figure. Here, the composite substrate 430 includes a substrate 400 composed of a first semiconductor material, a mask layer 402 patterned on the substrate 400, and a portion of the mask layer 402 on the patterned mask layer 402 and a portion of the mask layer 402. Semiconductor layer 404. In one embodiment, the substrate 400 may include a first semiconductor material such as tantalum, and a plurality of openings 403 are formed in the patterned mask layer 402 on the substrate 400, and the openings 403 respectively expose one portion of the substrate 400. Therefore, the semiconductor layer 404 can be grown in the surface of the mask layer 402 and the opening 403 and physically contact the substrate 400 by using techniques such as aspect ratio capture and epitaxial lateral growth disclosed in the foregoing embodiments. Here, the semiconductor layer 404 may include a semiconductor material such as germanium whose lattice does not match the first semiconductor material such as germanium included in the substrate 400.
接著於半導體層404上依序形成材質不同之三個半導體膜層406、408與410，而此些半導體膜層406、408與410之間則為一穿隧二極體層412所分隔。於一實施例中，半導體膜層406例如為具p/n接面之鍺層、半導體膜層408例如為具p/n接面之GaAs膜層以及半導體膜層410例如為具p/n接面之InGaP膜層。上述半導體膜層410內InGaP材料的p/n接面具有高能隙(1.8eV)且可收集高能量之光線，而半導體膜層408內GaAs材料的p/n接面(1.4eV)則具有一中階能隙且可收集中能量之光線。Then, three semiconductor film layers 406, 408 and 410 having different materials are sequentially formed on the semiconductor layer 404, and the semiconductor film layers 406, 408 and 410 are separated by a tunneling diode layer 412. In one embodiment, the semiconductor film layer 406 is, for example, a germanium layer having a p/n junction, the semiconductor film layer 408 is, for example, a GaAs film layer having a p/n junction, and the semiconductor film layer 410 is, for example, having a p/n connection. InGaP film layer. The p/n junction of the InGaP material in the semiconductor film layer 410 has a high energy gap (1.8 eV) and can collect high energy light, and the p/n junction (1.4 eV) of the GaAs material in the semiconductor film layer 408 has a A medium-order energy gap that collects light in the middle energy.
於如第4圖所示之實施例中，當使用鍺的深寬比捕捉與磊晶側向成長技術所製備得到之複合基板430以取代習知形態中應用之鍺晶圓時，如第4圖所製備得到之太陽能電池的表現並不好。其兩個可能原因如下。首先，其內所應用之鍺電池(即半導體層406)可能太厚。鍺的熱膨脹係數(coefficient of thermal expansion，CTE)遠不同於矽的熱膨脹係數。鍺的成長通常於成長溫度中並未承受到應力，但是於其冷卻後便會承受到應力。故當鍺成長至一過厚程度時，為了以釋放應力便可能於鍺中形成破裂(cracks)。可導致破裂之上述厚度約介於5-10微米，其實際厚度則依據成長溫度而定。於如此之多重接面形態中所應用之鍺電池應用較佳地至少20微米厚。上述較佳厚度係由於鍺的能隙(band-gap)為間接(indirect)的，故對於光而言鍺並非為一極佳的吸收物。當所製作的鍺電池太薄時，大多數的光線會穿透鍺電池而沒有為其所吸收，如此將降低電池效率。上述厚度之需求亦基於電流匹配(current matching)特性，即當鍺電池太薄時，於電池底部所產生的電流可能低於其頂部處所產生的電流，進而降低了串連裝置內之電流與其效率。In the embodiment shown in FIG. 4, when the composite substrate 430 prepared by the aspect ratio capture and epitaxial lateral growth technique of tantalum is used to replace the tantalum wafer applied in the conventional form, as in the fourth The solar cells prepared in the figure did not perform well. The two possible reasons are as follows. First, the germanium battery (i.e., semiconductor layer 406) used therein may be too thick. The coefficient of thermal expansion (CTE) is much different from the coefficient of thermal expansion of helium. The growth of bismuth is usually not subjected to stress at the growth temperature, but it is subjected to stress after it is cooled. Therefore, when the crucible grows to a degree of excessive thickness, cracks may be formed in the crucible in order to release the stress. The above thickness which may cause cracking is about 5-10 microns, and the actual thickness depends on the growth temperature. The tantalum battery application applied in such multiple junction configurations is preferably at least 20 microns thick. The above preferred thickness is due to the fact that the band-gap of the germanium is indirect, so that germanium is not an excellent absorber for light. When the fabricated battery is too thin, most of the light will penetrate the battery without being absorbed, which will reduce battery efficiency. The above thickness requirements are also based on current matching characteristics, that is, when the battery is too thin, the current generated at the bottom of the battery may be lower than the current generated at the top of the battery, thereby reducing the current and efficiency in the series device. .
於如第4圖所示之太陽能電池可能無法施行鍺的深寬比捕捉與磊晶側向成長技術之的第二理由係由於此形態中之位於鍺與矽基底之間的高電阻值。電流可能僅能透過連結於上述兩者之間的窄的開口403而於鍺與矽之間流通。而形成開口403之罩幕層402所可能包括之氧化物材質則將阻擋了於其他路徑之電流傳導情形。如此高電阻值將降低了太陽能電池的效率。The second reason why the solar cell shown in Fig. 4 may not be able to perform the aspect ratio capture and epitaxial lateral growth technique is the high resistance value between the tantalum and tantalum substrates in this form. The current may only flow between the crucible and the crucible through a narrow opening 403 connected between the two. The oxide material that may be included in the mask layer 402 forming the opening 403 will block the current conduction of other paths. Such high resistance values will reduce the efficiency of the solar cell.
第5a圖與第5b圖則描述了用於解決上述問題之可能方法。如第5a圖內所示，可於採用鍺的深寬比捕捉與磊晶側向成長等技術之一複合基板530上形成一反向型太陽能電池(inversed solar cell)。其製作包括提供包括先前第1-2圖所示之半導體結構之一複合基板530，其包括具有如矽材質之第一半導體材料之基板500、形成於基板500上且具有數個開口504形成於其內之罩幕層502、形成於罩幕層502上且填入於開口504內之半導體層506。在此，半導體層506係具有一平坦表面，且半導體層506係包括晶格不匹配於基板500之第一半導體材料之一第二半導體材料，例如為鍺。Figures 5a and 5b depict possible ways to solve the above problems. As shown in FIG. 5a, an inverted solar cell can be formed on the composite substrate 530 of one of the techniques of capturing the aspect ratio of the germanium and the lateral growth of the epitaxial growth. The fabrication includes providing a composite substrate 530 comprising a semiconductor structure as shown in the previous figures 1-2, comprising a substrate 500 having a first semiconductor material such as a germanium material, formed on the substrate 500 and having a plurality of openings 504 formed therein A mask layer 502 is formed thereon, and is formed on the mask layer 502 and filled in the semiconductor layer 506 in the opening 504. Here, the semiconductor layer 506 has a flat surface, and the semiconductor layer 506 includes a second semiconductor material that is lattice-matched to one of the first semiconductor materials of the substrate 500, such as germanium.
接著於複合基板530之半導體層506上依序成長數個材質彼此之間不相同且不同於複合基板530所包括材料之半導體膜層508、510、512與514，其所含材質例如為III-V族半導體材質。於半導體膜層508、510與512之間則為一穿隧二極體層520所分隔。於一實施例中，半導體膜層508可包括一高能隙(約1.8eV)之InGaP材料，而半導體層510可包括GaAs(約1.4eV)材料，以及半導體層514可包括InGaAs(約1.0eV)材料。形成於半導體層510之GaAs材料與半導體層514之InGaAs材料之間的半導體層512則可包括GaInP材料以作為調節介於半導體層514之InGaAs材料與半導體層510之GaAs材料之間的晶格常數差異之一緩衝層。參照第5a圖所示，最後製備出之包括InGaAs材質之太陽能電池可具有極薄厚度，通常為2微米，其係基於InGaAs係為直接能隙半導體，故可有效地吸收光線。於電池成長完畢之後，可反置第5a圖所示結構且將之連結於含金屬材質且導電之一握持晶圓(handle wafer)600。接著可藉由選擇性蝕刻移除採用鍺的深寬比捕捉與磊晶側向成長等技術所形成之複合基板530。由於欲移除之複合基板530內的矽基板500遠厚於不欲移除之化合物半導體太陽能電池部份，故上述選擇性蝕刻較佳地需非常正確地完成。如此之選擇性移除可藉由採用如氫氧化鉀(KOH)之選擇性極佳之濕蝕刻，其可快速地蝕刻矽但卻緩慢地蝕刻鍺。而罩幕層502內可能包括之氧化物與由深寬比捕捉與磊晶側向成長等技術所形成之鍺材質之半導體膜層506則可接著於另一步驟中移除，且於此步驟中由於此些膜層相對於化合物半導體太陽能電池來說並不厚，故其挑戰性並不高。Then, on the semiconductor layer 506 of the composite substrate 530, a plurality of semiconductor film layers 508, 510, 512 and 514 which are different from each other and different from the material included in the composite substrate 530 are sequentially grown, and the material thereof is, for example, III- V family semiconductor material. Between the semiconductor film layers 508, 510 and 512 is separated by a tunneling diode layer 520. In one embodiment, the semiconductor film layer 508 may comprise a high energy gap (about 1.8 eV) of InGaP material, while the semiconductor layer 510 may comprise GaAs (about 1.4 eV) material, and the semiconductor layer 514 may comprise InGaAs (about 1.0 eV). material. The semiconductor layer 512 formed between the GaAs material of the semiconductor layer 510 and the InGaAs material of the semiconductor layer 514 may then include a GaInP material as a lattice constant between the GaAs material of the InGaAs material and the semiconductor layer 510 of the semiconductor layer 514. One of the differences is the buffer layer. Referring to Fig. 5a, the solar cell including the InGaAs material which is finally prepared can have an extremely thin thickness, usually 2 micrometers, which is based on the InGaAs system as a direct energy gap semiconductor, so that light can be efficiently absorbed. After the battery has been grown, the structure shown in FIG. 5a can be reversed and attached to a metal-containing material and a conductive handle wafer 600. The composite substrate 530 formed by techniques such as capture of the aspect ratio of the germanium and lateral growth of the epitaxial growth can then be removed by selective etching. Since the germanium substrate 500 in the composite substrate 530 to be removed is much thicker than the compound semiconductor solar cell portion that is not to be removed, the selective etching described above preferably needs to be performed very accurately. Such selective removal can be achieved by using a wet etching such as potassium hydroxide (KOH) which is excellent in etching, but which etches germanium rapidly but slowly. The semiconductor film layer 506 of the germanium material formed by the oxide and the lateral growth of the epitaxial layer 502 may be removed in another step, and this step is performed. Since these layers are not thick relative to compound semiconductor solar cells, they are not challenging.
參照第5b圖之顯示情形，本發明之一實施例中所示之反向型太陽能電池可極佳地解決前述兩個問題。可吸收低能量光線之此InGaAs太陽能電池夠薄，故可成長於採用鍺的深寬比捕捉與磊晶側向成長等技術之基板上而不會造成破裂情形。而握持晶圓600則提供了用於太陽能電池電流之一低電阻值路徑。Referring to the display case of Fig. 5b, the reverse type solar cell shown in one embodiment of the present invention can solve the above two problems excellently. The InGaAs solar cell, which can absorb low-energy light, is thin enough to grow on a substrate using a technique such as aspect ratio capture and epitaxial lateral growth without causing cracking. Holding the wafer 600 provides a low resistance path for the solar cell current.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.
100、200、400、500．．．基板100, 200, 400, 500. . . Substrate
102、202、402、502．．．罩幕層102, 202, 402, 502. . . Mask layer
103、203．．．差排缺陷103, 203. . . Differential defect
104、204、403、504．．．開口104, 204, 403, 504. . . Opening
106、206．．．第一膜層106, 206. . . First film
108、208．．．第二膜層108, 208. . . Second film
300．．．矽基板300. . .矽 substrate
302．．．絕緣物302. . . Insulator
304．．．開口304. . . Opening
306．．．鍺或III-V族立方材料306. . .锗 or III-V cubic material
308．．．差排缺陷308. . . Differential defect
404、406、408、410、506、508、510、512、514．．．半導體層404, 406, 408, 410, 506, 508, 510, 512, 514. . . Semiconductor layer
412、520．．．穿隧二極體層412, 520. . . Tunneling diode layer
430、530．．．複合基板430, 530. . . Composite substrate
600．．．握持晶圓600. . . Holding wafer
W1 ．．．開口之寬度W 1 . . . Width of the opening
W2 ．．．第一膜層於罩幕層上之寬度W 2 . . . The width of the first film layer on the mask layer
W3 ．．．第二膜層於罩幕層上之寬度W 3 . . . The width of the second film layer on the mask layer
t1 ．．．第一膜層於罩幕層上之厚度t 1 . . . Thickness of the first film layer on the mask layer
t2 ．．．第二膜層於罩幕層上之厚度t 2 . . . Thickness of the second film layer on the mask layer
第1圖為一示意圖，顯示了採用磊晶側向成長(ELO)之一剖面情形，其藉由於溝槽內採用深寬比捕捉技術(ART)並使用摻質而得到控制；Figure 1 is a schematic diagram showing a profile using epitaxial lateral growth (ELO), which is controlled by the use of an aspect ratio capture technique (ART) and the use of dopants;
第2圖為一示意圖，顯示了具有於溝槽內採用深寬比捕捉技術(ART)之重複移除與再成長膜層之磊晶側向成長(ELO)之一剖面情形；Figure 2 is a schematic diagram showing a profile of epitaxial lateral growth (ELO) with repeated removal and re-growth of the film using an aspect ratio capture technique (ART);
第3圖為一示意圖，顯示了於溝槽內利用深寬比捕捉技術(ART)之半導體材料之磊晶側向成長(ELO)之剖面情形；Figure 3 is a schematic diagram showing the profile of epitaxial lateral growth (ELO) of a semiconductor material utilizing an aspect ratio capture technique (ART) in a trench;
第4圖為一示意圖，顯示了採用深寬比捕捉(ART)與磊晶側向成長(ELO)等技術所形成之太陽能電池之剖面情形；Figure 4 is a schematic diagram showing the profile of a solar cell formed by techniques such as aspect ratio capture (ART) and epitaxial lateral growth (ELO);
第5a圖與第5b圖為一系列示意圖，顯示了成長於鍺之深寬比捕捉(ART)與磊晶側向成長(ELO)基板上之反向型太陽能電池之剖面情形。Figures 5a and 5b are a series of schematic diagrams showing the profile of a reverse solar cell grown on a deep aspect ratio capture (ART) and an epitaxial lateral growth (ELO) substrate.
100．．．基板100. . . Substrate
102．．．罩幕層102. . . Mask layer
103．．．差排缺陷103. . . Differential defect
104．．．開口104. . . Opening
106．．．第一膜層106. . . First film
108．．．第二膜層108. . . Second film
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