TWI431626B - Data storage device and method for combining block pairs of a flash memory - Google Patents
Data storage device and method for combining block pairs of a flash memory Download PDFInfo
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Description
本發明係有關於記憶體，特別是有關於快閃記憶體。The present invention relates to memory, and more particularly to flash memory.
第1圖為主機傳送寫入命令至一資料儲存裝置的時序圖。假設該資料儲存裝置包括一快閃記憶體以供儲存資料。當一主機欲將資料寫入至一資料儲存裝置，首先會經由輸入/輸出資料匯流排傳送第一寫入命令(0x80)至資料儲存裝置。接著，主機依序向資料儲存裝置傳送列位址及行位址，以指明資料欲存入之位址。接著主機向資料儲存裝置傳送欲寫入快閃記憶體之資料，並向資料儲存裝置傳送第二寫入命令(0x10)。當第二寫入命令傳送完畢，資料儲存裝置會將一待命/忙碌(ready/busy)導線之電位下拉，以阻止主機繼續發送後續命令或資料。一般而言，資料儲存裝置的控制器便於此段電位下拉時間Tprog 依據寫入命令完成資料之寫入。依資料儲存裝置與主機間資料傳送之規格，此段處理時間Tprog 不可長於250ms。待資料寫入完畢之後，資料儲存裝置會將待命/忙碌導線之電位上拉。主機便接著傳送一讀取狀態(read status)命令，以向資料儲存裝置詢問資料寫入是否成功。Figure 1 is a timing diagram of the host transmitting a write command to a data storage device. It is assumed that the data storage device includes a flash memory for storing data. When a host wants to write data to a data storage device, the first write command (0x80) is first transmitted to the data storage device via the input/output data bus. Then, the host sequentially transmits the column address and the row address to the data storage device to indicate the address to which the data is to be stored. The host then transmits the data to be written to the flash memory to the data storage device and transmits a second write command (0x10) to the data storage device. When the second write command is transmitted, the data storage device pulls down the potential of a ready/busy wire to prevent the host from continuing to send subsequent commands or data. In general, the controller of the data storage device facilitates the writing of the data by the step-down period T prog according to the write command. Depending on the specification data transfer between the host and the data storage device, the processing time T prog this paragraph is not longer than 250ms. After the data has been written, the data storage device will pull up the potential of the standby/busy wire. The host then transmits a read status command to ask the data storage device if the data write was successful.
快閃記憶體通常包括多個區塊(block)，而每一區塊包括多個頁(page)以供儲存資料。通常一頁僅能夠被寫入一次資料，若要將該頁的資料更新，則必須將整個區塊的所有頁所儲存的資料一併抹除，才能再次將資料寫入該頁。因此，當資料儲存裝置欲執行寫入命令時，若主機指定的寫入位址所對應的頁之前已儲存資料，資料儲存裝置必須將新接收的更新資料寫入至一空白區塊，再建立該空白區塊與寫入位址所對應的原本區塊間之對應關係。此一對應關係稱之為區塊配對(block pair)，原本區塊稱為區塊配對的母區塊(mother block)，而儲存更新資料之區塊稱為區塊配對的子區塊(child block)。Flash memory typically includes a plurality of blocks, and each block includes a plurality of pages for storing data. Usually, a page can only be written once. To update the data of the page, the data stored in all pages of the entire block must be erased together to write the data to the page again. Therefore, when the data storage device is to execute the write command, if the data corresponding to the page corresponding to the write address specified by the host has been stored, the data storage device must write the newly received update data to a blank block, and then establish The correspondence between the blank block and the original block corresponding to the write address. This correspondence is called a block pair. The original block is called the mother block of the block pairing, and the block storing the updated data is called the block paired sub-block (child Block).
一般而言，由於維持一區塊配對需額外紀錄許多配對關係，因此資料儲存裝置必須控制區塊配對的數目，使快閃記憶體中僅儲存固定數目的區塊配對。在一般的情況下，資料儲存裝置可以於250ms的處理時段Tprog 內將所接收的資料寫入至快閃記憶體內。然而，當執行主機傳送的寫入命令需要新增一區塊配對時，為了使快閃記憶體中的區塊配對數目維持固定，必須於執行主機傳送的寫入命令之前，先將快閃記憶體的部份區塊配對所包含的母區塊所儲存的原始資料與子區塊所儲存的更新資料相整合為單一區塊，以便先使原本的區塊配對數目下降，接著才能執行主機傳送的寫入命令而新增區塊配對。In general, since maintaining a block pairing requires an additional record of many pairing relationships, the data storage device must control the number of block pairs so that only a fixed number of block pairs are stored in the flash memory. In the general case, the data storage device can write the received data into the flash memory within the processing period T prog of 250 ms. However, when a write command to perform host transfer requires a new block pairing, in order to keep the number of block pairs in the flash memory fixed, it is necessary to flash the memory before executing the write command transmitted by the host. The original data stored in the parent block included in the partial block pair is integrated into the single block in the updated data stored in the sub-block, so that the original block pair number is reduced first, and then the host transfer can be performed. New block pairing with the write command.
再者，由於每一區塊均包含許多頁以儲存資料，整合區塊配對的母區塊與子區塊之資料需耗費許多時間。尤其是當快閃記憶體為多層單元(multi-level-cell,MLC)快閃記憶體或三層單元(three-level-cell,TLC)快閃記憶體時，快閃記憶體的每一區塊所儲存的資料量龐大，而整合區塊配對的母區塊與子區塊之資料需耗費更多時間，常常無法於短短的250ms處理時段內完成，而無法達成資料儲存裝置與主機間資料傳送的規格之要求。因此，需要一種寫入資料至快閃記憶體的方法，以解決上述問題。Moreover, since each block contains many pages to store data, it takes a lot of time to integrate the data of the parent block and the sub-blocks of the block pairing. Especially when the flash memory is a multi-level-cell (MLC) flash memory or a three-level-cell (TLC) flash memory, each area of the flash memory The amount of data stored in the block is huge, and the data of the parent block and the sub-block paired by the integrated block takes more time, and often cannot be completed in a short processing period of 250 ms, and the data storage device and the host cannot be reached. Specification of data transfer specifications. Therefore, there is a need for a method of writing data to flash memory to solve the above problems.
有鑑於此，本發明之目的在於提供一種整合快閃記憶體之區塊配對的方法，以解決習知技術存在之問題。首先，自該快閃記憶體之多個區塊配對選取一目標區塊配對以供整合。接著，將該目標區塊配對之母區塊所儲存的資料分為多個資料區段。接著，選取該快閃記憶體之一空白區塊作為儲存該目標區塊配對之整合資料的一整合區塊。接著，自一主機接收多個寫入命令。接著，於該等寫入命令所對應之多個處理時段內，分別將該等資料區段與該目標區塊配對之子區塊儲存之更新資料整合並寫入該整合區塊。In view of the above, it is an object of the present invention to provide a method for integrating block pairing of flash memory to solve the problems of the prior art. First, a target block pair is selected for integration from a plurality of block pairs of the flash memory. Then, the data stored in the parent block of the target block pair is divided into a plurality of data sections. Then, one of the blank blocks of the flash memory is selected as an integrated block for storing the integrated data of the target block pair. Next, multiple write commands are received from a host. Then, in the plurality of processing periods corresponding to the write commands, the update data stored in the sub-blocks of the data segment and the target block are respectively integrated and written into the integrated block.
本發明提供一種資料儲存裝置，耦接至一主機。於一實施例中，該資料儲存裝置包括一快閃記憶體以及一控制器。該快閃記憶體包括一資料暫存區塊以及多個區塊配對(block pair)。該控制器自該快閃記憶體之該等區塊配對選取一目標區塊配對以供整合，將該目標區塊配對之母區塊所儲存的資料分為多個資料區段，選取該快閃記憶體之一空白區塊作為儲存該目標區塊配對之整合資料的一整合區塊，自該主機接收多個寫入命令，以及於該等寫入命令所對應之多個處理時段內分別將該等資料區段與該目標區塊配對之子區塊儲存之更新資料整合並寫入該整合區塊。The invention provides a data storage device coupled to a host. In one embodiment, the data storage device includes a flash memory and a controller. The flash memory includes a data temporary storage block and a plurality of block pairs. The controller selects a target block pair from the block pair of the flash memory for integration, and divides the data stored in the parent block of the target block into a plurality of data segments, and selects the fast a blank block of the flash memory as an integrated block storing the integrated data of the target block pair, receiving a plurality of write commands from the host, and respectively performing a plurality of processing periods corresponding to the write commands The data sections are updated with the updated data stored in the sub-blocks of the target block and written into the integrated block.
為了讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉數較佳實施例，並配合所附圖示，作詳細說明如下：The above and other objects, features, and advantages of the present invention will become more apparent and understood.
第2圖為依據本發明之資料儲存裝置204之區塊圖。資料儲存裝置204耦接至一主機202，並依據主機202之指示存取資料。於一實施例中，資料儲存裝置204包括控制器212、快閃記憶體214、以及隨機存取記憶體216。快閃記憶體214包含多個區塊(block)以供儲存資料，該等區塊包括一資料暫存區塊222。快閃記憶體214尚包含多組區塊配對224。每一區塊配對包含一母區塊(mother block)及一子區塊(child block)，該母區塊儲存一邏輯區塊位址之原始資料，而該子區塊儲存該邏輯區塊位址之更新資料。例如，母區塊231與對應的子區塊241為一組區塊配對，而母區塊23k與對應的子區塊24k為另一組區塊配對。隨機存取記憶體216儲存一位址儲存表220。於一實施例中，資料儲存裝置204為一記憶卡。Figure 2 is a block diagram of a data storage device 204 in accordance with the present invention. The data storage device 204 is coupled to a host 202 and accesses data according to the instructions of the host 202. In one embodiment, the data storage device 204 includes a controller 212, a flash memory 214, and a random access memory 216. The flash memory 214 includes a plurality of blocks for storing data, and the blocks include a data temporary storage block 222. Flash memory 214 also includes multiple sets of block pairs 224. Each block pair includes a mother block and a child block, the parent block stores the original data of a logical block address, and the sub-block stores the logical block bit. Update information of the address. For example, the parent block 231 is paired with the corresponding sub-block 241 for a group of blocks, and the parent block 23k is paired with the corresponding sub-block 24k for another group of blocks. The random access memory 216 stores the address storage table 220. In one embodiment, the data storage device 204 is a memory card.
由於紀錄區塊配對的母區塊的各頁原始資料與子區塊的各頁更新資料之對應關係需要佔據大量的資料儲存空間，為了有效運用隨機存取記憶體216的資料儲存空間，控制器212會將快閃記憶體214內的區塊配對數目限制在一界限值N。當快閃記憶體214內的區塊配對數目K即將超過界限值N時，控制器212便會自快閃記憶體214的多組區塊配對224中選取一組目標區塊配對，然後將目標區塊配對的母區塊所儲存之原始資料與子區塊所儲存之更新資料整合後儲存入一整合區塊中，然後將原本的目標區塊配對之母區塊與子區塊之資料抹除。如此快閃記憶體214的區塊配對數目K便可維持在不超過界限值N。Since the correspondence between the original data of the parent block of the record block and the update data of each page of the sub-block needs to occupy a large amount of data storage space, in order to effectively use the data storage space of the random access memory 216, the controller 212 limits the number of block pairs in flash memory 214 to a threshold value of N. When the number of block pairs K in the flash memory 214 is about to exceed the threshold value N, the controller 212 selects a group of target block pairs from the plurality of sets of block pairs 224 of the flash memory 214, and then targets the target. The original data stored in the parent block of the block pair is integrated with the updated data stored in the sub-block and stored in an integrated block, and then the data of the parent block and the sub-block paired with the original target block are wiped. except. Thus, the number K of block pairs of the flash memory 214 can be maintained at a limit value N.
當執行一寫入命令會造成控制器212於快閃記憶體214中新增一組區塊配對時，而快閃記憶體214中的區塊配對數目N已達界限值K時，為了避免區塊配對之數目K超過界限值N，控制器212必須先選取一目標區塊配對進行整合以使區塊配對數目K下降，才能執行寫入命令並增加區塊配對數目，以維持區塊配對數目K不超過界限值N。然而，整合一目標區塊配對的母區塊與子區塊為一整合區塊需要耗費較長的時間，通常此段整合時間會超過第1圖中所示之處理時間Tprog 的250ms，例如可能為1000ms。此時，控制器212便先將目前接收的寫入位址儲存入隨機存取記憶體216的一位址儲存表220中，並將目前接收的寫入資料儲存入快閃記憶體214的一資料暫存區塊222中。接著，控制器212將目標區塊配對的母區塊中所儲存的資料分為數個資料區段，利用資料儲存裝置204自主機202接收多個後續寫入命令所對應的多個250ms處理時間分別將數個資料區段的其中之一與子區塊中儲存的更新資料進行整合，其中每一資料區段之整合時間不超過規格所規定的250ms。如此控制器212便能將目標區塊配對的母區塊與子區塊整合完畢以維持區塊配對數目不變，又能符合主機202與資料儲存裝置204間執行寫入命令的規格要求。When a write command is executed, the controller 212 adds a group of block pairs to the flash memory 214, and when the number of block pairs N in the flash memory 214 has reached the limit value K, in order to avoid the area The number of block pairs K exceeds the threshold value N, and the controller 212 must first select a target block pair for integration to reduce the number of block pairs K to execute the write command and increase the number of block pairs to maintain the number of block pairs. K does not exceed the limit value N. However, it takes a long time to integrate the parent block and the sub-block of a target block into one integrated block. Usually, the integration time will exceed 250 ms of the processing time T prog shown in FIG. 1 , for example, May be 1000ms. At this time, the controller 212 first stores the currently received write address into the address storage table 220 of the random access memory 216, and stores the currently received write data into the flash memory 214. The data is temporarily stored in block 222. Then, the controller 212 divides the data stored in the parent block of the target block into a plurality of data segments, and uses the data storage device 204 to receive a plurality of 250 ms processing times corresponding to the plurality of subsequent write commands from the host 202 respectively. One of the data sections is integrated with the updated data stored in the sub-blocks, wherein the integration time of each data section does not exceed 250 ms as specified by the specification. Thus, the controller 212 can integrate the parent block paired with the child block to maintain the number of block pairs, and can meet the specification requirements for executing the write command between the host 202 and the data storage device 204.
第3圖為依據本發明整合區塊配對的方法300之流程圖。首先，控制器212自快閃記憶體214之多個區塊配對224選取一目標區塊配對供整合。假設控制器所選取的目標區塊配對為區塊231及241。接著，控制器212將目標區塊配對之母區塊所儲存的資料分為多個資料區段。於一實施例中，資料區段的數目必須大於整合一區塊配對所需的處理時間除以一寫入命令之處理時間Tprog 所得到之商數值。舉例來說，若整合一區塊配對需要的時間為700ms，而以一寫入命令之處理時間Tprog 為250ms，則資料區段的數目為3(≧700/250)。因此，控制器212將目標區塊配對之母區塊231所儲存的資料分為三個資料區段。Figure 3 is a flow diagram of a method 300 of integrating block pairing in accordance with the present invention. First, the controller 212 selects a target block pair for integration from the plurality of block pairs 224 of the flash memory 214. It is assumed that the target blocks selected by the controller are paired into blocks 231 and 241. Next, the controller 212 divides the data stored in the parent block of the target block pair into a plurality of data segments. In one embodiment, the number of data segments must be greater than the quotient value obtained by integrating the processing time required to integrate a block by the processing time T prog of a write command. For example, if the time required to integrate a block pairing is 700 ms, and the processing time T prog with a write command is 250 ms, the number of data segments is 3 (≧700/250). Therefore, the controller 212 divides the data stored in the parent block pair 231 of the target block into three data segments.
接著，控制器212自快閃記憶體214選取一空白區塊作為儲存該目標區塊配對之整合資料的一整合區塊(步驟306)。接著，控制器212自主機202接收寫入命令、寫入位址、及寫入資料(步驟308)。接著，控制器212決定是否執行該寫入命令需新建一區塊配對(步驟310)。若執行該寫入命令不需新增一區塊配對，則控制器212直接將寫入資料寫入該寫入位址所對應之區塊(步驟314)。反之，若執行該寫入命令需要新增一區塊配對，則控制器212將該寫入位址存入一位址儲存表220，並將該寫入資料存入快閃記憶體214之一資料暫存區塊222(步驟312)。舉例來說，若寫入位址所對應的區塊之頁已儲存有資料，而該區塊尚未具有用以儲存更新資料之子區塊，則欲執行該寫入命令必須新增該區塊所對應之子區塊以供儲存該寫入資料，導致新增一組區塊配對。然而，當尚未整合一區塊配對完畢之前，區塊配對的數目無法再增加，因此必須於步驟312先將該寫入位址存入位址儲存表220，待區塊配對整合完畢再依據位址儲存表220儲存的寫入位址將寫入資料寫入快閃記憶體214。Next, the controller 212 selects a blank block from the flash memory 214 as an integrated block for storing the integrated data of the target block pair (step 306). Controller 212 then receives a write command, writes an address, and writes data from host 202 (step 308). Next, the controller 212 determines whether to perform the write command to create a new block pair (step 310). If the write command is executed without adding a block pair, the controller 212 directly writes the write data to the block corresponding to the write address (step 314). On the other hand, if a new block pairing is required to execute the write command, the controller 212 stores the write address in the address storage table 220, and stores the write data in one of the flash memory 214. Data temporary storage block 222 (step 312). For example, if the page of the block corresponding to the write address has stored data, and the block does not have a sub-block for storing the update data, the block must be added to execute the write command. The corresponding sub-block is used for storing the written data, resulting in a new set of block pairing. However, the number of block pairs cannot be increased until the integration of one block has been completed. Therefore, the write address must be stored in the address storage table 220 in step 312, and the block pairing is integrated and then based on the bit. The write address stored in the address storage table 220 writes the write data to the flash memory 214.
接著，控制器212自目標區塊配對之母區塊的多個資料區段選取一待整合資料區段(步驟316)。接著，控制器212於該寫入命令所對應之處理時段內，將該待整合資料區段與目標區塊配對之子區塊儲存之更新資料整合為一整合資料區段，並將該整合資料區段寫入該整合區塊(步驟318)。接著，控制器212檢查是否目標區塊配對之母區塊的所有資料區段均已整合完畢並寫入整合區塊(步驟320)。若否，則控制器212繼續自主機202接收後續寫入命令(步驟308)，並利用後續寫入命令所對應的處理時段，繼續將目標區塊配對的母區塊的其他資料區段與目標區塊配對之子區塊儲存之更新資料相整合並寫入該整合區塊(步驟318)，直到目標區塊配對之母區塊的所有資料區段均已整合完畢並寫入整合區塊為止(步驟320)。最後，由於目標區塊配對之母區塊及子區塊所儲存之資料已整合入整合區塊中，控制器212抹除目標區塊配對之母區塊及子區塊所儲存之資料(步驟320)，從而使快閃記憶體214之區塊配對數目減少一。Next, the controller 212 selects a data segment to be consolidated from the plurality of data segments of the parent block of the target block pair (step 316). Then, the controller 212 integrates the updated data stored in the sub-block paired with the target block into the integrated data segment in the processing period corresponding to the write command, and integrates the integrated data region. The segment is written to the integration block (step 318). Next, the controller 212 checks if all of the data sectors of the parent block paired target block have been integrated and written to the integrated block (step 320). If not, the controller 212 continues to receive subsequent write commands from the host 202 (step 308), and continues to use the processing period corresponding to the subsequent write command to continue to other data segments and targets of the parent block paired with the target block. The updated data of the sub-block storage of the block pairing is integrated and written into the integrated block (step 318) until all the data sections of the parent block of the target block pair have been integrated and written into the integrated block ( Step 320). Finally, since the data stored in the parent block and the sub-block of the target block pair has been integrated into the integrated block, the controller 212 erases the data stored in the parent block and the sub-block of the target block pair (steps) 320), thereby reducing the number of block pairs of the flash memory 214 by one.
第4圖為對應於第3圖之方法300的整合快閃記憶體214的多個區塊配對之示意圖。假設快閃記憶體214共有區塊配對30、區塊配對31、區塊配對60、區塊配對82等4組區塊配對，而控制器212挑選區塊配對30作為目標區塊配對以進行整合。假設控制器212將目標區塊配對30之母區塊的資料分為三個資料區段以分別進行資料整合。控制器212首先自主機202接收第一寫入命令，並於第一寫入命令的處理時間250ms內將區塊配對30之母區塊的第一資料區段與子區塊之更新資料進行整合以得到第一整合資料區段4A，並將第一整合資料區段4A寫入區塊配對30之整合區塊。接著，控制器212自主機202接收第二寫入命令，並於第二寫入命令的處理時間250ms內將區塊配對30之母區塊的第二資料區段與子區塊之更新資料進行整合以得到第二整合資料區段4B，並將第二整合資料區段4B寫入區塊配對30之整合區塊。接著，控制器212自主機202接收第三寫入命令，並於第三寫入命令的處理時間250ms內將區塊配對30之母區塊的第三資料區段與子區塊之更新資料進行整合以得到第三整合資料區段4C，並將第三整合資料區段4C寫入區塊配對30之整合區塊，從而完成區塊配對30之資料整合。接著，控制器212便可將區塊配對30的母區塊與子區塊的資料清除，以使快閃記憶體214之區塊配對數目減一。4 is a schematic diagram of multiple block pairings of integrated flash memory 214 corresponding to method 300 of FIG. It is assumed that the flash memory 214 has a total of four block pairs such as block pairing 30, block pairing 31, block pairing 60, and block pairing 82, and the controller 212 selects the block pairing 30 as the target block pairing for integration. . It is assumed that the controller 212 divides the data of the parent block of the target block pair 30 into three data sections for data integration, respectively. The controller 212 first receives the first write command from the host 202, and integrates the first data segment of the parent block of the block pair 30 with the update data of the sub-block within 250 ms of the processing time of the first write command. The first integrated data section 4A is obtained, and the first integrated data section 4A is written into the integrated block of the block pair 30. Then, the controller 212 receives the second write command from the host 202, and performs the update data of the second data segment and the sub-block of the parent block of the block pair 30 within 250 ms of the processing time of the second write command. The integration is to obtain the second integrated material section 4B, and the second integrated data section 4B is written into the integrated block of the block pairing 30. Then, the controller 212 receives the third write command from the host 202, and performs the third data segment of the parent block of the block pair 30 and the update data of the sub-block within 250 ms of the processing time of the third write command. Integration is performed to obtain the third integrated data section 4C, and the third integrated data section 4C is written into the integrated block of the block pairing 30, thereby completing data integration of the block pairing 30. Then, the controller 212 can clear the data of the parent block and the sub-block of the block pair 30 to reduce the number of block pairs of the flash memory 214 by one.
同樣的，假設控制器212更接著挑選區塊配對31作為目標區塊配對以進行整合。同樣地，假設控制器212將目標區塊配對31之母區塊的資料分為三個資料區段以分別進行資料整合。控制器212首先自主機202接收第四寫入命令，並於第四寫入命令的處理時間250ms內將區塊配對31之母區塊的第一資料區段與子區塊之更新資料進行整合以得到第一整合資料區段4D，並將第一整合資料區段4D寫入區塊配對31之整合區塊。接著，控制器212自主機202接收第五寫入命令，並於第五寫入命令的處理時間250ms內將區塊配對31之母區塊的第二資料區段與子區塊之更新資料進行整合以得到第二整合資料區段4E，並將第二整合資料區段4E寫入區塊配對31之整合區塊。接著，控制器212自主機202接收第六寫入命令，並於第六寫入命令的處理時間250ms內將區塊配對31之母區塊的第三資料區段與子區塊之更新資料進行整合以得到第三整合資料區段4F，並將第三整合資料區段4F寫入區塊配對31之整合區塊，從而完成區塊配對31之資料整合。接著，控制器212便可將區塊配對31的母區塊與子區塊的資料清除，以使快閃記憶體214之區塊配對數目再減一。Similarly, assume that controller 212 then selects block pair 31 as the target block pair for integration. Similarly, it is assumed that the controller 212 divides the data of the parent block of the target block pair 31 into three data sections to perform data integration, respectively. The controller 212 first receives the fourth write command from the host 202, and integrates the first data segment of the parent block of the block pair 31 with the update data of the sub-block within 250 ms of the processing time of the fourth write command. The first integrated data section 4D is obtained, and the first integrated data section 4D is written into the integrated block of the block pair 31. Next, the controller 212 receives the fifth write command from the host 202, and performs the update data of the second data segment and the sub-block of the parent block of the block pair 31 within 250 ms of the processing time of the fifth write command. The integration is to obtain the second integrated data section 4E, and the second integrated data section 4E is written into the integrated block of the block pair 31. Next, the controller 212 receives the sixth write command from the host 202, and performs the third data segment of the parent block of the block pair 31 and the updated data of the sub-block within 250 ms of the processing time of the sixth write command. The integration is performed to obtain the third integrated data section 4F, and the third integrated data section 4F is written into the integrated block of the block pair 31, thereby completing data integration of the block pairing 31. Then, the controller 212 can clear the data of the parent block and the sub-block of the block pair 31, so that the number of block pairs of the flash memory 214 is further reduced by one.
第5圖為依據本發明之位址儲存表500的一實施例。當控制器212自主機202依序接收多筆寫入命令後，控制器212便將該等寫入命令所對應的寫入位址儲存入位址儲存表500。位址儲存表500包括多個儲存單元，每一儲存單元可儲存一筆寫入位址。每一儲存單元更具有一對應的儲存旗標，以表示是否該儲存單元有儲存寫入位址。於一實施例中，當儲存旗標之值為1，表示對應的儲存單元儲存有寫入位址；當儲存旗標之值為0，表示對應的儲存單元並無儲存寫入位址。位址儲存表500更包括一儲存指標及一清理指標。儲存指標指向位址儲存表500之可供儲存下一個寫入位址的儲存單元，而清理指標指向位址儲存表500之儲存有下一個待清除的寫入位址的儲存單元。於一實施例中，儲存指標會自動於位址儲存表500中搜尋儲存旗標為0的儲存單元。當控制器212欲將自主機所接收的寫入命令儲存入位址儲存表500，便將寫入命令存入儲存指標所指向的儲存單元。於一實施例中，清理指標會自動於位址儲存表500中搜尋儲存有對應於最高頻率之區塊序號之寫入位址的儲存單元。當控制器212欲將自位址儲存表500清除寫入位址時，便由儲存指標所指向的儲存單元讀取寫入位址，再依寫入位址將資料暫存區塊222所暫存之資料寫入快閃記憶體214。Figure 5 is an embodiment of an address storage table 500 in accordance with the present invention. After the controller 212 sequentially receives a plurality of write commands from the host 202, the controller 212 stores the write addresses corresponding to the write commands into the address storage table 500. The address storage table 500 includes a plurality of storage units, each of which stores a write address. Each storage unit further has a corresponding storage flag to indicate whether the storage unit has a storage write address. In one embodiment, when the value of the storage flag is 1, it indicates that the corresponding storage unit stores the write address; when the value of the storage flag is 0, it indicates that the corresponding storage unit does not store the write address. The address storage table 500 further includes a storage indicator and a cleaning indicator. The storage indicator points to the storage unit of the address storage table 500 for storing the next write address, and the cleanup indicator points to the storage unit of the address storage table 500 storing the next write address to be cleared. In an embodiment, the storage indicator automatically searches for the storage unit with the storage flag of 0 in the address storage table 500. When the controller 212 wants to store the write command received from the host into the address storage table 500, the write command is stored in the storage unit pointed to by the storage indicator. In an embodiment, the cleanup indicator automatically searches the address storage table 500 for the storage unit storing the write address corresponding to the block number of the highest frequency. When the controller 212 wants to clear the write address from the address storage table 500, the write address is read by the storage unit pointed to by the storage indicator, and the data temporary storage block 222 is temporarily placed according to the write address. The stored data is written to the flash memory 214.
第6圖為依據本發明之清除位址儲存表所儲存之寫入位址的方法600的流程圖。首先，控制器212決定位址儲存表所儲存的多筆寫入位址所對應的多個待寫入區塊(步驟602)。舉例來說，位址儲存表500所儲存的多個寫入位址所對應的待寫入區塊包括區塊150、200、133、以及167。接著，控制器212計算多個待寫入區塊於位址儲存表中所對應之寫入位址之數目(步驟604)。例如，控制器212可計算得到區塊150、200、133、以及167於位址儲存表500所儲存的寫入位址之數目分別為4、2、3、1。接著，控制器212自多個待寫入區塊中選取具有最大之寫入位址數目的一目標待寫入區塊(步驟606)。因此，控制器212選取對應最大之寫入位址數目4的區塊150為目標待寫入區塊。Figure 6 is a flow diagram of a method 600 of clearing a write address stored in an address storage table in accordance with the present invention. First, the controller 212 determines a plurality of blocks to be written corresponding to the plurality of write addresses stored in the address storage table (step 602). For example, the to-be-written block corresponding to the plurality of write addresses stored in the address storage table 500 includes the blocks 150, 200, 133, and 167. Next, the controller 212 calculates the number of write addresses corresponding to the plurality of blocks to be written in the address storage table (step 604). For example, the controller 212 can calculate that the number of write addresses stored in the address storage table 500 by the blocks 150, 200, 133, and 167 are 4, 2, 3, 1, respectively. Next, the controller 212 selects a target to-be-written block having the largest number of write addresses from the plurality of blocks to be written (step 606). Therefore, the controller 212 selects the block 150 corresponding to the largest number of write address numbers 4 as the target to be written block.
接著，控制器212自快閃記憶體214取得一空白區塊作為該目標待寫入區塊之子區塊(步驟608)。接著，控制器212依據位址儲存表500中對應於目標待寫入區塊的寫入位址將資料暫存區塊222中欲寫入該目標待寫入區塊之資料寫入至目標待寫入區塊之子區塊(步驟610)。由於位址儲存表500中對應於目標待寫入區塊500的寫入位址共有4筆，分別寫入至區塊150的第4頁、第5頁、第6頁、第7頁，因此此時控制器212將由資料暫存區塊222中取出的資料寫入區塊150的之子區塊以儲存區塊150的第4頁、第5頁、第6頁、第7頁之更新資料。接著，控制器212自位址儲存表500中刪除對應於目標待寫入區塊500之多個寫入位址(步驟612)。第7圖為對應於第6圖之方法600的於清除第5圖之位址儲存表500之寫入位址後新增快閃記憶體214的多個區塊配對之示意圖。假設快閃記憶體214原有區塊配對60及區塊配對82等2組區塊配對。當自位址儲存表500清除對應於區塊150的4筆寫入位址後，快閃記憶體214中新增一個區塊配對150，其中區塊配對150的子區塊儲存了區塊150的第4頁、第5頁、第6頁、第7頁之更新資料。Next, the controller 212 retrieves a blank block from the flash memory 214 as a sub-block of the target to-be-written block (step 608). Then, the controller 212 writes, according to the write address of the address storage table 500 corresponding to the target to-be-written block, the data to be written into the target to-be-written block in the data temporary storage block 222 to the target to be written. A sub-block of the block is written (step 610). Since the write address corresponding to the target to-be-written block 500 in the address storage table 500 has four pens, it is written to the fourth page, the fifth page, the sixth page, and the seventh page of the block 150, respectively. At this time, the controller 212 writes the data extracted from the data temporary storage block 222 into the sub-block of the block 150 to store the updated data of the fourth page, the fifth page, the sixth page, and the seventh page of the block 150. Next, the controller 212 deletes a plurality of write addresses corresponding to the target to-be-written block 500 from the address storage table 500 (step 612). FIG. 7 is a schematic diagram of a plurality of block pairs added to the flash memory 214 after clearing the write address of the address storage table 500 of FIG. 5 corresponding to the method 600 of FIG. Assume that the flash memory 214 is paired with the original block pair 60 and the block pair 82. When the self-address storage table 500 clears the four write addresses corresponding to the block 150, a block pair 150 is added to the flash memory 214, wherein the sub-block of the block pair 150 stores the block 150. Updates on pages 4, 5, 6, and 7.
接著，控制器212檢查是否位址儲存表500中尚有寫入位址待寫入(步驟614)。由於位址儲存表500中對應於區塊150的4筆寫入位址已被清除，因此目前位址儲存表500中尚有對應於區塊200、133、及167的寫入位址，其中對應於區塊133的寫入位址數目為最多。因此，控制器212繼續選取對應最大之寫入位址數目3的區塊133為目標待寫入區塊(步驟606)，並依據位址儲存表500之寫入位址將由資料暫存區塊222中取出的資料寫入區塊133的之子區塊以儲存區塊133的第34頁、第35頁、第36頁之更新資料(步驟610)。見第7圖，當自位址儲存表500清除對應於區塊133的3筆寫入位址後，快閃記憶體214中新增了一個區塊配對133，其中區塊配對133的子區塊儲存了區塊133的第34頁、第35頁、第36頁之更新資料。步驟606~612的迴圈將持續進行直到位址儲存表500中的寫入位址均被清除完畢為止。Next, the controller 212 checks if there is still a write address to be written in the address storage table 500 (step 614). Since the four write addresses corresponding to the block 150 in the address storage table 500 have been cleared, the current address storage table 500 still has write addresses corresponding to the blocks 200, 133, and 167, wherein The number of write addresses corresponding to block 133 is the most. Therefore, the controller 212 continues to select the block 133 corresponding to the maximum number of write address numbers 3 as the target to be written block (step 606), and the write address according to the address storage table 500 will be used by the data temporary storage block. The data fetched in 222 is written to the sub-block of block 133 to store the updated data on pages 34, 35, and 36 of block 133 (step 610). Referring to FIG. 7, when the self-address storage table 500 clears the three write addresses corresponding to the block 133, a block pair 133 is added to the flash memory 214, and the sub-area of the block pair 133 is added. The block stores the updated information on pages 34, 35, and 36 of block 133. The loop of steps 606-612 will continue until the write address in the address storage table 500 is cleared.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技術者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
202．．．主機202. . . Host
204．．．資料儲存裝置204. . . Data storage device
212．．．控制器212. . . Controller
214．．．快閃記憶體214. . . Flash memory
216．．．隨機存取記憶體216. . . Random access memory
220．．．位址儲存表220. . . Address storage table
222．．．資料暫存區塊222. . . Data temporary storage block
224．．．區塊配對224. . . Block pairing
231、232、…、23k、241、242、…、24k．．．區塊231, 232, ..., 23k, 241, 242, ..., 24k. . . Block
30、31、60、82．．．區塊配對30, 31, 60, 82. . . Block pairing
150、133、60、82．．．區塊配對150, 133, 60, 82. . . Block pairing
第1圖為主機傳送寫入命令至一資料儲存裝置的時序圖；Figure 1 is a timing diagram of a host transmitting a write command to a data storage device;
第2圖為依據本發明之資料儲存裝置之區塊圖；Figure 2 is a block diagram of a data storage device in accordance with the present invention;
第3圖為依據本發明整合區塊配對的方法之流程圖；Figure 3 is a flow chart of a method for integrating block pairing according to the present invention;
第4圖為對應於第3圖之方法的整合快閃記憶體的多個區塊配對之示意圖；Figure 4 is a schematic diagram of multiple block pairing of integrated flash memory corresponding to the method of Figure 3;
第5圖為依據本發明之位址儲存表的一實施例；Figure 5 is an embodiment of an address storage table in accordance with the present invention;
第6圖為依據本發明之清除位址儲存表所儲存之寫入位址的方法的流程圖；以及Figure 6 is a flow chart showing a method of clearing a write address stored in an address storage table in accordance with the present invention;
第7圖為對應於第6圖之方法的於清除第5圖之位址儲存表之寫入位址後新增快閃記憶體的多個區塊配對之示意圖。FIG. 7 is a schematic diagram showing a plurality of block pairs of the flash memory added after the write address of the address storage table of FIG. 5 is cleared corresponding to the method of FIG. 6.
Claims (19)
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