TWI426515B - Single port sram having a lower power voltage in writing operation - Google Patents
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本發明係有關於一種寫入操作時降低電源電壓之單埠SRAM(Static Random Access Memory，簡稱SRAM)，尤指一種可降低漏電流(leakage current)且能解決習知具單一位元線之單埠SRAM寫入邏輯1困難之單埠靜態隨機存取記憶體，同時即使於高記憶容量及/或高速操作時仍能具有高可靠性與高穩定性之寫入操作。The present invention relates to a static random access memory (SRAM) for reducing a power supply voltage during a write operation, and more particularly to a method for reducing leakage current and solving a single single bit line.埠SRAM writes logic 1 difficult static random access memory, while still having high reliability and high stability write operation even at high memory capacity and/or high speed operation.
隨機存取記憶體在電腦工業中扮演著無可或缺的角色，主要有動態隨機存取記憶體(DRAM)及靜態隨機存取記憶體(SRAM)兩種。動態隨機存取記憶體(DRAM)具有面積小及價格低等優點，但操作時必須不時地更新(refresh)以防止資料因漏電流而遺失，而導致存在有高速化困難及消耗功率大等缺失。相反地，靜態隨機存取記憶體(SRAM)的操作則較為簡易且毋須更新操作，因此具有高速化及消耗功率低等優點。Random access memory plays an indispensable role in the computer industry, mainly including dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory (DRAM) has the advantages of small area and low price, but it must be refreshed from time to time to prevent data from being lost due to leakage current, resulting in high speed and power consumption. Missing. Conversely, the operation of the static random access memory (SRAM) is simple and does not require an update operation, so it has the advantages of high speed and low power consumption.
目前以行動電話為代表之行動電子設備所採用之半導體記憶裝置，係以SRAM為主流。此乃由於SRAM待機電流小，適於連續通話時間、連續待機時間盡可能延長之手機。The semiconductor memory devices currently used in mobile electronic devices represented by mobile phones are mainly SRAM. This is due to the small standby current of the SRAM, which is suitable for mobile phones with continuous talk time and continuous standby time.
靜態隨機存取記憶體(SRAM)主要包括一記憶體陣列(memory array)，該記憶體陣列係由複數列記憶體晶胞(a plurality of rows of memory cells)與複數行記憶體晶胞(a plurality of columns of memory cells)所組成，每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶胞；複數條字元線(word line)，每一字元線對應至複數列記憶體晶胞中之一列；以及複數位元線對(bit line pairs)，每一位元線對係對應至複數行記憶體晶胞中之一行，且每一位元線對係由一位元線及一互補位元線所組成。A static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of columns of memory cells and a plurality of rows of memory cells (a). The plurality of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines, each word line corresponding to a column of a plurality of memory cells; and a plurality of bit line pairs, each bit line pair corresponding to one of the plurality of rows of memory cells, and each bit line pair is A meta-line and a complementary bit line are formed.
第1圖所示即是6T靜態隨機存取記憶體(SRAM)晶胞之電路示意圖，其中，PMOS電晶體P1和P2稱為負載電晶體(load transistor)，NMOS電晶體M1和M2稱為驅動電晶體(driving transistor)，NMOS電晶體M3和M4稱為存取電晶體(access transistor)，WL為字元線(word line)，而BL及BLB分別為位元線(bit line)及互補位元線(complementary bit line)，由於該SRAM晶胞需要6個電晶體，且驅動電晶體與存取電晶體間的電流驅動能力比(即單元比率(cell ratio)通常設定在2至3之間，而導致存在有高集積化困難及價格高等缺失。第1圖所示6T靜態隨機存取記憶體晶胞，於寫入操作時之HSPICE暫態分析模擬結果，如第2圖所示，其係以level 49模型且使用TSMC 0.35微米CMOS製程參數加以模擬。Figure 1 is a schematic diagram of a 6T static random access memory (SRAM) cell. The PMOS transistors P1 and P2 are called load transistors, and the NMOS transistors M1 and M2 are called drivers. Driving transistors, NMOS transistors M3 and M4 are called access transistors, WL is a word line, and BL and BLB are bit lines and complementary bits, respectively. A complementary bit line, since the SRAM cell requires six transistors, and the current drive capability ratio between the drive transistor and the access transistor (ie, the cell ratio is usually set between 2 and 3) However, there is a problem of high integration difficulty and high price. The 6T static random access memory cell shown in Fig. 1 shows the HSPICE transient analysis simulation result during the write operation, as shown in Fig. 2, The simulation was performed using the level 49 model and using TSMC 0.35 micron CMOS process parameters.
用來減少6T靜態隨機存取記憶體(SRAM)晶胞之電晶體數之一種方式係揭露於第3圖中。第3圖顯示一種僅具單一位元線之5T靜態隨機存取記憶體晶胞之電路示意圖，與第1圖之6T靜態隨機存取記憶體晶胞相比，此種5T靜態隨機存取記憶體晶胞比6T靜態隨機存取記憶體晶胞少一個電晶體及少一條位元線，惟該5T靜態隨機存取記憶體晶胞在不變更PMOS電晶體P1和P2以及NMOS電晶體M1、M2和M3的通道寬長比的情況下存在寫入邏輯1相當困難之問題。茲考慮記憶晶胞左側節點A原本儲存邏輯0的情況，由於節點A之電荷僅單獨自位元線(BL)傳送，因此很難將節點A中先前寫入的邏輯0蓋寫成邏輯1。第3圖所示5T靜態隨機存取記憶體晶胞，於寫入操作時之HSPICE暫態分析模擬結果，如第4圖所示，其係以level 49模型且使用TSMC 0.35微米CMOS製程參數加以模擬，由該模擬結果可証實，具單一位元線之5T靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T SRAM cell with only a single bit line. Compared with the 6T SRAM cell of Figure 1, the 5T static random access memory. The bulk cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T SRAM cell does not change the PMOS transistors P1 and P2 and the NMOS transistor M1. In the case of the channel width to length ratio of M2 and M3, there is a problem that writing logic 1 is quite difficult. Considering that the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A to logic 1. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is modeled using the level 49 model using TSMC 0.35 micron CMOS process parameters. Simulation, from the simulation results, it can be confirmed that the 5T SRAM cell with a single bit line has a problem that writing logic 1 is quite difficult.
迄今，有許多具單一位元線之5T靜態隨機存取記憶體晶胞之技術被提出，例如非專利文獻1(I. Carlson et al.,”A high density,low leakage,5T SRAM for embedded caches,”Solid-State Circuits Conference,2004. ESSCIRC 2004. Proceeding of the 30th European,pp.215-218,2004.)之5T SRAM由於係藉由重新設計晶胞中之二驅動電晶體、二負載電晶體以及一存取電晶體之通道寬長比以解決寫入邏輯1困難之問題，而造成破壞原有晶胞中之驅動電晶體與負載電晶體之對稱性關係並從而易受製程變異的影響；非專利文獻2(M. Wieckowski et al.,”A novel five-transistor(5T)sram cell for high performance cach,”IEEE Conference on SOC,pp.1001-1002,2005.)之5T SRAM由於係於晶胞中之二負載電晶體間設置一長通道長度之存取電晶體以解決寫入邏輯1困難之問題，而造成降低存取速度之缺失；專利文獻3(98年6月1日第TW M358390號)所提出之寫入操作時降低電源電壓之單埠SRAM(其主要代表圖如第5圖所示)雖可有效解決寫入邏輯1困難之問題，惟寫入操作時，由於高電壓節點(VH)在由高電源供應電壓(HVDD )下降至低電源供應電壓(LVDD )的過程中缺乏有效的放電路徑，而造成於高記憶容量及/或高速操作時存在低寫入可靠度與低寫入穩定度等問題，因此仍有改進空間。To date, many techniques have been proposed for a 5T SRAM cell with a single bit line, such as Non-Patent Document 1 (I. Carlson et al., "A high density, low leakage, 5T SRAM for embedded caches". , "Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, pp. 215-218, 2004.) The 5T SRAM is due to the redesign of the two of the unit cell, the two-load transistor And accessing the channel width-to-length ratio of the transistor to solve the problem of writing logic 1 is difficult, thereby causing damage to the symmetry relationship between the driving transistor and the load transistor in the original unit cell and thus being susceptible to process variation; 5T SRAM of Non-Patent Document 2 (M. Wieckowski et al., "A novel five-transistor (5T) sram cell for high performance cach," IEEE Conference on SOC, pp. 1001-1002, 2005.) A long channel length access transistor is disposed between the two load cells of the cell to solve the problem of difficulty in writing logic 1, and the loss of access speed is reduced. Patent Document 3 (June 1, 1998, TW M358390) No.) Reduce the power supply during the write operation proposed The pressure of the single port SRAM (as shown in FIG main representative of FIG. 5), although the time can solve the problem of writing a logic 1 difficulties, but a write operation, since the high voltage node (VH) by the high-voltage power supply (HV DD ) lacks an effective discharge path during the process of dropping to a low power supply voltage (LV DD ), resulting in problems such as low write reliability and low write stability at high memory capacity and/or high speed operation. There is room for improvement.
有鑑於此，本發明之主要目的係提出一種寫入操作時降低電源電壓之單埠SRAM，其能藉由寫入操作時降低電源電壓以有效避免習知具單一位元線之單埠靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。In view of this, the main object of the present invention is to provide a 單埠SRAM that reduces the power supply voltage during a write operation, which can reduce the power supply voltage by a write operation to effectively avoid the static randomness of a single bit line. It is quite difficult to access the memory cell to write logic 1.
本發明作之次要目的係提出一種寫入操作時降低電源電壓之單埠SRAM，其能有效降低待機模式時之漏電流。A secondary object of the present invention is to provide a 單埠SRAM that reduces the power supply voltage during a write operation, which can effectively reduce the leakage current in the standby mode.
本發明之再一目的係提出一種寫入操作時降低電源電壓之單埠SRAM，其即使於高記憶容量及/或高速操作時仍能具有高可靠性與高穩定性之寫入操作。Still another object of the present invention is to provide a 單埠SRAM that reduces a power supply voltage during a write operation, which can have a high reliability and high stability write operation even at high memory capacity and/or high speed operation.
本發明提出一種寫入操作時降低電源電壓之單埠SRAM，其係包括一記憶體陣列，該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶胞(1)；複數個第一偏壓電路(2)，每一列記憶體晶胞設置一個第一偏壓電路(2)；一第二偏壓電路(3)；以及複數個放電路徑(4)，每一列記憶體晶胞設置一個放電路徑(4)。該第一偏壓電路(2)係用以接收一待機模式控制信號(S)與一控制信號(CTL)，且該第一偏壓電路(2)僅於該待機模式控制信號(S)為代表待機模式(standby mode)之邏輯高位準或該控制信號(CTL)為代表選定寫入狀態之邏輯高位準時，方將一低電源供應電壓(LVDD )供應至一高電壓節點(VH)，除此之外，則將一高電源供應電壓(HVDD )供應至該高電壓節點(VH)。該第二偏壓電路(3)係用以接收該待機模式控制信號(S)之反相信號(為了便於說明起見，爾後稱該待機模式控制信號(S)之反相信號為一反相待機模式控制信號(/S)，且於該反相待機模式控制信號(/S)為代表主動模式之邏輯高位準時，將接地電壓供應至一低電壓節點(VL)，而於該反相待機模式控制信號(/S)為代表待機模式之邏輯低位準時，則將較接地電壓為高之一電壓供應至該低電壓節點(VL)。再者，為了於高記憶容量及/或高速操作時仍能具有高可靠性與高穩定性之寫入操作，以及為了於待機模式時確實將該高電壓節點(VH)固定在該低電源供應電壓(LVDD )之位準，本發明於每一列記憶體晶胞設置一個放電路徑(4)，當一控制信號(CTL)為代表選定寫入狀態之邏輯高位準時，可藉由對應之放電路徑(4)所提供之放電路徑，以將儲存在該高電壓節點(VH)之電荷放電一預定時間，而當該待機模式控制信號(S)為代表待機模式之邏輯高位準時，則藉由對應之放電路徑(4)所提供之放電路徑，以將儲存在該高電壓節點(VH)之電荷放電另一預定時間。The present invention provides a 單埠SRAM for reducing a power supply voltage during a write operation, which includes a memory array composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory. The unit cell and each row of memory cells each include a plurality of memory cells (1); a plurality of first bias circuits (2), each column of memory cells is provided with a first bias circuit (2) a second bias circuit (3); and a plurality of discharge paths (4), each column of memory cells is provided with a discharge path (4). The first bias circuit (2) is configured to receive a standby mode control signal (S) and a control signal (CTL), and the first bias circuit (2) is only in the standby mode control signal (S) A low power supply voltage (LV DD ) is supplied to a high voltage node (VH) to represent a logic high level in standby mode or a control signal (CTL) representing a logic high level of the selected write state. In addition, a high power supply voltage (HV DD ) is supplied to the high voltage node (VH). The second bias circuit (3) is configured to receive an inverted signal of the standby mode control signal (S) (for convenience of explanation, the inverted signal of the standby mode control signal (S) is said to be a reverse The phase standby mode control signal (/S), and when the inverted standby mode control signal (/S) is a logic high level representing the active mode, the ground voltage is supplied to a low voltage node (VL), and the phase is inverted The standby mode control signal (/S) is a logic low level on behalf of the standby mode, and a voltage higher than the ground voltage is supplied to the low voltage node (VL). Furthermore, for high memory capacity and/or high speed operation The present invention can still have a high reliability and high stability write operation, and in order to fix the high voltage node (VH) at the low power supply voltage (LV DD ) level in the standby mode, the present invention A column of memory cells is provided with a discharge path (4). When a control signal (CTL) is a logic high level representing the selected write state, the discharge path provided by the corresponding discharge path (4) can be stored. The charge at the high voltage node (VH) is discharged for a predetermined time And when the standby mode control signal (S) is a logic high level representing the standby mode, the discharge path provided by the corresponding discharge path (4) is used to discharge the charge stored at the high voltage node (VH). Another scheduled time.
根據上述之主要目的，本發明提出一種寫入操作時降低電源電壓之單埠SRAM，該寫入操作時降低電源電壓之單埠SRAM係包括一記憶體陣列，該記憶體陣列係由複數列記憶體晶胞與複數行記憶體晶胞所組成，每一列記憶體晶胞與每一行記憶體晶胞各包括有複數個記憶體晶胞(1)；複數個第一偏壓電路(2)，每一列記憶體晶胞設置一個第一偏壓電路(2)；一第二偏壓電路(3)；以及複數個放電路徑(4)，每一列記憶體晶胞設置一個放電路徑(4)。According to the above main object, the present invention provides a 單埠SRAM for reducing a power supply voltage during a write operation, and the SRAM for reducing the power supply voltage during the write operation includes a memory array which is composed of a plurality of columns of memories. The unit cell is composed of a plurality of memory cells, each column of memory cells and each row of memory cells each including a plurality of memory cells (1); a plurality of first bias circuits (2) Each column of memory cells is provided with a first bias circuit (2); a second bias circuit (3); and a plurality of discharge paths (4), each column of memory cells is provided with a discharge path ( 4).
為了便於說明起見，第6圖所示之寫入操作時降低電源電壓之單埠SRAM僅以一個記憶體晶胞(1)、一條字元線(WL)、一條位元線(BL)、一控制信號(CTL)、一第一偏壓電路(2)、一第二偏壓電路(3)以及一放電路徑(4)做為實施例來說明，其中該控制信號(CTL)為一寫入致能(Write Enable，簡稱WE)信號與對應之字元線(WL)信號的及閘(AND gate)運算結果，亦即僅於該寫入致能(WE)信號與該對應之字元線(WL)信號均為邏輯高位準時，該控制信號(CTL)方為邏輯高位準。該記憶體晶胞(1)係包括一第一反相器(由第一PMOS電晶體P1與第一NMOS電晶體M1所組成)、一第二反相器(由第二PMOS電晶體P2與第二NMOS電晶體M2所組成)、一第三NMOS電晶體(M3)，其中，該第一反相器和該第二反相器係呈交互耦合連接，亦即該第一反相器之輸出(即節點A)係連接該第二反相器之輸入，而該第二反相器之輸出(即節點B)則連接該第一反相器之輸入，並且該第一反相器之輸出(節點A)係用於儲存SRAM晶胞之資料，而該第二反相器之輸出(節點B)則用於儲存SRAM晶胞之反相資料，該第三NMOS電晶體(M3)，係連接在該儲存節點(A)與位元線(BL)之間，且閘極連接至字元線(WL)。For convenience of explanation, the SRAM for reducing the power supply voltage during the write operation shown in FIG. 6 is only one memory cell (1), one word line (WL), one bit line (BL), A control signal (CTL), a first bias circuit (2), a second bias circuit (3), and a discharge path (4) are illustrated as embodiments, wherein the control signal (CTL) is a write enable (WE) signal and an AND gate operation result of the corresponding word line (WL) signal, that is, only the write enable (WE) signal and the corresponding When the word line (WL) signal is at a logic high level, the control signal (CTL) side is a logic high level. The memory cell (1) includes a first inverter (composed of the first PMOS transistor P1 and the first NMOS transistor M1) and a second inverter (by the second PMOS transistor P2 and a second NMOS transistor M2), a third NMOS transistor (M3), wherein the first inverter and the second inverter are connected in an alternating coupling manner, that is, the first inverter An output (ie, node A) is coupled to the input of the second inverter, and an output of the second inverter (ie, node B) is coupled to the input of the first inverter, and the first inverter is The output (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell, the third NMOS transistor (M3), The connection is between the storage node (A) and the bit line (BL), and the gate is connected to the word line (WL).
請參考第6圖，該第一偏壓電路(2)係由一第三PMOS電晶體(P21)、一第四PMOS電晶體(P22)、一第五PMOS電晶體(P24)、第六PMOS電晶體(P25)、一第三反相器(I23)及一第四反相器(I26)所組成，該第三PMOS電晶體(P21)之源極、閘極與汲極係分別連接至該第五PMOS電晶體(P24)之汲極端、一控制信號(CTL)與一高電壓節點(VH)；該第四PMOS電晶體(P22)之源極、閘極與汲極係分別連接至一低電源供應電壓(LVDD )、該第三反相器(I23)之輸出端與該高電壓節點(VH)，該第三反相器(I23)之輸入端則用以接收該控制信號(CTL)；該第五PMOS電晶體(P24)之源極、閘極與汲極係分別連接至一高電源供應電壓(HVDD )、一待機模式控制信號(S)與該第三PMOS電晶體(P21)之源極端；該第六PMOS電晶體(P25)之源極、閘極與汲極係分別連接至該低電源供應電壓(LVDD )、該第四反相器(I26)之輸出端與該高電壓節點(VH)，該第四反相器(I26)之輸入端則用以接收該待機模式控制信號(S)，並輸出一反相待機模式控制信號(/S)。Referring to FIG. 6, the first bias circuit (2) is composed of a third PMOS transistor (P21), a fourth PMOS transistor (P22), a fifth PMOS transistor (P24), and a sixth a PMOS transistor (P25), a third inverter (I23) and a fourth inverter (I26), the source, the gate and the drain of the third PMOS transistor (P21) are respectively connected To the 汲 terminal of the fifth PMOS transistor (P24), a control signal (CTL) and a high voltage node (VH); the source, the gate and the drain of the fourth PMOS transistor (P22) are respectively connected a low power supply voltage (LV DD ), an output of the third inverter (I23) and the high voltage node (VH), and an input of the third inverter (I23) is used to receive the control a signal (CTL); the source, the gate and the drain of the fifth PMOS transistor (P24) are respectively connected to a high power supply voltage (HV DD ), a standby mode control signal (S) and the third PMOS a source terminal of the transistor (P21); a source, a gate and a drain of the sixth PMOS transistor (P25) are respectively connected to the low power supply voltage (LV DD ), and the fourth inverter (I26) The output terminal and the high voltage node (VH), the fourth inversion (I26) for receiving the input of the standby mode control signal (S), and an inverted output of the standby mode control signal (/ S).
再者，該第二偏壓電路(3)係由一第四NMOS電晶體(M31)以及一第五NMOS電晶體(M32)所組成，該第四NMOS電晶體(M31)之源極、閘極與汲極係分別連接至接地電壓、該反相待機模式控制信號(/S)與一低電壓節點(VL)，該第五NMOS電晶體(M32)之源極係連接至接地電壓，而閘極與汲極係連接在一起，並連接至該低電壓節點(VL)。Furthermore, the second bias circuit (3) is composed of a fourth NMOS transistor (M31) and a fifth NMOS transistor (M32), the source of the fourth NMOS transistor (M31), The gate and the drain are respectively connected to a ground voltage, the reverse standby mode control signal (/S) and a low voltage node (VL), and the source of the fifth NMOS transistor (M32) is connected to a ground voltage. The gate is connected to the drain and connected to the low voltage node (VL).
請再參考第六圖，該放電路徑(4)係由一第六NMOS電晶體(M41)、一第七NMOS電晶體(M42)、一第八NMOS電晶體(M43)、一第九NMOS電晶體(M44)、一第七PMOS電晶體(P45)以及一延遲電路(D46)所組成，該第六NMOS電晶體(M41)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(M43)之汲極、該控制信號(CTL)與該高電壓節點(VH)；該第七NMOS電晶體(M42)之源極、閘極與汲極係分別連接至該第八NMOS電晶體(M43)之汲極、該待機模式控制信號(S)與該高電壓節點(VH)；該第八NMOS電晶體(M43)之源極、閘極與汲極係分別連接至接地電壓、該延遲電路(D46)之輸出端與該第六NMOS電晶體(M41)之源極和該第七NMOS電晶體(M42)之源極；該第九NMOS電晶體(M44)之源極、閘極與汲極係分別連接至接地電壓、該控制信號(CTL)與該延遲電路(D46)之輸入端；該第七PMOS電晶體(P45)之源極、閘極與汲極係分別連接至該第一偏壓電路(2)中之該第四反相器(I26)之輸出端(即該反相待機模式控制信號/S)、該控制信號(CTL)與該延遲電路(D46)之輸入端。Referring again to the sixth figure, the discharge path (4) is composed of a sixth NMOS transistor (M41), a seventh NMOS transistor (M42), an eighth NMOS transistor (M43), and a ninth NMOS device. a crystal (M44), a seventh PMOS transistor (P45) and a delay circuit (D46), the source, the gate and the drain of the sixth NMOS transistor (M41) are respectively connected to the eighth NMOS a drain of the transistor (M43), the control signal (CTL) and the high voltage node (VH); a source, a gate and a drain of the seventh NMOS transistor (M42) are respectively connected to the eighth NMOS a drain of the transistor (M43), the standby mode control signal (S) and the high voltage node (VH); the source, the gate and the drain of the eighth NMOS transistor (M43) are respectively connected to a ground voltage An output end of the delay circuit (D46) and a source of the sixth NMOS transistor (M41) and a source of the seventh NMOS transistor (M42); a source of the ninth NMOS transistor (M44), The gate and the drain are respectively connected to a ground voltage, the control signal (CTL) and an input end of the delay circuit (D46); the source, the gate and the drain of the seventh PMOS transistor (P45) are respectively connected To the first bias circuit ( 2) The output of the fourth inverter (I26) (ie, the inverted standby mode control signal /S), the control signal (CTL), and the input of the delay circuit (D46).
其中，當該控制信號(CTL)為代表選定寫入狀態之邏輯高位準時，可藉由對應之放電路徑(4)所提供之放電路徑，以將儲存在該高電壓節點(VH)之電荷放電一預定時間，該預定時間係等於該延遲電路(D46)所提供之延遲時間再加上該第九NMOS電晶體(M44)傳遞邏輯低位準之傳遞延遲時間(propagation delay time)；而當該待機模式控制信號(S)為代表待機模式之邏輯高位準時，則藉由對應之放電路徑(4)所提供之放電路徑，以將儲存在該高電壓節點(VH)之電荷放電另一預定時間，該另一預定時間係等於該延遲電路(D46)所提供之延遲時間加上該第七PMOS電晶體(P45)之傳遞延遲時間再加上該第一偏壓電路(2)中之該第四反相器(I26)之下降傳遞延遲時間(fall propagation delay time)，在此值得注意的是，該延遲電路(D46)係由偶數個反相器串接而成，因此可藉由變更該偶數個反相器之數量以調整該延遲電路(D46)所提供之延遲時間，故當該控制信號(CTL)為代表選定寫入狀態之邏輯高位準或該待機模式控制信號(S)為代表待機模式之邏輯高位準時，可藉由該放電路徑(4)所提供之放電路徑，以輕易地將該高電壓節點(VH)之電壓位準由該高電源供應電壓(HVDD )之位準放電至略低於該低電源供應電壓(LVDD )之位準，並藉由該第一偏壓電路(2)以及以精確地將該高電壓節點(VH)之電壓位準固定為該低電源供應電壓(LVDD )所提供之電壓位準。Wherein, when the control signal (CTL) is a logic high level representing the selected write state, the charge path provided by the corresponding discharge path (4) can be discharged to discharge the charge stored at the high voltage node (VH). a predetermined time, the predetermined time is equal to the delay time provided by the delay circuit (D46) plus the propagation delay time of the ninth NMOS transistor (M44) transmitting a logic low level; and when the standby The mode control signal (S) is a logic high level on behalf of the standby mode, and the discharge path provided by the corresponding discharge path (4) is discharged to discharge the charge stored at the high voltage node (VH) for another predetermined time. The other predetermined time is equal to the delay time provided by the delay circuit (D46) plus the transfer delay time of the seventh PMOS transistor (P45) plus the first one of the first bias circuit (2) The fall propagation delay time of the four-inverter (I26), it is worth noting that the delay circuit (D46) is formed by connecting an even number of inverters, so that the The number of even inverters to adjust the The delay time provided by the late circuit (D46), so when the control signal (CTL) is a logic high level representing the selected write state or the standby mode control signal (S) is a logic high level representing the standby mode, a discharge path provided by the discharge path (4) to easily discharge the voltage level of the high voltage node (VH) from the level of the high power supply voltage (HV DD ) to slightly lower than the low power supply voltage a level of (LV DD ) and provided by the first bias circuit (2) and to accurately fix the voltage level of the high voltage node (VH) to the low power supply voltage (LV DD ) The voltage level.
依單埠SRAM之工作模式說明第6圖之本發明較佳實施例的工作原理如下：According to the working mode of the SRAM, the working principle of the preferred embodiment of the present invention is as follows:
(I)主動模式(active mode)(I) active mode
此時該待機模式控制信號(S)為邏輯低位準，該邏輯低位準之待機模式控制信號(S)經該第一偏壓電路(2)中之該第四反相器(I26)反相後輸出邏輯高位準之該反相待機模式控制信號(/S)，該邏輯低位準之該待機模式控制信號(S)可使得該第一偏壓電路(2)中之該第五PMOS電晶體(P24)ON(導通)，此時若該控制信號(CTL)為代表非選定寫入狀態之邏輯低位準時，則使該第一偏壓電路(2)中之第三PMOS電晶體(P21)ON(導通)，於是可將高電源供應電壓(HVDD )供應至該高電壓節點(VH)；反之，若此時該控制信號(CTL)為代表選定寫入狀態之邏輯高位準時，則使該第一偏壓電路(2)中之第三PMOS電晶體(P21)OFF(截止)，並使第四PMOS電晶體(P22)ON(導通)，於是可將該低電源供應電壓(LVDD )供應至該高電壓節點(VH)。At this time, the standby mode control signal (S) is a logic low level, and the logic low level standby mode control signal (S) is reversed by the fourth inverter (I26) in the first bias circuit (2) The phase output logic high level of the inverted standby mode control signal (/S), the logic low level of the standby mode control signal (S) can cause the fifth PMOS of the first bias circuit (2) The transistor (P24) is ON. At this time, if the control signal (CTL) is a logic low level representing the unselected write state, the third PMOS transistor in the first bias circuit (2) is caused. (P21) ON (turn-on), then the high power supply voltage (HV DD ) can be supplied to the high voltage node (VH); conversely, if the control signal (CTL) is at the logic high level of the selected write state at this time , the third PMOS transistor (P21) in the first bias circuit (2) is turned OFF (turned off), and the fourth PMOS transistor (P22) is turned ON (on), so that the low power supply can be supplied. A voltage (LV DD ) is supplied to the high voltage node (VH).
而該邏輯高位準之反相待機模式控制信號(/S)可使得該第二偏壓電路(3)中之該第四NMOS電晶體(M31)ON(導通)，於是可將該低電壓節點(VL)拉下至接地電壓。And the logic high level inverted standby mode control signal (/S) can make the fourth NMOS transistor (M31) in the second bias circuit (3) ON (on), so the low voltage can be The node (VL) is pulled down to ground.
接下來依單埠靜態隨機存取記憶晶胞之4種寫入狀態來說明第6圖之本發明較佳實施例如何完成寫入動作。Next, how the write operation of the preferred embodiment of the present invention in FIG. 6 is completed depends on the four write states of the static random access memory cell.
在寫入動作發生前(該字元線WL為接地電壓)，該第一NMOS電晶體(M1)為ON(導通)，該高電源供應電壓(HVDD )供應至該高電壓節點(VH)。因為該第一NMOS電晶體(M1)為ON，所以當寫入動作開始時，該字元線(WL)由Low(接地電壓)轉High(高電源供應電壓HVDD )。當該字元線(WL)的電壓大於該第三NMOS電晶體(M3)(即存取電晶體)的臨界電壓時，該第三NMOS電晶體(M3)由OFF(截止)轉變為ON(導通)，此時因為位元線(BL)是接地電壓，所以會將該節點A放電，而完成邏輯0的寫入動作，直到寫入週期結束。在此值得注意的是，該高電壓節點(VH)於寫入初期係具有該低電源供應電壓(LVDD )之位準，而於寫入週期結束後則具有該高電源供應電壓(HVDD )之位準。Before the writing operation occurs (the word line WL is a ground voltage), the first NMOS transistor (M1) is ON (on), and the high power supply voltage (HV DD ) is supplied to the high voltage node (VH). . Since the first NMOS transistor (M1) is ON, the word line (WL) is turned from Low (ground voltage) to High (high power supply voltage HV DD ) when the write operation starts. When the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M3) (ie, the access transistor), the third NMOS transistor (M3) is turned from OFF (OFF) to ON ( Turn on) At this time, since the bit line (BL) is the ground voltage, the node A is discharged, and the logic 0 write operation is completed until the end of the write cycle. It is worth noting here that the high voltage node (VH) has the low power supply voltage (LV DD ) level at the beginning of writing, and has the high power supply voltage (HV DD ) after the end of the write cycle. ) The standard.
在寫入動作發生前(該字元線WL為接地電壓)，該第一NMOS電晶體(M1)為ON(導通)，該高電源供應電壓(HVDD )供應至該高電壓節點(VH)。因為該第一NMOS電晶體(M1)為ON，所以當寫入動作開始時，該字元線(WL)由Low(接地電壓)轉High(該高電源供應電壓HVDD )，該節點A的電壓會跟隨該字元線(WL)的電壓而上升。Before the writing operation occurs (the word line WL is a ground voltage), the first NMOS transistor (M1) is ON (on), and the high power supply voltage (HV DD ) is supplied to the high voltage node (VH). . Since the first NMOS transistor (M1) is ON, when the write operation starts, the word line (WL) is turned from Low (ground voltage) to High (the high power supply voltage HV DD ), the node A The voltage will rise following the voltage of the word line (WL).
當該字元線(WL)的電壓大於該第三NMOS電晶體(M3)的臨界電壓時以及該控制信號(CTL)的電壓大於該放電路徑(4)中之該第六NMOS電晶體(M41)的臨界電壓時，該第三NMOS電晶體(M3)以及該第六NMOS電晶體(M41)由OFF(截止)轉變為ON(導通)，此時因為該位元線(BL)是High(高電源供應電壓HVDD )，並且因為該第一NMOS電晶體M1仍為ON且該節點B仍處於電壓位準為接近於該高電源供應電壓(HVDD )之電壓位準的初始放電狀態，所以該第一PMOS電晶體P1仍為OFF(截止)，而該節點A則會快速充電至該第三NMOS電晶體(M3)之導通等效電阻(RM3 )與該第一NMOS電晶體(M1)之導通等效電阻(RM1 )所呈現之分壓電壓位準，該分壓電壓位準等於RM1 /(RM3 +RM1 )乘以該高電源供應電壓(HVDD )所提供之電壓位準，此時由於該第三NMOS電晶體(M3)係工作於飽和區(saturation region)且該第一NMOS電晶體(M1)係工作於線性區(triode region)，因此該第三NMOS電晶體(M3)之導通等效電阻(RM3 )會遠大於該第一NMOS電晶體(M1)之導通等效電阻(RM1 )，於是該節點A會呈現低的分壓電壓位準，其值約等於第4圖之習知5T靜態隨機存取記憶體晶胞在時間為25奈秒至30奈秒期間所模擬之0.52mV。When the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M3) and the voltage of the control signal (CTL) is greater than the sixth NMOS transistor (M41) in the discharge path (4) When the threshold voltage is applied, the third NMOS transistor (M3) and the sixth NMOS transistor (M41) are turned from OFF to ON, because the bit line (BL) is High ( High power supply voltage HV DD ), and because the first NMOS transistor M1 is still ON and the node B is still in an initial discharge state where the voltage level is close to the voltage level of the high power supply voltage (HV DD ), Therefore, the first PMOS transistor P1 is still OFF, and the node A is quickly charged to the on-resistance equivalent (R M3 ) of the third NMOS transistor ( M3 ) and the first NMOS transistor ( M1) The on-voltage equivalent of the on-resistance equivalent (R M1 ), which is equal to R M1 /(R M3 +R M1 ) multiplied by the high supply voltage (HV DD ) The voltage level, at this time, because the third NMOS transistor (M3) operates in a saturation region and the first NMOS transistor (M1) operates in a triode region, This third NMOS transistor (M3) is turned the equivalent resistance (R M3) is considerably greater than the first NMOS transistor (M1) is turned the equivalent resistance (R M1), then the node A can exhibit low partial The voltage level is approximately equal to 0.52 mV simulated by the conventional 5T SRAM cell of Figure 4 during a period of 25 nanoseconds to 30 nanoseconds.
接著該節點B逐步放電至較低電壓位準，該節點B之較低電壓位準會使得該第一NMOS電晶體(M1)之導通等效電阻(RM1 )呈現較高的電阻值，該第一NMOS電晶體(M1)之該較高的電阻值會於該節點A獲得較高電壓位準，該節點A之較高電壓位準又會經由一第二反相器(由第二PMOS電晶體P2與第二NMOS電晶體M2所組成)，而使得該節點B呈現更低電壓位準，該節點B之更低電壓位準又會經由一第一反相器(由第一PMOS電晶體P1與第一NMOS電晶體M1所組成)，而使得該節點A獲得更高電壓位準，依此循環，即可將該節點A充電至該高電源供應電壓(HVDD )扣減該第三NMOS電晶體(M3)的臨界電壓或該低電源供應電壓(LVDD )兩者中之較大者，而完成邏輯1的寫入動作。在此值得注意的是，由於該電壓節點(VH)於寫入初期係具有該低電源供應電壓(LVDD )之位準，而於寫入週期結束後則具有該高電源供應電壓(HVDD )之位準，因此，寫入週期結束後，該節點A會被充電至該高電源供應電壓(HVDD )之位準。Then, the node B is gradually discharged to a lower voltage level, and the lower voltage level of the node B causes the on-resistance equivalent (R M1 ) of the first NMOS transistor ( M1 ) to exhibit a higher resistance value. The higher resistance value of the first NMOS transistor (M1) will obtain a higher voltage level at the node A, and the higher voltage level of the node A will pass through a second inverter (by the second PMOS). The transistor P2 is composed of the second NMOS transistor M2), so that the node B exhibits a lower voltage level, and the lower voltage level of the node B is again passed through a first inverter (by the first PMOS The crystal P1 is composed of the first NMOS transistor M1), so that the node A obtains a higher voltage level, and according to the cycle, the node A can be charged to the high power supply voltage (HV DD ) to deduct the first The larger of the threshold voltage of the three NMOS transistors (M3) or the low power supply voltage (LV DD ), completes the write operation of the logic 1. It is worth noting here that since the voltage node (VH) has the low power supply voltage (LV DD ) level at the beginning of writing, the high power supply voltage (HV DD ) is present after the end of the writing period. The level is such that after the end of the write cycle, the node A is charged to the level of the high power supply voltage (HV DD ).
在寫入動作發生前(該字元線WL為接地電壓)，該第一PMOS電晶體(P1)為ON(導通)，該高電源供應電壓(HVDD )供應至該電壓節點(VH)。當該字元線(WL)由Low(接地電壓)轉High(該高電源供應電壓HVDD )，且該字元線(WL)的電壓大於該第三NMOS電晶體(M3)的臨界電壓以及該控制信號(CTL)的電壓大於該放電路徑(4)中之該第六NMOS電晶體(M41)的臨界電壓時，該第三NMOS電晶體(M3)以及該第六NMOS電晶體(M41)由OFF(截止)轉變為ON(導通)；待該低電源供應電壓(LVDD )供應至該高電源節點(HVDD )後，此時因為該位元線(BL)是High(該高電源供應電壓HVDD )，並且因為該第一PMOS電晶體(P1)仍為ON，所以該節點A的電壓會降低至高電源供應電壓(HVDD )扣減該該第三NMOS電晶體(M3)的臨界電壓或該低電源供應電壓(LVDD )兩者中之較大者，直到寫入週期結束該高電源供應電壓(HVDD )供應至電壓節點(VH)。Before the write operation occurs (the word line WL is a ground voltage), the first PMOS transistor (P1) is ON (on), and the high power supply voltage (HV DD ) is supplied to the voltage node (VH). When the word line (WL) is turned from Low (ground voltage) to High (the high power supply voltage HV DD ), and the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M3) and When the voltage of the control signal (CTL) is greater than a threshold voltage of the sixth NMOS transistor (M41) in the discharge path (4), the third NMOS transistor (M3) and the sixth NMOS transistor (M41) From OFF (turned off) to ON (on); after the low power supply voltage (LV DD ) is supplied to the high power supply node (HV DD ), at this time, because the bit line (BL) is High (the high power supply) Supplying voltage HV DD ), and because the first PMOS transistor (P1) is still ON, the voltage of the node A is lowered to a high power supply voltage (HV DD ) to deduct the third NMOS transistor (M3) The larger of the threshold voltage or the low power supply voltage (LV DD ), the high power supply voltage (HV DD ) is supplied to the voltage node (VH) until the end of the write cycle.
在寫入動作發生前(該字元線WL為接地電壓)，該第一PMOS電晶體(P1)為ON(導通)，該高電源供應電壓(HVDD )供應至電壓節點(VH)。當該字元線(WL)由Low(接地電壓)轉High(該高電源供應電壓HVDD )，且該字元線(WL)的電壓大於該第三NMOS電晶體(M3)的臨界電壓時，該第三NMOS電晶體(M3)由OFF(截止)轉變為ON(導通)，此時因為該位元線(BL)是Low(接地電壓)，所以會將該節點A放電而完成邏輯0的寫入動作，直到寫入週期結束。在此值得注意的是，該高電壓節點(VH)於寫入初期係具有該低電源供應電壓(LVDD )之位準，而於寫入週期結束後則具有該高電源供應電壓(HVDD )之位準。Before the write operation occurs (the word line WL is a ground voltage), the first PMOS transistor (P1) is ON (on), and the high power supply voltage (HV DD ) is supplied to the voltage node (VH). When the word line (WL) is turned from Low (ground voltage) to High (the high power supply voltage HV DD ), and the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (M3) The third NMOS transistor (M3) is turned from OFF to ON. At this time, since the bit line (BL) is Low (ground voltage), the node A is discharged to complete the logic 0. Write action until the end of the write cycle. It is worth noting here that the high voltage node (VH) has the low power supply voltage (LV DD ) level at the beginning of writing, and has the high power supply voltage (HV DD ) after the end of the write cycle. ) The standard.
第6圖所示之本發明較佳實施例，於寫入操作時之HSPICE暫態分析模擬結果，如第圖所示，其係以level 49模型且使用TSMC 0.35微米CMOS製程參數加以模擬，由該模擬結果可証實，本發明所提出之具放電路徑之單埠SRAM，能藉由寫入操作時降低電源電壓，以有效避免習知具單一位元線之單埠靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題。再者，本發明所提出之具寫入操作時降低電源電壓之單埠SRAM，即使操作於具有高記憶容量及/或高速操作之靜態隨機存取記憶體時，仍可藉由本發明所提供之放電路徑(4)以有效提高寫入操作之可靠度與穩定度。In the preferred embodiment of the present invention shown in FIG. 6, the HSPICE transient analysis simulation result during the write operation is as shown in the figure, which is simulated by the level 49 model and using TSMC 0.35 micron CMOS process parameters. The simulation results prove that the 單埠SRAM with the discharge path proposed by the present invention can reduce the power supply voltage by the writing operation, thereby effectively avoiding the conventional static random access memory crystal with a single bit line. It is quite difficult for cells to write logic 1. Furthermore, the SRAM of the present invention for reducing the power supply voltage during a write operation can be provided by the present invention even when operating in a static random access memory having a high memory capacity and/or high speed operation. The discharge path (4) is effective to improve the reliability and stability of the write operation.
(II)待機模式(standby mode)(II) Standby mode
此時該待機模式控制信號(S)為邏輯高位準，該邏輯高位準之待機模式控制信號(S)經該第一偏壓電路(2)中之該第四反相器(I26)反相後輸出邏輯低位準之該反相待機模式控制信號(/S)，該邏輯高位準之該待機模式控制信號(S)可使得該第一偏壓電路(2)中之該第五PMOS電晶體(P24)OFF(截止)，並使得該第六PMOS電晶體(P25)ON(導通)，於是可將該低電源供應電壓(LVDD )供應至該高電壓節點(VH)；此外，該邏輯低位準之該反相待機模式控制信號(/S)可使得該第二偏壓電路(3)中之該第四NMOS電晶體(M31)OFF(截止)，由於此時該第二偏壓電路(3)中之該第五NMOS電晶體(M32)為ON(導通)，於是可將該低電壓節點(VL)維持在該第五NMOS電晶體(M32)之臨界電壓的位準。At this time, the standby mode control signal (S) is a logic high level, and the logic high level standby mode control signal (S) is reversed by the fourth inverter (I26) in the first bias circuit (2) After the phase output logic low level, the inverted standby mode control signal (/S), the logic high level of the standby mode control signal (S) can make the fifth PMOS in the first bias circuit (2) The transistor (P24) is turned OFF, and the sixth PMOS transistor (P25) is turned ON, so that the low power supply voltage (LV DD ) can be supplied to the high voltage node (VH); The logic low level of the inverted standby mode control signal (/S) can cause the fourth NMOS transistor (M31) in the second bias circuit (3) to be OFF (turned off), since the second The fifth NMOS transistor (M32) in the bias circuit (3) is ON, so that the low voltage node (VL) can be maintained at the threshold voltage of the fifth NMOS transistor (M32). quasi.
接下來說明本發明於待機模式(standby mode)時如何減少漏電流，請參考8圖，第8表示了第6圖處於待機模式時所產生之各次臨界漏電流(subthreshold leakage current)I1、I2和I3，其中假設SRAM晶胞中之該第一反相器之輸出(即節點A)為邏輯Low(接地電壓)，而該第二反相器之輸出(即節點B)為邏輯High(低電源供應電壓LVDD )。請再參考第1圖之先前技藝與第8之本發明實施例，關於流經該第三NMOS電晶體(M3)之漏電流I1之比較，由於待機模式時該字元線(WL)係為接地電壓，因此流經該第三NMOS電晶體(M3)之漏電流I1與第1圖之先前技藝(先前技藝中之NMOS電晶體M3即相當於本發明實施例中之該第三NMOS電晶體M3)具有相同的漏電流；關於流經該第一PMOS電晶體(P1)之漏電流I2之比較，由於待機模式時該高電壓節點(VH)係具有低電源供應電壓(LVDD )之電壓位準，該低電源供應電壓(LVDD )之電壓位準係小於該高電源供應電壓(HVDD )，因此可藉由降低汲極引發能障下跌(Drain-Induced Barrier Lowering，簡稱DIBL)效應以有效減少漏電流，結果流經第一PMOS電晶體(P1)之漏電流I2係小於第1圖之先前技藝者(先前技藝中之PMOS電晶體P1即相當於本發明實施例中之該第一PMOS電晶體P1)；最後關於流經第二NMOS電晶體(M2)之漏電流I3之比較，由於待機模式時該低電壓節點(VL)係維持在該第四NMOS電晶體(M32)之臨界電壓的位準，又因為該儲存節點A為邏輯Low(接地電壓)，根據本體效應(body effect)，第二NMOS電晶體(M2)之臨界電壓上升，又依2005年3月8日第US6865119號專利案第3(A)及3(B)圖之結果(該結果顯示，對於NMOS電晶體而言，閘源極電壓為-0.1伏特時之次臨界電流約為閘源極電壓為0伏特時之次臨界電流的1%)，因此流經該第二NMOS電晶體(M2)之漏電流I3係遠小於第1圖之先前技藝者(先前技藝中之NMOS電晶體M2即相當於本發明實施例中之該第二NMOS電晶體M2)。Next, how to reduce leakage current in the standby mode of the present invention will be described. Please refer to FIG. 8 and FIG. 8 shows the subthreshold leakage currents I1 and I2 generated in the standby mode of FIG. And I3, wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (ground voltage), and the output of the second inverter (ie, node B) is a logic high (low) Power supply voltage LV DD ). Referring again to the prior art of FIG. 1 and the eighth embodiment of the present invention, regarding the comparison of the leakage current I1 flowing through the third NMOS transistor (M3), the word line (WL) is The grounding voltage, therefore, the leakage current I1 flowing through the third NMOS transistor (M3) and the prior art of FIG. 1 (the NMOS transistor M3 in the prior art is equivalent to the third NMOS transistor in the embodiment of the present invention) M3) has the same leakage current; with respect to the leakage current I2 flowing through the first PMOS transistor (P1), the high voltage node (VH) has a low power supply voltage (LV DD ) voltage due to the standby mode. The voltage level of the low power supply voltage (LV DD ) is less than the high power supply voltage (HV DD ), so the Drain-Induced Barrier Lowering (DIBL) effect can be reduced. In order to effectively reduce the leakage current, the leakage current I2 flowing through the first PMOS transistor (P1) is smaller than that of the prior art of FIG. 1 (the PMOS transistor P1 in the prior art is equivalent to the first embodiment of the present invention. a PMOS transistor P1); finally, a leakage current I3 flowing through the second NMOS transistor (M2) In comparison, since the low voltage node (VL) maintains the level of the threshold voltage of the fourth NMOS transistor (M32) in the standby mode, and because the storage node A is logic Low (ground voltage), according to the bulk effect ( Body effect), the threshold voltage of the second NMOS transistor (M2) rises, and according to the results of the third (A) and 3 (B) drawings of US Pat. No. 6,865,119, March 8, 2005 (the result shows that for the NMOS In the case of a transistor, the subcritical current when the gate source voltage is -0.1 volt is about 1% of the subcritical current when the gate source voltage is 0 volts, and thus flows through the second NMOS transistor (M2). The leakage current I3 is much smaller than the prior art of FIG. 1 (the NMOS transistor M2 in the prior art is equivalent to the second NMOS transistor M2 in the embodiment of the present invention).
本發明所提出之寫入操作時降低電源電壓之單埠SRAM與第1圖之先前技藝於待機模式時，在各種不同製程(TT、SS、FF)與溫度的HSPICE暫態分析模擬結果，如表1所示，其係以level 49模型且使用TSMC 0.35微米CMOS製程參數加以模擬，由該模擬結果可証實，本發明於待機模式(standby mode)時確實可有效減少漏電流。The HSPICE transient analysis simulation results of various process (TT, SS, FF) and temperature in the different processes (TT, SS, FF) and temperature, such as the SRAM of the power supply voltage during the write operation and the prior art of the first figure in the standby mode, such as As shown in Table 1, it is simulated by the level 49 model and using TSMC 0.35 micron CMOS process parameters. From the simulation results, it can be confirmed that the present invention can effectively reduce the leakage current in the standby mode.
本發明所提出之寫入操作時降低電源電壓之單埠SRAM，具有如下功效：本發明所提出之寫入操作時降低電源電壓之單埠SRAM，具有如下功效：The 單埠SRAM which reduces the power supply voltage during the write operation proposed by the present invention has the following effects: the 單埠SRAM which reduces the power supply voltage during the write operation proposed by the present invention has the following effects:
本發明所提出之寫入操作時降低電源電壓之單埠靜態隨機存取記憶體，具有如下功效：The static random access memory for reducing the power supply voltage during the write operation of the present invention has the following effects:
(1)避免寫入邏輯1困難之問題：本發明所提出之寫入操作時降低電源電壓之單埠SRAM於寫入操作時，可藉由寫入操作時降低高電壓節點(VH)之電壓位準以有效避免習知具單一位元線之單埠靜態隨機存取記憶體晶胞存在寫入邏輯1相當困難之問題；(1) Avoiding the problem of writing logic 1: When the write operation reduces the power supply voltage during the write operation, the SRAM can reduce the voltage of the high voltage node (VH) by the write operation during the write operation. Levels are effective in avoiding the problem of writing a logic 1 in a static random access memory cell with a single bit line;
(2)於高記憶容量及/或高速操作時仍具高寫入可靠度與高寫入穩定度：由於本發明所提出之寫入操作時降低電源電壓之單埠SRAM即使於高記憶容量及/或高速操作時，仍可藉由本發明所提供之放電路徑(4)以有效提高寫入操作之可靠度與穩定度；(2) High write reliability and high write stability at high memory capacity and/or high-speed operation: due to the high memory capacity of the SRAM which reduces the power supply voltage during the write operation proposed by the present invention / or high speed operation, the discharge path (4) provided by the present invention can still be used to effectively improve the reliability and stability of the write operation;
(3)低次臨界漏電流：由於本發明所提出之寫入操作時降低電源電壓之單埠SRAM於待機模式時，高電壓節點(VH)係為低電源供應電壓(LVDD )之電壓位準，而低電壓節點(VL)係固定在該第四NMOS電晶體(M32)之臨界電壓的位準，因此本發明所提出之寫入操作時降低電源電壓之單埠SRAM亦具備低次臨界漏電流之功效。(3) Low-threshold leakage current: The high-voltage node (VH) is the voltage level of the low power supply voltage (LV DD ) when the SRAM of the power supply voltage is lowered in the standby mode during the write operation proposed by the present invention. The low voltage node (VL) is fixed at the level of the threshold voltage of the fourth NMOS transistor (M32), so the SRAM of the present invention is reduced in the write operation to reduce the power supply voltage. The effect of leakage current.
雖然本發明特別揭露並描述了所選之較佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本發明的精神與範圍。因此，所有相關技術範疇內之改變都包括在本發明之申請專利範圍內。While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.
P1．．．第一PMOS電晶體P1. . . First PMOS transistor
P2．．．第二PMOS電晶體P2. . . Second PMOS transistor
M1．．．第一NMOS電晶體M1. . . First NMOS transistor
M2．．．第二NMOS電晶體M2. . . Second NMOS transistor
M3．．．第三NMOS電晶體M3. . . Third NMOS transistor
WL．．．字元線WL. . . Word line
BL．．．位元線BL. . . Bit line
A．．．儲存節點A. . . Storage node
B．．．反相儲存節點B. . . Inverting storage node
HVDD ．．．高電源供應電壓HV DD . . . High power supply voltage
LVDD ．．．低電源供應電壓LV DD . . . Low power supply voltage
S．．．待機模式控制信號S. . . Standby mode control signal
/S．．．反相待機模式控制信號/S. . . Inverting standby mode control signal
VH．．．高電壓節點VH. . . High voltage node
VL．．．低電壓節點VL. . . Low voltage node
P21．．．第三PMOS電晶體P21. . . Third PMOS transistor
P22．．．第四PMOS電晶體P22. . . Fourth PMOS transistor
P24．．．第五PMOS電晶體P24. . . Fifth PMOS transistor
P25．．．第六PMOS電晶體P25. . . Sixth PMOS transistor
CTL．．．控制信號CTL. . . control signal
M31．．．第四NMOS電晶體M31. . . Fourth NMOS transistor
M32．．．第五NMOS電晶體M32. . . Fifth NMOS transistor
M41．．．第六NMOS電晶體M41. . . Sixth NMOS transistor
M42．．．第七NMOS電晶體M42. . . Seventh NMOS transistor
M43．．．第八NMOS電晶體M43. . . Eighth NMOS transistor
D46．．．延遲電路D46. . . Delay circuit
M44．．．第九NMOS電晶體M44. . . Ninth NMOS transistor
P45．．．第七POMS電晶體P45. . . Seventh POMS transistor
1．．．SRAM晶胞1. . . SRAM cell
2．．．第一偏壓電路2. . . First bias circuit
3．．．第二偏壓電路3. . . Second bias circuit
4．．．放電路徑4. . . Discharge path
I23．．．第三反相器I23. . . Third inverter
I26．．．第四反相器I26. . . Fourth inverter
第1圖係顯示習知6T靜態隨機存取記憶體晶胞之電路示意圖；Figure 1 is a circuit diagram showing a conventional 6T static random access memory cell;
第2圖係顯示習知6T靜態隨機存取記憶體晶胞之寫入動作時序圖；Figure 2 is a timing chart showing the write operation of a conventional 6T static random access memory cell;
第3圖係顯示習知5T靜態隨機存取記憶體晶胞之電路示意圖；Figure 3 is a circuit diagram showing a conventional 5T static random access memory cell;
第4圖係顯示習知5T靜態隨機存取記憶體晶胞之寫入動作時序圖；Figure 4 is a timing chart showing the write operation of a conventional 5T static random access memory cell;
第5圖係顯示習知第TW M358390號之5T靜態隨機存取記憶體晶胞之電路示意圖；Figure 5 is a circuit diagram showing a 5T static random access memory cell of the conventional TW M358390;
第6圖係顯示本發明較佳實施例所提出之寫入操作時降低電源電壓之單埠SRAM電路示意圖；Figure 6 is a schematic diagram showing the SRAM circuit for reducing the power supply voltage during the write operation of the preferred embodiment of the present invention;
第7圖係顯示第6圖之本發明較佳實施例之寫入動作時序圖；Figure 7 is a timing chart showing the write operation of the preferred embodiment of the present invention in Figure 6;
第8圖係顯示第6圖單埠SRAM於待機模式時所產生之各次臨界漏電流。Figure 8 shows the critical leakage currents generated by the SRAM in standby mode.
P1．．．第一PMOS電晶體P1. . . First PMOS transistor
P2．．．第二PMOS電晶體P2. . . Second PMOS transistor
M1．．．第一NMOS電晶體M1. . . First NMOS transistor
M2．．．第二NMOS電晶體M2. . . Second NMOS transistor
M3．．．第三NMOS電晶體M3. . . Third NMOS transistor
WL．．．字元線WL. . . Word line
BL．．．位元線BL. . . Bit line
A．．．儲存節點A. . . Storage node
B．．．反相儲存節點B. . . Inverting storage node
HVDD ．．．高電源供應電壓HV DD . . . High power supply voltage
LVDD ．．．低電源供應電壓LV DD . . . Low power supply voltage
S．．．待機模式控制信號S. . . Standby mode control signal
/S．．．反相待機模式控制信號/S. . . Inverting standby mode control signal
VH．．．高電壓節點VH. . . High voltage node
VL．．．低電壓節點VL. . . Low voltage node
P21．．．第三PMOS電晶體P21. . . Third PMOS transistor
P22．．．第四PMOS電晶體P22. . . Fourth PMOS transistor
P24．．．第五PMOS電晶體P24. . . Fifth PMOS transistor
P25．．．第六PMOS電晶體P25. . . Sixth PMOS transistor
CTL．．．控制信號CTL. . . control signal
M31．．．第四NMOS電晶體M31. . . Fourth NMOS transistor
M32．．．第五NMOS電晶體M32. . . Fifth NMOS transistor
M41．．．第六NMOS電晶體M41. . . Sixth NMOS transistor
M42．．．第七NMOS電晶體M42. . . Seventh NMOS transistor
M43．．．第八NMOS電晶體M43. . . Eighth NMOS transistor
D46．．．延遲電路D46. . . Delay circuit
M44．．．第九NMOS電晶體M44. . . Ninth NMOS transistor
P45．．．第七POMS電晶體P45. . . Seventh POMS transistor
1．．．SRAM晶胞1. . . SRAM cell
2．．．第一偏壓電路2. . . First bias circuit
3．．．第二偏壓電路3. . . Second bias circuit
4．．．放電路徑4. . . Discharge path
I23．．．第三反相器I23. . . Third inverter
I26．．．第四反相器I26. . . Fourth inverter
Claims (6)
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| TW98138931A TWI426515B (en) | 2009-11-17 | 2009-11-17 | Single port sram having a lower power voltage in writing operation |
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| TW98138931A TWI426515B (en) | 2009-11-17 | 2009-11-17 | Single port sram having a lower power voltage in writing operation |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11353880A (en) * | 1998-05-06 | 1999-12-24 | Hewlett Packard Co <Hp> | Asymmetric design for sram cell applied to high-density memory |
| US6781870B1 (en) * | 2003-02-25 | 2004-08-24 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| TWM302763U (en) * | 2006-07-06 | 2006-12-11 | Jia-Rong Shiau | Dual port SRAM with lower leakage current |
| TW200822144A (en) * | 2006-11-13 | 2008-05-16 | Taiwan Semiconductor Mfg | Memeoy cell writing system and method thereof |
| US7460391B2 (en) * | 2007-01-18 | 2008-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Write VCCMIN improvement scheme |
| TWM358390U (en) * | 2008-12-24 | 2009-06-01 | Hsiuping Inst Technology | Single port SRAM having a lower power voltage in writing operation |
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2009
- 2009-11-17 TW TW98138931A patent/TWI426515B/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11353880A (en) * | 1998-05-06 | 1999-12-24 | Hewlett Packard Co <Hp> | Asymmetric design for sram cell applied to high-density memory |
| US6781870B1 (en) * | 2003-02-25 | 2004-08-24 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| TWM302763U (en) * | 2006-07-06 | 2006-12-11 | Jia-Rong Shiau | Dual port SRAM with lower leakage current |
| TW200822144A (en) * | 2006-11-13 | 2008-05-16 | Taiwan Semiconductor Mfg | Memeoy cell writing system and method thereof |
| US7460391B2 (en) * | 2007-01-18 | 2008-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Write VCCMIN improvement scheme |
| TWM358390U (en) * | 2008-12-24 | 2009-06-01 | Hsiuping Inst Technology | Single port SRAM having a lower power voltage in writing operation |
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| TW201118875A (en) | 2011-06-01 |
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