TWI426394B - Empirical Mode Decomposition Operation Device and Its Envelope Line Operation Circuit - Google Patents
Empirical Mode Decomposition Operation Device and Its Envelope Line Operation Circuit Download PDFInfo
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本發明係有關於一種運算電路，特別是一種經驗模態分解運算裝置及其包絡線運算電路。
The invention relates to an arithmetic circuit, in particular to an empirical mode decomposition operation device and an envelope operation circuit thereof.
希爾伯特轉換（Hilbert Transform）自從1940年代(蓋伯Gabor 1946)開始便已廣為人知且廣泛使用於信號處理領域。然而當應用於計算瞬間頻率時，希爾伯特轉換仍有許多缺點(貝德羅西安Bedrosian 1963、納托爾Nuttall 1966)。最嚴重的缺點是當信號不是單一分量或為調頻/調幅可分開的振盪信號時，則信號的導出瞬間頻率會失去其物理意義(黃等人1998)，因此黃鄂博士在1998年提出希爾伯特-黃轉換（Hilbert-Huang Transform，HHT），其藉由將經驗模態分解法與希爾伯特頻譜分析相結合，而改善傳統希爾伯特轉換之缺點。最初發展經驗模態分解法是用來克服此缺點，使得數據可以在物理上有意義的時間-頻率-振幅空間中被檢驗。經驗模態分解法在改進之後，成為信號處理以及科學數據分析的強大工具，而應用於氣候循環、地震工程、地球物理探測、潛艇設計、架構損害偵測、衛星資料分析、血壓變化和心律不整等各項研究。
幾乎與所有先前分解方法相反，經驗模態分解法為經驗的、直覺的、直接的以及可調適的，而不需要預先的基底函式。此分解法以可在局部時間尺度內的任一數據中，尋找振盪信號的各種簡單內在模式。一個簡單的振盪模式(simple oscillatory mode)會被稱為本徵模式函數(intrinsic mode function，IMF)，此本徵模態函數滿足下列條件：(a)在整個數據集合當中，極值(最大值或最小值)的數目以及零點交叉(zero-crossing)的數目必須相同或是最多相差1；以及(b)在任一時間點，局部最大值所定義的上包絡值和局部最小值所定義的下包絡值之平均為0。簡而言之，經驗模態分解法是一種適配法，按照本徵模態函數cj以及剩餘分量rn來分解數據x(t)，意即，在等式(1)中，剩餘分量rn可以是常數、單調函數或是僅包含單一極值的函數，此包含單一極值的函數無法再取得更多本徵模態函數。如此一來，此分解法為可調適的，且因此為高效率的。由於此分解法是基於數據的局部特徵，因此亦可以使用在非線性以及非平穩程序當中。
然而，上述之總體經驗模態分解演算法(Ensemble Empirical Mode Decomposition，EEMD)不論如何演進，其運算量仍然龐大，因此即使利用電腦系統執行相關運算軟體進行運算仍無法即時運算出結果，且分解本徵模態函數需要多次迴圈的反覆運算，因此直到現今總體經驗模態分解演算法無論在哪一領域之應用皆未能脫離利用電腦系統進行計算，而無法將希爾伯特-黃轉換直接應用於硬體上的經驗模態分解，如此，無論針對各應用之運算需隨時準備電腦系統，是種不便。
為了解決HHT無法應用於硬體上的經驗模態分解的問題，李柏磊博士與徐國鎧博士等人因而提出「Hardware implementation of EMD using FPGA and DSP for on-line processing」，其利用場效可程式化邏輯閘陣列(Field Programmable Gate Array，FPGA)作為控制器，以將輸入資料儲存於乒乓緩衝暫存器中，再依序將每1000取樣數值透過數位訊號處理器(Digital Signal Processor，DSP)逐次運算出經驗模態分解，然而，此種硬體上的運算為操作於360Hz的取樣頻率，因而每完成1000取樣數值之運算需耗時2.78秒，因此，硬體上的經驗模態分解之反應效率仍未即時反應，此外，運算過程中會發生端點效應，因而讓整體運算結果受到端點效應的影響。
針對上述的問題，本發明提出一種經驗模態分解運算裝置及其包絡線運算電路，其直接利用極值運算包絡線，而減少運算電路於單位時間內針對傳統EMD的曲線運算量，以便於應用於運算電路之設計。
The Hilbert Transform has been widely known since the 1940s (Gaibel Gabor 1946) and is widely used in signal processing. However, when applied to the calculation of instantaneous frequencies, Hilbert transformation still has many shortcomings (Bedrosian 1963, Natall Nuttall 1966). The most serious disadvantage is that when the signal is not a single component or a modulating signal that can be separated by FM/AM, the instantaneous frequency of the signal will lose its physical meaning (Huang et al. 1998), so Dr. Huang E proposed Hill in 1998. Hilbert-Huang Transform (HHT), which combines empirical modal decomposition with Hilbert spectral analysis to improve the shortcomings of traditional Hilbert transforms. The initial development of empirical mode decomposition is used to overcome this shortcoming, so that data can be tested in a physically meaningful time-frequency-amplitude space. After the improvement, the empirical mode decomposition method becomes a powerful tool for signal processing and scientific data analysis, and is applied to climate cycle, earthquake engineering, geophysical exploration, submarine design, structural damage detection, satellite data analysis, blood pressure changes and arrhythmia. And other studies.
Almost in contrast to all previous decomposition methods, empirical mode decomposition is empirical, intuitive, straightforward, and adaptable, without the need for a pre-basic function. This decomposition method finds various simple intrinsic modes of the oscillating signal in any data that can be on a local time scale. A simple oscillatory mode is called an intrinsic mode function (IMF). The eigenmode function satisfies the following conditions: (a) among the entire data set, the extremum (maximum value) The number of or minimum values and the number of zero-crossings must be the same or at most 1 difference; and (b) at any point in time, the local maximum value defined by the local maximum and the local minimum defined by The average of the envelope values is zero. In short, the empirical mode decomposition method is an adaptation method that decomposes the data x(t) according to the eigenmode function cj and the residual component rn, that is, in equation (1), the residual component rn can It is a constant, a monotonic function, or a function that contains only a single extremum. A function that contains a single extremum can no longer acquire more eigenmode functions. As such, the decomposition method is adaptable and therefore highly efficient. Since this decomposition method is based on local features of the data, it can also be used in non-linear and non-stationary programs.
However, the above-mentioned Ensemble Empirical Mode Decomposition (EEMD) is still computationally intensive, so even if the computer system is used to execute the related computing software, the result cannot be calculated immediately, and the decomposition is not performed. The modal function requires repeated operations of multiple loops, so until the application of the current empirical modal decomposition algorithm in any field is not out of the computer system for calculation, the Hilbert-Yellow conversion cannot be performed. It is directly applied to the empirical mode decomposition on the hardware. Therefore, it is inconvenient to prepare the computer system regardless of the operation of each application.
In order to solve the problem that HHT can not be applied to the empirical mode decomposition of hardware, Dr. Li Bailei and Dr. Xu Guozhen proposed "Hardware implementation of EMD using FPGA and DSP for on-line processing", which uses field effect programmable logic. A Field Programmable Gate Array (FPGA) is used as a controller to store input data in a ping-pong buffer register, and sequentially calculate each 1000 sample values through a Digital Signal Processor (DSP). Empirical mode decomposition, however, this hardware operation is operated at a sampling frequency of 360 Hz, so it takes 2.78 seconds to complete the calculation of 1000 samples. Therefore, the efficiency of the empirical mode decomposition on the hardware is still There is no immediate response. In addition, the endpoint effect occurs during the operation, thus causing the overall operation result to be affected by the endpoint effect.
In view of the above problems, the present invention provides an empirical mode decomposition operation device and an envelope operation circuit thereof, which directly utilizes an extremum operation envelope, and reduces the amount of curve operation of the operation circuit for a conventional EMD per unit time, so as to facilitate application. Design of the arithmetic circuit.
本發明之主要目的，在於提供一種經驗模態分解運算裝置及其包絡線運算電路，其係直接利用取樣數值選取極值，進而利用極值構成包絡線的端點，以迅速求得包絡線。
本發明之次要目的，在於提供一種經驗模態分解運算裝置及其包絡線運算電路，更利用包絡線運算電路整合於一積體電路，以廣泛應用於各技術領域的運算，並提升運算效率。
本發明提供一種經驗模態分解運算裝置及其包絡線運算電路，其包含一接收單元、一選取單元、一第一儲存單元、一第二儲存單元與一運算單元，其中接收單元依據一取樣週期接收一數值曲線之複數取樣數值；選取單元依序自該些取樣數值選取複數極值並輸出；第一儲存單元在該選取單元輸出該些極值時儲存該些極值；第二儲存單元在該選取單元輸出該些極值時儲存該些極值所對應之複數取樣次序；以及運算單元分別自該第一儲存單元與該第二儲存單元之前端讀取該些極值與對應之該些取樣次序，並依據該些取樣次序計算該些極值而求得一由複數直線組成之包絡線。如此直接以直線運算取代曲線運算，以降低包絡線之運算量，因而提高運算效率。
茲為使 貴審查委員對本發明之結構特徵及所達成之功效更有進一步之瞭解與認識，謹佐以較佳之實施例圖及配合詳細之說明，說明如後：
The main object of the present invention is to provide an empirical mode decomposition operation device and an envelope operation circuit thereof, which directly selects an extreme value by using a sample value, and then uses an extreme value to form an end point of the envelope to quickly obtain an envelope.
A secondary object of the present invention is to provide an empirical mode decomposition operation device and an envelope operation circuit thereof, which are further integrated into an integrated circuit by using an envelope operation circuit, so as to be widely applied to calculations in various technical fields and improve operation efficiency. .
The present invention provides an empirical mode decomposition operation device and an envelope operation circuit thereof, including a receiving unit, a selection unit, a first storage unit, a second storage unit and an operation unit, wherein the receiving unit is based on a sampling period Receiving a plurality of sample values of a numerical curve; the selecting unit sequentially selects the complex extremum from the sampled values and outputs the first value; the first storage unit stores the extreme values when the selecting unit outputs the extreme values; the second storage unit is The selecting unit outputs the extreme values and stores the complex sampling order corresponding to the extreme values; and the computing unit reads the extreme values and corresponding to the first storage unit and the second storage unit respectively Sampling order, and calculating the extreme values according to the sampling orders to obtain an envelope composed of complex lines. In this way, the curve operation is directly replaced by a straight line operation to reduce the amount of calculation of the envelope, thereby improving the calculation efficiency.
In order to give the review board members a better understanding and understanding of the structural features and the efficacies of the present invention, please refer to the preferred embodiment diagrams and the detailed descriptions as follows:
請參閱第一A圖與第一B圖，其為本發明之一較佳實施例之方塊圖。如第一A圖所示，本發明為一種包絡線運算電路10，其包含一輸入單元12、一選取單元14、一儲存模組16與一運算單元18。如第一B圖所示，該輸入單元12包含一第一緩衝器122、一第二緩衝器124與一第三緩衝器126，選取單元14包含一第一比較器142、一第二比較器144與一及閘146，儲存模組16包含一第一儲存單元162與一第二儲存單元164。此外，包絡線運算電路10更包含有一計數器102與一延遲單元104。
輸入單元12之一輸出端係連接選取單元14之輸入端，選取單元14之一輸出端係連接儲存模組16之第一儲存單元162之一輸入端、延遲單元104與計數器102之一輸入端，計數器102之一輸出端係連接儲存模組16之第二儲存單元164之一輸入端，延遲單元104之輸出端係分別連接至儲存模組16之第一儲存單元162與第二儲存單元164，運算單元18之一輸入端係連接儲存模組16之一輸出端。
輸入單元12係用以依序接收外部之輸入資料的複數取樣數值，其中該輸入資料可為多項次之函數或非線性函數資料或線性函數資料，且該些函數資料可為一維資料參數或二維資料參數或三維資料參數或多維資料參數。輸入單元12係依序將該些取樣數值接收輸入資料至第一緩衝器122、第二緩衝器124與第三緩衝器126中，因此輸入資料更可自第一緩衝器122輸入而隨著該些取樣數值之取樣次序將輸入資料傳送至下一緩衝器，例如:自第一緩衝器122移動一第一資料至第二緩衝器124，且第一緩衝器122同時接續接收一第二資料。
選取單元14係分別接收第一緩衝器122之第一暫存資料與第二緩衝器124之第二暫存資料並傳送至第一比較器142，且選取單元14係分別接收第二緩衝器124之第二暫存資料與第三緩衝器126之第三暫存資料並傳送至第二比較器144，藉由第一比較器142比較第一緩衝器122與第二緩衝器124之取樣數值大小，並同時藉由第二比較器144比較第二緩衝器124與第三緩衝器126之取樣數值大小，以確定取樣數值是否為極值，其中本實施例之輸入單元12係以第一緩衝器122儲存前一取樣數值S（t-1），以第二緩衝器124儲存目前之取樣數值S（t），並以第三緩衝器126儲存下一取樣數值S（t+1），因此選取單元14係以第一比較器142與第二比較器144比較輸入單元12所接收之前一取樣數值S（t-1）、目前取樣數值S（t）與下一取樣數值S（t+1），若第二緩衝器124之取樣數值S（t）同時大於第一緩衝器122所儲存之取樣數值S（t-1）與第三緩衝器126所儲存之取樣數值S（t+1），則第二緩衝器124之取樣數值S（t）即為極大值，若第二緩衝器124之取樣數值S（t）同時小於第一緩衝器122所儲存之取樣數值S（t-1）與第三緩衝器126所儲存之取樣數值S（t+1），則第二緩衝器124之取樣數值S（t）即為極小值，當經由第一比較器142與第二比較器144得知取樣數值S（t）為極值時，即驅使及閘146輸出對應之控制訊號（例如:高準位之數位訊號）至計數器102、延遲單元104與第二緩衝器124，計數器102將極值之取樣次序輸出至儲存模組16，且控制第二緩衝器124之取樣數值S（t）傳送至儲存模組16。由此可知，本案之選取單元14並非經由方程式運算以求得極值，而是藉由較簡單之數值比較，以自複數取樣數值中選取出極值，例如:該取樣數值S（t）為極大值，選取單元14即自第二緩衝器124讀取該取樣數值S（t）。
儲存模組16在選取單元14自該些取樣數值中選取出極值並輸出時，即接收到選取單元14所輸出之極值，同時，儲存模組16亦會將計數器102針對該些取樣數值計數所得之計數值，以作為該極值之取樣次序，其中儲存模組16係以第一儲存單元162儲存選取單元14所輸出之極值，並以第二儲存單元164儲存計數器102所計數之計數值(取樣次序)，此外，本實施例之儲存模組16之第一儲存單元162與第二儲存單元164為環狀佇列，因此第一儲存單元162與第二儲存單元164前端儲存之極值與取樣次序會優先由運算電路18所讀取，以讓運算單元18依序將極值連接成複數直線(線性函數)，並將該些直線串聯成類似鋸齒狀之曲線，因而求得包絡線，其依據選取單元14所選取之極值而決定為上包絡線或下包絡線，其中運算單元18係利用內插運算法求得極值之間的內插值，以讓極值間可相互連接成直線。
計數器102係計數輸入至輸入單元12之複數取樣數值之取樣次序，本實施例之計數器102係以輸入單元12之極值判斷訊號作為清零訊號，若選取單元14判斷輸入單元12之取樣數值為極值，即驅使計數器102清零，如果該輸入單元12之取樣數值不是極值，計數器102加1；延遲單元104設置為一個定值，該定值係不小於第一存儲單元162與第二存儲單元164的長度，可依據需要而設定，本實施例之延遲單元104設為30個取樣次數，第一存儲單元162與第二存儲單元164的儲存長度亦為30。
另外，及閘146輸出對應之控制訊號經延遲單元104，輸出至第一儲存單元162與第二儲存單元164，以控制第一儲存單元162丟棄前端所儲存之極值並控制第二儲存單元164丟棄前端所對應儲存之次序，以將儲存模組16中原前端所儲存之該極值相鄰之下一極值設為儲存模組16之環狀佇列前端，也就是儲存模組16之第一儲存單元162與第二儲存單元164之前端，用於提供運算電路18讀取並運算。
由上述可知，本發明未經由任何曲線之運算，而直接依據輸入資料之取樣數值進行極值之選取，而選取出極值後，將極值兩兩連成直線，以串聯成曲線，因而無需將電路耗費於運算量大之曲線運算電路。
此外，本發明之另一實施例為選取單元14更設置一第四緩衝器，其連接該第二緩衝器124與第一儲存單元162，該第四緩衝器係用以暫存第二緩衝器124之取樣數值S（t），當及閘146之輸出訊號為對應於取樣數值S（t）為極值時，即驅使儲存模組16之第一儲存單元162儲存該第四緩衝器所暫存之取樣數值S（t），當及閘146之輸出訊號為對應於取樣數值S（t）非極值時，即驅使第一儲存單元162不執行儲存動作。
請參閱第二A圖與第二B圖，其為本發明之另一較佳實施例之方塊圖。如第二A圖所示，本發明之經驗模態分解運算裝置20係包含一輸入電路22、一運算電路24與一輸出電路26。如第二B圖所示，本發明之運算電路24係包含一第一運算模組242、一第二運算模組244、一延遲電路246、一加法器248、一除法器250與一減法器252。
運算電路24之一輸入端係連接輸入電路22之一輸出端，運算電路24之一輸出端係連接輸出電路26之一輸入端，其中運算電路24之第一運算模組242、第二運算模組244與延遲電路246之輸入端係連接至運算電路24之輸入端，因此第一運算模組242、第二運算模組244與延遲電路246之輸入端即電性連接至輸入電路22之輸入端，第一運算模組242、第二運算模組244之輸出端係分別連接至加法器248之輸入端，加法器248之輸出端連接至除法器250之輸入端，減法器252之輸入端係分別連接延遲電路246之輸出端與除法器250之輸出端，減法器252之輸出端即連接運算電路24之輸出端，因此減法器252之輸出端即電性連接至輸出電路26之輸入端。
如第二C圖所示，第一運算模組242其內部包含輸入單元2421、一選取單元2422、一計數器2423、一延遲單元2424、一儲存模組2425、一第一儲存單元2426、一第二儲存單元2427與一運算單元2428，其中第一儲存單元2426與第二儲存單元2427設於儲存模組2425中，由於第一運算模組242所包含之元件的連接關係與作動關係已揭露於第一A圖與第一B圖之實施例中，因此本實施例不再贅述。第一運算模組242係由輸入電路22接收該輸入資料之取樣數值至輸入單元2421中，因而藉由運算單元2428於最後計算出上包絡線；第二運算模組244其內部包含輸入單元2441、一選取單元2442、一計數器2443、一延遲單元2444、一儲存模組2445、一第一儲存單元2446、一第二儲存單元2447與一運算單元2448，其中第一儲存單元2446與第二儲存單元2447設於儲存模組2445中，由於第二運算模組244所包含之元件的連接關係與作動關係已揭露於第一A圖與第一B圖之實施例中，因此本實施例不再贅述。第二運算模組244係由輸入電路22接收該輸入資料之取樣數值至輸入單元2441中，因而藉由運算單元2448於最後計算出下包絡線。
當一筆資料在經過第一運算模組242、第二運算模組244、加法器248及除法器250的運算，因此運算電路24求得運算結果之時間相較於初始運算時間有一延遲時間，延遲電路246係依據該延遲時間之設定，以控制減法器252之輸入端資料為來自同一運算時間之兩筆資料，進而由減法器252之輸出端得到本徵模態函數(IMF)。
加法器248係將第一運算模組242之上包絡線與第二運算模組244之下包絡線相加，以輸出一和值至除法器250，將該和值除以2得到一均值曲線，其為上包絡線所對應之函數與下包絡線所對應之函數相加並除以2，以求得均值曲線所對應之函數(即IMF)。此外，減法器252藉由延遲電路246將輸入之該些取樣數值所對應之曲線減去除法器250所得之本徵模態函數(IMF)，以求得第一分量(h1)。另外，為了提高精確度，經驗模態分解運算裝置20更可設置複數運算電路24並相互串聯，例如:輸入電路22與輸出電路26之間設置三個運算電路24，因此輸入電路22之輸出值經三個運算電路24運算出本徵模態函數(IMF)，即本實施例係可讓經驗模態分解運算裝置20於求得第一分量(h1)後，再以第一分量(h1)作為輸入之複數取樣數值，以求得第二分量(h2)，以此類推，可由本發明之經驗模態分解運算裝置20求得第三分量(h3)，以運算出本徵模態函數(IMF)，為了更加以提高精確度，甚至可求得第n分量(hn)，其中本發明之經驗模態分解運算裝置20的分量運算精確度亦由延遲電路246所控制。
此外，由於本發明之包絡線演算電路10之取樣頻率為12.5MHz，因此採用包絡線演算電路10作為第一運算模組242與第二運算模組244之經驗模態分解運算裝置20，其每1000筆取樣數值之運算所耗費之時間為10E-4秒，因而大大提升運算效能，而有助於即時取得經驗模態分解運算之運算結果。
以上所述之實施例皆以選取單元內設置第四緩衝器，以暫存輸入單元之第二緩衝器所儲存之取樣數值S（t）並由選取單元之及閘所輸出之控制訊號控制第四緩衝器輸出代表極值之取樣數值S（t）至儲存模組，但本發明並不限於此，除此之外，更可由選取單元之及閘所輸出之控制訊號控制第二緩衝器輸出代表極值之取樣數值S（t）至儲存模組，再者，本發明之另一實施例更可為第四緩衝器設置於選取單元外部，並由選取單元之及閘所輸出之控制訊號控制第四緩衝器輸出代表極值之取樣數值S（t）至儲存模組。
綜上所述，本發明係為一種演算電路，其係利用經輕量化之演算法應用於演算電路中，使演算電路於每單位時間內減少大量運算，並提高演算電路整合於積體電路中的運算效能，故，本發明可廣泛應用於經驗模態分解演算法之各式用途上的積體電路。
故本發明實為一具有新穎性、進步性及可供產業上利用者，應符合我國專利法專利申請要件無疑，爰依法提出發明專利申請，祈鈞局早日賜至准專利，至感為禱。
惟以上所述者，僅為本發明之較佳實施例而已，並非用來限定本發明實施之範圍，故舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。
Please refer to FIG. 1A and FIG. B, which are block diagrams of a preferred embodiment of the present invention. As shown in FIG. 1A, the present invention is an envelope operation circuit 10 including an input unit 12, a selection unit 14, a storage module 16, and an operation unit 18. As shown in FIG. B, the input unit 12 includes a first buffer 122, a second buffer 124, and a third buffer 126. The selecting unit 14 includes a first comparator 142 and a second comparator. The storage module 16 includes a first storage unit 162 and a second storage unit 164. In addition, the envelope operation circuit 10 further includes a counter 102 and a delay unit 104.
An output end of the input unit 12 is connected to the input end of the selecting unit 14. One output end of the selecting unit 14 is connected to one input end of the first storage unit 162 of the storage module 16, and one input end of the delay unit 104 and the counter 102. The output end of the counter 102 is connected to one input end of the second storage unit 164 of the storage module 16. The output end of the delay unit 104 is connected to the first storage unit 162 and the second storage unit 164 of the storage module 16, respectively. One input end of the computing unit 18 is connected to one of the output terminals of the storage module 16.
The input unit 12 is configured to sequentially receive the plurality of sampled values of the external input data, wherein the input data may be a multi-order function or a non-linear function data or a linear function data, and the function data may be a one-dimensional data parameter or 2D data parameters or 3D data parameters or multidimensional data parameters. The input unit 12 sequentially receives the sampled values into the first buffer 122, the second buffer 124, and the third buffer 126, so that the input data can be input from the first buffer 122 along with the The sampling order of the sampled values transfers the input data to the next buffer, for example, moving a first data from the first buffer 122 to the second buffer 124, and the first buffer 122 simultaneously receives a second data.
The selecting unit 14 receives the first temporary storage data of the first buffer 122 and the second temporary storage data of the second buffer 124 and transmits the second temporary storage data to the first comparator 142, and the selecting unit 14 receives the second buffer 124 respectively. The second temporary storage data and the third temporary storage data of the third buffer 126 are transmitted to the second comparator 144, and the first comparator 142 compares the sample values of the first buffer 122 and the second buffer 124. And comparing the sample value of the second buffer 124 and the third buffer 126 by the second comparator 144 to determine whether the sample value is an extreme value, wherein the input unit 12 of the embodiment is the first buffer. 122 stores the previous sample value S(t-1), stores the current sample value S(t) with the second buffer 124, and stores the next sample value S(t+1) with the third buffer 126, thus selecting The unit 14 compares the previous sample value S(t-1), the current sample value S(t) and the next sample value S(t+1) received by the input unit 12 with the first comparator 142 and the second comparator 144. If the sample value S(t) of the second buffer 124 is greater than the first buffer 12 at the same time 2 stored sample value S (t-1) and the sample value S(t+1) stored in the third buffer 126, then the sample value S(t) of the second buffer 124 is a maximum value, if The sample value S(t) of the second buffer 124 is simultaneously smaller than the sample value S(t-1) stored in the first buffer 122 and the sample value S(t+1) stored in the third buffer 126, and then the second The sampled value S(t) of the buffer 124 is a minimum value. When the first comparator 142 and the second comparator 144 know that the sampled value S(t) is an extreme value, that is, the control of the drive and gate 146 output is controlled. a signal (for example, a digital signal of a high level) to a counter 102, a delay unit 104, and a second buffer 124. The counter 102 outputs the sampling order of the extreme values to the storage module 16, and controls the sampling value of the second buffer 124. S(t) is transmitted to the storage module 16. It can be seen that the selection unit 14 of the present case does not calculate the extreme value through the equation operation, but selects the extreme value from the complex sample value by a simpler numerical comparison, for example, the sample value S(t) is The maximum value, the selection unit 14 reads the sampled value S(t) from the second buffer 124.
The storage module 16 receives the extreme value outputted by the selecting unit 14 when the selecting unit 14 selects the extreme value from the sampling values, and the storage module 16 also applies the counter 102 to the sampling values. The count value is counted as the sampling order of the extreme value, wherein the storage module 16 stores the extreme value output by the selecting unit 14 in the first storage unit 162, and stores the counter 102 in the second storage unit 164. The first storage unit 162 and the second storage unit 164 of the storage module 16 of the present embodiment are in a ring-shaped array. Therefore, the first storage unit 162 and the second storage unit 164 are stored at the front end. The extreme value and the sampling order are preferentially read by the arithmetic circuit 18, so that the arithmetic unit 18 sequentially connects the extreme values into a complex straight line (linear function), and connects the straight lines into a sawtooth-like curve, thereby obtaining The envelope is determined as an upper envelope or a lower envelope according to the extreme value selected by the selection unit 14, wherein the operation unit 18 uses the interpolation algorithm to obtain an interpolation value between the extreme values, so that the extreme value can be mutual Then a straight line.
The counter 102 counts the sampling order of the plurality of sampled values input to the input unit 12. The counter 102 of the present embodiment uses the extreme value judgment signal of the input unit 12 as the clear signal, and if the selecting unit 14 determines that the sampling value of the input unit 12 is The extreme value, that is, driving the counter 102 to be cleared, if the sampling value of the input unit 12 is not an extreme value, the counter 102 is incremented by one; the delay unit 104 is set to a fixed value, which is not less than the first storage unit 162 and the second The length of the storage unit 164 can be set as needed. The delay unit 104 of the embodiment is set to 30 sampling times, and the storage length of the first storage unit 162 and the second storage unit 164 is also 30.
In addition, the gate 146 outputs a corresponding control signal via the delay unit 104 to the first storage unit 162 and the second storage unit 164 to control the first storage unit 162 to discard the extreme value stored in the front end and control the second storage unit 164. The order of the storage of the front end is discarded, so that the extreme value of the extreme value stored in the original front end of the storage module 16 is set as the front end of the ring array of the storage module 16, that is, the storage module 16 A storage unit 162 and a front end of the second storage unit 164 are configured to provide an operation circuit 18 to read and operate.
It can be seen from the above that the present invention does not use any curve calculation, but directly selects the extreme value according to the sampled value of the input data, and after selecting the extreme value, the extreme values are connected into a straight line to form a curve in series, thus eliminating the need for The circuit is consumed by a curve operation circuit with a large amount of calculation.
In addition, another embodiment of the present invention further includes a fourth buffer that is connected to the second buffer 124 and the first storage unit 162, and the fourth buffer is used to temporarily store the second buffer. The sampling value S(t) of 124, when the output signal of the gate 146 is the extreme value corresponding to the sampling value S(t), the first storage unit 162 of the storage module 16 is driven to store the fourth buffer. The stored sample value S(t), when the output signal of the AND gate 146 corresponds to the non-extreme value of the sampled value S(t), drives the first storage unit 162 to not perform the storage action.
Please refer to FIG. 2A and FIG. 2B, which are block diagrams of another preferred embodiment of the present invention. As shown in FIG. 2A, the empirical mode decomposition computing device 20 of the present invention includes an input circuit 22, an arithmetic circuit 24, and an output circuit 26. As shown in FIG. 2B, the arithmetic circuit 24 of the present invention includes a first computing module 242, a second computing module 244, a delay circuit 246, an adder 248, a divider 250, and a subtractor. 252.
An input end of the operation circuit 24 is connected to an output end of the input circuit 22, and an output end of the operation circuit 24 is connected to one input end of the output circuit 26, wherein the first operation module 242 and the second operation mode of the operation circuit 24 The input of the group 244 and the delay circuit 246 is connected to the input end of the arithmetic circuit 24, so the input terminals of the first computing module 242, the second computing module 244 and the delay circuit 246 are electrically connected to the input of the input circuit 22. The output ends of the first computing module 242 and the second computing module 244 are respectively connected to the input end of the adder 248, and the output end of the adder 248 is connected to the input end of the divider 250, and the input end of the subtractor 252 The output terminal of the delay circuit 246 is connected to the output terminal of the divider circuit 252, and the output terminal of the subtracter 252 is connected to the output terminal of the arithmetic circuit 24, so that the output terminal of the subtractor 252 is electrically connected to the input terminal of the output circuit 26. .
As shown in the second C, the first computing module 242 includes an input unit 2421, a selection unit 2422, a counter 2423, a delay unit 2424, a storage module 2425, a first storage unit 2426, and a first The storage unit 2427 and the computing unit 2428, wherein the first storage unit 2426 and the second storage unit 2427 are disposed in the storage module 2425. The connection relationship and the active relationship of the components included in the first computing module 242 have been disclosed. In the embodiment of the first A and the first B, the embodiment will not be described again. The first computing module 242 receives the sampled value of the input data from the input circuit 22 to the input unit 2421. Therefore, the upper envelope is calculated by the computing unit 2428. The second computing module 244 includes the input unit 2441 therein. a selection unit 2442, a counter 2443, a delay unit 2444, a storage module 2445, a first storage unit 2446, a second storage unit 2447 and an operation unit 2448, wherein the first storage unit 2446 and the second storage The unit 2447 is disposed in the storage module 2445. Since the connection relationship and the active relationship of the components included in the second operation module 244 are disclosed in the first A and first B embodiments, the embodiment is no longer used. Narration. The second operation module 244 receives the sampled value of the input data from the input circuit 22 into the input unit 2441, and finally calculates the lower envelope by the operation unit 2448.
When a piece of data is subjected to the operations of the first operation module 242, the second operation module 244, the adder 248, and the divider 250, the operation circuit 24 obtains the operation result with a delay time and delay compared to the initial operation time. The circuit 246 is configured to control the input data of the subtracter 252 as two data from the same operation time according to the setting of the delay time, and further obtain an eigenmode function (IMF) from the output of the subtractor 252.
The adder 248 adds the envelope of the first computing module 242 to the envelope below the second computing module 244 to output a sum value to the divider 250, and divides the sum by 2 to obtain a mean curve. The function corresponding to the upper envelope is added to the function corresponding to the lower envelope and divided by 2 to obtain the function corresponding to the mean curve (ie, IMF). In addition, the subtracter 252 subtracts the curve corresponding to the sampled values from the input by the delay circuit 246 to remove the eigenmode function (IMF) obtained by the subtractor 250 to obtain the first component (h1). In addition, in order to improve the accuracy, the empirical mode decomposition computing device 20 may further provide a plurality of arithmetic circuits 24 and are connected in series with each other. For example, three arithmetic circuits 24 are provided between the input circuit 22 and the output circuit 26, and thus the output value of the input circuit 22 is The eigenmode function (IMF) is calculated by the three arithmetic circuits 24, that is, the present embodiment allows the empirical mode decomposition computing device 20 to obtain the first component (h1) and then the first component (h1). As the input complex sample value, to obtain the second component (h2), and so on, the third component (h3) can be obtained by the empirical mode decomposition operation device 20 of the present invention to calculate the eigenmode function ( IMF), in order to further improve the accuracy, even the nth component (hn) can be obtained, wherein the component operation accuracy of the empirical mode decomposition operation device 20 of the present invention is also controlled by the delay circuit 246.
In addition, since the sampling frequency of the envelope calculation circuit 10 of the present invention is 12.5 MHz, the envelope calculation circuit 10 is employed as the empirical mode decomposition operation device 20 of the first operation module 242 and the second operation module 244, each of which The calculation time of 1000 sample values is 10E-4 seconds, which greatly improves the performance of the calculation, and helps to obtain the operation result of the empirical mode decomposition operation in real time.
In the above embodiments, the fourth buffer is set in the selected unit to temporarily store the sampled value S(t) stored in the second buffer of the input unit and is controlled by the control signal outputted by the gate of the selected unit. The four buffer output represents the sampling value S(t) of the extreme value to the storage module, but the present invention is not limited thereto, and the second buffer output may be controlled by the control signal outputted by the selection unit and the gate. The sampling value S(t) representing the extreme value is added to the storage module. Further, in another embodiment of the present invention, the fourth buffer is disposed outside the selection unit, and the control signal outputted by the gate of the selection unit is outputted. The fourth buffer is controlled to output a sample value S(t) representing the extreme value to the storage module.
In summary, the present invention is a calculus circuit which is applied to an calculus circuit by using a lightweight algorithm, so that the calculus circuit reduces a large number of operations per unit time, and improves the calculus circuit integrated in the integrated circuit. The performance of the algorithm is such that the present invention can be widely applied to integrated circuits on various applications of the empirical mode decomposition algorithm.
Therefore, the present invention is a novelty, progressive and available for industrial use. It should be in accordance with the patent application requirements of the Chinese Patent Law. It is undoubtedly the invention patent application, and the Prayer Council will grant the patent as soon as possible. .
The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally changed. Modifications are intended to be included in the scope of the patent application of the present invention.
10‧‧‧包絡線運算電路10‧‧‧Envelope operation circuit
102‧‧‧計數器102‧‧‧ counter
104‧‧‧延遲單元104‧‧‧Delay unit
12‧‧‧輸入單元12‧‧‧ input unit
14‧‧‧選取單元14‧‧‧Selection unit
142‧‧‧第一比較器142‧‧‧First comparator
144‧‧‧第二比較器144‧‧‧Second comparator
146‧‧‧及閘146‧‧‧ and gate
16‧‧‧儲存模組16‧‧‧Storage module
162‧‧‧第一儲存單元162‧‧‧First storage unit
164‧‧‧第二儲存單元164‧‧‧Second storage unit
18‧‧‧運算電路18‧‧‧Operating circuit
20‧‧‧經驗模態分解運算裝置20‧‧‧Experience mode decomposition operation device
22‧‧‧輸入電路22‧‧‧Input circuit
24‧‧‧運算電路24‧‧‧Operating circuit
242‧‧‧第一運算模組242‧‧‧First Computing Module
2421‧‧‧輸入單元2421‧‧‧ Input unit
2422‧‧‧選取單元2422‧‧‧Selection unit
2423‧‧‧計數器2423‧‧‧ counter
2424‧‧‧延遲單元2424‧‧‧Delay unit
2425‧‧‧儲存模組2425‧‧‧ storage module
2426‧‧‧第一儲存單元2426‧‧‧First storage unit
2427‧‧‧第二儲存單元2427‧‧‧Second storage unit
2428‧‧‧運算單元2428‧‧‧ arithmetic unit
244‧‧‧第二運算模組244‧‧‧Second computing module
2441‧‧‧輸入單元2441‧‧‧Input unit
2442‧‧‧選取單元2442‧‧‧Selection unit
2443‧‧‧計數器2443‧‧‧Counter
2444‧‧‧延遲單元2444‧‧‧Delay unit
2445‧‧‧儲存模組2445‧‧‧ Storage Module
2446‧‧‧第一儲存單元2446‧‧‧First storage unit
2447‧‧‧第二儲存單元2447‧‧‧Second storage unit
2448‧‧‧運算單元2448‧‧‧ arithmetic unit
246‧‧‧延遲電路246‧‧‧Delay circuit
248‧‧‧加法器248‧‧‧Adder
250‧‧‧除法器250‧‧‧ divider
252‧‧‧減法器252‧‧‧Subtractor
26‧‧‧輸出電路26‧‧‧Output circuit
第一A圖為本發明之一較佳實施例的方塊圖；
第一B圖為本發明之演算電路之一實施例的方塊圖；
第二A圖為本發明之另一較佳實施例的方塊圖；
第二B圖為本發明之演算電路之另一較佳實施例的方塊圖；以及
第二C圖為本發明之演算電路之另一較佳實施例的方塊圖。
Figure 1A is a block diagram of a preferred embodiment of the present invention;
The first B is a block diagram of an embodiment of the calculus circuit of the present invention;
Figure 2A is a block diagram of another preferred embodiment of the present invention;
2 is a block diagram of another preferred embodiment of the calculus circuit of the present invention; and a second C diagram is a block diagram of another preferred embodiment of the calculus circuit of the present invention.
10‧‧‧包絡線運算電路 10‧‧‧Envelope operation circuit
102‧‧‧計數器 102‧‧‧ counter
104‧‧‧延遲單元 104‧‧‧Delay unit
12‧‧‧輸入單元 12‧‧‧ input unit
14‧‧‧選取單元 14‧‧‧Selection unit
16‧‧‧儲存模組 16‧‧‧Storage module
162‧‧‧第一儲存單元 162‧‧‧First storage unit
164‧‧‧第二儲存單元 164‧‧‧Second storage unit
18‧‧‧運算單元 18‧‧‧ arithmetic unit
Claims (9)
一接收單元，其依據一取樣週期接收一數值曲線之複數取樣數值；
一選取單元，其連接該接收單元並依序自該些取樣數值選取複數極值及其複數對應取樣次序並輸出；
一第一儲存單元，其在該選取單元輸出該些極值時接收並儲存該些極值；
一第二儲存單元，其在該選取單元輸出該些極值時接收並儲存該些極值之該些對應取樣次序；以及
一運算單元，分別自該第一儲存單元與該第二儲存單元之前端讀取該些極值與該些對應取樣次序，並依據該些對應取樣次序計算該些極值而求得一由複數直線組成之包絡線。An empirical mode decomposition operation device and an envelope operation circuit thereof, comprising:
a receiving unit that receives a complex sample value of a numerical curve according to a sampling period;
a selection unit connected to the receiving unit and sequentially selecting a complex extreme value and a complex number corresponding sampling order from the sampled values and outputting;
a first storage unit that receives and stores the extreme values when the selection unit outputs the extreme values;
a second storage unit that receives and stores the corresponding sampling orders of the extreme values when the selecting unit outputs the extreme values; and an arithmetic unit that is respectively from the first storage unit and the second storage unit The front end reads the extreme values and the corresponding sampling orders, and calculates the extreme values according to the corresponding sampling orders to obtain an envelope composed of a plurality of straight lines.
一計數器，其連接該接收單元、該選取單元與該第二儲存單元，並計數該些取樣數值之複數取樣次序，該選取單元依據該計數器之該些取樣次序儲存該些極值之該些對應取樣次序至該第二儲存單元；
一延遲單元，其依據該計數器之計數值而延遲該運算單元輸出運算結果。For example, the envelope operation circuit described in claim 1 further includes:
a counter connecting the receiving unit, the selecting unit and the second storing unit, and counting a plurality of sampling orders of the sampling values, wherein the selecting unit stores the corresponding values of the extreme values according to the sampling order of the counter Sampling sequence to the second storage unit;
A delay unit delays the operation unit to output an operation result according to the count value of the counter.
一第一運算模組，其包含如申請專利範圍第1項所述之該包絡線運算電路，該第一運算模組依據一輸入資料運算出一上包絡線；
一第二運算模組，其包含如申請專利範圍第1項所述之該包絡線運算電路，該第二運算模組依據該輸入資料運算出一下包絡線；以及
一整合電路，其依據該上包絡線與該下包絡線求得一均值曲線與一差值曲線。An empirical mode decomposition operation circuit, comprising:
a first computing module, comprising the envelope operation circuit according to claim 1, wherein the first operation module calculates an upper envelope according to an input data;
a second computing module, comprising the envelope operation circuit according to claim 1, wherein the second operation module calculates an envelope according to the input data; and an integrated circuit according to the upper circuit The envelope and the lower envelope obtain a mean curve and a difference curve.
一加法器，其連接該第一運算模組與該第二運算模組，並相加該上包絡線與該下包絡線，以求得一和值；
一除法器，其依據該和值除以2，以求得該均值曲線；
一延遲電路，其依據該第一運算模組、該第二運算模組、該加法器、該除法器之運算時間進行延遲運算；
一減法器，其連接該除法器與該延遲電路接收該均值曲線並延遲接收該輸入資料，該減法器依據該輸入資料減去該均值曲線，求得該差值曲線。The empirical mode decomposition operation circuit of claim 8, wherein the integrated circuit comprises:
An adder connecting the first computing module and the second computing module, and adding the upper envelope and the lower envelope to obtain a sum value;
a divider that divides the sum value by 2 to obtain the mean curve;
a delay circuit, which performs a delay operation according to an operation time of the first operation module, the second operation module, the adder, and the divider;
a subtractor connected to the divider and the delay circuit receives the mean curve and delays receiving the input data, and the subtractor subtracts the mean curve according to the input data to obtain the difference curve.
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| US4984188A (en) * | 1986-12-11 | 1991-01-08 | Kabushiki Kaisha Toshiba | Digital signal processing device for calculating real and imaginary parts of an input signal |
| TW425794B (en) * | 1997-07-25 | 2001-03-11 | Globespan Semiconductor Inc | System and method for obtaining clock recovery from a received data signal |
| TW201018147A (en) * | 2008-10-27 | 2010-05-01 | Realtek Semiconductor Corp | Communication signal receiver for estimating an imaginary-part component of a complex data signal and method thereof |
| TW201027361A (en) * | 2009-01-10 | 2010-07-16 | Ind Tech Res Inst | Signal processing method for hierarchical empirical mode decomposition and apparatus therefor |
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| US4984188A (en) * | 1986-12-11 | 1991-01-08 | Kabushiki Kaisha Toshiba | Digital signal processing device for calculating real and imaginary parts of an input signal |
| JPH01136407A (en) * | 1987-11-24 | 1989-05-29 | Hitachi Ltd | Hilbert transformation device |
| TW425794B (en) * | 1997-07-25 | 2001-03-11 | Globespan Semiconductor Inc | System and method for obtaining clock recovery from a received data signal |
| TW201018147A (en) * | 2008-10-27 | 2010-05-01 | Realtek Semiconductor Corp | Communication signal receiver for estimating an imaginary-part component of a complex data signal and method thereof |
| TW201027361A (en) * | 2009-01-10 | 2010-07-16 | Ind Tech Res Inst | Signal processing method for hierarchical empirical mode decomposition and apparatus therefor |
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